xref: /dpdk/app/test-pmd/testpmd.h (revision 9e6b36c34ce928d13a5182e8e76580058366bf7c)
1174a1631SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
2174a1631SBruce Richardson  * Copyright(c) 2010-2017 Intel Corporation
3af75078fSIntel  */
4af75078fSIntel 
5af75078fSIntel #ifndef _TESTPMD_H_
6af75078fSIntel #define _TESTPMD_H_
7af75078fSIntel 
84f1ed78eSThomas Monjalon #include <stdbool.h>
94f1ed78eSThomas Monjalon 
1085c18dcbSGaetan Rivet #include <rte_pci.h>
11c752998bSGaetan Rivet #include <rte_bus_pci.h>
12b40f8d78SJiayu Hu #include <rte_gro.h>
1352f38a20SJiayu Hu #include <rte_gso.h>
1430626defSXiaoyu Min #include <cmdline.h>
1585c18dcbSGaetan Rivet 
16ce8d5614SIntel #define RTE_PORT_ALL            (~(portid_t)0x0)
17ce8d5614SIntel 
18ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX    2048
19ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX    2048
20ce8d5614SIntel 
21ce8d5614SIntel #define RTE_PORT_STOPPED        (uint16_t)0
22ce8d5614SIntel #define RTE_PORT_STARTED        (uint16_t)1
23ce8d5614SIntel #define RTE_PORT_CLOSED         (uint16_t)2
24ce8d5614SIntel #define RTE_PORT_HANDLING       (uint16_t)3
25ce8d5614SIntel 
26af75078fSIntel /*
270f6f219eSMohammad Abdul Awal  * It is used to allocate the memory for hash key.
280f6f219eSMohammad Abdul Awal  * The hash key size is NIC dependent.
290f6f219eSMohammad Abdul Awal  */
300f6f219eSMohammad Abdul Awal #define RSS_HASH_KEY_LENGTH 64
310f6f219eSMohammad Abdul Awal 
320f6f219eSMohammad Abdul Awal /*
33af75078fSIntel  * Default size of the mbuf data buffer to receive standard 1518-byte
34af75078fSIntel  * Ethernet frames in a mono-segment memory buffer.
35af75078fSIntel  */
36824cb29cSKonstantin Ananyev #define DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE
37824cb29cSKonstantin Ananyev /**< Default size of mbuf data buffer. */
38af75078fSIntel 
39af75078fSIntel /*
40af75078fSIntel  * The maximum number of segments per packet is used when creating
41af75078fSIntel  * scattered transmit packets composed of a list of mbufs.
42af75078fSIntel  */
43ea672a8bSOlivier Matz #define RTE_MAX_SEGS_PER_PKT 255 /**< nb_segs is a 8-bit unsigned char. */
44af75078fSIntel 
45af75078fSIntel #define MAX_PKT_BURST 512
46836853d3SCunming Liang #define DEF_PKT_BURST 32
47af75078fSIntel 
48e9378bbcSCunming Liang #define DEF_MBUF_CACHE 250
49e9378bbcSCunming Liang 
50fdf20fa7SSergio Gonzalez Monroy #define RTE_CACHE_LINE_SIZE_ROUNDUP(size) \
51fdf20fa7SSergio Gonzalez Monroy 	(RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))
52af75078fSIntel 
53b6ea6408SIntel #define NUMA_NO_CONFIG 0xFF
54b6ea6408SIntel #define UMA_NO_CONFIG  0xFF
55b6ea6408SIntel 
56af75078fSIntel typedef uint8_t  lcoreid_t;
57f8244c63SZhiyong Yang typedef uint16_t portid_t;
58af75078fSIntel typedef uint16_t queueid_t;
59af75078fSIntel typedef uint16_t streamid_t;
60af75078fSIntel 
610ad778b3SJasvinder Singh #if defined RTE_LIBRTE_PMD_SOFTNIC
620ad778b3SJasvinder Singh #define SOFTNIC			1
635b590fbeSJasvinder Singh #else
640ad778b3SJasvinder Singh #define SOFTNIC			0
655b590fbeSJasvinder Singh #endif
665b590fbeSJasvinder Singh 
67af75078fSIntel enum {
68af75078fSIntel 	PORT_TOPOLOGY_PAIRED,
693e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_CHAINED,
703e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_LOOP,
71af75078fSIntel };
72af75078fSIntel 
73c7f5dba7SAnatoly Burakov enum {
74c7f5dba7SAnatoly Burakov 	MP_ALLOC_NATIVE, /**< allocate and populate mempool natively */
75c7f5dba7SAnatoly Burakov 	MP_ALLOC_ANON,
76c7f5dba7SAnatoly Burakov 	/**< allocate mempool natively, but populate using anonymous memory */
77c7f5dba7SAnatoly Burakov 	MP_ALLOC_XMEM,
78c7f5dba7SAnatoly Burakov 	/**< allocate and populate mempool using anonymous memory */
79c7f5dba7SAnatoly Burakov 	MP_ALLOC_XMEM_HUGE
80c7f5dba7SAnatoly Burakov 	/**< allocate and populate mempool using anonymous hugepage memory */
81c7f5dba7SAnatoly Burakov };
82c7f5dba7SAnatoly Burakov 
83af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
84af75078fSIntel /**
85af75078fSIntel  * The data structure associated with RX and TX packet burst statistics
86af75078fSIntel  * that are recorded for each forwarding stream.
87af75078fSIntel  */
88af75078fSIntel struct pkt_burst_stats {
89af75078fSIntel 	unsigned int pkt_burst_spread[MAX_PKT_BURST];
90af75078fSIntel };
91af75078fSIntel #endif
92af75078fSIntel 
93f4d623f9SAdrien Mazarguil /** Information for a given RSS type. */
94f4d623f9SAdrien Mazarguil struct rss_type_info {
95f4d623f9SAdrien Mazarguil 	const char *str; /**< Type name. */
96f4d623f9SAdrien Mazarguil 	uint64_t rss_type; /**< Type value. */
97f4d623f9SAdrien Mazarguil };
98f4d623f9SAdrien Mazarguil 
99f4d623f9SAdrien Mazarguil /**
100f4d623f9SAdrien Mazarguil  * RSS type information table.
101f4d623f9SAdrien Mazarguil  *
102f4d623f9SAdrien Mazarguil  * An entry with a NULL type name terminates the list.
103f4d623f9SAdrien Mazarguil  */
104f4d623f9SAdrien Mazarguil extern const struct rss_type_info rss_type_table[];
105f4d623f9SAdrien Mazarguil 
106af75078fSIntel /**
107af75078fSIntel  * The data structure associated with a forwarding stream between a receive
108af75078fSIntel  * port/queue and a transmit port/queue.
109af75078fSIntel  */
110af75078fSIntel struct fwd_stream {
111af75078fSIntel 	/* "read-only" data */
112af75078fSIntel 	portid_t   rx_port;   /**< port to poll for received packets */
113af75078fSIntel 	queueid_t  rx_queue;  /**< RX queue to poll on "rx_port" */
114af75078fSIntel 	portid_t   tx_port;   /**< forwarding port of received packets */
115af75078fSIntel 	queueid_t  tx_queue;  /**< TX queue to send forwarded packets */
116af75078fSIntel 	streamid_t peer_addr; /**< index of peer ethernet address of packets */
117af75078fSIntel 
118bf56fce1SZhihong Wang 	unsigned int retry_enabled;
119bf56fce1SZhihong Wang 
120af75078fSIntel 	/* "read-write" results */
121c185d42cSDavid Marchand 	uint64_t rx_packets;  /**< received packets */
122c185d42cSDavid Marchand 	uint64_t tx_packets;  /**< received packets transmitted */
123c185d42cSDavid Marchand 	uint64_t fwd_dropped; /**< received packets not forwarded */
124c185d42cSDavid Marchand 	uint64_t rx_bad_ip_csum ; /**< received packets has bad ip checksum */
125c185d42cSDavid Marchand 	uint64_t rx_bad_l4_csum ; /**< received packets has bad l4 checksum */
126c185d42cSDavid Marchand 	uint64_t rx_bad_outer_l4_csum;
12758d475b7SJerin Jacob 	/**< received packets has bad outer l4 checksum */
128b7091f1dSJiayu Hu 	unsigned int gro_times;	/**< GRO operation times */
129af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
130af75078fSIntel 	uint64_t     core_cycles; /**< used for RX and TX processing */
131af75078fSIntel #endif
132af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
133af75078fSIntel 	struct pkt_burst_stats rx_burst_stats;
134af75078fSIntel 	struct pkt_burst_stats tx_burst_stats;
135af75078fSIntel #endif
136af75078fSIntel };
137af75078fSIntel 
138938a184aSAdrien Mazarguil /** Descriptor for a single flow. */
139938a184aSAdrien Mazarguil struct port_flow {
140938a184aSAdrien Mazarguil 	struct port_flow *next; /**< Next flow in list. */
141938a184aSAdrien Mazarguil 	struct port_flow *tmp; /**< Temporary linking. */
142938a184aSAdrien Mazarguil 	uint32_t id; /**< Flow rule ID. */
143938a184aSAdrien Mazarguil 	struct rte_flow *flow; /**< Opaque flow object returned by PMD. */
14444b257ffSAdrien Mazarguil 	struct rte_flow_conv_rule rule; /* Saved flow rule description. */
14544b257ffSAdrien Mazarguil 	uint8_t data[]; /**< Storage for flow rule description */
146938a184aSAdrien Mazarguil };
147938a184aSAdrien Mazarguil 
1480ad778b3SJasvinder Singh #ifdef SOFTNIC
1495b590fbeSJasvinder Singh /**
1505b590fbeSJasvinder Singh  * The data structure associate with softnic port
1515b590fbeSJasvinder Singh  */
1525b590fbeSJasvinder Singh struct softnic_port {
1530ad778b3SJasvinder Singh 	uint32_t default_tm_hierarchy_enable; /**< default tm hierarchy */
1540ad778b3SJasvinder Singh 	struct fwd_lcore **fwd_lcore_arg; /**< softnic fwd core parameters */
1555b590fbeSJasvinder Singh };
1565b590fbeSJasvinder Singh #endif
1575b590fbeSJasvinder Singh 
158af75078fSIntel /**
159af75078fSIntel  * The data structure associated with each port.
160af75078fSIntel  */
161af75078fSIntel struct rte_port {
162af75078fSIntel 	struct rte_eth_dev_info dev_info;   /**< PCI info + driver name */
163af75078fSIntel 	struct rte_eth_conf     dev_conf;   /**< Port configuration. */
1646d13ea8eSOlivier Matz 	struct rte_ether_addr       eth_addr;   /**< Port ethernet address */
165af75078fSIntel 	struct rte_eth_stats    stats;      /**< Last port statistics */
166af75078fSIntel 	unsigned int            socket_id;  /**< For NUMA support */
1673eecba26SShahaf Shuler 	uint16_t		parse_tunnel:1; /**< Parse internal headers */
1680f62d635SJianfeng Tan 	uint16_t                tso_segsz;  /**< Segmentation offload MSS for non-tunneled packets. */
1690f62d635SJianfeng Tan 	uint16_t                tunnel_tso_segsz; /**< Segmentation offload MSS for tunneled pkts. */
17092ebda07SHelin Zhang 	uint16_t                tx_vlan_id;/**< The tag ID */
17192ebda07SHelin Zhang 	uint16_t                tx_vlan_id_outer;/**< The outer tag ID */
172ed30d9b6SIntel 	uint8_t                 tx_queue_stats_mapping_enabled;
173ed30d9b6SIntel 	uint8_t                 rx_queue_stats_mapping_enabled;
174ce8d5614SIntel 	volatile uint16_t        port_status;    /**< port started or not */
1754f1ed78eSThomas Monjalon 	uint8_t                 need_setup;     /**< port just attached */
176ce8d5614SIntel 	uint8_t                 need_reconfig;  /**< need reconfiguring port or not */
177ce8d5614SIntel 	uint8_t                 need_reconfig_queues; /**< need reconfiguring queues or not */
178ce8d5614SIntel 	uint8_t                 rss_flag;   /**< enable rss or not */
1797741e4cfSIntel 	uint8_t                 dcb_flag;   /**< enable dcb */
180*9e6b36c3SDavid Marchand 	uint16_t                nb_rx_desc[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue rx desc number */
181*9e6b36c3SDavid Marchand 	uint16_t                nb_tx_desc[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue tx desc number */
182*9e6b36c3SDavid Marchand 	struct rte_eth_rxconf   rx_conf[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue rx configuration */
183*9e6b36c3SDavid Marchand 	struct rte_eth_txconf   tx_conf[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue tx configuration */
1846d13ea8eSOlivier Matz 	struct rte_ether_addr   *mc_addr_pool; /**< pool of multicast addrs */
1858fff6675SIvan Boule 	uint32_t                mc_addr_nb; /**< nb. of addr. in mc_addr_pool */
18641b05095SBernard Iremonger 	uint8_t                 slave_flag; /**< bonding slave port */
187938a184aSAdrien Mazarguil 	struct port_flow        *flow_list; /**< Associated flows. */
188*9e6b36c3SDavid Marchand 	const struct rte_eth_rxtx_callback *rx_dump_cb[RTE_MAX_QUEUES_PER_PORT+1];
189*9e6b36c3SDavid Marchand 	const struct rte_eth_rxtx_callback *tx_dump_cb[RTE_MAX_QUEUES_PER_PORT+1];
1900ad778b3SJasvinder Singh #ifdef SOFTNIC
1910ad778b3SJasvinder Singh 	struct softnic_port     softport;  /**< softnic params */
1925b590fbeSJasvinder Singh #endif
193c18feafaSDekel Peled 	/**< metadata value to insert in Tx packets. */
1949bf26e13SViacheslav Ovsiienko 	uint32_t		tx_metadata;
195*9e6b36c3SDavid Marchand 	const struct rte_eth_rxtx_callback *tx_set_md_cb[RTE_MAX_QUEUES_PER_PORT+1];
196af75078fSIntel };
197af75078fSIntel 
198af75078fSIntel /**
199af75078fSIntel  * The data structure associated with each forwarding logical core.
200af75078fSIntel  * The logical cores are internally numbered by a core index from 0 to
201af75078fSIntel  * the maximum number of logical cores - 1.
202af75078fSIntel  * The system CPU identifier of all logical cores are setup in a global
203af75078fSIntel  * CPU id. configuration table.
204af75078fSIntel  */
205af75078fSIntel struct fwd_lcore {
20652f38a20SJiayu Hu 	struct rte_gso_ctx gso_ctx;     /**< GSO context */
207af75078fSIntel 	struct rte_mempool *mbp; /**< The mbuf pool to use by this core */
208b7091f1dSJiayu Hu 	void *gro_ctx;		/**< GRO context */
209af75078fSIntel 	streamid_t stream_idx;   /**< index of 1st stream in "fwd_streams" */
210af75078fSIntel 	streamid_t stream_nb;    /**< number of streams in "fwd_streams" */
211af75078fSIntel 	lcoreid_t  cpuid_idx;    /**< index of logical core in CPU id table */
212af75078fSIntel 	queueid_t  tx_queue;     /**< TX queue to send forwarded packets */
213af75078fSIntel 	volatile char stopped;   /**< stop forwarding when set */
214af75078fSIntel };
215af75078fSIntel 
216af75078fSIntel /*
217af75078fSIntel  * Forwarding mode operations:
218af75078fSIntel  *   - IO forwarding mode (default mode)
219af75078fSIntel  *     Forwards packets unchanged.
220af75078fSIntel  *
221af75078fSIntel  *   - MAC forwarding mode
222af75078fSIntel  *     Set the source and the destination Ethernet addresses of packets
223af75078fSIntel  *     before forwarding them.
224af75078fSIntel  *
225af75078fSIntel  *   - IEEE1588 forwarding mode
226af75078fSIntel  *     Check that received IEEE1588 Precise Time Protocol (PTP) packets are
227af75078fSIntel  *     filtered and timestamped by the hardware.
228af75078fSIntel  *     Forwards packets unchanged on the same port.
229af75078fSIntel  *     Check that sent IEEE1588 PTP packets are timestamped by the hardware.
230af75078fSIntel  */
231af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi);
232af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi);
233af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs);
234af75078fSIntel 
235af75078fSIntel struct fwd_engine {
236af75078fSIntel 	const char       *fwd_mode_name; /**< Forwarding mode name. */
237af75078fSIntel 	port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */
238af75078fSIntel 	port_fwd_end_t   port_fwd_end;   /**< NULL if nothing special to do. */
239af75078fSIntel 	packet_fwd_t     packet_fwd;     /**< Mandatory. */
240af75078fSIntel };
241af75078fSIntel 
242bf56fce1SZhihong Wang #define BURST_TX_WAIT_US 1
243bf56fce1SZhihong Wang #define BURST_TX_RETRIES 64
244bf56fce1SZhihong Wang 
245bf56fce1SZhihong Wang extern uint32_t burst_tx_delay_time;
246bf56fce1SZhihong Wang extern uint32_t burst_tx_retry_num;
247bf56fce1SZhihong Wang 
248af75078fSIntel extern struct fwd_engine io_fwd_engine;
249af75078fSIntel extern struct fwd_engine mac_fwd_engine;
250d47388f1SCyril Chemparathy extern struct fwd_engine mac_swap_engine;
251e9e23a61SCyril Chemparathy extern struct fwd_engine flow_gen_engine;
252af75078fSIntel extern struct fwd_engine rx_only_engine;
253af75078fSIntel extern struct fwd_engine tx_only_engine;
254af75078fSIntel extern struct fwd_engine csum_fwd_engine;
255168dfa61SIvan Boule extern struct fwd_engine icmp_echo_engine;
2563c156061SJens Freimann extern struct fwd_engine noisy_vnf_engine;
2570ad778b3SJasvinder Singh #ifdef SOFTNIC
2580ad778b3SJasvinder Singh extern struct fwd_engine softnic_fwd_engine;
2595b590fbeSJasvinder Singh #endif
260af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588
261af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine;
262af75078fSIntel #endif
263af75078fSIntel 
264af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */
26530626defSXiaoyu Min extern cmdline_parse_inst_t cmd_set_raw;
266739e045bSXiaoyu Min extern cmdline_parse_inst_t cmd_show_set_raw;
267739e045bSXiaoyu Min extern cmdline_parse_inst_t cmd_show_set_raw_all;
268af75078fSIntel 
26959fcf854SShahaf Shuler extern uint16_t mempool_flags;
27059fcf854SShahaf Shuler 
271af75078fSIntel /**
272af75078fSIntel  * Forwarding Configuration
273af75078fSIntel  *
274af75078fSIntel  */
275af75078fSIntel struct fwd_config {
276af75078fSIntel 	struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */
277af75078fSIntel 	streamid_t nb_fwd_streams;  /**< Nb. of forward streams to process. */
278af75078fSIntel 	lcoreid_t  nb_fwd_lcores;   /**< Nb. of logical cores to launch. */
279af75078fSIntel 	portid_t   nb_fwd_ports;    /**< Nb. of ports involved. */
280af75078fSIntel };
281af75078fSIntel 
282900550deSIntel /**
283900550deSIntel  * DCB mode enable
284900550deSIntel  */
285900550deSIntel enum dcb_mode_enable
286900550deSIntel {
287900550deSIntel 	DCB_VT_ENABLED,
288900550deSIntel 	DCB_ENABLED
289900550deSIntel };
290900550deSIntel 
291ed30d9b6SIntel #define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */
292ed30d9b6SIntel #define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */
293ed30d9b6SIntel 
294ed30d9b6SIntel struct queue_stats_mappings {
295f8244c63SZhiyong Yang 	portid_t port_id;
296ed30d9b6SIntel 	uint16_t queue_id;
297ed30d9b6SIntel 	uint8_t stats_counter_id;
298ed30d9b6SIntel } __rte_cache_aligned;
299ed30d9b6SIntel 
300ed30d9b6SIntel extern struct queue_stats_mappings tx_queue_stats_mappings_array[];
301ed30d9b6SIntel extern struct queue_stats_mappings rx_queue_stats_mappings_array[];
302ed30d9b6SIntel 
303ed30d9b6SIntel /* Assign both tx and rx queue stats mappings to the same default values */
304ed30d9b6SIntel extern struct queue_stats_mappings *tx_queue_stats_mappings;
305ed30d9b6SIntel extern struct queue_stats_mappings *rx_queue_stats_mappings;
306ed30d9b6SIntel 
307ed30d9b6SIntel extern uint16_t nb_tx_queue_stats_mappings;
308ed30d9b6SIntel extern uint16_t nb_rx_queue_stats_mappings;
309ed30d9b6SIntel 
310a4fd5eeeSElza Mathew extern uint8_t xstats_hide_zero; /**< Hide zero values for xstats display */
311a4fd5eeeSElza Mathew 
312af75078fSIntel /* globals used for configuration */
313af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */
314285fd101SOlivier Matz extern int testpmd_logtype; /**< Log type for testpmd logs */
315af75078fSIntel extern uint8_t  interactive;
316ca7feb22SCyril Chemparathy extern uint8_t  auto_start;
31799cabef0SPablo de Lara extern uint8_t  tx_first;
31881ef862bSAllain Legacy extern char cmdline_filename[PATH_MAX]; /**< offline commands file */
319af75078fSIntel extern uint8_t  numa_support; /**< set by "--numa" parameter */
320af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */
3217741e4cfSIntel extern uint8_t no_flush_rx; /**<set by "--no-flush-rx" parameter */
3227ee3e944SVasily Philipov extern uint8_t flow_isolate_all; /**< set by "--flow-isolate-all */
323c7f5dba7SAnatoly Burakov extern uint8_t  mp_alloc_type;
324c7f5dba7SAnatoly Burakov /**< set by "--mp-anon" or "--mp-alloc" parameter */
325bc202406SDavid Marchand extern uint8_t no_link_check; /**<set by "--disable-link-check" parameter */
3266937d210SStephen Hemminger extern uint8_t no_device_start; /**<set by "--disable-device-start" parameter */
3272950a769SDeclan Doherty extern volatile int test_done; /* stop packet forwarding when set to 1. */
3288ea656f8SGaetan Rivet extern uint8_t lsc_interrupt; /**< disabled by "--no-lsc-interrupt" parameter */
329284c908cSGaetan Rivet extern uint8_t rmv_interrupt; /**< disabled by "--no-rmv-interrupt" parameter */
3303af72783SGaetan Rivet extern uint32_t event_print_mask;
3313af72783SGaetan Rivet /**< set by "--print-event xxxx" and "--mask-event xxxx parameters */
3324f1ed78eSThomas Monjalon extern bool setup_on_probe_event; /**< disabled by port setup-on iterator */
333e505d84cSAnatoly Burakov extern uint8_t hot_plug; /**< enable by "--hot-plug" parameter */
334e505d84cSAnatoly Burakov extern int do_mlockall; /**< set by "--mlockall" or "--no-mlockall" parameter */
335b0a9354aSPavan Nikhilesh extern uint8_t clear_ptypes; /**< disabled by set ptype cmd */
336af75078fSIntel 
337e261265eSRadu Nicolau #ifdef RTE_LIBRTE_IXGBE_BYPASS
3387b7e5ba7SIntel extern uint32_t bypass_timeout; /**< Store the NIC bypass watchdog timeout */
3397b7e5ba7SIntel #endif
3407b7e5ba7SIntel 
341b6ea6408SIntel /*
342b6ea6408SIntel  * Store specified sockets on which memory pool to be used by ports
343b6ea6408SIntel  * is allocated.
344b6ea6408SIntel  */
34563531389SGeorgios Katsikas extern uint8_t port_numa[RTE_MAX_ETHPORTS];
346b6ea6408SIntel 
347b6ea6408SIntel /*
348b6ea6408SIntel  * Store specified sockets on which RX ring to be used by ports
349b6ea6408SIntel  * is allocated.
350b6ea6408SIntel  */
35163531389SGeorgios Katsikas extern uint8_t rxring_numa[RTE_MAX_ETHPORTS];
352b6ea6408SIntel 
353b6ea6408SIntel /*
354b6ea6408SIntel  * Store specified sockets on which TX ring to be used by ports
355b6ea6408SIntel  * is allocated.
356b6ea6408SIntel  */
35763531389SGeorgios Katsikas extern uint8_t txring_numa[RTE_MAX_ETHPORTS];
358b6ea6408SIntel 
359b6ea6408SIntel extern uint8_t socket_num;
360b6ea6408SIntel 
361af75078fSIntel /*
362af75078fSIntel  * Configuration of logical cores:
363af75078fSIntel  * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores
364af75078fSIntel  */
365af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */
366af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */
367af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */
368af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE];
369c9cafcc8SShahaf Shuler extern unsigned int num_sockets;
370c9cafcc8SShahaf Shuler extern unsigned int socket_ids[RTE_MAX_NUMA_NODES];
371af75078fSIntel 
372af75078fSIntel /*
373af75078fSIntel  * Configuration of Ethernet ports:
374af75078fSIntel  * nb_fwd_ports <= nb_cfg_ports <= nb_ports
375af75078fSIntel  */
376af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */
377af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */
378af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */
379af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS];
380af75078fSIntel extern struct rte_port *ports;
381af75078fSIntel 
382af75078fSIntel extern struct rte_eth_rxmode rx_mode;
383fd8c20aaSShahaf Shuler extern struct rte_eth_txmode tx_mode;
384fd8c20aaSShahaf Shuler 
3858a387fa8SHelin Zhang extern uint64_t rss_hf;
386af75078fSIntel 
3871c69df45SOri Kam extern queueid_t nb_hairpinq;
388af75078fSIntel extern queueid_t nb_rxq;
389af75078fSIntel extern queueid_t nb_txq;
390af75078fSIntel 
391af75078fSIntel extern uint16_t nb_rxd;
392af75078fSIntel extern uint16_t nb_txd;
393af75078fSIntel 
394f2c5125aSPablo de Lara extern int16_t rx_free_thresh;
395f2c5125aSPablo de Lara extern int8_t rx_drop_en;
396f2c5125aSPablo de Lara extern int16_t tx_free_thresh;
397f2c5125aSPablo de Lara extern int16_t tx_rs_thresh;
398af75078fSIntel 
3993c156061SJens Freimann extern uint16_t noisy_tx_sw_bufsz;
4003c156061SJens Freimann extern uint16_t noisy_tx_sw_buf_flush_time;
4013c156061SJens Freimann extern uint64_t noisy_lkup_mem_sz;
4023c156061SJens Freimann extern uint64_t noisy_lkup_num_writes;
4033c156061SJens Freimann extern uint64_t noisy_lkup_num_reads;
4043c156061SJens Freimann extern uint64_t noisy_lkup_num_reads_writes;
4053c156061SJens Freimann 
406900550deSIntel extern uint8_t dcb_config;
407900550deSIntel extern uint8_t dcb_test;
408900550deSIntel 
409af75078fSIntel extern uint16_t mbuf_data_size; /**< Mbuf data space size. */
410c8798818SIntel extern uint32_t param_total_num_mbufs;
411af75078fSIntel 
412cfea1f30SPablo de Lara extern uint16_t stats_period;
41362d3216dSReshma Pattan 
41462d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS
41562d3216dSReshma Pattan extern uint8_t latencystats_enabled;
41662d3216dSReshma Pattan extern lcoreid_t latencystats_lcore_id;
41762d3216dSReshma Pattan #endif
41862d3216dSReshma Pattan 
419e25e6c70SRemy Horton #ifdef RTE_LIBRTE_BITRATE
420e25e6c70SRemy Horton extern lcoreid_t bitrate_lcore_id;
421e25e6c70SRemy Horton extern uint8_t bitrate_enabled;
422e25e6c70SRemy Horton #endif
423e25e6c70SRemy Horton 
424af75078fSIntel extern struct rte_fdir_conf fdir_conf;
425af75078fSIntel 
426af75078fSIntel /*
427af75078fSIntel  * Configuration of packet segments used by the "txonly" processing engine.
428af75078fSIntel  */
429af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64
430af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */
431af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */
432af75078fSIntel extern uint8_t  tx_pkt_nb_segs; /**< Number of segments in TX packets */
433af75078fSIntel 
43479bec05bSKonstantin Ananyev enum tx_pkt_split {
43579bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_OFF,
43679bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_ON,
43779bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_RND,
43879bec05bSKonstantin Ananyev };
43979bec05bSKonstantin Ananyev 
44079bec05bSKonstantin Ananyev extern enum tx_pkt_split tx_pkt_split;
44179bec05bSKonstantin Ananyev 
44282010ef5SYongseok Koh extern uint8_t txonly_multi_flow;
44382010ef5SYongseok Koh 
444af75078fSIntel extern uint16_t nb_pkt_per_burst;
445af75078fSIntel extern uint16_t mb_mempool_cache;
446f2c5125aSPablo de Lara extern int8_t rx_pthresh;
447f2c5125aSPablo de Lara extern int8_t rx_hthresh;
448f2c5125aSPablo de Lara extern int8_t rx_wthresh;
449f2c5125aSPablo de Lara extern int8_t tx_pthresh;
450f2c5125aSPablo de Lara extern int8_t tx_hthresh;
451f2c5125aSPablo de Lara extern int8_t tx_wthresh;
452af75078fSIntel 
453bf5b2126SStephen Hemminger extern uint16_t tx_udp_src_port;
454bf5b2126SStephen Hemminger extern uint16_t tx_udp_dst_port;
455bf5b2126SStephen Hemminger 
456bf5b2126SStephen Hemminger extern uint32_t tx_ip_src_addr;
457bf5b2126SStephen Hemminger extern uint32_t tx_ip_dst_addr;
458bf5b2126SStephen Hemminger 
459af75078fSIntel extern struct fwd_config cur_fwd_config;
460af75078fSIntel extern struct fwd_engine *cur_fwd_eng;
461bf56fce1SZhihong Wang extern uint32_t retry_enabled;
462af75078fSIntel extern struct fwd_lcore  **fwd_lcores;
463af75078fSIntel extern struct fwd_stream **fwd_streams;
464af75078fSIntel 
46539e5e20fSXueming Li extern uint16_t vxlan_gpe_udp_port; /**< UDP port of tunnel VXLAN-GPE. */
46639e5e20fSXueming Li 
467af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */
4686d13ea8eSOlivier Matz extern struct rte_ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS];
469af75078fSIntel 
47057e85242SBruce Richardson extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */
47157e85242SBruce Richardson extern uint32_t burst_tx_retry_num;  /**< Burst tx retry number for mac-retry. */
47257e85242SBruce Richardson 
473b7091f1dSJiayu Hu #define GRO_DEFAULT_ITEM_NUM_PER_FLOW 32
474b7091f1dSJiayu Hu #define GRO_DEFAULT_FLOW_NUM (RTE_GRO_MAX_BURST_ITEM_NUM / \
475b7091f1dSJiayu Hu 		GRO_DEFAULT_ITEM_NUM_PER_FLOW)
476b7091f1dSJiayu Hu 
477b7091f1dSJiayu Hu #define GRO_DEFAULT_FLUSH_CYCLES 1
478b7091f1dSJiayu Hu #define GRO_MAX_FLUSH_CYCLES 4
479b7091f1dSJiayu Hu 
480b40f8d78SJiayu Hu struct gro_status {
481b40f8d78SJiayu Hu 	struct rte_gro_param param;
482b40f8d78SJiayu Hu 	uint8_t enable;
483b40f8d78SJiayu Hu };
484b40f8d78SJiayu Hu extern struct gro_status gro_ports[RTE_MAX_ETHPORTS];
485b7091f1dSJiayu Hu extern uint8_t gro_flush_cycles;
486b40f8d78SJiayu Hu 
48752f38a20SJiayu Hu #define GSO_MAX_PKT_BURST 2048
48852f38a20SJiayu Hu struct gso_status {
48952f38a20SJiayu Hu 	uint8_t enable;
49052f38a20SJiayu Hu };
49152f38a20SJiayu Hu extern struct gso_status gso_ports[RTE_MAX_ETHPORTS];
49252f38a20SJiayu Hu extern uint16_t gso_max_segment_size;
49352f38a20SJiayu Hu 
4941960be7dSNelio Laranjeiro /* VXLAN encap/decap parameters. */
4951960be7dSNelio Laranjeiro struct vxlan_encap_conf {
4961960be7dSNelio Laranjeiro 	uint32_t select_ipv4:1;
4971960be7dSNelio Laranjeiro 	uint32_t select_vlan:1;
49862e8a5a8SViacheslav Ovsiienko 	uint32_t select_tos_ttl:1;
4991960be7dSNelio Laranjeiro 	uint8_t vni[3];
5001960be7dSNelio Laranjeiro 	rte_be16_t udp_src;
5011960be7dSNelio Laranjeiro 	rte_be16_t udp_dst;
5021960be7dSNelio Laranjeiro 	rte_be32_t ipv4_src;
5031960be7dSNelio Laranjeiro 	rte_be32_t ipv4_dst;
5041960be7dSNelio Laranjeiro 	uint8_t ipv6_src[16];
5051960be7dSNelio Laranjeiro 	uint8_t ipv6_dst[16];
5061960be7dSNelio Laranjeiro 	rte_be16_t vlan_tci;
50762e8a5a8SViacheslav Ovsiienko 	uint8_t ip_tos;
50862e8a5a8SViacheslav Ovsiienko 	uint8_t ip_ttl;
50935b2d13fSOlivier Matz 	uint8_t eth_src[RTE_ETHER_ADDR_LEN];
51035b2d13fSOlivier Matz 	uint8_t eth_dst[RTE_ETHER_ADDR_LEN];
5111960be7dSNelio Laranjeiro };
512f6e63e59SFerruh Yigit 
513f6e63e59SFerruh Yigit extern struct vxlan_encap_conf vxlan_encap_conf;
5141960be7dSNelio Laranjeiro 
515dcd962fcSNelio Laranjeiro /* NVGRE encap/decap parameters. */
516dcd962fcSNelio Laranjeiro struct nvgre_encap_conf {
517dcd962fcSNelio Laranjeiro 	uint32_t select_ipv4:1;
518dcd962fcSNelio Laranjeiro 	uint32_t select_vlan:1;
519dcd962fcSNelio Laranjeiro 	uint8_t tni[3];
520dcd962fcSNelio Laranjeiro 	rte_be32_t ipv4_src;
521dcd962fcSNelio Laranjeiro 	rte_be32_t ipv4_dst;
522dcd962fcSNelio Laranjeiro 	uint8_t ipv6_src[16];
523dcd962fcSNelio Laranjeiro 	uint8_t ipv6_dst[16];
524dcd962fcSNelio Laranjeiro 	rte_be16_t vlan_tci;
52535b2d13fSOlivier Matz 	uint8_t eth_src[RTE_ETHER_ADDR_LEN];
52635b2d13fSOlivier Matz 	uint8_t eth_dst[RTE_ETHER_ADDR_LEN];
527dcd962fcSNelio Laranjeiro };
528f6e63e59SFerruh Yigit 
529f6e63e59SFerruh Yigit extern struct nvgre_encap_conf nvgre_encap_conf;
530dcd962fcSNelio Laranjeiro 
531a1191d39SOri Kam /* L2 encap parameters. */
532a1191d39SOri Kam struct l2_encap_conf {
533a1191d39SOri Kam 	uint32_t select_ipv4:1;
534a1191d39SOri Kam 	uint32_t select_vlan:1;
535a1191d39SOri Kam 	rte_be16_t vlan_tci;
53635b2d13fSOlivier Matz 	uint8_t eth_src[RTE_ETHER_ADDR_LEN];
53735b2d13fSOlivier Matz 	uint8_t eth_dst[RTE_ETHER_ADDR_LEN];
538a1191d39SOri Kam };
539f6e63e59SFerruh Yigit extern struct l2_encap_conf l2_encap_conf;
540a1191d39SOri Kam 
541a1191d39SOri Kam /* L2 decap parameters. */
542a1191d39SOri Kam struct l2_decap_conf {
543a1191d39SOri Kam 	uint32_t select_vlan:1;
544a1191d39SOri Kam };
545f6e63e59SFerruh Yigit extern struct l2_decap_conf l2_decap_conf;
546a1191d39SOri Kam 
5473e77031bSOri Kam /* MPLSoGRE encap parameters. */
5483e77031bSOri Kam struct mplsogre_encap_conf {
5493e77031bSOri Kam 	uint32_t select_ipv4:1;
5503e77031bSOri Kam 	uint32_t select_vlan:1;
5513e77031bSOri Kam 	uint8_t label[3];
5523e77031bSOri Kam 	rte_be32_t ipv4_src;
5533e77031bSOri Kam 	rte_be32_t ipv4_dst;
5543e77031bSOri Kam 	uint8_t ipv6_src[16];
5553e77031bSOri Kam 	uint8_t ipv6_dst[16];
5563e77031bSOri Kam 	rte_be16_t vlan_tci;
55735b2d13fSOlivier Matz 	uint8_t eth_src[RTE_ETHER_ADDR_LEN];
55835b2d13fSOlivier Matz 	uint8_t eth_dst[RTE_ETHER_ADDR_LEN];
5593e77031bSOri Kam };
560f6e63e59SFerruh Yigit extern struct mplsogre_encap_conf mplsogre_encap_conf;
5613e77031bSOri Kam 
5623e77031bSOri Kam /* MPLSoGRE decap parameters. */
5633e77031bSOri Kam struct mplsogre_decap_conf {
5643e77031bSOri Kam 	uint32_t select_ipv4:1;
5653e77031bSOri Kam 	uint32_t select_vlan:1;
5663e77031bSOri Kam };
567f6e63e59SFerruh Yigit extern struct mplsogre_decap_conf mplsogre_decap_conf;
5683e77031bSOri Kam 
569a1191d39SOri Kam /* MPLSoUDP encap parameters. */
570a1191d39SOri Kam struct mplsoudp_encap_conf {
571a1191d39SOri Kam 	uint32_t select_ipv4:1;
572a1191d39SOri Kam 	uint32_t select_vlan:1;
573a1191d39SOri Kam 	uint8_t label[3];
574a1191d39SOri Kam 	rte_be16_t udp_src;
575a1191d39SOri Kam 	rte_be16_t udp_dst;
576a1191d39SOri Kam 	rte_be32_t ipv4_src;
577a1191d39SOri Kam 	rte_be32_t ipv4_dst;
578a1191d39SOri Kam 	uint8_t ipv6_src[16];
579a1191d39SOri Kam 	uint8_t ipv6_dst[16];
580a1191d39SOri Kam 	rte_be16_t vlan_tci;
58135b2d13fSOlivier Matz 	uint8_t eth_src[RTE_ETHER_ADDR_LEN];
58235b2d13fSOlivier Matz 	uint8_t eth_dst[RTE_ETHER_ADDR_LEN];
583a1191d39SOri Kam };
584f6e63e59SFerruh Yigit extern struct mplsoudp_encap_conf mplsoudp_encap_conf;
585a1191d39SOri Kam 
586a1191d39SOri Kam /* MPLSoUDP decap parameters. */
587a1191d39SOri Kam struct mplsoudp_decap_conf {
588a1191d39SOri Kam 	uint32_t select_ipv4:1;
589a1191d39SOri Kam 	uint32_t select_vlan:1;
590a1191d39SOri Kam };
591f6e63e59SFerruh Yigit extern struct mplsoudp_decap_conf mplsoudp_decap_conf;
592a1191d39SOri Kam 
593af75078fSIntel static inline unsigned int
594af75078fSIntel lcore_num(void)
595af75078fSIntel {
596af75078fSIntel 	unsigned int i;
597af75078fSIntel 
598af75078fSIntel 	for (i = 0; i < RTE_MAX_LCORE; ++i)
599af75078fSIntel 		if (fwd_lcores_cpuids[i] == rte_lcore_id())
600af75078fSIntel 			return i;
601af75078fSIntel 
602af75078fSIntel 	rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n");
603af75078fSIntel }
604af75078fSIntel 
605af75078fSIntel static inline struct fwd_lcore *
606af75078fSIntel current_fwd_lcore(void)
607af75078fSIntel {
608af75078fSIntel 	return fwd_lcores[lcore_num()];
609af75078fSIntel }
610af75078fSIntel 
611af75078fSIntel /* Mbuf Pools */
612af75078fSIntel static inline void
613af75078fSIntel mbuf_poolname_build(unsigned int sock_id, char* mp_name, int name_size)
614af75078fSIntel {
6156f41fe75SStephen Hemminger 	snprintf(mp_name, name_size, "mbuf_pool_socket_%u", sock_id);
616af75078fSIntel }
617af75078fSIntel 
618af75078fSIntel static inline struct rte_mempool *
619af75078fSIntel mbuf_pool_find(unsigned int sock_id)
620af75078fSIntel {
621af75078fSIntel 	char pool_name[RTE_MEMPOOL_NAMESIZE];
622af75078fSIntel 
623af75078fSIntel 	mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name));
624693f715dSHuawei Xie 	return rte_mempool_lookup((const char *)pool_name);
625af75078fSIntel }
626af75078fSIntel 
627af75078fSIntel /**
628af75078fSIntel  * Read/Write operations on a PCI register of a port.
629af75078fSIntel  */
630af75078fSIntel static inline uint32_t
631af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off)
632af75078fSIntel {
633cd8c7c7cSFerruh Yigit 	const struct rte_pci_device *pci_dev;
634cd8c7c7cSFerruh Yigit 	const struct rte_bus *bus;
635af75078fSIntel 	void *reg_addr;
636af75078fSIntel 	uint32_t reg_v;
637af75078fSIntel 
638cd8c7c7cSFerruh Yigit 	if (!port->dev_info.device) {
639cd8c7c7cSFerruh Yigit 		printf("Invalid device\n");
640cd8c7c7cSFerruh Yigit 		return 0;
641cd8c7c7cSFerruh Yigit 	}
642cd8c7c7cSFerruh Yigit 
643cd8c7c7cSFerruh Yigit 	bus = rte_bus_find_by_device(port->dev_info.device);
644cd8c7c7cSFerruh Yigit 	if (bus && !strcmp(bus->name, "pci")) {
645cd8c7c7cSFerruh Yigit 		pci_dev = RTE_DEV_TO_PCI(port->dev_info.device);
646cd8c7c7cSFerruh Yigit 	} else {
647cd8c7c7cSFerruh Yigit 		printf("Not a PCI device\n");
648cd8c7c7cSFerruh Yigit 		return 0;
649cd8c7c7cSFerruh Yigit 	}
650cd8c7c7cSFerruh Yigit 
651cd8c7c7cSFerruh Yigit 	reg_addr = ((char *)pci_dev->mem_resource[0].addr + reg_off);
652af75078fSIntel 	reg_v = *((volatile uint32_t *)reg_addr);
653af75078fSIntel 	return rte_le_to_cpu_32(reg_v);
654af75078fSIntel }
655af75078fSIntel 
656af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \
657af75078fSIntel 	port_pci_reg_read(&ports[(pt_id)], (reg_off))
658af75078fSIntel 
659af75078fSIntel static inline void
660af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v)
661af75078fSIntel {
662cd8c7c7cSFerruh Yigit 	const struct rte_pci_device *pci_dev;
663cd8c7c7cSFerruh Yigit 	const struct rte_bus *bus;
664af75078fSIntel 	void *reg_addr;
665af75078fSIntel 
666cd8c7c7cSFerruh Yigit 	if (!port->dev_info.device) {
667cd8c7c7cSFerruh Yigit 		printf("Invalid device\n");
668cd8c7c7cSFerruh Yigit 		return;
669cd8c7c7cSFerruh Yigit 	}
670cd8c7c7cSFerruh Yigit 
671cd8c7c7cSFerruh Yigit 	bus = rte_bus_find_by_device(port->dev_info.device);
672cd8c7c7cSFerruh Yigit 	if (bus && !strcmp(bus->name, "pci")) {
673cd8c7c7cSFerruh Yigit 		pci_dev = RTE_DEV_TO_PCI(port->dev_info.device);
674cd8c7c7cSFerruh Yigit 	} else {
675cd8c7c7cSFerruh Yigit 		printf("Not a PCI device\n");
676cd8c7c7cSFerruh Yigit 		return;
677cd8c7c7cSFerruh Yigit 	}
678cd8c7c7cSFerruh Yigit 
679cd8c7c7cSFerruh Yigit 	reg_addr = ((char *)pci_dev->mem_resource[0].addr + reg_off);
680af75078fSIntel 	*((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v);
681af75078fSIntel }
682af75078fSIntel 
683af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \
684af75078fSIntel 	port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value))
685af75078fSIntel 
686af75078fSIntel /* Prototypes */
687950d1516SBruce Richardson unsigned int parse_item_list(char* str, const char* item_name,
688950d1516SBruce Richardson 			unsigned int max_items,
689950d1516SBruce Richardson 			unsigned int *parsed_items, int check_unique_values);
690af75078fSIntel void launch_args_parse(int argc, char** argv);
69181ef862bSAllain Legacy void cmdline_read_from_file(const char *filename);
692af75078fSIntel void prompt(void);
693d3a274ceSZhihong Wang void prompt_exit(void);
694af75078fSIntel void nic_stats_display(portid_t port_id);
695af75078fSIntel void nic_stats_clear(portid_t port_id);
696bfd5051bSOlivier Matz void nic_xstats_display(portid_t port_id);
697bfd5051bSOlivier Matz void nic_xstats_clear(portid_t port_id);
698ed30d9b6SIntel void nic_stats_mapping_display(portid_t port_id);
69955e51c96SNithin Dabilpuram void device_infos_display(const char *identifier);
700af75078fSIntel void port_infos_display(portid_t port_id);
7014bfcbcf5SEmma Finn void port_summary_display(portid_t port_id);
7024bfcbcf5SEmma Finn void port_summary_header_display(void);
703d28645c7SQiming Yang void port_offload_cap_display(portid_t port_id);
704ab3257e1SKonstantin Ananyev void rx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
705ab3257e1SKonstantin Ananyev void tx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
706af75078fSIntel void fwd_lcores_config_display(void);
7070c0db76fSBernard Iremonger void pkt_fwd_config_display(struct fwd_config *cfg);
708af75078fSIntel void rxtx_config_display(void);
709af75078fSIntel void fwd_config_setup(void);
710af75078fSIntel void set_def_fwd_config(void);
711a21d5a4bSDeclan Doherty void reconfig(portid_t new_port_id, unsigned socket_id);
712013af9b6SIntel int init_fwd_streams(void);
71303ce2c53SMatan Azrad void update_fwd_ports(portid_t new_pid);
714013af9b6SIntel 
715aac6f11fSWisam Jaddo void set_fwd_eth_peer(portid_t port_id, char *peer_addr);
716aac6f11fSWisam Jaddo 
717ae03d0d1SIvan Boule void port_mtu_set(portid_t port_id, uint16_t mtu);
718af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos);
719af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos,
720af75078fSIntel 		      uint8_t bit_v);
721af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off,
722af75078fSIntel 				uint8_t bit1_pos, uint8_t bit2_pos);
723af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off,
724af75078fSIntel 			    uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value);
725af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off);
726af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value);
727938a184aSAdrien Mazarguil int port_flow_validate(portid_t port_id,
728938a184aSAdrien Mazarguil 		       const struct rte_flow_attr *attr,
729938a184aSAdrien Mazarguil 		       const struct rte_flow_item *pattern,
730938a184aSAdrien Mazarguil 		       const struct rte_flow_action *actions);
731938a184aSAdrien Mazarguil int port_flow_create(portid_t port_id,
732938a184aSAdrien Mazarguil 		     const struct rte_flow_attr *attr,
733938a184aSAdrien Mazarguil 		     const struct rte_flow_item *pattern,
734938a184aSAdrien Mazarguil 		     const struct rte_flow_action *actions);
735938a184aSAdrien Mazarguil int port_flow_destroy(portid_t port_id, uint32_t n, const uint32_t *rule);
736938a184aSAdrien Mazarguil int port_flow_flush(portid_t port_id);
737938a184aSAdrien Mazarguil int port_flow_query(portid_t port_id, uint32_t rule,
738fb8fd96dSDeclan Doherty 		    const struct rte_flow_action *action);
739938a184aSAdrien Mazarguil void port_flow_list(portid_t port_id, uint32_t n, const uint32_t *group);
740323f811aSAdrien Mazarguil int port_flow_isolate(portid_t port_id, int set);
741af75078fSIntel 
742af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id);
743af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id);
744af75078fSIntel 
745013af9b6SIntel int set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc);
746013af9b6SIntel int set_fwd_lcores_mask(uint64_t lcoremask);
747af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc);
748af75078fSIntel 
749af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt);
750af75078fSIntel void set_fwd_ports_mask(uint64_t portmask);
751af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt);
752a8ef3e3aSBernard Iremonger int port_is_forwarding(portid_t port_id);
753af75078fSIntel 
754a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on);
755a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on);
756a47aa8b9SIntel 
757a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on);
758af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on);
7592a0b4198SVivek Sharma void rx_vlan_qinq_strip_set(portid_t port_id, int on);
76064b01ee0SMichal Jastrzebski int rx_vft_set(portid_t port_id, uint16_t vlan_id, int on);
761a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on);
76219b16e2fSHelin Zhang void vlan_tpid_set(portid_t port_id, enum rte_vlan_type vlan_type,
76319b16e2fSHelin Zhang 		   uint16_t tp_id);
764af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id);
76592ebda07SHelin Zhang void tx_qinq_set(portid_t port_id, uint16_t vlan_id, uint16_t vlan_id_outer);
766af75078fSIntel void tx_vlan_reset(portid_t port_id);
767529ba951SHelin Zhang void tx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on);
768ed30d9b6SIntel 
769ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value);
770ed30d9b6SIntel 
771a4fd5eeeSElza Mathew void set_xstats_hide_zero(uint8_t on_off);
772a4fd5eeeSElza Mathew 
773af75078fSIntel void set_verbose_level(uint16_t vb_level);
774af75078fSIntel void set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs);
77579bec05bSKonstantin Ananyev void show_tx_pkt_segments(void);
77679bec05bSKonstantin Ananyev void set_tx_pkt_split(const char *name);
777af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst);
778769ce6b1SThomas Monjalon char *list_pkt_forwarding_modes(void);
779bf56fce1SZhihong Wang char *list_pkt_forwarding_retry_modes(void);
780af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode);
781af75078fSIntel void start_packet_forwarding(int with_tx_first);
78253324971SDavid Marchand void fwd_stats_display(void);
78353324971SDavid Marchand void fwd_stats_reset(void);
784af75078fSIntel void stop_packet_forwarding(void);
785cfae07fdSOuyang Changchun void dev_set_link_up(portid_t pid);
786cfae07fdSOuyang Changchun void dev_set_link_down(portid_t pid);
787ce8d5614SIntel void init_port_config(void);
78841b05095SBernard Iremonger void set_port_slave_flag(portid_t slave_pid);
78941b05095SBernard Iremonger void clear_port_slave_flag(portid_t slave_pid);
7900e545d30SBernard Iremonger uint8_t port_is_bonding_slave(portid_t slave_pid);
7910e545d30SBernard Iremonger 
7921a572499SJingjing Wu int init_port_dcb_config(portid_t pid, enum dcb_mode_enable dcb_mode,
7931a572499SJingjing Wu 		     enum rte_eth_nb_tcs num_tcs,
7941a572499SJingjing Wu 		     uint8_t pfc_en);
795148f963fSBruce Richardson int start_port(portid_t pid);
796ce8d5614SIntel void stop_port(portid_t pid);
797ce8d5614SIntel void close_port(portid_t pid);
79897f1e196SWei Dai void reset_port(portid_t pid);
799edab33b1STetsuya Mukawa void attach_port(char *identifier);
80055e51c96SNithin Dabilpuram void detach_device(char *identifier);
801f8e5baa2SThomas Monjalon void detach_port_device(portid_t port_id);
802ce8d5614SIntel int all_ports_stopped(void);
8036018eb8cSShahaf Shuler int port_is_stopped(portid_t port_id);
8045f4ec54fSChen Jing D(Mark) int port_is_started(portid_t port_id);
805af75078fSIntel void pmd_test_exit(void);
806af75078fSIntel void fdir_get_infos(portid_t port_id);
807aeca06dfSJingjing Wu void fdir_set_flex_mask(portid_t port_id,
808aeca06dfSJingjing Wu 			   struct rte_eth_fdir_flex_mask *cfg);
80997b74464SJingjing Wu void fdir_set_flex_payload(portid_t port_id,
81097b74464SJingjing Wu 			   struct rte_eth_flex_payload_cfg *cfg);
81166c59490SHelin Zhang void port_rss_reta_info(portid_t port_id,
81266c59490SHelin Zhang 			struct rte_eth_rss_reta_entry64 *reta_conf,
81366c59490SHelin Zhang 			uint16_t nb_entries);
8146a18e1afSOuyang Changchun 
8157741e4cfSIntel void set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on);
816af75078fSIntel 
8176a18e1afSOuyang Changchun int set_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate);
8186a18e1afSOuyang Changchun int set_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate,
8196a18e1afSOuyang Changchun 				uint64_t q_msk);
8206a18e1afSOuyang Changchun 
8215b4557ecSFerruh Yigit void port_rss_hash_conf_show(portid_t port_id, int show_rss_key);
8228205e241SNelio Laranjeiro void port_rss_hash_key_update(portid_t port_id, char rss_type[],
8238205e241SNelio Laranjeiro 			      uint8_t *hash_key, uint hash_key_len);
8245f4ec54fSChen Jing D(Mark) int rx_queue_id_is_invalid(queueid_t rxq_id);
8255f4ec54fSChen Jing D(Mark) int tx_queue_id_is_invalid(queueid_t txq_id);
826b7091f1dSJiayu Hu void setup_gro(const char *onoff, portid_t port_id);
827b7091f1dSJiayu Hu void setup_gro_flush_cycles(uint8_t cycles);
828b7091f1dSJiayu Hu void show_gro(portid_t port_id);
82952f38a20SJiayu Hu void setup_gso(const char *mode, portid_t port_id);
8306f51deb9SIvan Ilchenko int eth_dev_info_get_print_err(uint16_t port_id,
8316f51deb9SIvan Ilchenko 			struct rte_eth_dev_info *dev_info);
83234fc1051SIvan Ilchenko void eth_set_promisc_mode(uint16_t port_id, int enable);
8338835806dSIvan Ilchenko void eth_set_allmulticast_mode(uint16_t port, int enable);
834e661a08bSIgor Romanov int eth_link_get_nowait_print_err(uint16_t port_id, struct rte_eth_link *link);
835a5279d25SIgor Romanov int eth_macaddr_get_print_err(uint16_t port_id,
836a5279d25SIgor Romanov 			struct rte_ether_addr *mac_addr);
8376f51deb9SIvan Ilchenko 
83816321de0SIvan Boule 
8398fff6675SIvan Boule /* Functions to manage the set of filtered Multicast MAC addresses */
8406d13ea8eSOlivier Matz void mcast_addr_add(portid_t port_id, struct rte_ether_addr *mc_addr);
8416d13ea8eSOlivier Matz void mcast_addr_remove(portid_t port_id, struct rte_ether_addr *mc_addr);
84228caa76aSZhiyong Yang void port_dcb_info_display(portid_t port_id);
8438fff6675SIvan Boule 
8449999dc6fSKirill Rybalchenko uint8_t *open_file(const char *file_path, uint32_t *size);
8459999dc6fSKirill Rybalchenko int save_file(const char *file_path, uint8_t *buf, uint32_t size);
8469999dc6fSKirill Rybalchenko int close_file(uint8_t *buf);
847a92a5a2cSBeilei Xing 
8483c272b28SWei Zhao void port_queue_region_info_display(portid_t port_id, void *buf);
8493c272b28SWei Zhao 
850edab33b1STetsuya Mukawa enum print_warning {
851edab33b1STetsuya Mukawa 	ENABLED_WARN = 0,
852edab33b1STetsuya Mukawa 	DISABLED_WARN
853edab33b1STetsuya Mukawa };
854edab33b1STetsuya Mukawa int port_id_is_invalid(portid_t port_id, enum print_warning warning);
8558f3c4176SMatan Azrad void print_valid_ports(void);
856c9cafcc8SShahaf Shuler int new_socket_id(unsigned int socket_id);
857edab33b1STetsuya Mukawa 
8583f7311baSWei Dai queueid_t get_allowed_max_nb_rxq(portid_t *pid);
8593f7311baSWei Dai int check_nb_rxq(queueid_t rxq);
86036db4f6cSWei Dai queueid_t get_allowed_max_nb_txq(portid_t *pid);
86136db4f6cSWei Dai int check_nb_txq(queueid_t txq);
8621c69df45SOri Kam queueid_t get_allowed_max_nb_hairpinq(portid_t *pid);
8631c69df45SOri Kam int check_nb_hairpinq(queueid_t hairpinq);
8643f7311baSWei Dai 
865c77ad9deSRaslan Darawsheh uint16_t dump_rx_pkts(uint16_t port_id, uint16_t queue, struct rte_mbuf *pkts[],
866c77ad9deSRaslan Darawsheh 		      uint16_t nb_pkts, __rte_unused uint16_t max_pkts,
867c77ad9deSRaslan Darawsheh 		      __rte_unused void *user_param);
868c77ad9deSRaslan Darawsheh 
869c77ad9deSRaslan Darawsheh uint16_t dump_tx_pkts(uint16_t port_id, uint16_t queue, struct rte_mbuf *pkts[],
870c77ad9deSRaslan Darawsheh 		      uint16_t nb_pkts, __rte_unused void *user_param);
871c77ad9deSRaslan Darawsheh 
872c77ad9deSRaslan Darawsheh void add_rx_dump_callbacks(portid_t portid);
873c77ad9deSRaslan Darawsheh void remove_rx_dump_callbacks(portid_t portid);
874c77ad9deSRaslan Darawsheh void add_tx_dump_callbacks(portid_t portid);
875c77ad9deSRaslan Darawsheh void remove_tx_dump_callbacks(portid_t portid);
876b5b38ed8SRaslan Darawsheh void configure_rxtx_dump_callbacks(uint16_t verbose);
877d862c45bSRaslan Darawsheh 
8781e45c908SDekel Peled uint16_t tx_pkt_set_md(uint16_t port_id, __rte_unused uint16_t queue,
8791e45c908SDekel Peled 		       struct rte_mbuf *pkts[], uint16_t nb_pkts,
8801e45c908SDekel Peled 		       __rte_unused void *user_param);
8811e45c908SDekel Peled void add_tx_md_callback(portid_t portid);
8821e45c908SDekel Peled void remove_tx_md_callback(portid_t portid);
8831e45c908SDekel Peled 
884af75078fSIntel /*
885af75078fSIntel  * Work-around of a compilation error with ICC on invocations of the
886af75078fSIntel  * rte_be_to_cpu_16() function.
887af75078fSIntel  */
888af75078fSIntel #ifdef __GCC__
889af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  rte_be_to_cpu_16((be_16_v))
890af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v))
891af75078fSIntel #else
89244eb9456SThomas Monjalon #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
893af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  (be_16_v)
894af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v)
895af75078fSIntel #else
896af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \
897af75078fSIntel 	(uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8))
898af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \
899af75078fSIntel 	(uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8))
900af75078fSIntel #endif
901af75078fSIntel #endif /* __GCC__ */
902af75078fSIntel 
903285fd101SOlivier Matz #define TESTPMD_LOG(level, fmt, args...) \
904285fd101SOlivier Matz 	rte_log(RTE_LOG_ ## level, testpmd_logtype, "testpmd: " fmt, ## args)
905285fd101SOlivier Matz 
906af75078fSIntel #endif /* _TESTPMD_H_ */
907