xref: /dpdk/app/test-pmd/testpmd.h (revision 1e8a4e97b057c2ec4350bfe2eeb67e1746e14568)
1174a1631SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
2174a1631SBruce Richardson  * Copyright(c) 2010-2017 Intel Corporation
3af75078fSIntel  */
4af75078fSIntel 
5af75078fSIntel #ifndef _TESTPMD_H_
6af75078fSIntel #define _TESTPMD_H_
7af75078fSIntel 
84f1ed78eSThomas Monjalon #include <stdbool.h>
94f1ed78eSThomas Monjalon 
1085c18dcbSGaetan Rivet #include <rte_pci.h>
11c752998bSGaetan Rivet #include <rte_bus_pci.h>
12b40f8d78SJiayu Hu #include <rte_gro.h>
1352f38a20SJiayu Hu #include <rte_gso.h>
1430626defSXiaoyu Min #include <cmdline.h>
1585c18dcbSGaetan Rivet 
16ce8d5614SIntel #define RTE_PORT_ALL            (~(portid_t)0x0)
17ce8d5614SIntel 
18ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX    2048
19ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX    2048
20ce8d5614SIntel 
21ce8d5614SIntel #define RTE_PORT_STOPPED        (uint16_t)0
22ce8d5614SIntel #define RTE_PORT_STARTED        (uint16_t)1
23ce8d5614SIntel #define RTE_PORT_CLOSED         (uint16_t)2
24ce8d5614SIntel #define RTE_PORT_HANDLING       (uint16_t)3
25ce8d5614SIntel 
26af75078fSIntel /*
270f6f219eSMohammad Abdul Awal  * It is used to allocate the memory for hash key.
280f6f219eSMohammad Abdul Awal  * The hash key size is NIC dependent.
290f6f219eSMohammad Abdul Awal  */
300f6f219eSMohammad Abdul Awal #define RSS_HASH_KEY_LENGTH 64
310f6f219eSMohammad Abdul Awal 
320f6f219eSMohammad Abdul Awal /*
33af75078fSIntel  * Default size of the mbuf data buffer to receive standard 1518-byte
34af75078fSIntel  * Ethernet frames in a mono-segment memory buffer.
35af75078fSIntel  */
36824cb29cSKonstantin Ananyev #define DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE
37824cb29cSKonstantin Ananyev /**< Default size of mbuf data buffer. */
38af75078fSIntel 
39af75078fSIntel /*
40af75078fSIntel  * The maximum number of segments per packet is used when creating
41af75078fSIntel  * scattered transmit packets composed of a list of mbufs.
42af75078fSIntel  */
43ea672a8bSOlivier Matz #define RTE_MAX_SEGS_PER_PKT 255 /**< nb_segs is a 8-bit unsigned char. */
44af75078fSIntel 
45af75078fSIntel #define MAX_PKT_BURST 512
46836853d3SCunming Liang #define DEF_PKT_BURST 32
47af75078fSIntel 
48e9378bbcSCunming Liang #define DEF_MBUF_CACHE 250
49e9378bbcSCunming Liang 
50fdf20fa7SSergio Gonzalez Monroy #define RTE_CACHE_LINE_SIZE_ROUNDUP(size) \
51fdf20fa7SSergio Gonzalez Monroy 	(RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))
52af75078fSIntel 
53b6ea6408SIntel #define NUMA_NO_CONFIG 0xFF
54b6ea6408SIntel #define UMA_NO_CONFIG  0xFF
55b6ea6408SIntel 
56af75078fSIntel typedef uint8_t  lcoreid_t;
57f8244c63SZhiyong Yang typedef uint16_t portid_t;
58af75078fSIntel typedef uint16_t queueid_t;
59af75078fSIntel typedef uint16_t streamid_t;
60af75078fSIntel 
610ad778b3SJasvinder Singh #if defined RTE_LIBRTE_PMD_SOFTNIC
620ad778b3SJasvinder Singh #define SOFTNIC			1
635b590fbeSJasvinder Singh #else
640ad778b3SJasvinder Singh #define SOFTNIC			0
655b590fbeSJasvinder Singh #endif
665b590fbeSJasvinder Singh 
67af75078fSIntel enum {
68af75078fSIntel 	PORT_TOPOLOGY_PAIRED,
693e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_CHAINED,
703e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_LOOP,
71af75078fSIntel };
72af75078fSIntel 
73c7f5dba7SAnatoly Burakov enum {
74c7f5dba7SAnatoly Burakov 	MP_ALLOC_NATIVE, /**< allocate and populate mempool natively */
75c7f5dba7SAnatoly Burakov 	MP_ALLOC_ANON,
76c7f5dba7SAnatoly Burakov 	/**< allocate mempool natively, but populate using anonymous memory */
77c7f5dba7SAnatoly Burakov 	MP_ALLOC_XMEM,
78c7f5dba7SAnatoly Burakov 	/**< allocate and populate mempool using anonymous memory */
79c7f5dba7SAnatoly Burakov 	MP_ALLOC_XMEM_HUGE
80c7f5dba7SAnatoly Burakov 	/**< allocate and populate mempool using anonymous hugepage memory */
81c7f5dba7SAnatoly Burakov };
82c7f5dba7SAnatoly Burakov 
83af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
84af75078fSIntel /**
85af75078fSIntel  * The data structure associated with RX and TX packet burst statistics
86af75078fSIntel  * that are recorded for each forwarding stream.
87af75078fSIntel  */
88af75078fSIntel struct pkt_burst_stats {
89af75078fSIntel 	unsigned int pkt_burst_spread[MAX_PKT_BURST];
90af75078fSIntel };
91af75078fSIntel #endif
92af75078fSIntel 
93f4d623f9SAdrien Mazarguil /** Information for a given RSS type. */
94f4d623f9SAdrien Mazarguil struct rss_type_info {
95f4d623f9SAdrien Mazarguil 	const char *str; /**< Type name. */
96f4d623f9SAdrien Mazarguil 	uint64_t rss_type; /**< Type value. */
97f4d623f9SAdrien Mazarguil };
98f4d623f9SAdrien Mazarguil 
99f4d623f9SAdrien Mazarguil /**
100f4d623f9SAdrien Mazarguil  * RSS type information table.
101f4d623f9SAdrien Mazarguil  *
102f4d623f9SAdrien Mazarguil  * An entry with a NULL type name terminates the list.
103f4d623f9SAdrien Mazarguil  */
104f4d623f9SAdrien Mazarguil extern const struct rss_type_info rss_type_table[];
105f4d623f9SAdrien Mazarguil 
106af75078fSIntel /**
107b57b66a9SOri Kam  * Dynf name array.
108b57b66a9SOri Kam  *
109b57b66a9SOri Kam  * Array that holds the name for each dynf.
110b57b66a9SOri Kam  */
111b57b66a9SOri Kam extern char dynf_names[64][RTE_MBUF_DYN_NAMESIZE];
112b57b66a9SOri Kam 
113b57b66a9SOri Kam /**
114af75078fSIntel  * The data structure associated with a forwarding stream between a receive
115af75078fSIntel  * port/queue and a transmit port/queue.
116af75078fSIntel  */
117af75078fSIntel struct fwd_stream {
118af75078fSIntel 	/* "read-only" data */
119af75078fSIntel 	portid_t   rx_port;   /**< port to poll for received packets */
120af75078fSIntel 	queueid_t  rx_queue;  /**< RX queue to poll on "rx_port" */
121af75078fSIntel 	portid_t   tx_port;   /**< forwarding port of received packets */
122af75078fSIntel 	queueid_t  tx_queue;  /**< TX queue to send forwarded packets */
123af75078fSIntel 	streamid_t peer_addr; /**< index of peer ethernet address of packets */
124af75078fSIntel 
125bf56fce1SZhihong Wang 	unsigned int retry_enabled;
126bf56fce1SZhihong Wang 
127af75078fSIntel 	/* "read-write" results */
128c185d42cSDavid Marchand 	uint64_t rx_packets;  /**< received packets */
129c185d42cSDavid Marchand 	uint64_t tx_packets;  /**< received packets transmitted */
130c185d42cSDavid Marchand 	uint64_t fwd_dropped; /**< received packets not forwarded */
131c185d42cSDavid Marchand 	uint64_t rx_bad_ip_csum ; /**< received packets has bad ip checksum */
132c185d42cSDavid Marchand 	uint64_t rx_bad_l4_csum ; /**< received packets has bad l4 checksum */
133c185d42cSDavid Marchand 	uint64_t rx_bad_outer_l4_csum;
13458d475b7SJerin Jacob 	/**< received packets has bad outer l4 checksum */
135b7091f1dSJiayu Hu 	unsigned int gro_times;	/**< GRO operation times */
136af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
137af75078fSIntel 	uint64_t     core_cycles; /**< used for RX and TX processing */
138af75078fSIntel #endif
139af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
140af75078fSIntel 	struct pkt_burst_stats rx_burst_stats;
141af75078fSIntel 	struct pkt_burst_stats tx_burst_stats;
142af75078fSIntel #endif
143af75078fSIntel };
144af75078fSIntel 
145938a184aSAdrien Mazarguil /** Descriptor for a single flow. */
146938a184aSAdrien Mazarguil struct port_flow {
147938a184aSAdrien Mazarguil 	struct port_flow *next; /**< Next flow in list. */
148938a184aSAdrien Mazarguil 	struct port_flow *tmp; /**< Temporary linking. */
149938a184aSAdrien Mazarguil 	uint32_t id; /**< Flow rule ID. */
150938a184aSAdrien Mazarguil 	struct rte_flow *flow; /**< Opaque flow object returned by PMD. */
15144b257ffSAdrien Mazarguil 	struct rte_flow_conv_rule rule; /* Saved flow rule description. */
15244b257ffSAdrien Mazarguil 	uint8_t data[]; /**< Storage for flow rule description */
153938a184aSAdrien Mazarguil };
154938a184aSAdrien Mazarguil 
1550ad778b3SJasvinder Singh #ifdef SOFTNIC
1565b590fbeSJasvinder Singh /**
1575b590fbeSJasvinder Singh  * The data structure associate with softnic port
1585b590fbeSJasvinder Singh  */
1595b590fbeSJasvinder Singh struct softnic_port {
1600ad778b3SJasvinder Singh 	uint32_t default_tm_hierarchy_enable; /**< default tm hierarchy */
1610ad778b3SJasvinder Singh 	struct fwd_lcore **fwd_lcore_arg; /**< softnic fwd core parameters */
1625b590fbeSJasvinder Singh };
1635b590fbeSJasvinder Singh #endif
1645b590fbeSJasvinder Singh 
165af75078fSIntel /**
166af75078fSIntel  * The data structure associated with each port.
167af75078fSIntel  */
168af75078fSIntel struct rte_port {
169af75078fSIntel 	struct rte_eth_dev_info dev_info;   /**< PCI info + driver name */
170af75078fSIntel 	struct rte_eth_conf     dev_conf;   /**< Port configuration. */
1716d13ea8eSOlivier Matz 	struct rte_ether_addr       eth_addr;   /**< Port ethernet address */
172af75078fSIntel 	struct rte_eth_stats    stats;      /**< Last port statistics */
173af75078fSIntel 	unsigned int            socket_id;  /**< For NUMA support */
1743eecba26SShahaf Shuler 	uint16_t		parse_tunnel:1; /**< Parse internal headers */
1750f62d635SJianfeng Tan 	uint16_t                tso_segsz;  /**< Segmentation offload MSS for non-tunneled packets. */
1760f62d635SJianfeng Tan 	uint16_t                tunnel_tso_segsz; /**< Segmentation offload MSS for tunneled pkts. */
17792ebda07SHelin Zhang 	uint16_t                tx_vlan_id;/**< The tag ID */
17892ebda07SHelin Zhang 	uint16_t                tx_vlan_id_outer;/**< The outer tag ID */
179ed30d9b6SIntel 	uint8_t                 tx_queue_stats_mapping_enabled;
180ed30d9b6SIntel 	uint8_t                 rx_queue_stats_mapping_enabled;
181ce8d5614SIntel 	volatile uint16_t        port_status;    /**< port started or not */
1824f1ed78eSThomas Monjalon 	uint8_t                 need_setup;     /**< port just attached */
183ce8d5614SIntel 	uint8_t                 need_reconfig;  /**< need reconfiguring port or not */
184ce8d5614SIntel 	uint8_t                 need_reconfig_queues; /**< need reconfiguring queues or not */
185ce8d5614SIntel 	uint8_t                 rss_flag;   /**< enable rss or not */
1867741e4cfSIntel 	uint8_t                 dcb_flag;   /**< enable dcb */
1879e6b36c3SDavid Marchand 	uint16_t                nb_rx_desc[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue rx desc number */
1889e6b36c3SDavid Marchand 	uint16_t                nb_tx_desc[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue tx desc number */
1899e6b36c3SDavid Marchand 	struct rte_eth_rxconf   rx_conf[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue rx configuration */
1909e6b36c3SDavid Marchand 	struct rte_eth_txconf   tx_conf[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue tx configuration */
1916d13ea8eSOlivier Matz 	struct rte_ether_addr   *mc_addr_pool; /**< pool of multicast addrs */
1928fff6675SIvan Boule 	uint32_t                mc_addr_nb; /**< nb. of addr. in mc_addr_pool */
19341b05095SBernard Iremonger 	uint8_t                 slave_flag; /**< bonding slave port */
194938a184aSAdrien Mazarguil 	struct port_flow        *flow_list; /**< Associated flows. */
1959e6b36c3SDavid Marchand 	const struct rte_eth_rxtx_callback *rx_dump_cb[RTE_MAX_QUEUES_PER_PORT+1];
1969e6b36c3SDavid Marchand 	const struct rte_eth_rxtx_callback *tx_dump_cb[RTE_MAX_QUEUES_PER_PORT+1];
1970ad778b3SJasvinder Singh #ifdef SOFTNIC
1980ad778b3SJasvinder Singh 	struct softnic_port     softport;  /**< softnic params */
1995b590fbeSJasvinder Singh #endif
200c18feafaSDekel Peled 	/**< metadata value to insert in Tx packets. */
2019bf26e13SViacheslav Ovsiienko 	uint32_t		tx_metadata;
2029e6b36c3SDavid Marchand 	const struct rte_eth_rxtx_callback *tx_set_md_cb[RTE_MAX_QUEUES_PER_PORT+1];
203b57b66a9SOri Kam 	/**< dynamic flags. */
204b57b66a9SOri Kam 	uint64_t		mbuf_dynf;
205b57b66a9SOri Kam 	const struct rte_eth_rxtx_callback *tx_set_dynf_cb[RTE_MAX_QUEUES_PER_PORT+1];
206af75078fSIntel };
207af75078fSIntel 
208af75078fSIntel /**
209af75078fSIntel  * The data structure associated with each forwarding logical core.
210af75078fSIntel  * The logical cores are internally numbered by a core index from 0 to
211af75078fSIntel  * the maximum number of logical cores - 1.
212af75078fSIntel  * The system CPU identifier of all logical cores are setup in a global
213af75078fSIntel  * CPU id. configuration table.
214af75078fSIntel  */
215af75078fSIntel struct fwd_lcore {
21652f38a20SJiayu Hu 	struct rte_gso_ctx gso_ctx;     /**< GSO context */
217af75078fSIntel 	struct rte_mempool *mbp; /**< The mbuf pool to use by this core */
218b7091f1dSJiayu Hu 	void *gro_ctx;		/**< GRO context */
219af75078fSIntel 	streamid_t stream_idx;   /**< index of 1st stream in "fwd_streams" */
220af75078fSIntel 	streamid_t stream_nb;    /**< number of streams in "fwd_streams" */
221af75078fSIntel 	lcoreid_t  cpuid_idx;    /**< index of logical core in CPU id table */
222af75078fSIntel 	queueid_t  tx_queue;     /**< TX queue to send forwarded packets */
223af75078fSIntel 	volatile char stopped;   /**< stop forwarding when set */
224af75078fSIntel };
225af75078fSIntel 
226af75078fSIntel /*
227af75078fSIntel  * Forwarding mode operations:
228af75078fSIntel  *   - IO forwarding mode (default mode)
229af75078fSIntel  *     Forwards packets unchanged.
230af75078fSIntel  *
231af75078fSIntel  *   - MAC forwarding mode
232af75078fSIntel  *     Set the source and the destination Ethernet addresses of packets
233af75078fSIntel  *     before forwarding them.
234af75078fSIntel  *
235af75078fSIntel  *   - IEEE1588 forwarding mode
236af75078fSIntel  *     Check that received IEEE1588 Precise Time Protocol (PTP) packets are
237af75078fSIntel  *     filtered and timestamped by the hardware.
238af75078fSIntel  *     Forwards packets unchanged on the same port.
239af75078fSIntel  *     Check that sent IEEE1588 PTP packets are timestamped by the hardware.
240af75078fSIntel  */
241af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi);
242af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi);
243af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs);
244af75078fSIntel 
245af75078fSIntel struct fwd_engine {
246af75078fSIntel 	const char       *fwd_mode_name; /**< Forwarding mode name. */
247af75078fSIntel 	port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */
248af75078fSIntel 	port_fwd_end_t   port_fwd_end;   /**< NULL if nothing special to do. */
249af75078fSIntel 	packet_fwd_t     packet_fwd;     /**< Mandatory. */
250af75078fSIntel };
251af75078fSIntel 
252bf56fce1SZhihong Wang #define BURST_TX_WAIT_US 1
253bf56fce1SZhihong Wang #define BURST_TX_RETRIES 64
254bf56fce1SZhihong Wang 
255bf56fce1SZhihong Wang extern uint32_t burst_tx_delay_time;
256bf56fce1SZhihong Wang extern uint32_t burst_tx_retry_num;
257bf56fce1SZhihong Wang 
258af75078fSIntel extern struct fwd_engine io_fwd_engine;
259af75078fSIntel extern struct fwd_engine mac_fwd_engine;
260d47388f1SCyril Chemparathy extern struct fwd_engine mac_swap_engine;
261e9e23a61SCyril Chemparathy extern struct fwd_engine flow_gen_engine;
262af75078fSIntel extern struct fwd_engine rx_only_engine;
263af75078fSIntel extern struct fwd_engine tx_only_engine;
264af75078fSIntel extern struct fwd_engine csum_fwd_engine;
265168dfa61SIvan Boule extern struct fwd_engine icmp_echo_engine;
2663c156061SJens Freimann extern struct fwd_engine noisy_vnf_engine;
2670ad778b3SJasvinder Singh #ifdef SOFTNIC
2680ad778b3SJasvinder Singh extern struct fwd_engine softnic_fwd_engine;
2695b590fbeSJasvinder Singh #endif
270af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588
271af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine;
272af75078fSIntel #endif
273af75078fSIntel 
274af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */
27530626defSXiaoyu Min extern cmdline_parse_inst_t cmd_set_raw;
276739e045bSXiaoyu Min extern cmdline_parse_inst_t cmd_show_set_raw;
277739e045bSXiaoyu Min extern cmdline_parse_inst_t cmd_show_set_raw_all;
278af75078fSIntel 
27959fcf854SShahaf Shuler extern uint16_t mempool_flags;
28059fcf854SShahaf Shuler 
281af75078fSIntel /**
282af75078fSIntel  * Forwarding Configuration
283af75078fSIntel  *
284af75078fSIntel  */
285af75078fSIntel struct fwd_config {
286af75078fSIntel 	struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */
287af75078fSIntel 	streamid_t nb_fwd_streams;  /**< Nb. of forward streams to process. */
288af75078fSIntel 	lcoreid_t  nb_fwd_lcores;   /**< Nb. of logical cores to launch. */
289af75078fSIntel 	portid_t   nb_fwd_ports;    /**< Nb. of ports involved. */
290af75078fSIntel };
291af75078fSIntel 
292900550deSIntel /**
293900550deSIntel  * DCB mode enable
294900550deSIntel  */
295900550deSIntel enum dcb_mode_enable
296900550deSIntel {
297900550deSIntel 	DCB_VT_ENABLED,
298900550deSIntel 	DCB_ENABLED
299900550deSIntel };
300900550deSIntel 
301ed30d9b6SIntel #define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */
302ed30d9b6SIntel #define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */
303ed30d9b6SIntel 
304ed30d9b6SIntel struct queue_stats_mappings {
305f8244c63SZhiyong Yang 	portid_t port_id;
306ed30d9b6SIntel 	uint16_t queue_id;
307ed30d9b6SIntel 	uint8_t stats_counter_id;
308ed30d9b6SIntel } __rte_cache_aligned;
309ed30d9b6SIntel 
310ed30d9b6SIntel extern struct queue_stats_mappings tx_queue_stats_mappings_array[];
311ed30d9b6SIntel extern struct queue_stats_mappings rx_queue_stats_mappings_array[];
312ed30d9b6SIntel 
313ed30d9b6SIntel /* Assign both tx and rx queue stats mappings to the same default values */
314ed30d9b6SIntel extern struct queue_stats_mappings *tx_queue_stats_mappings;
315ed30d9b6SIntel extern struct queue_stats_mappings *rx_queue_stats_mappings;
316ed30d9b6SIntel 
317ed30d9b6SIntel extern uint16_t nb_tx_queue_stats_mappings;
318ed30d9b6SIntel extern uint16_t nb_rx_queue_stats_mappings;
319ed30d9b6SIntel 
320a4fd5eeeSElza Mathew extern uint8_t xstats_hide_zero; /**< Hide zero values for xstats display */
321a4fd5eeeSElza Mathew 
322af75078fSIntel /* globals used for configuration */
323af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */
324285fd101SOlivier Matz extern int testpmd_logtype; /**< Log type for testpmd logs */
325af75078fSIntel extern uint8_t  interactive;
326ca7feb22SCyril Chemparathy extern uint8_t  auto_start;
32799cabef0SPablo de Lara extern uint8_t  tx_first;
32881ef862bSAllain Legacy extern char cmdline_filename[PATH_MAX]; /**< offline commands file */
329af75078fSIntel extern uint8_t  numa_support; /**< set by "--numa" parameter */
330af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */
3317741e4cfSIntel extern uint8_t no_flush_rx; /**<set by "--no-flush-rx" parameter */
3327ee3e944SVasily Philipov extern uint8_t flow_isolate_all; /**< set by "--flow-isolate-all */
333c7f5dba7SAnatoly Burakov extern uint8_t  mp_alloc_type;
334c7f5dba7SAnatoly Burakov /**< set by "--mp-anon" or "--mp-alloc" parameter */
335bc202406SDavid Marchand extern uint8_t no_link_check; /**<set by "--disable-link-check" parameter */
3366937d210SStephen Hemminger extern uint8_t no_device_start; /**<set by "--disable-device-start" parameter */
3372950a769SDeclan Doherty extern volatile int test_done; /* stop packet forwarding when set to 1. */
3388ea656f8SGaetan Rivet extern uint8_t lsc_interrupt; /**< disabled by "--no-lsc-interrupt" parameter */
339284c908cSGaetan Rivet extern uint8_t rmv_interrupt; /**< disabled by "--no-rmv-interrupt" parameter */
3403af72783SGaetan Rivet extern uint32_t event_print_mask;
3413af72783SGaetan Rivet /**< set by "--print-event xxxx" and "--mask-event xxxx parameters */
3424f1ed78eSThomas Monjalon extern bool setup_on_probe_event; /**< disabled by port setup-on iterator */
343e505d84cSAnatoly Burakov extern uint8_t hot_plug; /**< enable by "--hot-plug" parameter */
344e505d84cSAnatoly Burakov extern int do_mlockall; /**< set by "--mlockall" or "--no-mlockall" parameter */
345b0a9354aSPavan Nikhilesh extern uint8_t clear_ptypes; /**< disabled by set ptype cmd */
346af75078fSIntel 
347e261265eSRadu Nicolau #ifdef RTE_LIBRTE_IXGBE_BYPASS
3487b7e5ba7SIntel extern uint32_t bypass_timeout; /**< Store the NIC bypass watchdog timeout */
3497b7e5ba7SIntel #endif
3507b7e5ba7SIntel 
351b6ea6408SIntel /*
352b6ea6408SIntel  * Store specified sockets on which memory pool to be used by ports
353b6ea6408SIntel  * is allocated.
354b6ea6408SIntel  */
35563531389SGeorgios Katsikas extern uint8_t port_numa[RTE_MAX_ETHPORTS];
356b6ea6408SIntel 
357b6ea6408SIntel /*
358b6ea6408SIntel  * Store specified sockets on which RX ring to be used by ports
359b6ea6408SIntel  * is allocated.
360b6ea6408SIntel  */
36163531389SGeorgios Katsikas extern uint8_t rxring_numa[RTE_MAX_ETHPORTS];
362b6ea6408SIntel 
363b6ea6408SIntel /*
364b6ea6408SIntel  * Store specified sockets on which TX ring to be used by ports
365b6ea6408SIntel  * is allocated.
366b6ea6408SIntel  */
36763531389SGeorgios Katsikas extern uint8_t txring_numa[RTE_MAX_ETHPORTS];
368b6ea6408SIntel 
369b6ea6408SIntel extern uint8_t socket_num;
370b6ea6408SIntel 
371af75078fSIntel /*
372af75078fSIntel  * Configuration of logical cores:
373af75078fSIntel  * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores
374af75078fSIntel  */
375af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */
376af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */
377af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */
378af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE];
379c9cafcc8SShahaf Shuler extern unsigned int num_sockets;
380c9cafcc8SShahaf Shuler extern unsigned int socket_ids[RTE_MAX_NUMA_NODES];
381af75078fSIntel 
382af75078fSIntel /*
383af75078fSIntel  * Configuration of Ethernet ports:
384af75078fSIntel  * nb_fwd_ports <= nb_cfg_ports <= nb_ports
385af75078fSIntel  */
386af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */
387af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */
388af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */
389af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS];
390af75078fSIntel extern struct rte_port *ports;
391af75078fSIntel 
392af75078fSIntel extern struct rte_eth_rxmode rx_mode;
393fd8c20aaSShahaf Shuler extern struct rte_eth_txmode tx_mode;
394fd8c20aaSShahaf Shuler 
3958a387fa8SHelin Zhang extern uint64_t rss_hf;
396af75078fSIntel 
3971c69df45SOri Kam extern queueid_t nb_hairpinq;
398af75078fSIntel extern queueid_t nb_rxq;
399af75078fSIntel extern queueid_t nb_txq;
400af75078fSIntel 
401af75078fSIntel extern uint16_t nb_rxd;
402af75078fSIntel extern uint16_t nb_txd;
403af75078fSIntel 
404f2c5125aSPablo de Lara extern int16_t rx_free_thresh;
405f2c5125aSPablo de Lara extern int8_t rx_drop_en;
406f2c5125aSPablo de Lara extern int16_t tx_free_thresh;
407f2c5125aSPablo de Lara extern int16_t tx_rs_thresh;
408af75078fSIntel 
4093c156061SJens Freimann extern uint16_t noisy_tx_sw_bufsz;
4103c156061SJens Freimann extern uint16_t noisy_tx_sw_buf_flush_time;
4113c156061SJens Freimann extern uint64_t noisy_lkup_mem_sz;
4123c156061SJens Freimann extern uint64_t noisy_lkup_num_writes;
4133c156061SJens Freimann extern uint64_t noisy_lkup_num_reads;
4143c156061SJens Freimann extern uint64_t noisy_lkup_num_reads_writes;
4153c156061SJens Freimann 
416900550deSIntel extern uint8_t dcb_config;
417900550deSIntel extern uint8_t dcb_test;
418900550deSIntel 
419af75078fSIntel extern uint16_t mbuf_data_size; /**< Mbuf data space size. */
420c8798818SIntel extern uint32_t param_total_num_mbufs;
421af75078fSIntel 
422cfea1f30SPablo de Lara extern uint16_t stats_period;
42362d3216dSReshma Pattan 
42462d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS
42562d3216dSReshma Pattan extern uint8_t latencystats_enabled;
42662d3216dSReshma Pattan extern lcoreid_t latencystats_lcore_id;
42762d3216dSReshma Pattan #endif
42862d3216dSReshma Pattan 
429e25e6c70SRemy Horton #ifdef RTE_LIBRTE_BITRATE
430e25e6c70SRemy Horton extern lcoreid_t bitrate_lcore_id;
431e25e6c70SRemy Horton extern uint8_t bitrate_enabled;
432e25e6c70SRemy Horton #endif
433e25e6c70SRemy Horton 
434af75078fSIntel extern struct rte_fdir_conf fdir_conf;
435af75078fSIntel 
436af75078fSIntel /*
437af75078fSIntel  * Configuration of packet segments used by the "txonly" processing engine.
438af75078fSIntel  */
439af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64
440af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */
441af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */
442af75078fSIntel extern uint8_t  tx_pkt_nb_segs; /**< Number of segments in TX packets */
443af75078fSIntel 
44479bec05bSKonstantin Ananyev enum tx_pkt_split {
44579bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_OFF,
44679bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_ON,
44779bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_RND,
44879bec05bSKonstantin Ananyev };
44979bec05bSKonstantin Ananyev 
45079bec05bSKonstantin Ananyev extern enum tx_pkt_split tx_pkt_split;
45179bec05bSKonstantin Ananyev 
45282010ef5SYongseok Koh extern uint8_t txonly_multi_flow;
45382010ef5SYongseok Koh 
454af75078fSIntel extern uint16_t nb_pkt_per_burst;
455af75078fSIntel extern uint16_t mb_mempool_cache;
456f2c5125aSPablo de Lara extern int8_t rx_pthresh;
457f2c5125aSPablo de Lara extern int8_t rx_hthresh;
458f2c5125aSPablo de Lara extern int8_t rx_wthresh;
459f2c5125aSPablo de Lara extern int8_t tx_pthresh;
460f2c5125aSPablo de Lara extern int8_t tx_hthresh;
461f2c5125aSPablo de Lara extern int8_t tx_wthresh;
462af75078fSIntel 
463bf5b2126SStephen Hemminger extern uint16_t tx_udp_src_port;
464bf5b2126SStephen Hemminger extern uint16_t tx_udp_dst_port;
465bf5b2126SStephen Hemminger 
466bf5b2126SStephen Hemminger extern uint32_t tx_ip_src_addr;
467bf5b2126SStephen Hemminger extern uint32_t tx_ip_dst_addr;
468bf5b2126SStephen Hemminger 
469af75078fSIntel extern struct fwd_config cur_fwd_config;
470af75078fSIntel extern struct fwd_engine *cur_fwd_eng;
471bf56fce1SZhihong Wang extern uint32_t retry_enabled;
472af75078fSIntel extern struct fwd_lcore  **fwd_lcores;
473af75078fSIntel extern struct fwd_stream **fwd_streams;
474af75078fSIntel 
47539e5e20fSXueming Li extern uint16_t vxlan_gpe_udp_port; /**< UDP port of tunnel VXLAN-GPE. */
47639e5e20fSXueming Li 
477af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */
4786d13ea8eSOlivier Matz extern struct rte_ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS];
479af75078fSIntel 
48057e85242SBruce Richardson extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */
48157e85242SBruce Richardson extern uint32_t burst_tx_retry_num;  /**< Burst tx retry number for mac-retry. */
48257e85242SBruce Richardson 
483b7091f1dSJiayu Hu #define GRO_DEFAULT_ITEM_NUM_PER_FLOW 32
484b7091f1dSJiayu Hu #define GRO_DEFAULT_FLOW_NUM (RTE_GRO_MAX_BURST_ITEM_NUM / \
485b7091f1dSJiayu Hu 		GRO_DEFAULT_ITEM_NUM_PER_FLOW)
486b7091f1dSJiayu Hu 
487b7091f1dSJiayu Hu #define GRO_DEFAULT_FLUSH_CYCLES 1
488b7091f1dSJiayu Hu #define GRO_MAX_FLUSH_CYCLES 4
489b7091f1dSJiayu Hu 
490b40f8d78SJiayu Hu struct gro_status {
491b40f8d78SJiayu Hu 	struct rte_gro_param param;
492b40f8d78SJiayu Hu 	uint8_t enable;
493b40f8d78SJiayu Hu };
494b40f8d78SJiayu Hu extern struct gro_status gro_ports[RTE_MAX_ETHPORTS];
495b7091f1dSJiayu Hu extern uint8_t gro_flush_cycles;
496b40f8d78SJiayu Hu 
49752f38a20SJiayu Hu #define GSO_MAX_PKT_BURST 2048
49852f38a20SJiayu Hu struct gso_status {
49952f38a20SJiayu Hu 	uint8_t enable;
50052f38a20SJiayu Hu };
50152f38a20SJiayu Hu extern struct gso_status gso_ports[RTE_MAX_ETHPORTS];
50252f38a20SJiayu Hu extern uint16_t gso_max_segment_size;
50352f38a20SJiayu Hu 
5041960be7dSNelio Laranjeiro /* VXLAN encap/decap parameters. */
5051960be7dSNelio Laranjeiro struct vxlan_encap_conf {
5061960be7dSNelio Laranjeiro 	uint32_t select_ipv4:1;
5071960be7dSNelio Laranjeiro 	uint32_t select_vlan:1;
50862e8a5a8SViacheslav Ovsiienko 	uint32_t select_tos_ttl:1;
5091960be7dSNelio Laranjeiro 	uint8_t vni[3];
5101960be7dSNelio Laranjeiro 	rte_be16_t udp_src;
5111960be7dSNelio Laranjeiro 	rte_be16_t udp_dst;
5121960be7dSNelio Laranjeiro 	rte_be32_t ipv4_src;
5131960be7dSNelio Laranjeiro 	rte_be32_t ipv4_dst;
5141960be7dSNelio Laranjeiro 	uint8_t ipv6_src[16];
5151960be7dSNelio Laranjeiro 	uint8_t ipv6_dst[16];
5161960be7dSNelio Laranjeiro 	rte_be16_t vlan_tci;
51762e8a5a8SViacheslav Ovsiienko 	uint8_t ip_tos;
51862e8a5a8SViacheslav Ovsiienko 	uint8_t ip_ttl;
51935b2d13fSOlivier Matz 	uint8_t eth_src[RTE_ETHER_ADDR_LEN];
52035b2d13fSOlivier Matz 	uint8_t eth_dst[RTE_ETHER_ADDR_LEN];
5211960be7dSNelio Laranjeiro };
522f6e63e59SFerruh Yigit 
523f6e63e59SFerruh Yigit extern struct vxlan_encap_conf vxlan_encap_conf;
5241960be7dSNelio Laranjeiro 
525dcd962fcSNelio Laranjeiro /* NVGRE encap/decap parameters. */
526dcd962fcSNelio Laranjeiro struct nvgre_encap_conf {
527dcd962fcSNelio Laranjeiro 	uint32_t select_ipv4:1;
528dcd962fcSNelio Laranjeiro 	uint32_t select_vlan:1;
529dcd962fcSNelio Laranjeiro 	uint8_t tni[3];
530dcd962fcSNelio Laranjeiro 	rte_be32_t ipv4_src;
531dcd962fcSNelio Laranjeiro 	rte_be32_t ipv4_dst;
532dcd962fcSNelio Laranjeiro 	uint8_t ipv6_src[16];
533dcd962fcSNelio Laranjeiro 	uint8_t ipv6_dst[16];
534dcd962fcSNelio Laranjeiro 	rte_be16_t vlan_tci;
53535b2d13fSOlivier Matz 	uint8_t eth_src[RTE_ETHER_ADDR_LEN];
53635b2d13fSOlivier Matz 	uint8_t eth_dst[RTE_ETHER_ADDR_LEN];
537dcd962fcSNelio Laranjeiro };
538f6e63e59SFerruh Yigit 
539f6e63e59SFerruh Yigit extern struct nvgre_encap_conf nvgre_encap_conf;
540dcd962fcSNelio Laranjeiro 
541a1191d39SOri Kam /* L2 encap parameters. */
542a1191d39SOri Kam struct l2_encap_conf {
543a1191d39SOri Kam 	uint32_t select_ipv4:1;
544a1191d39SOri Kam 	uint32_t select_vlan:1;
545a1191d39SOri Kam 	rte_be16_t vlan_tci;
54635b2d13fSOlivier Matz 	uint8_t eth_src[RTE_ETHER_ADDR_LEN];
54735b2d13fSOlivier Matz 	uint8_t eth_dst[RTE_ETHER_ADDR_LEN];
548a1191d39SOri Kam };
549f6e63e59SFerruh Yigit extern struct l2_encap_conf l2_encap_conf;
550a1191d39SOri Kam 
551a1191d39SOri Kam /* L2 decap parameters. */
552a1191d39SOri Kam struct l2_decap_conf {
553a1191d39SOri Kam 	uint32_t select_vlan:1;
554a1191d39SOri Kam };
555f6e63e59SFerruh Yigit extern struct l2_decap_conf l2_decap_conf;
556a1191d39SOri Kam 
5573e77031bSOri Kam /* MPLSoGRE encap parameters. */
5583e77031bSOri Kam struct mplsogre_encap_conf {
5593e77031bSOri Kam 	uint32_t select_ipv4:1;
5603e77031bSOri Kam 	uint32_t select_vlan:1;
5613e77031bSOri Kam 	uint8_t label[3];
5623e77031bSOri Kam 	rte_be32_t ipv4_src;
5633e77031bSOri Kam 	rte_be32_t ipv4_dst;
5643e77031bSOri Kam 	uint8_t ipv6_src[16];
5653e77031bSOri Kam 	uint8_t ipv6_dst[16];
5663e77031bSOri Kam 	rte_be16_t vlan_tci;
56735b2d13fSOlivier Matz 	uint8_t eth_src[RTE_ETHER_ADDR_LEN];
56835b2d13fSOlivier Matz 	uint8_t eth_dst[RTE_ETHER_ADDR_LEN];
5693e77031bSOri Kam };
570f6e63e59SFerruh Yigit extern struct mplsogre_encap_conf mplsogre_encap_conf;
5713e77031bSOri Kam 
5723e77031bSOri Kam /* MPLSoGRE decap parameters. */
5733e77031bSOri Kam struct mplsogre_decap_conf {
5743e77031bSOri Kam 	uint32_t select_ipv4:1;
5753e77031bSOri Kam 	uint32_t select_vlan:1;
5763e77031bSOri Kam };
577f6e63e59SFerruh Yigit extern struct mplsogre_decap_conf mplsogre_decap_conf;
5783e77031bSOri Kam 
579a1191d39SOri Kam /* MPLSoUDP encap parameters. */
580a1191d39SOri Kam struct mplsoudp_encap_conf {
581a1191d39SOri Kam 	uint32_t select_ipv4:1;
582a1191d39SOri Kam 	uint32_t select_vlan:1;
583a1191d39SOri Kam 	uint8_t label[3];
584a1191d39SOri Kam 	rte_be16_t udp_src;
585a1191d39SOri Kam 	rte_be16_t udp_dst;
586a1191d39SOri Kam 	rte_be32_t ipv4_src;
587a1191d39SOri Kam 	rte_be32_t ipv4_dst;
588a1191d39SOri Kam 	uint8_t ipv6_src[16];
589a1191d39SOri Kam 	uint8_t ipv6_dst[16];
590a1191d39SOri Kam 	rte_be16_t vlan_tci;
59135b2d13fSOlivier Matz 	uint8_t eth_src[RTE_ETHER_ADDR_LEN];
59235b2d13fSOlivier Matz 	uint8_t eth_dst[RTE_ETHER_ADDR_LEN];
593a1191d39SOri Kam };
594f6e63e59SFerruh Yigit extern struct mplsoudp_encap_conf mplsoudp_encap_conf;
595a1191d39SOri Kam 
596a1191d39SOri Kam /* MPLSoUDP decap parameters. */
597a1191d39SOri Kam struct mplsoudp_decap_conf {
598a1191d39SOri Kam 	uint32_t select_ipv4:1;
599a1191d39SOri Kam 	uint32_t select_vlan:1;
600a1191d39SOri Kam };
601f6e63e59SFerruh Yigit extern struct mplsoudp_decap_conf mplsoudp_decap_conf;
602a1191d39SOri Kam 
603af75078fSIntel static inline unsigned int
604af75078fSIntel lcore_num(void)
605af75078fSIntel {
606af75078fSIntel 	unsigned int i;
607af75078fSIntel 
608af75078fSIntel 	for (i = 0; i < RTE_MAX_LCORE; ++i)
609af75078fSIntel 		if (fwd_lcores_cpuids[i] == rte_lcore_id())
610af75078fSIntel 			return i;
611af75078fSIntel 
612af75078fSIntel 	rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n");
613af75078fSIntel }
614af75078fSIntel 
615af75078fSIntel static inline struct fwd_lcore *
616af75078fSIntel current_fwd_lcore(void)
617af75078fSIntel {
618af75078fSIntel 	return fwd_lcores[lcore_num()];
619af75078fSIntel }
620af75078fSIntel 
621af75078fSIntel /* Mbuf Pools */
622af75078fSIntel static inline void
623af75078fSIntel mbuf_poolname_build(unsigned int sock_id, char* mp_name, int name_size)
624af75078fSIntel {
6256f41fe75SStephen Hemminger 	snprintf(mp_name, name_size, "mbuf_pool_socket_%u", sock_id);
626af75078fSIntel }
627af75078fSIntel 
628af75078fSIntel static inline struct rte_mempool *
629af75078fSIntel mbuf_pool_find(unsigned int sock_id)
630af75078fSIntel {
631af75078fSIntel 	char pool_name[RTE_MEMPOOL_NAMESIZE];
632af75078fSIntel 
633af75078fSIntel 	mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name));
634693f715dSHuawei Xie 	return rte_mempool_lookup((const char *)pool_name);
635af75078fSIntel }
636af75078fSIntel 
637af75078fSIntel /**
638af75078fSIntel  * Read/Write operations on a PCI register of a port.
639af75078fSIntel  */
640af75078fSIntel static inline uint32_t
641af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off)
642af75078fSIntel {
643cd8c7c7cSFerruh Yigit 	const struct rte_pci_device *pci_dev;
644cd8c7c7cSFerruh Yigit 	const struct rte_bus *bus;
645af75078fSIntel 	void *reg_addr;
646af75078fSIntel 	uint32_t reg_v;
647af75078fSIntel 
648cd8c7c7cSFerruh Yigit 	if (!port->dev_info.device) {
649cd8c7c7cSFerruh Yigit 		printf("Invalid device\n");
650cd8c7c7cSFerruh Yigit 		return 0;
651cd8c7c7cSFerruh Yigit 	}
652cd8c7c7cSFerruh Yigit 
653cd8c7c7cSFerruh Yigit 	bus = rte_bus_find_by_device(port->dev_info.device);
654cd8c7c7cSFerruh Yigit 	if (bus && !strcmp(bus->name, "pci")) {
655cd8c7c7cSFerruh Yigit 		pci_dev = RTE_DEV_TO_PCI(port->dev_info.device);
656cd8c7c7cSFerruh Yigit 	} else {
657cd8c7c7cSFerruh Yigit 		printf("Not a PCI device\n");
658cd8c7c7cSFerruh Yigit 		return 0;
659cd8c7c7cSFerruh Yigit 	}
660cd8c7c7cSFerruh Yigit 
661cd8c7c7cSFerruh Yigit 	reg_addr = ((char *)pci_dev->mem_resource[0].addr + reg_off);
662af75078fSIntel 	reg_v = *((volatile uint32_t *)reg_addr);
663af75078fSIntel 	return rte_le_to_cpu_32(reg_v);
664af75078fSIntel }
665af75078fSIntel 
666af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \
667af75078fSIntel 	port_pci_reg_read(&ports[(pt_id)], (reg_off))
668af75078fSIntel 
669af75078fSIntel static inline void
670af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v)
671af75078fSIntel {
672cd8c7c7cSFerruh Yigit 	const struct rte_pci_device *pci_dev;
673cd8c7c7cSFerruh Yigit 	const struct rte_bus *bus;
674af75078fSIntel 	void *reg_addr;
675af75078fSIntel 
676cd8c7c7cSFerruh Yigit 	if (!port->dev_info.device) {
677cd8c7c7cSFerruh Yigit 		printf("Invalid device\n");
678cd8c7c7cSFerruh Yigit 		return;
679cd8c7c7cSFerruh Yigit 	}
680cd8c7c7cSFerruh Yigit 
681cd8c7c7cSFerruh Yigit 	bus = rte_bus_find_by_device(port->dev_info.device);
682cd8c7c7cSFerruh Yigit 	if (bus && !strcmp(bus->name, "pci")) {
683cd8c7c7cSFerruh Yigit 		pci_dev = RTE_DEV_TO_PCI(port->dev_info.device);
684cd8c7c7cSFerruh Yigit 	} else {
685cd8c7c7cSFerruh Yigit 		printf("Not a PCI device\n");
686cd8c7c7cSFerruh Yigit 		return;
687cd8c7c7cSFerruh Yigit 	}
688cd8c7c7cSFerruh Yigit 
689cd8c7c7cSFerruh Yigit 	reg_addr = ((char *)pci_dev->mem_resource[0].addr + reg_off);
690af75078fSIntel 	*((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v);
691af75078fSIntel }
692af75078fSIntel 
693af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \
694af75078fSIntel 	port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value))
695af75078fSIntel 
696af75078fSIntel /* Prototypes */
697950d1516SBruce Richardson unsigned int parse_item_list(char* str, const char* item_name,
698950d1516SBruce Richardson 			unsigned int max_items,
699950d1516SBruce Richardson 			unsigned int *parsed_items, int check_unique_values);
700af75078fSIntel void launch_args_parse(int argc, char** argv);
70181ef862bSAllain Legacy void cmdline_read_from_file(const char *filename);
702af75078fSIntel void prompt(void);
703d3a274ceSZhihong Wang void prompt_exit(void);
704af75078fSIntel void nic_stats_display(portid_t port_id);
705af75078fSIntel void nic_stats_clear(portid_t port_id);
706bfd5051bSOlivier Matz void nic_xstats_display(portid_t port_id);
707bfd5051bSOlivier Matz void nic_xstats_clear(portid_t port_id);
708ed30d9b6SIntel void nic_stats_mapping_display(portid_t port_id);
70955e51c96SNithin Dabilpuram void device_infos_display(const char *identifier);
710af75078fSIntel void port_infos_display(portid_t port_id);
7114bfcbcf5SEmma Finn void port_summary_display(portid_t port_id);
7124bfcbcf5SEmma Finn void port_summary_header_display(void);
713d28645c7SQiming Yang void port_offload_cap_display(portid_t port_id);
714ab3257e1SKonstantin Ananyev void rx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
715ab3257e1SKonstantin Ananyev void tx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
716af75078fSIntel void fwd_lcores_config_display(void);
7170c0db76fSBernard Iremonger void pkt_fwd_config_display(struct fwd_config *cfg);
718af75078fSIntel void rxtx_config_display(void);
719af75078fSIntel void fwd_config_setup(void);
720af75078fSIntel void set_def_fwd_config(void);
721a21d5a4bSDeclan Doherty void reconfig(portid_t new_port_id, unsigned socket_id);
722013af9b6SIntel int init_fwd_streams(void);
72303ce2c53SMatan Azrad void update_fwd_ports(portid_t new_pid);
724013af9b6SIntel 
725aac6f11fSWisam Jaddo void set_fwd_eth_peer(portid_t port_id, char *peer_addr);
726aac6f11fSWisam Jaddo 
727ae03d0d1SIvan Boule void port_mtu_set(portid_t port_id, uint16_t mtu);
728af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos);
729af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos,
730af75078fSIntel 		      uint8_t bit_v);
731af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off,
732af75078fSIntel 				uint8_t bit1_pos, uint8_t bit2_pos);
733af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off,
734af75078fSIntel 			    uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value);
735af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off);
736af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value);
737938a184aSAdrien Mazarguil int port_flow_validate(portid_t port_id,
738938a184aSAdrien Mazarguil 		       const struct rte_flow_attr *attr,
739938a184aSAdrien Mazarguil 		       const struct rte_flow_item *pattern,
740938a184aSAdrien Mazarguil 		       const struct rte_flow_action *actions);
741938a184aSAdrien Mazarguil int port_flow_create(portid_t port_id,
742938a184aSAdrien Mazarguil 		     const struct rte_flow_attr *attr,
743938a184aSAdrien Mazarguil 		     const struct rte_flow_item *pattern,
744938a184aSAdrien Mazarguil 		     const struct rte_flow_action *actions);
745938a184aSAdrien Mazarguil int port_flow_destroy(portid_t port_id, uint32_t n, const uint32_t *rule);
746938a184aSAdrien Mazarguil int port_flow_flush(portid_t port_id);
747*1e8a4e97SXueming Li int port_flow_dump(portid_t port_id, const char *file_name);
748938a184aSAdrien Mazarguil int port_flow_query(portid_t port_id, uint32_t rule,
749fb8fd96dSDeclan Doherty 		    const struct rte_flow_action *action);
750938a184aSAdrien Mazarguil void port_flow_list(portid_t port_id, uint32_t n, const uint32_t *group);
751323f811aSAdrien Mazarguil int port_flow_isolate(portid_t port_id, int set);
752af75078fSIntel 
753af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id);
754af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id);
755af75078fSIntel 
756013af9b6SIntel int set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc);
757013af9b6SIntel int set_fwd_lcores_mask(uint64_t lcoremask);
758af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc);
759af75078fSIntel 
760af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt);
761af75078fSIntel void set_fwd_ports_mask(uint64_t portmask);
762af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt);
763a8ef3e3aSBernard Iremonger int port_is_forwarding(portid_t port_id);
764af75078fSIntel 
765a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on);
766a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on);
767a47aa8b9SIntel 
768a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on);
769af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on);
7702a0b4198SVivek Sharma void rx_vlan_qinq_strip_set(portid_t port_id, int on);
77164b01ee0SMichal Jastrzebski int rx_vft_set(portid_t port_id, uint16_t vlan_id, int on);
772a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on);
77319b16e2fSHelin Zhang void vlan_tpid_set(portid_t port_id, enum rte_vlan_type vlan_type,
77419b16e2fSHelin Zhang 		   uint16_t tp_id);
775af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id);
77692ebda07SHelin Zhang void tx_qinq_set(portid_t port_id, uint16_t vlan_id, uint16_t vlan_id_outer);
777af75078fSIntel void tx_vlan_reset(portid_t port_id);
778529ba951SHelin Zhang void tx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on);
779ed30d9b6SIntel 
780ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value);
781ed30d9b6SIntel 
782a4fd5eeeSElza Mathew void set_xstats_hide_zero(uint8_t on_off);
783a4fd5eeeSElza Mathew 
784af75078fSIntel void set_verbose_level(uint16_t vb_level);
785af75078fSIntel void set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs);
78679bec05bSKonstantin Ananyev void show_tx_pkt_segments(void);
78779bec05bSKonstantin Ananyev void set_tx_pkt_split(const char *name);
788af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst);
789769ce6b1SThomas Monjalon char *list_pkt_forwarding_modes(void);
790bf56fce1SZhihong Wang char *list_pkt_forwarding_retry_modes(void);
791af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode);
792af75078fSIntel void start_packet_forwarding(int with_tx_first);
79353324971SDavid Marchand void fwd_stats_display(void);
79453324971SDavid Marchand void fwd_stats_reset(void);
795af75078fSIntel void stop_packet_forwarding(void);
796cfae07fdSOuyang Changchun void dev_set_link_up(portid_t pid);
797cfae07fdSOuyang Changchun void dev_set_link_down(portid_t pid);
798ce8d5614SIntel void init_port_config(void);
79941b05095SBernard Iremonger void set_port_slave_flag(portid_t slave_pid);
80041b05095SBernard Iremonger void clear_port_slave_flag(portid_t slave_pid);
8010e545d30SBernard Iremonger uint8_t port_is_bonding_slave(portid_t slave_pid);
8020e545d30SBernard Iremonger 
8031a572499SJingjing Wu int init_port_dcb_config(portid_t pid, enum dcb_mode_enable dcb_mode,
8041a572499SJingjing Wu 		     enum rte_eth_nb_tcs num_tcs,
8051a572499SJingjing Wu 		     uint8_t pfc_en);
806148f963fSBruce Richardson int start_port(portid_t pid);
807ce8d5614SIntel void stop_port(portid_t pid);
808ce8d5614SIntel void close_port(portid_t pid);
80997f1e196SWei Dai void reset_port(portid_t pid);
810edab33b1STetsuya Mukawa void attach_port(char *identifier);
81155e51c96SNithin Dabilpuram void detach_device(char *identifier);
812f8e5baa2SThomas Monjalon void detach_port_device(portid_t port_id);
813ce8d5614SIntel int all_ports_stopped(void);
8146018eb8cSShahaf Shuler int port_is_stopped(portid_t port_id);
8155f4ec54fSChen Jing D(Mark) int port_is_started(portid_t port_id);
816af75078fSIntel void pmd_test_exit(void);
817af75078fSIntel void fdir_get_infos(portid_t port_id);
818aeca06dfSJingjing Wu void fdir_set_flex_mask(portid_t port_id,
819aeca06dfSJingjing Wu 			   struct rte_eth_fdir_flex_mask *cfg);
82097b74464SJingjing Wu void fdir_set_flex_payload(portid_t port_id,
82197b74464SJingjing Wu 			   struct rte_eth_flex_payload_cfg *cfg);
82266c59490SHelin Zhang void port_rss_reta_info(portid_t port_id,
82366c59490SHelin Zhang 			struct rte_eth_rss_reta_entry64 *reta_conf,
82466c59490SHelin Zhang 			uint16_t nb_entries);
8256a18e1afSOuyang Changchun 
8267741e4cfSIntel void set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on);
827af75078fSIntel 
8286a18e1afSOuyang Changchun int set_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate);
8296a18e1afSOuyang Changchun int set_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate,
8306a18e1afSOuyang Changchun 				uint64_t q_msk);
8316a18e1afSOuyang Changchun 
8325b4557ecSFerruh Yigit void port_rss_hash_conf_show(portid_t port_id, int show_rss_key);
8338205e241SNelio Laranjeiro void port_rss_hash_key_update(portid_t port_id, char rss_type[],
8348205e241SNelio Laranjeiro 			      uint8_t *hash_key, uint hash_key_len);
8355f4ec54fSChen Jing D(Mark) int rx_queue_id_is_invalid(queueid_t rxq_id);
8365f4ec54fSChen Jing D(Mark) int tx_queue_id_is_invalid(queueid_t txq_id);
837b7091f1dSJiayu Hu void setup_gro(const char *onoff, portid_t port_id);
838b7091f1dSJiayu Hu void setup_gro_flush_cycles(uint8_t cycles);
839b7091f1dSJiayu Hu void show_gro(portid_t port_id);
84052f38a20SJiayu Hu void setup_gso(const char *mode, portid_t port_id);
8416f51deb9SIvan Ilchenko int eth_dev_info_get_print_err(uint16_t port_id,
8426f51deb9SIvan Ilchenko 			struct rte_eth_dev_info *dev_info);
84334fc1051SIvan Ilchenko void eth_set_promisc_mode(uint16_t port_id, int enable);
8448835806dSIvan Ilchenko void eth_set_allmulticast_mode(uint16_t port, int enable);
845e661a08bSIgor Romanov int eth_link_get_nowait_print_err(uint16_t port_id, struct rte_eth_link *link);
846a5279d25SIgor Romanov int eth_macaddr_get_print_err(uint16_t port_id,
847a5279d25SIgor Romanov 			struct rte_ether_addr *mac_addr);
8486f51deb9SIvan Ilchenko 
849e1d44d0aSKalesh AP /* Functions to display the set of MAC addresses added to a port*/
850e1d44d0aSKalesh AP void show_macs(portid_t port_id);
851e1d44d0aSKalesh AP void show_mcast_macs(portid_t port_id);
85216321de0SIvan Boule 
8538fff6675SIvan Boule /* Functions to manage the set of filtered Multicast MAC addresses */
8546d13ea8eSOlivier Matz void mcast_addr_add(portid_t port_id, struct rte_ether_addr *mc_addr);
8556d13ea8eSOlivier Matz void mcast_addr_remove(portid_t port_id, struct rte_ether_addr *mc_addr);
85628caa76aSZhiyong Yang void port_dcb_info_display(portid_t port_id);
8578fff6675SIvan Boule 
8589999dc6fSKirill Rybalchenko uint8_t *open_file(const char *file_path, uint32_t *size);
8599999dc6fSKirill Rybalchenko int save_file(const char *file_path, uint8_t *buf, uint32_t size);
8609999dc6fSKirill Rybalchenko int close_file(uint8_t *buf);
861a92a5a2cSBeilei Xing 
8623c272b28SWei Zhao void port_queue_region_info_display(portid_t port_id, void *buf);
8633c272b28SWei Zhao 
864edab33b1STetsuya Mukawa enum print_warning {
865edab33b1STetsuya Mukawa 	ENABLED_WARN = 0,
866edab33b1STetsuya Mukawa 	DISABLED_WARN
867edab33b1STetsuya Mukawa };
868edab33b1STetsuya Mukawa int port_id_is_invalid(portid_t port_id, enum print_warning warning);
8698f3c4176SMatan Azrad void print_valid_ports(void);
870c9cafcc8SShahaf Shuler int new_socket_id(unsigned int socket_id);
871edab33b1STetsuya Mukawa 
8723f7311baSWei Dai queueid_t get_allowed_max_nb_rxq(portid_t *pid);
8733f7311baSWei Dai int check_nb_rxq(queueid_t rxq);
87436db4f6cSWei Dai queueid_t get_allowed_max_nb_txq(portid_t *pid);
87536db4f6cSWei Dai int check_nb_txq(queueid_t txq);
8761c69df45SOri Kam queueid_t get_allowed_max_nb_hairpinq(portid_t *pid);
8771c69df45SOri Kam int check_nb_hairpinq(queueid_t hairpinq);
8783f7311baSWei Dai 
879c77ad9deSRaslan Darawsheh uint16_t dump_rx_pkts(uint16_t port_id, uint16_t queue, struct rte_mbuf *pkts[],
880c77ad9deSRaslan Darawsheh 		      uint16_t nb_pkts, __rte_unused uint16_t max_pkts,
881c77ad9deSRaslan Darawsheh 		      __rte_unused void *user_param);
882c77ad9deSRaslan Darawsheh 
883c77ad9deSRaslan Darawsheh uint16_t dump_tx_pkts(uint16_t port_id, uint16_t queue, struct rte_mbuf *pkts[],
884c77ad9deSRaslan Darawsheh 		      uint16_t nb_pkts, __rte_unused void *user_param);
885c77ad9deSRaslan Darawsheh 
886c77ad9deSRaslan Darawsheh void add_rx_dump_callbacks(portid_t portid);
887c77ad9deSRaslan Darawsheh void remove_rx_dump_callbacks(portid_t portid);
888c77ad9deSRaslan Darawsheh void add_tx_dump_callbacks(portid_t portid);
889c77ad9deSRaslan Darawsheh void remove_tx_dump_callbacks(portid_t portid);
890b5b38ed8SRaslan Darawsheh void configure_rxtx_dump_callbacks(uint16_t verbose);
891d862c45bSRaslan Darawsheh 
8921e45c908SDekel Peled uint16_t tx_pkt_set_md(uint16_t port_id, __rte_unused uint16_t queue,
8931e45c908SDekel Peled 		       struct rte_mbuf *pkts[], uint16_t nb_pkts,
8941e45c908SDekel Peled 		       __rte_unused void *user_param);
8951e45c908SDekel Peled void add_tx_md_callback(portid_t portid);
8961e45c908SDekel Peled void remove_tx_md_callback(portid_t portid);
8971e45c908SDekel Peled 
898b57b66a9SOri Kam uint16_t tx_pkt_set_dynf(uint16_t port_id, __rte_unused uint16_t queue,
899b57b66a9SOri Kam 			 struct rte_mbuf *pkts[], uint16_t nb_pkts,
900b57b66a9SOri Kam 			 __rte_unused void *user_param);
901b57b66a9SOri Kam void add_tx_dynf_callback(portid_t portid);
902b57b66a9SOri Kam void remove_tx_dynf_callback(portid_t portid);
903b57b66a9SOri Kam 
904af75078fSIntel /*
905af75078fSIntel  * Work-around of a compilation error with ICC on invocations of the
906af75078fSIntel  * rte_be_to_cpu_16() function.
907af75078fSIntel  */
908af75078fSIntel #ifdef __GCC__
909af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  rte_be_to_cpu_16((be_16_v))
910af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v))
911af75078fSIntel #else
91244eb9456SThomas Monjalon #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
913af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  (be_16_v)
914af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v)
915af75078fSIntel #else
916af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \
917af75078fSIntel 	(uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8))
918af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \
919af75078fSIntel 	(uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8))
920af75078fSIntel #endif
921af75078fSIntel #endif /* __GCC__ */
922af75078fSIntel 
923285fd101SOlivier Matz #define TESTPMD_LOG(level, fmt, args...) \
924285fd101SOlivier Matz 	rte_log(RTE_LOG_ ## level, testpmd_logtype, "testpmd: " fmt, ## args)
925285fd101SOlivier Matz 
926af75078fSIntel #endif /* _TESTPMD_H_ */
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