xref: /dpdk/app/test-pmd/testpmd.h (revision 0e545d3047fe930d7792e159dc92df97c2fdfb1c)
1af75078fSIntel /*-
2af75078fSIntel  *   BSD LICENSE
3af75078fSIntel  *
4a8ef3e3aSBernard Iremonger  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
5af75078fSIntel  *   All rights reserved.
6af75078fSIntel  *
7af75078fSIntel  *   Redistribution and use in source and binary forms, with or without
8af75078fSIntel  *   modification, are permitted provided that the following conditions
9af75078fSIntel  *   are met:
10af75078fSIntel  *
11af75078fSIntel  *     * Redistributions of source code must retain the above copyright
12af75078fSIntel  *       notice, this list of conditions and the following disclaimer.
13af75078fSIntel  *     * Redistributions in binary form must reproduce the above copyright
14af75078fSIntel  *       notice, this list of conditions and the following disclaimer in
15af75078fSIntel  *       the documentation and/or other materials provided with the
16af75078fSIntel  *       distribution.
17af75078fSIntel  *     * Neither the name of Intel Corporation nor the names of its
18af75078fSIntel  *       contributors may be used to endorse or promote products derived
19af75078fSIntel  *       from this software without specific prior written permission.
20af75078fSIntel  *
21af75078fSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22af75078fSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23af75078fSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24af75078fSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25af75078fSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26af75078fSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27af75078fSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28af75078fSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29af75078fSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30af75078fSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31af75078fSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32af75078fSIntel  */
33af75078fSIntel 
34af75078fSIntel #ifndef _TESTPMD_H_
35af75078fSIntel #define _TESTPMD_H_
36af75078fSIntel 
37ce8d5614SIntel #define RTE_PORT_ALL            (~(portid_t)0x0)
38ce8d5614SIntel 
39ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX    2048
40ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX    2048
41ce8d5614SIntel 
42ce8d5614SIntel #define RTE_PORT_STOPPED        (uint16_t)0
43ce8d5614SIntel #define RTE_PORT_STARTED        (uint16_t)1
44ce8d5614SIntel #define RTE_PORT_CLOSED         (uint16_t)2
45ce8d5614SIntel #define RTE_PORT_HANDLING       (uint16_t)3
46ce8d5614SIntel 
47af75078fSIntel /*
48af75078fSIntel  * Default size of the mbuf data buffer to receive standard 1518-byte
49af75078fSIntel  * Ethernet frames in a mono-segment memory buffer.
50af75078fSIntel  */
51824cb29cSKonstantin Ananyev #define DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE
52824cb29cSKonstantin Ananyev /**< Default size of mbuf data buffer. */
53af75078fSIntel 
54af75078fSIntel /*
55af75078fSIntel  * The maximum number of segments per packet is used when creating
56af75078fSIntel  * scattered transmit packets composed of a list of mbufs.
57af75078fSIntel  */
58ea672a8bSOlivier Matz #define RTE_MAX_SEGS_PER_PKT 255 /**< nb_segs is a 8-bit unsigned char. */
59af75078fSIntel 
60af75078fSIntel #define MAX_PKT_BURST 512
61836853d3SCunming Liang #define DEF_PKT_BURST 32
62af75078fSIntel 
63e9378bbcSCunming Liang #define DEF_MBUF_CACHE 250
64e9378bbcSCunming Liang 
65fdf20fa7SSergio Gonzalez Monroy #define RTE_CACHE_LINE_SIZE_ROUNDUP(size) \
66fdf20fa7SSergio Gonzalez Monroy 	(RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))
67af75078fSIntel 
68b6ea6408SIntel #define NUMA_NO_CONFIG 0xFF
69b6ea6408SIntel #define UMA_NO_CONFIG  0xFF
70b6ea6408SIntel 
71af75078fSIntel typedef uint8_t  lcoreid_t;
72af75078fSIntel typedef uint8_t  portid_t;
73af75078fSIntel typedef uint16_t queueid_t;
74af75078fSIntel typedef uint16_t streamid_t;
75af75078fSIntel 
76af75078fSIntel #define MAX_QUEUE_ID ((1 << (sizeof(queueid_t) * 8)) - 1)
77af75078fSIntel 
78af75078fSIntel enum {
79af75078fSIntel 	PORT_TOPOLOGY_PAIRED,
803e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_CHAINED,
813e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_LOOP,
82af75078fSIntel };
83af75078fSIntel 
84af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
85af75078fSIntel /**
86af75078fSIntel  * The data structure associated with RX and TX packet burst statistics
87af75078fSIntel  * that are recorded for each forwarding stream.
88af75078fSIntel  */
89af75078fSIntel struct pkt_burst_stats {
90af75078fSIntel 	unsigned int pkt_burst_spread[MAX_PKT_BURST];
91af75078fSIntel };
92af75078fSIntel #endif
93af75078fSIntel 
94af75078fSIntel /**
95af75078fSIntel  * The data structure associated with a forwarding stream between a receive
96af75078fSIntel  * port/queue and a transmit port/queue.
97af75078fSIntel  */
98af75078fSIntel struct fwd_stream {
99af75078fSIntel 	/* "read-only" data */
100af75078fSIntel 	portid_t   rx_port;   /**< port to poll for received packets */
101af75078fSIntel 	queueid_t  rx_queue;  /**< RX queue to poll on "rx_port" */
102af75078fSIntel 	portid_t   tx_port;   /**< forwarding port of received packets */
103af75078fSIntel 	queueid_t  tx_queue;  /**< TX queue to send forwarded packets */
104af75078fSIntel 	streamid_t peer_addr; /**< index of peer ethernet address of packets */
105af75078fSIntel 
106af75078fSIntel 	/* "read-write" results */
107af75078fSIntel 	unsigned int rx_packets;  /**< received packets */
108af75078fSIntel 	unsigned int tx_packets;  /**< received packets transmitted */
109af75078fSIntel 	unsigned int fwd_dropped; /**< received packets not forwarded */
110af75078fSIntel 	unsigned int rx_bad_ip_csum ; /**< received packets has bad ip checksum */
111af75078fSIntel 	unsigned int rx_bad_l4_csum ; /**< received packets has bad l4 checksum */
112af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
113af75078fSIntel 	uint64_t     core_cycles; /**< used for RX and TX processing */
114af75078fSIntel #endif
115af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
116af75078fSIntel 	struct pkt_burst_stats rx_burst_stats;
117af75078fSIntel 	struct pkt_burst_stats tx_burst_stats;
118af75078fSIntel #endif
119af75078fSIntel };
120af75078fSIntel 
121cf543fdbSOlivier Matz /** Offload IP checksum in csum forward engine */
122cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_IP_CKSUM          0x0001
123cf543fdbSOlivier Matz /** Offload UDP checksum in csum forward engine */
124cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_UDP_CKSUM         0x0002
125cf543fdbSOlivier Matz /** Offload TCP checksum in csum forward engine */
126cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_TCP_CKSUM         0x0004
127cf543fdbSOlivier Matz /** Offload SCTP checksum in csum forward engine */
128cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_SCTP_CKSUM        0x0008
1293994a3e8SOlivier Matz /** Offload outer IP checksum in csum forward engine for recognized tunnels */
1303994a3e8SOlivier Matz #define TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM    0x0010
13164fc3606SOlivier Matz /** Parse tunnel in csum forward engine. If set, dissect tunnel headers
13264fc3606SOlivier Matz  * of rx packets. If not set, treat inner headers as payload. */
13364fc3606SOlivier Matz #define TESTPMD_TX_OFFLOAD_PARSE_TUNNEL      0x0020
134cf543fdbSOlivier Matz /** Insert VLAN header in forward engine */
13564fc3606SOlivier Matz #define TESTPMD_TX_OFFLOAD_INSERT_VLAN       0x0040
13692ebda07SHelin Zhang /** Insert double VLAN header in forward engine */
13792ebda07SHelin Zhang #define TESTPMD_TX_OFFLOAD_INSERT_QINQ       0x0080
13851f694ddSOlivier Matz 
139af75078fSIntel /**
140af75078fSIntel  * The data structure associated with each port.
141af75078fSIntel  */
142af75078fSIntel struct rte_port {
143edab33b1STetsuya Mukawa 	uint8_t                 enabled;    /**< Port enabled or not */
144af75078fSIntel 	struct rte_eth_dev_info dev_info;   /**< PCI info + driver name */
145af75078fSIntel 	struct rte_eth_conf     dev_conf;   /**< Port configuration. */
146af75078fSIntel 	struct ether_addr       eth_addr;   /**< Port ethernet address */
147af75078fSIntel 	struct rte_eth_stats    stats;      /**< Last port statistics */
148af75078fSIntel 	uint64_t                tx_dropped; /**< If no descriptor in TX ring */
149af75078fSIntel 	struct fwd_stream       *rx_stream; /**< Port RX stream, if unique */
150af75078fSIntel 	struct fwd_stream       *tx_stream; /**< Port TX stream, if unique */
151af75078fSIntel 	unsigned int            socket_id;  /**< For NUMA support */
152cf543fdbSOlivier Matz 	uint16_t                tx_ol_flags;/**< TX Offload Flags (TESTPMD_TX_OFFLOAD...). */
153b51c4753SOlivier Matz 	uint16_t                tso_segsz;  /**< MSS for segmentation offload. */
15492ebda07SHelin Zhang 	uint16_t                tx_vlan_id;/**< The tag ID */
15592ebda07SHelin Zhang 	uint16_t                tx_vlan_id_outer;/**< The outer tag ID */
156af75078fSIntel 	void                    *fwd_ctx;   /**< Forwarding mode context */
157af75078fSIntel 	uint64_t                rx_bad_ip_csum; /**< rx pkts with bad ip checksum  */
158af75078fSIntel 	uint64_t                rx_bad_l4_csum; /**< rx pkts with bad l4 checksum */
159ed30d9b6SIntel 	uint8_t                 tx_queue_stats_mapping_enabled;
160ed30d9b6SIntel 	uint8_t                 rx_queue_stats_mapping_enabled;
161ce8d5614SIntel 	volatile uint16_t        port_status;    /**< port started or not */
162ce8d5614SIntel 	uint8_t                 need_reconfig;  /**< need reconfiguring port or not */
163ce8d5614SIntel 	uint8_t                 need_reconfig_queues; /**< need reconfiguring queues or not */
164ce8d5614SIntel 	uint8_t                 rss_flag;   /**< enable rss or not */
1657741e4cfSIntel 	uint8_t                 dcb_flag;   /**< enable dcb */
166ce8d5614SIntel 	struct rte_eth_rxconf   rx_conf;    /**< rx configuration */
167ce8d5614SIntel 	struct rte_eth_txconf   tx_conf;    /**< tx configuration */
1688fff6675SIvan Boule 	struct ether_addr       *mc_addr_pool; /**< pool of multicast addrs */
1698fff6675SIvan Boule 	uint32_t                mc_addr_nb; /**< nb. of addr. in mc_addr_pool */
17041b05095SBernard Iremonger 	uint8_t                 slave_flag; /**< bonding slave port */
171af75078fSIntel };
172af75078fSIntel 
173edab33b1STetsuya Mukawa extern portid_t __rte_unused
174edab33b1STetsuya Mukawa find_next_port(portid_t p, struct rte_port *ports, int size);
175edab33b1STetsuya Mukawa 
176edab33b1STetsuya Mukawa #define FOREACH_PORT(p, ports) \
177edab33b1STetsuya Mukawa 	for (p = find_next_port(0, ports, RTE_MAX_ETHPORTS); \
178edab33b1STetsuya Mukawa 	    p < RTE_MAX_ETHPORTS; \
179edab33b1STetsuya Mukawa 	    p = find_next_port(p + 1, ports, RTE_MAX_ETHPORTS))
180edab33b1STetsuya Mukawa 
181af75078fSIntel /**
182af75078fSIntel  * The data structure associated with each forwarding logical core.
183af75078fSIntel  * The logical cores are internally numbered by a core index from 0 to
184af75078fSIntel  * the maximum number of logical cores - 1.
185af75078fSIntel  * The system CPU identifier of all logical cores are setup in a global
186af75078fSIntel  * CPU id. configuration table.
187af75078fSIntel  */
188af75078fSIntel struct fwd_lcore {
189af75078fSIntel 	struct rte_mempool *mbp; /**< The mbuf pool to use by this core */
190af75078fSIntel 	streamid_t stream_idx;   /**< index of 1st stream in "fwd_streams" */
191af75078fSIntel 	streamid_t stream_nb;    /**< number of streams in "fwd_streams" */
192af75078fSIntel 	lcoreid_t  cpuid_idx;    /**< index of logical core in CPU id table */
193af75078fSIntel 	queueid_t  tx_queue;     /**< TX queue to send forwarded packets */
194af75078fSIntel 	volatile char stopped;   /**< stop forwarding when set */
195af75078fSIntel };
196af75078fSIntel 
197af75078fSIntel /*
198af75078fSIntel  * Forwarding mode operations:
199af75078fSIntel  *   - IO forwarding mode (default mode)
200af75078fSIntel  *     Forwards packets unchanged.
201af75078fSIntel  *
202af75078fSIntel  *   - MAC forwarding mode
203af75078fSIntel  *     Set the source and the destination Ethernet addresses of packets
204af75078fSIntel  *     before forwarding them.
205af75078fSIntel  *
206af75078fSIntel  *   - IEEE1588 forwarding mode
207af75078fSIntel  *     Check that received IEEE1588 Precise Time Protocol (PTP) packets are
208af75078fSIntel  *     filtered and timestamped by the hardware.
209af75078fSIntel  *     Forwards packets unchanged on the same port.
210af75078fSIntel  *     Check that sent IEEE1588 PTP packets are timestamped by the hardware.
211af75078fSIntel  */
212af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi);
213af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi);
214af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs);
215af75078fSIntel 
216af75078fSIntel struct fwd_engine {
217af75078fSIntel 	const char       *fwd_mode_name; /**< Forwarding mode name. */
218af75078fSIntel 	port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */
219af75078fSIntel 	port_fwd_end_t   port_fwd_end;   /**< NULL if nothing special to do. */
220af75078fSIntel 	packet_fwd_t     packet_fwd;     /**< Mandatory. */
221af75078fSIntel };
222af75078fSIntel 
223af75078fSIntel extern struct fwd_engine io_fwd_engine;
224af75078fSIntel extern struct fwd_engine mac_fwd_engine;
22557e85242SBruce Richardson extern struct fwd_engine mac_retry_fwd_engine;
226d47388f1SCyril Chemparathy extern struct fwd_engine mac_swap_engine;
227e9e23a61SCyril Chemparathy extern struct fwd_engine flow_gen_engine;
228af75078fSIntel extern struct fwd_engine rx_only_engine;
229af75078fSIntel extern struct fwd_engine tx_only_engine;
230af75078fSIntel extern struct fwd_engine csum_fwd_engine;
231168dfa61SIvan Boule extern struct fwd_engine icmp_echo_engine;
232af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588
233af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine;
234af75078fSIntel #endif
235af75078fSIntel 
236af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */
237af75078fSIntel 
238af75078fSIntel /**
239af75078fSIntel  * Forwarding Configuration
240af75078fSIntel  *
241af75078fSIntel  */
242af75078fSIntel struct fwd_config {
243af75078fSIntel 	struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */
244af75078fSIntel 	streamid_t nb_fwd_streams;  /**< Nb. of forward streams to process. */
245af75078fSIntel 	lcoreid_t  nb_fwd_lcores;   /**< Nb. of logical cores to launch. */
246af75078fSIntel 	portid_t   nb_fwd_ports;    /**< Nb. of ports involved. */
247af75078fSIntel };
248af75078fSIntel 
249900550deSIntel /**
250900550deSIntel  * DCB mode enable
251900550deSIntel  */
252900550deSIntel enum dcb_mode_enable
253900550deSIntel {
254900550deSIntel 	DCB_VT_ENABLED,
255900550deSIntel 	DCB_ENABLED
256900550deSIntel };
257900550deSIntel 
258ed30d9b6SIntel #define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */
259ed30d9b6SIntel #define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */
260ed30d9b6SIntel 
261ed30d9b6SIntel struct queue_stats_mappings {
262ed30d9b6SIntel 	uint8_t port_id;
263ed30d9b6SIntel 	uint16_t queue_id;
264ed30d9b6SIntel 	uint8_t stats_counter_id;
265ed30d9b6SIntel } __rte_cache_aligned;
266ed30d9b6SIntel 
267ed30d9b6SIntel extern struct queue_stats_mappings tx_queue_stats_mappings_array[];
268ed30d9b6SIntel extern struct queue_stats_mappings rx_queue_stats_mappings_array[];
269ed30d9b6SIntel 
270ed30d9b6SIntel /* Assign both tx and rx queue stats mappings to the same default values */
271ed30d9b6SIntel extern struct queue_stats_mappings *tx_queue_stats_mappings;
272ed30d9b6SIntel extern struct queue_stats_mappings *rx_queue_stats_mappings;
273ed30d9b6SIntel 
274ed30d9b6SIntel extern uint16_t nb_tx_queue_stats_mappings;
275ed30d9b6SIntel extern uint16_t nb_rx_queue_stats_mappings;
276ed30d9b6SIntel 
277af75078fSIntel /* globals used for configuration */
278af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */
279af75078fSIntel extern uint8_t  interactive;
280ca7feb22SCyril Chemparathy extern uint8_t  auto_start;
281af75078fSIntel extern uint8_t  numa_support; /**< set by "--numa" parameter */
282af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */
2837741e4cfSIntel extern uint8_t no_flush_rx; /**<set by "--no-flush-rx" parameter */
284148f963fSBruce Richardson extern uint8_t  mp_anon; /**< set by "--mp-anon" parameter */
285bc202406SDavid Marchand extern uint8_t no_link_check; /**<set by "--disable-link-check" parameter */
2862950a769SDeclan Doherty extern volatile int test_done; /* stop packet forwarding when set to 1. */
287af75078fSIntel 
2887b7e5ba7SIntel #ifdef RTE_NIC_BYPASS
2897b7e5ba7SIntel extern uint32_t bypass_timeout; /**< Store the NIC bypass watchdog timeout */
2907b7e5ba7SIntel #endif
2917b7e5ba7SIntel 
292b6ea6408SIntel /*
293b6ea6408SIntel  * Store specified sockets on which memory pool to be used by ports
294b6ea6408SIntel  * is allocated.
295b6ea6408SIntel  */
296b6ea6408SIntel uint8_t port_numa[RTE_MAX_ETHPORTS];
297b6ea6408SIntel 
298b6ea6408SIntel /*
299b6ea6408SIntel  * Store specified sockets on which RX ring to be used by ports
300b6ea6408SIntel  * is allocated.
301b6ea6408SIntel  */
302b6ea6408SIntel uint8_t rxring_numa[RTE_MAX_ETHPORTS];
303b6ea6408SIntel 
304b6ea6408SIntel /*
305b6ea6408SIntel  * Store specified sockets on which TX ring to be used by ports
306b6ea6408SIntel  * is allocated.
307b6ea6408SIntel  */
308b6ea6408SIntel uint8_t txring_numa[RTE_MAX_ETHPORTS];
309b6ea6408SIntel 
310b6ea6408SIntel extern uint8_t socket_num;
311b6ea6408SIntel 
312af75078fSIntel /*
313af75078fSIntel  * Configuration of logical cores:
314af75078fSIntel  * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores
315af75078fSIntel  */
316af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */
317af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */
318af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */
319af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE];
3207acf894dSStephen Hurd extern unsigned max_socket;
321af75078fSIntel 
322af75078fSIntel /*
323af75078fSIntel  * Configuration of Ethernet ports:
324af75078fSIntel  * nb_fwd_ports <= nb_cfg_ports <= nb_ports
325af75078fSIntel  */
326af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */
327af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */
328af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */
329af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS];
330af75078fSIntel extern struct rte_port *ports;
331af75078fSIntel 
332af75078fSIntel extern struct rte_eth_rxmode rx_mode;
3338a387fa8SHelin Zhang extern uint64_t rss_hf;
334af75078fSIntel 
335af75078fSIntel extern queueid_t nb_rxq;
336af75078fSIntel extern queueid_t nb_txq;
337af75078fSIntel 
338af75078fSIntel extern uint16_t nb_rxd;
339af75078fSIntel extern uint16_t nb_txd;
340af75078fSIntel 
341f2c5125aSPablo de Lara extern int16_t rx_free_thresh;
342f2c5125aSPablo de Lara extern int8_t rx_drop_en;
343f2c5125aSPablo de Lara extern int16_t tx_free_thresh;
344f2c5125aSPablo de Lara extern int16_t tx_rs_thresh;
345f2c5125aSPablo de Lara extern int32_t txq_flags;
346af75078fSIntel 
347900550deSIntel extern uint8_t dcb_config;
348900550deSIntel extern uint8_t dcb_test;
349900550deSIntel extern enum dcb_queue_mapping_mode dcb_q_mapping;
350900550deSIntel 
351af75078fSIntel extern uint16_t mbuf_data_size; /**< Mbuf data space size. */
352c8798818SIntel extern uint32_t param_total_num_mbufs;
353af75078fSIntel 
354af75078fSIntel extern struct rte_fdir_conf fdir_conf;
355af75078fSIntel 
356af75078fSIntel /*
357af75078fSIntel  * Configuration of packet segments used by the "txonly" processing engine.
358af75078fSIntel  */
359af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64
360af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */
361af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */
362af75078fSIntel extern uint8_t  tx_pkt_nb_segs; /**< Number of segments in TX packets */
363af75078fSIntel 
36479bec05bSKonstantin Ananyev enum tx_pkt_split {
36579bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_OFF,
36679bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_ON,
36779bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_RND,
36879bec05bSKonstantin Ananyev };
36979bec05bSKonstantin Ananyev 
37079bec05bSKonstantin Ananyev extern enum tx_pkt_split tx_pkt_split;
37179bec05bSKonstantin Ananyev 
372af75078fSIntel extern uint16_t nb_pkt_per_burst;
373af75078fSIntel extern uint16_t mb_mempool_cache;
374f2c5125aSPablo de Lara extern int8_t rx_pthresh;
375f2c5125aSPablo de Lara extern int8_t rx_hthresh;
376f2c5125aSPablo de Lara extern int8_t rx_wthresh;
377f2c5125aSPablo de Lara extern int8_t tx_pthresh;
378f2c5125aSPablo de Lara extern int8_t tx_hthresh;
379f2c5125aSPablo de Lara extern int8_t tx_wthresh;
380af75078fSIntel 
381af75078fSIntel extern struct fwd_config cur_fwd_config;
382af75078fSIntel extern struct fwd_engine *cur_fwd_eng;
383af75078fSIntel extern struct fwd_lcore  **fwd_lcores;
384af75078fSIntel extern struct fwd_stream **fwd_streams;
385af75078fSIntel 
386af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */
387af75078fSIntel extern struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS];
388af75078fSIntel 
38957e85242SBruce Richardson extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */
39057e85242SBruce Richardson extern uint32_t burst_tx_retry_num;  /**< Burst tx retry number for mac-retry. */
39157e85242SBruce Richardson 
392af75078fSIntel static inline unsigned int
393af75078fSIntel lcore_num(void)
394af75078fSIntel {
395af75078fSIntel 	unsigned int i;
396af75078fSIntel 
397af75078fSIntel 	for (i = 0; i < RTE_MAX_LCORE; ++i)
398af75078fSIntel 		if (fwd_lcores_cpuids[i] == rte_lcore_id())
399af75078fSIntel 			return i;
400af75078fSIntel 
401af75078fSIntel 	rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n");
402af75078fSIntel }
403af75078fSIntel 
404af75078fSIntel static inline struct fwd_lcore *
405af75078fSIntel current_fwd_lcore(void)
406af75078fSIntel {
407af75078fSIntel 	return fwd_lcores[lcore_num()];
408af75078fSIntel }
409af75078fSIntel 
410af75078fSIntel /* Mbuf Pools */
411af75078fSIntel static inline void
412af75078fSIntel mbuf_poolname_build(unsigned int sock_id, char* mp_name, int name_size)
413af75078fSIntel {
4146f41fe75SStephen Hemminger 	snprintf(mp_name, name_size, "mbuf_pool_socket_%u", sock_id);
415af75078fSIntel }
416af75078fSIntel 
417af75078fSIntel static inline struct rte_mempool *
418af75078fSIntel mbuf_pool_find(unsigned int sock_id)
419af75078fSIntel {
420af75078fSIntel 	char pool_name[RTE_MEMPOOL_NAMESIZE];
421af75078fSIntel 
422af75078fSIntel 	mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name));
423693f715dSHuawei Xie 	return rte_mempool_lookup((const char *)pool_name);
424af75078fSIntel }
425af75078fSIntel 
426af75078fSIntel /**
427af75078fSIntel  * Read/Write operations on a PCI register of a port.
428af75078fSIntel  */
429af75078fSIntel static inline uint32_t
430af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off)
431af75078fSIntel {
432af75078fSIntel 	void *reg_addr;
433af75078fSIntel 	uint32_t reg_v;
434af75078fSIntel 
435eee16c96SStephen Hemminger 	reg_addr = (void *)
436eee16c96SStephen Hemminger 		((char *)port->dev_info.pci_dev->mem_resource[0].addr +
437af75078fSIntel 			reg_off);
438af75078fSIntel 	reg_v = *((volatile uint32_t *)reg_addr);
439af75078fSIntel 	return rte_le_to_cpu_32(reg_v);
440af75078fSIntel }
441af75078fSIntel 
442af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \
443af75078fSIntel 	port_pci_reg_read(&ports[(pt_id)], (reg_off))
444af75078fSIntel 
445af75078fSIntel static inline void
446af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v)
447af75078fSIntel {
448af75078fSIntel 	void *reg_addr;
449af75078fSIntel 
450eee16c96SStephen Hemminger 	reg_addr = (void *)
451eee16c96SStephen Hemminger 		((char *)port->dev_info.pci_dev->mem_resource[0].addr +
452af75078fSIntel 			reg_off);
453af75078fSIntel 	*((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v);
454af75078fSIntel }
455af75078fSIntel 
456af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \
457af75078fSIntel 	port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value))
458af75078fSIntel 
459af75078fSIntel /* Prototypes */
460950d1516SBruce Richardson unsigned int parse_item_list(char* str, const char* item_name,
461950d1516SBruce Richardson 			unsigned int max_items,
462950d1516SBruce Richardson 			unsigned int *parsed_items, int check_unique_values);
463af75078fSIntel void launch_args_parse(int argc, char** argv);
464af75078fSIntel void prompt(void);
465d3a274ceSZhihong Wang void prompt_exit(void);
466af75078fSIntel void nic_stats_display(portid_t port_id);
467af75078fSIntel void nic_stats_clear(portid_t port_id);
468bfd5051bSOlivier Matz void nic_xstats_display(portid_t port_id);
469bfd5051bSOlivier Matz void nic_xstats_clear(portid_t port_id);
470ed30d9b6SIntel void nic_stats_mapping_display(portid_t port_id);
471af75078fSIntel void port_infos_display(portid_t port_id);
472ab3257e1SKonstantin Ananyev void rx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
473ab3257e1SKonstantin Ananyev void tx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
474af75078fSIntel void fwd_lcores_config_display(void);
475af75078fSIntel void fwd_config_display(void);
476af75078fSIntel void rxtx_config_display(void);
477af75078fSIntel void fwd_config_setup(void);
478af75078fSIntel void set_def_fwd_config(void);
479a21d5a4bSDeclan Doherty void reconfig(portid_t new_port_id, unsigned socket_id);
480013af9b6SIntel int init_fwd_streams(void);
481013af9b6SIntel 
482ae03d0d1SIvan Boule void port_mtu_set(portid_t port_id, uint16_t mtu);
483af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos);
484af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos,
485af75078fSIntel 		      uint8_t bit_v);
486af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off,
487af75078fSIntel 				uint8_t bit1_pos, uint8_t bit2_pos);
488af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off,
489af75078fSIntel 			    uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value);
490af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off);
491af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value);
492af75078fSIntel 
493af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id);
494af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id);
495af75078fSIntel 
496013af9b6SIntel int set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc);
497013af9b6SIntel int set_fwd_lcores_mask(uint64_t lcoremask);
498af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc);
499af75078fSIntel 
500af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt);
501af75078fSIntel void set_fwd_ports_mask(uint64_t portmask);
502af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt);
503a8ef3e3aSBernard Iremonger int port_is_forwarding(portid_t port_id);
504af75078fSIntel 
505a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on);
506a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on);
507a47aa8b9SIntel 
508a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on);
509af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on);
51064b01ee0SMichal Jastrzebski int rx_vft_set(portid_t port_id, uint16_t vlan_id, int on);
511a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on);
51219b16e2fSHelin Zhang void vlan_tpid_set(portid_t port_id, enum rte_vlan_type vlan_type,
51319b16e2fSHelin Zhang 		   uint16_t tp_id);
514af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id);
51592ebda07SHelin Zhang void tx_qinq_set(portid_t port_id, uint16_t vlan_id, uint16_t vlan_id_outer);
516af75078fSIntel void tx_vlan_reset(portid_t port_id);
517529ba951SHelin Zhang void tx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on);
518ed30d9b6SIntel 
519ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value);
520ed30d9b6SIntel 
521af75078fSIntel void set_verbose_level(uint16_t vb_level);
522af75078fSIntel void set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs);
52379bec05bSKonstantin Ananyev void show_tx_pkt_segments(void);
52479bec05bSKonstantin Ananyev void set_tx_pkt_split(const char *name);
525af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst);
526769ce6b1SThomas Monjalon char *list_pkt_forwarding_modes(void);
527af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode);
528af75078fSIntel void start_packet_forwarding(int with_tx_first);
529af75078fSIntel void stop_packet_forwarding(void);
530cfae07fdSOuyang Changchun void dev_set_link_up(portid_t pid);
531cfae07fdSOuyang Changchun void dev_set_link_down(portid_t pid);
532ce8d5614SIntel void init_port_config(void);
53341b05095SBernard Iremonger void set_port_slave_flag(portid_t slave_pid);
53441b05095SBernard Iremonger void clear_port_slave_flag(portid_t slave_pid);
535*0e545d30SBernard Iremonger uint8_t port_is_bonding_slave(portid_t slave_pid);
536*0e545d30SBernard Iremonger 
5371a572499SJingjing Wu int init_port_dcb_config(portid_t pid, enum dcb_mode_enable dcb_mode,
5381a572499SJingjing Wu 		     enum rte_eth_nb_tcs num_tcs,
5391a572499SJingjing Wu 		     uint8_t pfc_en);
540148f963fSBruce Richardson int start_port(portid_t pid);
541ce8d5614SIntel void stop_port(portid_t pid);
542ce8d5614SIntel void close_port(portid_t pid);
543edab33b1STetsuya Mukawa void attach_port(char *identifier);
544edab33b1STetsuya Mukawa void detach_port(uint8_t port_id);
545ce8d5614SIntel int all_ports_stopped(void);
5465f4ec54fSChen Jing D(Mark) int port_is_started(portid_t port_id);
547af75078fSIntel void pmd_test_exit(void);
548af75078fSIntel void fdir_get_infos(portid_t port_id);
549aeca06dfSJingjing Wu void fdir_set_flex_mask(portid_t port_id,
550aeca06dfSJingjing Wu 			   struct rte_eth_fdir_flex_mask *cfg);
55197b74464SJingjing Wu void fdir_set_flex_payload(portid_t port_id,
55297b74464SJingjing Wu 			   struct rte_eth_flex_payload_cfg *cfg);
55366c59490SHelin Zhang void port_rss_reta_info(portid_t port_id,
55466c59490SHelin Zhang 			struct rte_eth_rss_reta_entry64 *reta_conf,
55566c59490SHelin Zhang 			uint16_t nb_entries);
5566a18e1afSOuyang Changchun 
5577741e4cfSIntel void set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on);
5587741e4cfSIntel void set_vf_rx_vlan(portid_t port_id, uint16_t vlan_id,
5597741e4cfSIntel 		uint64_t vf_mask, uint8_t on);
560af75078fSIntel 
5616a18e1afSOuyang Changchun int set_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate);
5626a18e1afSOuyang Changchun int set_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate,
5636a18e1afSOuyang Changchun 				uint64_t q_msk);
5646a18e1afSOuyang Changchun 
5658205e241SNelio Laranjeiro void port_rss_hash_conf_show(portid_t port_id, char rss_info[],
5668205e241SNelio Laranjeiro 			     int show_rss_key);
5678205e241SNelio Laranjeiro void port_rss_hash_key_update(portid_t port_id, char rss_type[],
5688205e241SNelio Laranjeiro 			      uint8_t *hash_key, uint hash_key_len);
5690db70a80SJingjing Wu void get_syn_filter(uint8_t port_id);
5700db70a80SJingjing Wu void get_ethertype_filter(uint8_t port_id, uint16_t index);
5710db70a80SJingjing Wu void get_2tuple_filter(uint8_t port_id, uint16_t index);
5720db70a80SJingjing Wu void get_5tuple_filter(uint8_t port_id, uint16_t index);
5735f4ec54fSChen Jing D(Mark) int rx_queue_id_is_invalid(queueid_t rxq_id);
5745f4ec54fSChen Jing D(Mark) int tx_queue_id_is_invalid(queueid_t txq_id);
57516321de0SIvan Boule 
5768fff6675SIvan Boule /* Functions to manage the set of filtered Multicast MAC addresses */
5778fff6675SIvan Boule void mcast_addr_add(uint8_t port_id, struct ether_addr *mc_addr);
5788fff6675SIvan Boule void mcast_addr_remove(uint8_t port_id, struct ether_addr *mc_addr);
579cd80f411SJingjing Wu void port_dcb_info_display(uint8_t port_id);
5808fff6675SIvan Boule 
581edab33b1STetsuya Mukawa enum print_warning {
582edab33b1STetsuya Mukawa 	ENABLED_WARN = 0,
583edab33b1STetsuya Mukawa 	DISABLED_WARN
584edab33b1STetsuya Mukawa };
585edab33b1STetsuya Mukawa int port_id_is_invalid(portid_t port_id, enum print_warning warning);
586edab33b1STetsuya Mukawa 
587af75078fSIntel /*
588af75078fSIntel  * Work-around of a compilation error with ICC on invocations of the
589af75078fSIntel  * rte_be_to_cpu_16() function.
590af75078fSIntel  */
591af75078fSIntel #ifdef __GCC__
592af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  rte_be_to_cpu_16((be_16_v))
593af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v))
594af75078fSIntel #else
59544eb9456SThomas Monjalon #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
596af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  (be_16_v)
597af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v)
598af75078fSIntel #else
599af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \
600af75078fSIntel 	(uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8))
601af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \
602af75078fSIntel 	(uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8))
603af75078fSIntel #endif
604af75078fSIntel #endif /* __GCC__ */
605af75078fSIntel 
606af75078fSIntel #endif /* _TESTPMD_H_ */
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