1af75078fSIntel /*- 2af75078fSIntel * BSD LICENSE 3af75078fSIntel * 4e9d48c00SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5af75078fSIntel * All rights reserved. 6af75078fSIntel * 7af75078fSIntel * Redistribution and use in source and binary forms, with or without 8af75078fSIntel * modification, are permitted provided that the following conditions 9af75078fSIntel * are met: 10af75078fSIntel * 11af75078fSIntel * * Redistributions of source code must retain the above copyright 12af75078fSIntel * notice, this list of conditions and the following disclaimer. 13af75078fSIntel * * Redistributions in binary form must reproduce the above copyright 14af75078fSIntel * notice, this list of conditions and the following disclaimer in 15af75078fSIntel * the documentation and/or other materials provided with the 16af75078fSIntel * distribution. 17af75078fSIntel * * Neither the name of Intel Corporation nor the names of its 18af75078fSIntel * contributors may be used to endorse or promote products derived 19af75078fSIntel * from this software without specific prior written permission. 20af75078fSIntel * 21af75078fSIntel * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22af75078fSIntel * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23af75078fSIntel * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24af75078fSIntel * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25af75078fSIntel * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26af75078fSIntel * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27af75078fSIntel * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28af75078fSIntel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29af75078fSIntel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30af75078fSIntel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31af75078fSIntel * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32af75078fSIntel */ 33af75078fSIntel 34af75078fSIntel #include <stdarg.h> 35af75078fSIntel #include <stdio.h> 36af75078fSIntel #include <stdlib.h> 37af75078fSIntel #include <signal.h> 38af75078fSIntel #include <string.h> 39af75078fSIntel #include <time.h> 40af75078fSIntel #include <fcntl.h> 41af75078fSIntel #include <sys/types.h> 42af75078fSIntel #include <errno.h> 43af75078fSIntel 44af75078fSIntel #include <sys/queue.h> 45af75078fSIntel #include <sys/stat.h> 46af75078fSIntel 47af75078fSIntel #include <stdint.h> 48af75078fSIntel #include <unistd.h> 49af75078fSIntel #include <inttypes.h> 50af75078fSIntel 51af75078fSIntel #include <rte_common.h> 52af75078fSIntel #include <rte_byteorder.h> 53af75078fSIntel #include <rte_log.h> 54af75078fSIntel #include <rte_debug.h> 55af75078fSIntel #include <rte_cycles.h> 56af75078fSIntel #include <rte_memory.h> 57af75078fSIntel #include <rte_memcpy.h> 58af75078fSIntel #include <rte_memzone.h> 59af75078fSIntel #include <rte_launch.h> 60af75078fSIntel #include <rte_tailq.h> 61af75078fSIntel #include <rte_eal.h> 62af75078fSIntel #include <rte_per_lcore.h> 63af75078fSIntel #include <rte_lcore.h> 64af75078fSIntel #include <rte_atomic.h> 65af75078fSIntel #include <rte_branch_prediction.h> 66af75078fSIntel #include <rte_ring.h> 67af75078fSIntel #include <rte_mempool.h> 68af75078fSIntel #include <rte_malloc.h> 69af75078fSIntel #include <rte_mbuf.h> 70af75078fSIntel #include <rte_interrupts.h> 71af75078fSIntel #include <rte_pci.h> 72af75078fSIntel #include <rte_ether.h> 73af75078fSIntel #include <rte_ethdev.h> 74edab33b1STetsuya Mukawa #include <rte_dev.h> 75af75078fSIntel #include <rte_string_fns.h> 76148f963fSBruce Richardson #ifdef RTE_LIBRTE_PMD_XENVIRT 77148f963fSBruce Richardson #include <rte_eth_xenvirt.h> 78148f963fSBruce Richardson #endif 79af75078fSIntel 80af75078fSIntel #include "testpmd.h" 81148f963fSBruce Richardson #include "mempool_osdep.h" 82af75078fSIntel 83af75078fSIntel uint16_t verbose_level = 0; /**< Silent by default. */ 84af75078fSIntel 85af75078fSIntel /* use master core for command line ? */ 86af75078fSIntel uint8_t interactive = 0; 87ca7feb22SCyril Chemparathy uint8_t auto_start = 0; 88af75078fSIntel 89af75078fSIntel /* 90af75078fSIntel * NUMA support configuration. 91af75078fSIntel * When set, the NUMA support attempts to dispatch the allocation of the 92af75078fSIntel * RX and TX memory rings, and of the DMA memory buffers (mbufs) for the 93af75078fSIntel * probed ports among the CPU sockets 0 and 1. 94af75078fSIntel * Otherwise, all memory is allocated from CPU socket 0. 95af75078fSIntel */ 96af75078fSIntel uint8_t numa_support = 0; /**< No numa support by default */ 97af75078fSIntel 98af75078fSIntel /* 99b6ea6408SIntel * In UMA mode,all memory is allocated from socket 0 if --socket-num is 100b6ea6408SIntel * not configured. 101b6ea6408SIntel */ 102b6ea6408SIntel uint8_t socket_num = UMA_NO_CONFIG; 103b6ea6408SIntel 104b6ea6408SIntel /* 105148f963fSBruce Richardson * Use ANONYMOUS mapped memory (might be not physically continuous) for mbufs. 106148f963fSBruce Richardson */ 107148f963fSBruce Richardson uint8_t mp_anon = 0; 108148f963fSBruce Richardson 109148f963fSBruce Richardson /* 110af75078fSIntel * Record the Ethernet address of peer target ports to which packets are 111af75078fSIntel * forwarded. 112af75078fSIntel * Must be instanciated with the ethernet addresses of peer traffic generator 113af75078fSIntel * ports. 114af75078fSIntel */ 115af75078fSIntel struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS]; 116af75078fSIntel portid_t nb_peer_eth_addrs = 0; 117af75078fSIntel 118af75078fSIntel /* 119af75078fSIntel * Probed Target Environment. 120af75078fSIntel */ 121af75078fSIntel struct rte_port *ports; /**< For all probed ethernet ports. */ 122af75078fSIntel portid_t nb_ports; /**< Number of probed ethernet ports. */ 123af75078fSIntel struct fwd_lcore **fwd_lcores; /**< For all probed logical cores. */ 124af75078fSIntel lcoreid_t nb_lcores; /**< Number of probed logical cores. */ 125af75078fSIntel 126af75078fSIntel /* 127af75078fSIntel * Test Forwarding Configuration. 128af75078fSIntel * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores 129af75078fSIntel * nb_fwd_ports <= nb_cfg_ports <= nb_ports 130af75078fSIntel */ 131af75078fSIntel lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */ 132af75078fSIntel lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */ 133af75078fSIntel portid_t nb_cfg_ports; /**< Number of configured ports. */ 134af75078fSIntel portid_t nb_fwd_ports; /**< Number of forwarding ports. */ 135af75078fSIntel 136af75078fSIntel unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE]; /**< CPU ids configuration. */ 137af75078fSIntel portid_t fwd_ports_ids[RTE_MAX_ETHPORTS]; /**< Port ids configuration. */ 138af75078fSIntel 139af75078fSIntel struct fwd_stream **fwd_streams; /**< For each RX queue of each port. */ 140af75078fSIntel streamid_t nb_fwd_streams; /**< Is equal to (nb_ports * nb_rxq). */ 141af75078fSIntel 142af75078fSIntel /* 143af75078fSIntel * Forwarding engines. 144af75078fSIntel */ 145af75078fSIntel struct fwd_engine * fwd_engines[] = { 146af75078fSIntel &io_fwd_engine, 147af75078fSIntel &mac_fwd_engine, 14857e85242SBruce Richardson &mac_retry_fwd_engine, 149d47388f1SCyril Chemparathy &mac_swap_engine, 150e9e23a61SCyril Chemparathy &flow_gen_engine, 151af75078fSIntel &rx_only_engine, 152af75078fSIntel &tx_only_engine, 153af75078fSIntel &csum_fwd_engine, 154168dfa61SIvan Boule &icmp_echo_engine, 155af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588 156af75078fSIntel &ieee1588_fwd_engine, 157af75078fSIntel #endif 158af75078fSIntel NULL, 159af75078fSIntel }; 160af75078fSIntel 161af75078fSIntel struct fwd_config cur_fwd_config; 162af75078fSIntel struct fwd_engine *cur_fwd_eng = &io_fwd_engine; /**< IO mode by default. */ 163af75078fSIntel 164af75078fSIntel uint16_t mbuf_data_size = DEFAULT_MBUF_DATA_SIZE; /**< Mbuf data space size. */ 165c8798818SIntel uint32_t param_total_num_mbufs = 0; /**< number of mbufs in all pools - if 166c8798818SIntel * specified on command-line. */ 167af75078fSIntel 168af75078fSIntel /* 169af75078fSIntel * Configuration of packet segments used by the "txonly" processing engine. 170af75078fSIntel */ 171af75078fSIntel uint16_t tx_pkt_length = TXONLY_DEF_PACKET_LEN; /**< TXONLY packet length. */ 172af75078fSIntel uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT] = { 173af75078fSIntel TXONLY_DEF_PACKET_LEN, 174af75078fSIntel }; 175af75078fSIntel uint8_t tx_pkt_nb_segs = 1; /**< Number of segments in TXONLY packets */ 176af75078fSIntel 177af75078fSIntel uint16_t nb_pkt_per_burst = DEF_PKT_BURST; /**< Number of packets per burst. */ 178e9378bbcSCunming Liang uint16_t mb_mempool_cache = DEF_MBUF_CACHE; /**< Size of mbuf mempool cache. */ 179af75078fSIntel 180900550deSIntel /* current configuration is in DCB or not,0 means it is not in DCB mode */ 181900550deSIntel uint8_t dcb_config = 0; 182900550deSIntel 183900550deSIntel /* Whether the dcb is in testing status */ 184900550deSIntel uint8_t dcb_test = 0; 185900550deSIntel 186900550deSIntel /* DCB on and VT on mapping is default */ 187900550deSIntel enum dcb_queue_mapping_mode dcb_q_mapping = DCB_VT_Q_MAPPING; 188af75078fSIntel 189af75078fSIntel /* 190af75078fSIntel * Configurable number of RX/TX queues. 191af75078fSIntel */ 192af75078fSIntel queueid_t nb_rxq = 1; /**< Number of RX queues per port. */ 193af75078fSIntel queueid_t nb_txq = 1; /**< Number of TX queues per port. */ 194af75078fSIntel 195af75078fSIntel /* 196af75078fSIntel * Configurable number of RX/TX ring descriptors. 197af75078fSIntel */ 198af75078fSIntel #define RTE_TEST_RX_DESC_DEFAULT 128 199af75078fSIntel #define RTE_TEST_TX_DESC_DEFAULT 512 200af75078fSIntel uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT; /**< Number of RX descriptors. */ 201af75078fSIntel uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT; /**< Number of TX descriptors. */ 202af75078fSIntel 203f2c5125aSPablo de Lara #define RTE_PMD_PARAM_UNSET -1 204af75078fSIntel /* 205af75078fSIntel * Configurable values of RX and TX ring threshold registers. 206af75078fSIntel */ 207af75078fSIntel 208f2c5125aSPablo de Lara int8_t rx_pthresh = RTE_PMD_PARAM_UNSET; 209f2c5125aSPablo de Lara int8_t rx_hthresh = RTE_PMD_PARAM_UNSET; 210f2c5125aSPablo de Lara int8_t rx_wthresh = RTE_PMD_PARAM_UNSET; 211af75078fSIntel 212f2c5125aSPablo de Lara int8_t tx_pthresh = RTE_PMD_PARAM_UNSET; 213f2c5125aSPablo de Lara int8_t tx_hthresh = RTE_PMD_PARAM_UNSET; 214f2c5125aSPablo de Lara int8_t tx_wthresh = RTE_PMD_PARAM_UNSET; 215af75078fSIntel 216af75078fSIntel /* 217af75078fSIntel * Configurable value of RX free threshold. 218af75078fSIntel */ 219f2c5125aSPablo de Lara int16_t rx_free_thresh = RTE_PMD_PARAM_UNSET; 220af75078fSIntel 221af75078fSIntel /* 222ce8d5614SIntel * Configurable value of RX drop enable. 223ce8d5614SIntel */ 224f2c5125aSPablo de Lara int8_t rx_drop_en = RTE_PMD_PARAM_UNSET; 225ce8d5614SIntel 226ce8d5614SIntel /* 227af75078fSIntel * Configurable value of TX free threshold. 228af75078fSIntel */ 229f2c5125aSPablo de Lara int16_t tx_free_thresh = RTE_PMD_PARAM_UNSET; 230af75078fSIntel 231af75078fSIntel /* 232af75078fSIntel * Configurable value of TX RS bit threshold. 233af75078fSIntel */ 234f2c5125aSPablo de Lara int16_t tx_rs_thresh = RTE_PMD_PARAM_UNSET; 235af75078fSIntel 236af75078fSIntel /* 237ce8d5614SIntel * Configurable value of TX queue flags. 238ce8d5614SIntel */ 239f2c5125aSPablo de Lara int32_t txq_flags = RTE_PMD_PARAM_UNSET; 240ce8d5614SIntel 241ce8d5614SIntel /* 242af75078fSIntel * Receive Side Scaling (RSS) configuration. 243af75078fSIntel */ 2448a387fa8SHelin Zhang uint64_t rss_hf = ETH_RSS_IP; /* RSS IP by default. */ 245af75078fSIntel 246af75078fSIntel /* 247af75078fSIntel * Port topology configuration 248af75078fSIntel */ 249af75078fSIntel uint16_t port_topology = PORT_TOPOLOGY_PAIRED; /* Ports are paired by default */ 250af75078fSIntel 2517741e4cfSIntel /* 2527741e4cfSIntel * Avoids to flush all the RX streams before starts forwarding. 2537741e4cfSIntel */ 2547741e4cfSIntel uint8_t no_flush_rx = 0; /* flush by default */ 2557741e4cfSIntel 256af75078fSIntel /* 257bc202406SDavid Marchand * Avoids to check link status when starting/stopping a port. 258bc202406SDavid Marchand */ 259bc202406SDavid Marchand uint8_t no_link_check = 0; /* check by default */ 260bc202406SDavid Marchand 261bc202406SDavid Marchand /* 2627b7e5ba7SIntel * NIC bypass mode configuration options. 2637b7e5ba7SIntel */ 2647b7e5ba7SIntel #ifdef RTE_NIC_BYPASS 2657b7e5ba7SIntel 2667b7e5ba7SIntel /* The NIC bypass watchdog timeout. */ 2677b7e5ba7SIntel uint32_t bypass_timeout = RTE_BYPASS_TMT_OFF; 2687b7e5ba7SIntel 2697b7e5ba7SIntel #endif 2707b7e5ba7SIntel 2717b7e5ba7SIntel /* 272af75078fSIntel * Ethernet device configuration. 273af75078fSIntel */ 274af75078fSIntel struct rte_eth_rxmode rx_mode = { 275af75078fSIntel .max_rx_pkt_len = ETHER_MAX_LEN, /**< Default maximum frame length. */ 276af75078fSIntel .split_hdr_size = 0, 277af75078fSIntel .header_split = 0, /**< Header Split disabled. */ 278af75078fSIntel .hw_ip_checksum = 0, /**< IP checksum offload disabled. */ 279af75078fSIntel .hw_vlan_filter = 1, /**< VLAN filtering enabled. */ 280a47aa8b9SIntel .hw_vlan_strip = 1, /**< VLAN strip enabled. */ 281a47aa8b9SIntel .hw_vlan_extend = 0, /**< Extended VLAN disabled. */ 282af75078fSIntel .jumbo_frame = 0, /**< Jumbo Frame Support disabled. */ 283af75078fSIntel .hw_strip_crc = 0, /**< CRC stripping by hardware disabled. */ 284af75078fSIntel }; 285af75078fSIntel 286af75078fSIntel struct rte_fdir_conf fdir_conf = { 287af75078fSIntel .mode = RTE_FDIR_MODE_NONE, 288af75078fSIntel .pballoc = RTE_FDIR_PBALLOC_64K, 289af75078fSIntel .status = RTE_FDIR_REPORT_STATUS, 290d9d5e6f2SJingjing Wu .mask = { 291d9d5e6f2SJingjing Wu .vlan_tci_mask = 0x0, 292d9d5e6f2SJingjing Wu .ipv4_mask = { 293d9d5e6f2SJingjing Wu .src_ip = 0xFFFFFFFF, 294d9d5e6f2SJingjing Wu .dst_ip = 0xFFFFFFFF, 295d9d5e6f2SJingjing Wu }, 296d9d5e6f2SJingjing Wu .ipv6_mask = { 297d9d5e6f2SJingjing Wu .src_ip = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 298d9d5e6f2SJingjing Wu .dst_ip = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 299d9d5e6f2SJingjing Wu }, 300d9d5e6f2SJingjing Wu .src_port_mask = 0xFFFF, 301d9d5e6f2SJingjing Wu .dst_port_mask = 0xFFFF, 302d9d5e6f2SJingjing Wu }, 303af75078fSIntel .drop_queue = 127, 304af75078fSIntel }; 305af75078fSIntel 3062950a769SDeclan Doherty volatile int test_done = 1; /* stop packet forwarding when set to 1. */ 307af75078fSIntel 308ed30d9b6SIntel struct queue_stats_mappings tx_queue_stats_mappings_array[MAX_TX_QUEUE_STATS_MAPPINGS]; 309ed30d9b6SIntel struct queue_stats_mappings rx_queue_stats_mappings_array[MAX_RX_QUEUE_STATS_MAPPINGS]; 310ed30d9b6SIntel 311ed30d9b6SIntel struct queue_stats_mappings *tx_queue_stats_mappings = tx_queue_stats_mappings_array; 312ed30d9b6SIntel struct queue_stats_mappings *rx_queue_stats_mappings = rx_queue_stats_mappings_array; 313ed30d9b6SIntel 314ed30d9b6SIntel uint16_t nb_tx_queue_stats_mappings = 0; 315ed30d9b6SIntel uint16_t nb_rx_queue_stats_mappings = 0; 316ed30d9b6SIntel 317ed30d9b6SIntel /* Forward function declarations */ 318ed30d9b6SIntel static void map_port_queue_stats_mapping_registers(uint8_t pi, struct rte_port *port); 319edab33b1STetsuya Mukawa static void check_all_ports_link_status(uint32_t port_mask); 320ce8d5614SIntel 321ce8d5614SIntel /* 322ce8d5614SIntel * Check if all the ports are started. 323ce8d5614SIntel * If yes, return positive value. If not, return zero. 324ce8d5614SIntel */ 325ce8d5614SIntel static int all_ports_started(void); 326ed30d9b6SIntel 327af75078fSIntel /* 328edab33b1STetsuya Mukawa * Find next enabled port 329edab33b1STetsuya Mukawa */ 330edab33b1STetsuya Mukawa portid_t 331edab33b1STetsuya Mukawa find_next_port(portid_t p, struct rte_port *ports, int size) 332edab33b1STetsuya Mukawa { 333edab33b1STetsuya Mukawa if (ports == NULL) 334edab33b1STetsuya Mukawa rte_exit(-EINVAL, "failed to find a next port id\n"); 335edab33b1STetsuya Mukawa 336edab33b1STetsuya Mukawa while ((ports[p].enabled == 0) && (p < size)) 337edab33b1STetsuya Mukawa p++; 338edab33b1STetsuya Mukawa return p; 339edab33b1STetsuya Mukawa } 340edab33b1STetsuya Mukawa 341edab33b1STetsuya Mukawa /* 342af75078fSIntel * Setup default configuration. 343af75078fSIntel */ 344af75078fSIntel static void 345af75078fSIntel set_default_fwd_lcores_config(void) 346af75078fSIntel { 347af75078fSIntel unsigned int i; 348af75078fSIntel unsigned int nb_lc; 349af75078fSIntel 350af75078fSIntel nb_lc = 0; 351af75078fSIntel for (i = 0; i < RTE_MAX_LCORE; i++) { 352af75078fSIntel if (! rte_lcore_is_enabled(i)) 353af75078fSIntel continue; 354af75078fSIntel if (i == rte_get_master_lcore()) 355af75078fSIntel continue; 356af75078fSIntel fwd_lcores_cpuids[nb_lc++] = i; 357af75078fSIntel } 358af75078fSIntel nb_lcores = (lcoreid_t) nb_lc; 359af75078fSIntel nb_cfg_lcores = nb_lcores; 360af75078fSIntel nb_fwd_lcores = 1; 361af75078fSIntel } 362af75078fSIntel 363af75078fSIntel static void 364af75078fSIntel set_def_peer_eth_addrs(void) 365af75078fSIntel { 366af75078fSIntel portid_t i; 367af75078fSIntel 368af75078fSIntel for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 369af75078fSIntel peer_eth_addrs[i].addr_bytes[0] = ETHER_LOCAL_ADMIN_ADDR; 370af75078fSIntel peer_eth_addrs[i].addr_bytes[5] = i; 371af75078fSIntel } 372af75078fSIntel } 373af75078fSIntel 374af75078fSIntel static void 375af75078fSIntel set_default_fwd_ports_config(void) 376af75078fSIntel { 377af75078fSIntel portid_t pt_id; 378af75078fSIntel 379af75078fSIntel for (pt_id = 0; pt_id < nb_ports; pt_id++) 380af75078fSIntel fwd_ports_ids[pt_id] = pt_id; 381af75078fSIntel 382af75078fSIntel nb_cfg_ports = nb_ports; 383af75078fSIntel nb_fwd_ports = nb_ports; 384af75078fSIntel } 385af75078fSIntel 386af75078fSIntel void 387af75078fSIntel set_def_fwd_config(void) 388af75078fSIntel { 389af75078fSIntel set_default_fwd_lcores_config(); 390af75078fSIntel set_def_peer_eth_addrs(); 391af75078fSIntel set_default_fwd_ports_config(); 392af75078fSIntel } 393af75078fSIntel 394af75078fSIntel /* 395af75078fSIntel * Configuration initialisation done once at init time. 396af75078fSIntel */ 397af75078fSIntel struct mbuf_ctor_arg { 398af75078fSIntel uint16_t seg_buf_offset; /**< offset of data in data segment of mbuf. */ 399af75078fSIntel uint16_t seg_buf_size; /**< size of data segment in mbuf. */ 400af75078fSIntel }; 401af75078fSIntel 402af75078fSIntel struct mbuf_pool_ctor_arg { 403af75078fSIntel uint16_t seg_buf_size; /**< size of data segment in mbuf. */ 404af75078fSIntel }; 405af75078fSIntel 406af75078fSIntel static void 407af75078fSIntel testpmd_mbuf_ctor(struct rte_mempool *mp, 408af75078fSIntel void *opaque_arg, 409af75078fSIntel void *raw_mbuf, 410af75078fSIntel __attribute__((unused)) unsigned i) 411af75078fSIntel { 412af75078fSIntel struct mbuf_ctor_arg *mb_ctor_arg; 413af75078fSIntel struct rte_mbuf *mb; 414af75078fSIntel 415af75078fSIntel mb_ctor_arg = (struct mbuf_ctor_arg *) opaque_arg; 416af75078fSIntel mb = (struct rte_mbuf *) raw_mbuf; 417af75078fSIntel 418af75078fSIntel mb->pool = mp; 419af75078fSIntel mb->buf_addr = (void *) ((char *)mb + mb_ctor_arg->seg_buf_offset); 420af75078fSIntel mb->buf_physaddr = (uint64_t) (rte_mempool_virt2phy(mp, mb) + 421af75078fSIntel mb_ctor_arg->seg_buf_offset); 422af75078fSIntel mb->buf_len = mb_ctor_arg->seg_buf_size; 423af75078fSIntel mb->ol_flags = 0; 42408b563ffSOlivier Matz mb->data_off = RTE_PKTMBUF_HEADROOM; 425ea672a8bSOlivier Matz mb->nb_segs = 1; 4264199fdeaSOlivier Matz mb->tx_offload = 0; 4277869536fSBruce Richardson mb->vlan_tci = 0; 428ea672a8bSOlivier Matz mb->hash.rss = 0; 429af75078fSIntel } 430af75078fSIntel 431af75078fSIntel static void 432af75078fSIntel testpmd_mbuf_pool_ctor(struct rte_mempool *mp, 433af75078fSIntel void *opaque_arg) 434af75078fSIntel { 435af75078fSIntel struct mbuf_pool_ctor_arg *mbp_ctor_arg; 436af75078fSIntel struct rte_pktmbuf_pool_private *mbp_priv; 437af75078fSIntel 438af75078fSIntel if (mp->private_data_size < sizeof(struct rte_pktmbuf_pool_private)) { 439af75078fSIntel printf("%s(%s) private_data_size %d < %d\n", 440af75078fSIntel __func__, mp->name, (int) mp->private_data_size, 441af75078fSIntel (int) sizeof(struct rte_pktmbuf_pool_private)); 442af75078fSIntel return; 443af75078fSIntel } 444af75078fSIntel mbp_ctor_arg = (struct mbuf_pool_ctor_arg *) opaque_arg; 445148f963fSBruce Richardson mbp_priv = rte_mempool_get_priv(mp); 446af75078fSIntel mbp_priv->mbuf_data_room_size = mbp_ctor_arg->seg_buf_size; 447af75078fSIntel } 448af75078fSIntel 449af75078fSIntel static void 450af75078fSIntel mbuf_pool_create(uint16_t mbuf_seg_size, unsigned nb_mbuf, 451af75078fSIntel unsigned int socket_id) 452af75078fSIntel { 453af75078fSIntel char pool_name[RTE_MEMPOOL_NAMESIZE]; 454af75078fSIntel struct rte_mempool *rte_mp; 455af75078fSIntel struct mbuf_pool_ctor_arg mbp_ctor_arg; 456af75078fSIntel struct mbuf_ctor_arg mb_ctor_arg; 457af75078fSIntel uint32_t mb_size; 458af75078fSIntel 459af75078fSIntel mbp_ctor_arg.seg_buf_size = (uint16_t) (RTE_PKTMBUF_HEADROOM + 460af75078fSIntel mbuf_seg_size); 461af75078fSIntel mb_ctor_arg.seg_buf_offset = 462fdf20fa7SSergio Gonzalez Monroy (uint16_t) RTE_CACHE_LINE_ROUNDUP(sizeof(struct rte_mbuf)); 463af75078fSIntel mb_ctor_arg.seg_buf_size = mbp_ctor_arg.seg_buf_size; 464af75078fSIntel mb_size = mb_ctor_arg.seg_buf_offset + mb_ctor_arg.seg_buf_size; 465af75078fSIntel mbuf_poolname_build(socket_id, pool_name, sizeof(pool_name)); 466148f963fSBruce Richardson 467148f963fSBruce Richardson #ifdef RTE_LIBRTE_PMD_XENVIRT 468148f963fSBruce Richardson rte_mp = rte_mempool_gntalloc_create(pool_name, nb_mbuf, mb_size, 469af75078fSIntel (unsigned) mb_mempool_cache, 470af75078fSIntel sizeof(struct rte_pktmbuf_pool_private), 471af75078fSIntel testpmd_mbuf_pool_ctor, &mbp_ctor_arg, 472af75078fSIntel testpmd_mbuf_ctor, &mb_ctor_arg, 473af75078fSIntel socket_id, 0); 474148f963fSBruce Richardson 475148f963fSBruce Richardson 476148f963fSBruce Richardson 477148f963fSBruce Richardson #else 478148f963fSBruce Richardson if (mp_anon != 0) 479148f963fSBruce Richardson rte_mp = mempool_anon_create(pool_name, nb_mbuf, mb_size, 480148f963fSBruce Richardson (unsigned) mb_mempool_cache, 481148f963fSBruce Richardson sizeof(struct rte_pktmbuf_pool_private), 482148f963fSBruce Richardson testpmd_mbuf_pool_ctor, &mbp_ctor_arg, 483148f963fSBruce Richardson testpmd_mbuf_ctor, &mb_ctor_arg, 484148f963fSBruce Richardson socket_id, 0); 485148f963fSBruce Richardson else 486148f963fSBruce Richardson rte_mp = rte_mempool_create(pool_name, nb_mbuf, mb_size, 487148f963fSBruce Richardson (unsigned) mb_mempool_cache, 488148f963fSBruce Richardson sizeof(struct rte_pktmbuf_pool_private), 489148f963fSBruce Richardson testpmd_mbuf_pool_ctor, &mbp_ctor_arg, 490148f963fSBruce Richardson testpmd_mbuf_ctor, &mb_ctor_arg, 491148f963fSBruce Richardson socket_id, 0); 492148f963fSBruce Richardson 493148f963fSBruce Richardson #endif 494148f963fSBruce Richardson 495af75078fSIntel if (rte_mp == NULL) { 496ce8d5614SIntel rte_exit(EXIT_FAILURE, "Creation of mbuf pool for socket %u " 497ce8d5614SIntel "failed\n", socket_id); 498148f963fSBruce Richardson } else if (verbose_level > 0) { 499591a9d79SStephen Hemminger rte_mempool_dump(stdout, rte_mp); 500af75078fSIntel } 501af75078fSIntel } 502af75078fSIntel 50320a0286fSLiu Xiaofeng /* 50420a0286fSLiu Xiaofeng * Check given socket id is valid or not with NUMA mode, 50520a0286fSLiu Xiaofeng * if valid, return 0, else return -1 50620a0286fSLiu Xiaofeng */ 50720a0286fSLiu Xiaofeng static int 50820a0286fSLiu Xiaofeng check_socket_id(const unsigned int socket_id) 50920a0286fSLiu Xiaofeng { 51020a0286fSLiu Xiaofeng static int warning_once = 0; 51120a0286fSLiu Xiaofeng 51220a0286fSLiu Xiaofeng if (socket_id >= MAX_SOCKET) { 51320a0286fSLiu Xiaofeng if (!warning_once && numa_support) 51420a0286fSLiu Xiaofeng printf("Warning: NUMA should be configured manually by" 51520a0286fSLiu Xiaofeng " using --port-numa-config and" 51620a0286fSLiu Xiaofeng " --ring-numa-config parameters along with" 51720a0286fSLiu Xiaofeng " --numa.\n"); 51820a0286fSLiu Xiaofeng warning_once = 1; 51920a0286fSLiu Xiaofeng return -1; 52020a0286fSLiu Xiaofeng } 52120a0286fSLiu Xiaofeng return 0; 52220a0286fSLiu Xiaofeng } 52320a0286fSLiu Xiaofeng 524af75078fSIntel static void 525af75078fSIntel init_config(void) 526af75078fSIntel { 527ce8d5614SIntel portid_t pid; 528af75078fSIntel struct rte_port *port; 529af75078fSIntel struct rte_mempool *mbp; 530af75078fSIntel unsigned int nb_mbuf_per_pool; 531af75078fSIntel lcoreid_t lc_id; 532b6ea6408SIntel uint8_t port_per_socket[MAX_SOCKET]; 533af75078fSIntel 534b6ea6408SIntel memset(port_per_socket,0,MAX_SOCKET); 535af75078fSIntel /* Configuration of logical cores. */ 536af75078fSIntel fwd_lcores = rte_zmalloc("testpmd: fwd_lcores", 537af75078fSIntel sizeof(struct fwd_lcore *) * nb_lcores, 538fdf20fa7SSergio Gonzalez Monroy RTE_CACHE_LINE_SIZE); 539af75078fSIntel if (fwd_lcores == NULL) { 540ce8d5614SIntel rte_exit(EXIT_FAILURE, "rte_zmalloc(%d (struct fwd_lcore *)) " 541ce8d5614SIntel "failed\n", nb_lcores); 542af75078fSIntel } 543af75078fSIntel for (lc_id = 0; lc_id < nb_lcores; lc_id++) { 544af75078fSIntel fwd_lcores[lc_id] = rte_zmalloc("testpmd: struct fwd_lcore", 545af75078fSIntel sizeof(struct fwd_lcore), 546fdf20fa7SSergio Gonzalez Monroy RTE_CACHE_LINE_SIZE); 547af75078fSIntel if (fwd_lcores[lc_id] == NULL) { 548ce8d5614SIntel rte_exit(EXIT_FAILURE, "rte_zmalloc(struct fwd_lcore) " 549ce8d5614SIntel "failed\n"); 550af75078fSIntel } 551af75078fSIntel fwd_lcores[lc_id]->cpuid_idx = lc_id; 552af75078fSIntel } 553af75078fSIntel 554af75078fSIntel /* 555af75078fSIntel * Create pools of mbuf. 556af75078fSIntel * If NUMA support is disabled, create a single pool of mbuf in 557b6ea6408SIntel * socket 0 memory by default. 558af75078fSIntel * Otherwise, create a pool of mbuf in the memory of sockets 0 and 1. 559c8798818SIntel * 560c8798818SIntel * Use the maximum value of nb_rxd and nb_txd here, then nb_rxd and 561c8798818SIntel * nb_txd can be configured at run time. 562af75078fSIntel */ 563c8798818SIntel if (param_total_num_mbufs) 564c8798818SIntel nb_mbuf_per_pool = param_total_num_mbufs; 565c8798818SIntel else { 566c8798818SIntel nb_mbuf_per_pool = RTE_TEST_RX_DESC_MAX + (nb_lcores * mb_mempool_cache) 567c8798818SIntel + RTE_TEST_TX_DESC_MAX + MAX_PKT_BURST; 568b6ea6408SIntel 569b6ea6408SIntel if (!numa_support) 570edab33b1STetsuya Mukawa nb_mbuf_per_pool = 571edab33b1STetsuya Mukawa (nb_mbuf_per_pool * RTE_MAX_ETHPORTS); 572c8798818SIntel } 573af75078fSIntel 574b6ea6408SIntel if (!numa_support) { 575b6ea6408SIntel if (socket_num == UMA_NO_CONFIG) 576b6ea6408SIntel mbuf_pool_create(mbuf_data_size, nb_mbuf_per_pool, 0); 577b6ea6408SIntel else 578b6ea6408SIntel mbuf_pool_create(mbuf_data_size, nb_mbuf_per_pool, 579b6ea6408SIntel socket_num); 580b6ea6408SIntel } 581af75078fSIntel 582edab33b1STetsuya Mukawa FOREACH_PORT(pid, ports) { 583ce8d5614SIntel port = &ports[pid]; 584ce8d5614SIntel rte_eth_dev_info_get(pid, &port->dev_info); 585ce8d5614SIntel 586b6ea6408SIntel if (numa_support) { 587b6ea6408SIntel if (port_numa[pid] != NUMA_NO_CONFIG) 588b6ea6408SIntel port_per_socket[port_numa[pid]]++; 589b6ea6408SIntel else { 590b6ea6408SIntel uint32_t socket_id = rte_eth_dev_socket_id(pid); 59120a0286fSLiu Xiaofeng 59220a0286fSLiu Xiaofeng /* if socket_id is invalid, set to 0 */ 59320a0286fSLiu Xiaofeng if (check_socket_id(socket_id) < 0) 59420a0286fSLiu Xiaofeng socket_id = 0; 595b6ea6408SIntel port_per_socket[socket_id]++; 596b6ea6408SIntel } 597b6ea6408SIntel } 598b6ea6408SIntel 599ce8d5614SIntel /* set flag to initialize port/queue */ 600ce8d5614SIntel port->need_reconfig = 1; 601ce8d5614SIntel port->need_reconfig_queues = 1; 602ce8d5614SIntel } 603ce8d5614SIntel 604b6ea6408SIntel if (numa_support) { 605b6ea6408SIntel uint8_t i; 606b6ea6408SIntel unsigned int nb_mbuf; 607ce8d5614SIntel 608b6ea6408SIntel if (param_total_num_mbufs) 609b6ea6408SIntel nb_mbuf_per_pool = nb_mbuf_per_pool/nb_ports; 610b6ea6408SIntel 611b6ea6408SIntel for (i = 0; i < MAX_SOCKET; i++) { 612edab33b1STetsuya Mukawa nb_mbuf = (nb_mbuf_per_pool * RTE_MAX_ETHPORTS); 613b6ea6408SIntel if (nb_mbuf) 614b6ea6408SIntel mbuf_pool_create(mbuf_data_size, 615b6ea6408SIntel nb_mbuf,i); 616b6ea6408SIntel } 617b6ea6408SIntel } 618b6ea6408SIntel init_port_config(); 6195886ae07SAdrien Mazarguil 6205886ae07SAdrien Mazarguil /* 6215886ae07SAdrien Mazarguil * Records which Mbuf pool to use by each logical core, if needed. 6225886ae07SAdrien Mazarguil */ 6235886ae07SAdrien Mazarguil for (lc_id = 0; lc_id < nb_lcores; lc_id++) { 6248fd8bebcSAdrien Mazarguil mbp = mbuf_pool_find( 6258fd8bebcSAdrien Mazarguil rte_lcore_to_socket_id(fwd_lcores_cpuids[lc_id])); 6268fd8bebcSAdrien Mazarguil 6275886ae07SAdrien Mazarguil if (mbp == NULL) 6285886ae07SAdrien Mazarguil mbp = mbuf_pool_find(0); 6295886ae07SAdrien Mazarguil fwd_lcores[lc_id]->mbp = mbp; 6305886ae07SAdrien Mazarguil } 6315886ae07SAdrien Mazarguil 632ce8d5614SIntel /* Configuration of packet forwarding streams. */ 633ce8d5614SIntel if (init_fwd_streams() < 0) 634ce8d5614SIntel rte_exit(EXIT_FAILURE, "FAIL from init_fwd_streams()\n"); 635ce8d5614SIntel } 636ce8d5614SIntel 6372950a769SDeclan Doherty 6382950a769SDeclan Doherty void 639a21d5a4bSDeclan Doherty reconfig(portid_t new_port_id, unsigned socket_id) 6402950a769SDeclan Doherty { 6412950a769SDeclan Doherty struct rte_port *port; 6422950a769SDeclan Doherty 6432950a769SDeclan Doherty /* Reconfiguration of Ethernet ports. */ 6442950a769SDeclan Doherty port = &ports[new_port_id]; 6452950a769SDeclan Doherty rte_eth_dev_info_get(new_port_id, &port->dev_info); 6462950a769SDeclan Doherty 6472950a769SDeclan Doherty /* set flag to initialize port/queue */ 6482950a769SDeclan Doherty port->need_reconfig = 1; 6492950a769SDeclan Doherty port->need_reconfig_queues = 1; 650a21d5a4bSDeclan Doherty port->socket_id = socket_id; 6512950a769SDeclan Doherty 6522950a769SDeclan Doherty init_port_config(); 6532950a769SDeclan Doherty } 6542950a769SDeclan Doherty 6552950a769SDeclan Doherty 656ce8d5614SIntel int 657ce8d5614SIntel init_fwd_streams(void) 658ce8d5614SIntel { 659ce8d5614SIntel portid_t pid; 660ce8d5614SIntel struct rte_port *port; 661ce8d5614SIntel streamid_t sm_id, nb_fwd_streams_new; 662ce8d5614SIntel 663ce8d5614SIntel /* set socket id according to numa or not */ 664edab33b1STetsuya Mukawa FOREACH_PORT(pid, ports) { 665ce8d5614SIntel port = &ports[pid]; 666ce8d5614SIntel if (nb_rxq > port->dev_info.max_rx_queues) { 667ce8d5614SIntel printf("Fail: nb_rxq(%d) is greater than " 668ce8d5614SIntel "max_rx_queues(%d)\n", nb_rxq, 669ce8d5614SIntel port->dev_info.max_rx_queues); 670ce8d5614SIntel return -1; 671ce8d5614SIntel } 672ce8d5614SIntel if (nb_txq > port->dev_info.max_tx_queues) { 673ce8d5614SIntel printf("Fail: nb_txq(%d) is greater than " 674ce8d5614SIntel "max_tx_queues(%d)\n", nb_txq, 675ce8d5614SIntel port->dev_info.max_tx_queues); 676ce8d5614SIntel return -1; 677ce8d5614SIntel } 67820a0286fSLiu Xiaofeng if (numa_support) { 67920a0286fSLiu Xiaofeng if (port_numa[pid] != NUMA_NO_CONFIG) 68020a0286fSLiu Xiaofeng port->socket_id = port_numa[pid]; 68120a0286fSLiu Xiaofeng else { 682b6ea6408SIntel port->socket_id = rte_eth_dev_socket_id(pid); 68320a0286fSLiu Xiaofeng 68420a0286fSLiu Xiaofeng /* if socket_id is invalid, set to 0 */ 68520a0286fSLiu Xiaofeng if (check_socket_id(port->socket_id) < 0) 68620a0286fSLiu Xiaofeng port->socket_id = 0; 68720a0286fSLiu Xiaofeng } 68820a0286fSLiu Xiaofeng } 689b6ea6408SIntel else { 690b6ea6408SIntel if (socket_num == UMA_NO_CONFIG) 691af75078fSIntel port->socket_id = 0; 692b6ea6408SIntel else 693b6ea6408SIntel port->socket_id = socket_num; 694b6ea6408SIntel } 695af75078fSIntel } 696af75078fSIntel 697ce8d5614SIntel nb_fwd_streams_new = (streamid_t)(nb_ports * nb_rxq); 698ce8d5614SIntel if (nb_fwd_streams_new == nb_fwd_streams) 699ce8d5614SIntel return 0; 700ce8d5614SIntel /* clear the old */ 701ce8d5614SIntel if (fwd_streams != NULL) { 702ce8d5614SIntel for (sm_id = 0; sm_id < nb_fwd_streams; sm_id++) { 703ce8d5614SIntel if (fwd_streams[sm_id] == NULL) 704ce8d5614SIntel continue; 705ce8d5614SIntel rte_free(fwd_streams[sm_id]); 706ce8d5614SIntel fwd_streams[sm_id] = NULL; 707af75078fSIntel } 708ce8d5614SIntel rte_free(fwd_streams); 709ce8d5614SIntel fwd_streams = NULL; 710ce8d5614SIntel } 711ce8d5614SIntel 712ce8d5614SIntel /* init new */ 713ce8d5614SIntel nb_fwd_streams = nb_fwd_streams_new; 714ce8d5614SIntel fwd_streams = rte_zmalloc("testpmd: fwd_streams", 715fdf20fa7SSergio Gonzalez Monroy sizeof(struct fwd_stream *) * nb_fwd_streams, RTE_CACHE_LINE_SIZE); 716ce8d5614SIntel if (fwd_streams == NULL) 717ce8d5614SIntel rte_exit(EXIT_FAILURE, "rte_zmalloc(%d (struct fwd_stream *)) " 718ce8d5614SIntel "failed\n", nb_fwd_streams); 719ce8d5614SIntel 720af75078fSIntel for (sm_id = 0; sm_id < nb_fwd_streams; sm_id++) { 721af75078fSIntel fwd_streams[sm_id] = rte_zmalloc("testpmd: struct fwd_stream", 722fdf20fa7SSergio Gonzalez Monroy sizeof(struct fwd_stream), RTE_CACHE_LINE_SIZE); 723ce8d5614SIntel if (fwd_streams[sm_id] == NULL) 724ce8d5614SIntel rte_exit(EXIT_FAILURE, "rte_zmalloc(struct fwd_stream)" 725ce8d5614SIntel " failed\n"); 726af75078fSIntel } 727ce8d5614SIntel 728ce8d5614SIntel return 0; 729af75078fSIntel } 730af75078fSIntel 731af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 732af75078fSIntel static void 733af75078fSIntel pkt_burst_stats_display(const char *rx_tx, struct pkt_burst_stats *pbs) 734af75078fSIntel { 735af75078fSIntel unsigned int total_burst; 736af75078fSIntel unsigned int nb_burst; 737af75078fSIntel unsigned int burst_stats[3]; 738af75078fSIntel uint16_t pktnb_stats[3]; 739af75078fSIntel uint16_t nb_pkt; 740af75078fSIntel int burst_percent[3]; 741af75078fSIntel 742af75078fSIntel /* 743af75078fSIntel * First compute the total number of packet bursts and the 744af75078fSIntel * two highest numbers of bursts of the same number of packets. 745af75078fSIntel */ 746af75078fSIntel total_burst = 0; 747af75078fSIntel burst_stats[0] = burst_stats[1] = burst_stats[2] = 0; 748af75078fSIntel pktnb_stats[0] = pktnb_stats[1] = pktnb_stats[2] = 0; 749af75078fSIntel for (nb_pkt = 0; nb_pkt < MAX_PKT_BURST; nb_pkt++) { 750af75078fSIntel nb_burst = pbs->pkt_burst_spread[nb_pkt]; 751af75078fSIntel if (nb_burst == 0) 752af75078fSIntel continue; 753af75078fSIntel total_burst += nb_burst; 754af75078fSIntel if (nb_burst > burst_stats[0]) { 755af75078fSIntel burst_stats[1] = burst_stats[0]; 756af75078fSIntel pktnb_stats[1] = pktnb_stats[0]; 757af75078fSIntel burst_stats[0] = nb_burst; 758af75078fSIntel pktnb_stats[0] = nb_pkt; 759af75078fSIntel } 760af75078fSIntel } 761af75078fSIntel if (total_burst == 0) 762af75078fSIntel return; 763af75078fSIntel burst_percent[0] = (burst_stats[0] * 100) / total_burst; 764af75078fSIntel printf(" %s-bursts : %u [%d%% of %d pkts", rx_tx, total_burst, 765af75078fSIntel burst_percent[0], (int) pktnb_stats[0]); 766af75078fSIntel if (burst_stats[0] == total_burst) { 767af75078fSIntel printf("]\n"); 768af75078fSIntel return; 769af75078fSIntel } 770af75078fSIntel if (burst_stats[0] + burst_stats[1] == total_burst) { 771af75078fSIntel printf(" + %d%% of %d pkts]\n", 772af75078fSIntel 100 - burst_percent[0], pktnb_stats[1]); 773af75078fSIntel return; 774af75078fSIntel } 775af75078fSIntel burst_percent[1] = (burst_stats[1] * 100) / total_burst; 776af75078fSIntel burst_percent[2] = 100 - (burst_percent[0] + burst_percent[1]); 777af75078fSIntel if ((burst_percent[1] == 0) || (burst_percent[2] == 0)) { 778af75078fSIntel printf(" + %d%% of others]\n", 100 - burst_percent[0]); 779af75078fSIntel return; 780af75078fSIntel } 781af75078fSIntel printf(" + %d%% of %d pkts + %d%% of others]\n", 782af75078fSIntel burst_percent[1], (int) pktnb_stats[1], burst_percent[2]); 783af75078fSIntel } 784af75078fSIntel #endif /* RTE_TEST_PMD_RECORD_BURST_STATS */ 785af75078fSIntel 786af75078fSIntel static void 787af75078fSIntel fwd_port_stats_display(portid_t port_id, struct rte_eth_stats *stats) 788af75078fSIntel { 789af75078fSIntel struct rte_port *port; 790013af9b6SIntel uint8_t i; 791af75078fSIntel 792af75078fSIntel static const char *fwd_stats_border = "----------------------"; 793af75078fSIntel 794af75078fSIntel port = &ports[port_id]; 795af75078fSIntel printf("\n %s Forward statistics for port %-2d %s\n", 796af75078fSIntel fwd_stats_border, port_id, fwd_stats_border); 797013af9b6SIntel 798013af9b6SIntel if ((!port->rx_queue_stats_mapping_enabled) && (!port->tx_queue_stats_mapping_enabled)) { 799af75078fSIntel printf(" RX-packets: %-14"PRIu64" RX-dropped: %-14"PRIu64"RX-total: " 800af75078fSIntel "%-"PRIu64"\n", 80170bdb186SIvan Boule stats->ipackets, stats->imissed, 80270bdb186SIvan Boule (uint64_t) (stats->ipackets + stats->imissed)); 803af75078fSIntel 804af75078fSIntel if (cur_fwd_eng == &csum_fwd_engine) 805af75078fSIntel printf(" Bad-ipcsum: %-14"PRIu64" Bad-l4csum: %-14"PRIu64" \n", 806af75078fSIntel port->rx_bad_ip_csum, port->rx_bad_l4_csum); 80770bdb186SIvan Boule if (((stats->ierrors - stats->imissed) + stats->rx_nombuf) > 0) { 80870bdb186SIvan Boule printf(" RX-badcrc: %-14"PRIu64" RX-badlen: %-14"PRIu64 80970bdb186SIvan Boule "RX-error: %-"PRIu64"\n", 81070bdb186SIvan Boule stats->ibadcrc, stats->ibadlen, stats->ierrors); 81170bdb186SIvan Boule printf(" RX-nombufs: %-14"PRIu64"\n", stats->rx_nombuf); 81270bdb186SIvan Boule } 813af75078fSIntel 814af75078fSIntel printf(" TX-packets: %-14"PRIu64" TX-dropped: %-14"PRIu64"TX-total: " 815af75078fSIntel "%-"PRIu64"\n", 816af75078fSIntel stats->opackets, port->tx_dropped, 817af75078fSIntel (uint64_t) (stats->opackets + port->tx_dropped)); 818013af9b6SIntel } 819013af9b6SIntel else { 820013af9b6SIntel printf(" RX-packets: %14"PRIu64" RX-dropped:%14"PRIu64" RX-total:" 821013af9b6SIntel "%14"PRIu64"\n", 82270bdb186SIvan Boule stats->ipackets, stats->imissed, 82370bdb186SIvan Boule (uint64_t) (stats->ipackets + stats->imissed)); 824013af9b6SIntel 825013af9b6SIntel if (cur_fwd_eng == &csum_fwd_engine) 826013af9b6SIntel printf(" Bad-ipcsum:%14"PRIu64" Bad-l4csum:%14"PRIu64"\n", 827013af9b6SIntel port->rx_bad_ip_csum, port->rx_bad_l4_csum); 82870bdb186SIvan Boule if (((stats->ierrors - stats->imissed) + stats->rx_nombuf) > 0) { 82970bdb186SIvan Boule printf(" RX-badcrc: %14"PRIu64" RX-badlen: %14"PRIu64 83070bdb186SIvan Boule " RX-error:%"PRIu64"\n", 83170bdb186SIvan Boule stats->ibadcrc, stats->ibadlen, stats->ierrors); 83270bdb186SIvan Boule printf(" RX-nombufs: %14"PRIu64"\n", 83370bdb186SIvan Boule stats->rx_nombuf); 83470bdb186SIvan Boule } 835013af9b6SIntel 836013af9b6SIntel printf(" TX-packets: %14"PRIu64" TX-dropped:%14"PRIu64" TX-total:" 837013af9b6SIntel "%14"PRIu64"\n", 838013af9b6SIntel stats->opackets, port->tx_dropped, 839013af9b6SIntel (uint64_t) (stats->opackets + port->tx_dropped)); 840013af9b6SIntel } 841e659b6b4SIvan Boule 842e659b6b4SIvan Boule /* Display statistics of XON/XOFF pause frames, if any. */ 843e659b6b4SIvan Boule if ((stats->tx_pause_xon | stats->rx_pause_xon | 844e659b6b4SIvan Boule stats->tx_pause_xoff | stats->rx_pause_xoff) > 0) { 845e659b6b4SIvan Boule printf(" RX-XOFF: %-14"PRIu64" RX-XON: %-14"PRIu64"\n", 846e659b6b4SIvan Boule stats->rx_pause_xoff, stats->rx_pause_xon); 847e659b6b4SIvan Boule printf(" TX-XOFF: %-14"PRIu64" TX-XON: %-14"PRIu64"\n", 848e659b6b4SIvan Boule stats->tx_pause_xoff, stats->tx_pause_xon); 849e659b6b4SIvan Boule } 850e659b6b4SIvan Boule 851af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 852af75078fSIntel if (port->rx_stream) 853013af9b6SIntel pkt_burst_stats_display("RX", 854013af9b6SIntel &port->rx_stream->rx_burst_stats); 855af75078fSIntel if (port->tx_stream) 856013af9b6SIntel pkt_burst_stats_display("TX", 857013af9b6SIntel &port->tx_stream->tx_burst_stats); 858af75078fSIntel #endif 859af75078fSIntel /* stats fdir */ 860af75078fSIntel if (fdir_conf.mode != RTE_FDIR_MODE_NONE) 861013af9b6SIntel printf(" Fdirmiss:%14"PRIu64" Fdirmatch:%14"PRIu64"\n", 862af75078fSIntel stats->fdirmiss, 863af75078fSIntel stats->fdirmatch); 864af75078fSIntel 865013af9b6SIntel if (port->rx_queue_stats_mapping_enabled) { 866013af9b6SIntel printf("\n"); 867013af9b6SIntel for (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) { 868013af9b6SIntel printf(" Stats reg %2d RX-packets:%14"PRIu64 869013af9b6SIntel " RX-errors:%14"PRIu64 870013af9b6SIntel " RX-bytes:%14"PRIu64"\n", 871013af9b6SIntel i, stats->q_ipackets[i], stats->q_errors[i], stats->q_ibytes[i]); 872013af9b6SIntel } 873013af9b6SIntel printf("\n"); 874013af9b6SIntel } 875013af9b6SIntel if (port->tx_queue_stats_mapping_enabled) { 876013af9b6SIntel for (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) { 877013af9b6SIntel printf(" Stats reg %2d TX-packets:%14"PRIu64 878013af9b6SIntel " TX-bytes:%14"PRIu64"\n", 879013af9b6SIntel i, stats->q_opackets[i], stats->q_obytes[i]); 880013af9b6SIntel } 881013af9b6SIntel } 882013af9b6SIntel 883af75078fSIntel printf(" %s--------------------------------%s\n", 884af75078fSIntel fwd_stats_border, fwd_stats_border); 885af75078fSIntel } 886af75078fSIntel 887af75078fSIntel static void 888af75078fSIntel fwd_stream_stats_display(streamid_t stream_id) 889af75078fSIntel { 890af75078fSIntel struct fwd_stream *fs; 891af75078fSIntel static const char *fwd_top_stats_border = "-------"; 892af75078fSIntel 893af75078fSIntel fs = fwd_streams[stream_id]; 894af75078fSIntel if ((fs->rx_packets == 0) && (fs->tx_packets == 0) && 895af75078fSIntel (fs->fwd_dropped == 0)) 896af75078fSIntel return; 897af75078fSIntel printf("\n %s Forward Stats for RX Port=%2d/Queue=%2d -> " 898af75078fSIntel "TX Port=%2d/Queue=%2d %s\n", 899af75078fSIntel fwd_top_stats_border, fs->rx_port, fs->rx_queue, 900af75078fSIntel fs->tx_port, fs->tx_queue, fwd_top_stats_border); 901af75078fSIntel printf(" RX-packets: %-14u TX-packets: %-14u TX-dropped: %-14u", 902af75078fSIntel fs->rx_packets, fs->tx_packets, fs->fwd_dropped); 903af75078fSIntel 904af75078fSIntel /* if checksum mode */ 905af75078fSIntel if (cur_fwd_eng == &csum_fwd_engine) { 906013af9b6SIntel printf(" RX- bad IP checksum: %-14u Rx- bad L4 checksum: " 907013af9b6SIntel "%-14u\n", fs->rx_bad_ip_csum, fs->rx_bad_l4_csum); 908af75078fSIntel } 909af75078fSIntel 910af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 911af75078fSIntel pkt_burst_stats_display("RX", &fs->rx_burst_stats); 912af75078fSIntel pkt_burst_stats_display("TX", &fs->tx_burst_stats); 913af75078fSIntel #endif 914af75078fSIntel } 915af75078fSIntel 916af75078fSIntel static void 9177741e4cfSIntel flush_fwd_rx_queues(void) 918af75078fSIntel { 919af75078fSIntel struct rte_mbuf *pkts_burst[MAX_PKT_BURST]; 920af75078fSIntel portid_t rxp; 9217741e4cfSIntel portid_t port_id; 922af75078fSIntel queueid_t rxq; 923af75078fSIntel uint16_t nb_rx; 924af75078fSIntel uint16_t i; 925af75078fSIntel uint8_t j; 926af75078fSIntel 927af75078fSIntel for (j = 0; j < 2; j++) { 9287741e4cfSIntel for (rxp = 0; rxp < cur_fwd_config.nb_fwd_ports; rxp++) { 929af75078fSIntel for (rxq = 0; rxq < nb_rxq; rxq++) { 9307741e4cfSIntel port_id = fwd_ports_ids[rxp]; 931af75078fSIntel do { 9327741e4cfSIntel nb_rx = rte_eth_rx_burst(port_id, rxq, 933013af9b6SIntel pkts_burst, MAX_PKT_BURST); 934af75078fSIntel for (i = 0; i < nb_rx; i++) 935af75078fSIntel rte_pktmbuf_free(pkts_burst[i]); 936af75078fSIntel } while (nb_rx > 0); 937af75078fSIntel } 938af75078fSIntel } 939af75078fSIntel rte_delay_ms(10); /* wait 10 milli-seconds before retrying */ 940af75078fSIntel } 941af75078fSIntel } 942af75078fSIntel 943af75078fSIntel static void 944af75078fSIntel run_pkt_fwd_on_lcore(struct fwd_lcore *fc, packet_fwd_t pkt_fwd) 945af75078fSIntel { 946af75078fSIntel struct fwd_stream **fsm; 947af75078fSIntel streamid_t nb_fs; 948af75078fSIntel streamid_t sm_id; 949af75078fSIntel 950af75078fSIntel fsm = &fwd_streams[fc->stream_idx]; 951af75078fSIntel nb_fs = fc->stream_nb; 952af75078fSIntel do { 953af75078fSIntel for (sm_id = 0; sm_id < nb_fs; sm_id++) 954af75078fSIntel (*pkt_fwd)(fsm[sm_id]); 955af75078fSIntel } while (! fc->stopped); 956af75078fSIntel } 957af75078fSIntel 958af75078fSIntel static int 959af75078fSIntel start_pkt_forward_on_core(void *fwd_arg) 960af75078fSIntel { 961af75078fSIntel run_pkt_fwd_on_lcore((struct fwd_lcore *) fwd_arg, 962af75078fSIntel cur_fwd_config.fwd_eng->packet_fwd); 963af75078fSIntel return 0; 964af75078fSIntel } 965af75078fSIntel 966af75078fSIntel /* 967af75078fSIntel * Run the TXONLY packet forwarding engine to send a single burst of packets. 968af75078fSIntel * Used to start communication flows in network loopback test configurations. 969af75078fSIntel */ 970af75078fSIntel static int 971af75078fSIntel run_one_txonly_burst_on_core(void *fwd_arg) 972af75078fSIntel { 973af75078fSIntel struct fwd_lcore *fwd_lc; 974af75078fSIntel struct fwd_lcore tmp_lcore; 975af75078fSIntel 976af75078fSIntel fwd_lc = (struct fwd_lcore *) fwd_arg; 977af75078fSIntel tmp_lcore = *fwd_lc; 978af75078fSIntel tmp_lcore.stopped = 1; 979af75078fSIntel run_pkt_fwd_on_lcore(&tmp_lcore, tx_only_engine.packet_fwd); 980af75078fSIntel return 0; 981af75078fSIntel } 982af75078fSIntel 983af75078fSIntel /* 984af75078fSIntel * Launch packet forwarding: 985af75078fSIntel * - Setup per-port forwarding context. 986af75078fSIntel * - launch logical cores with their forwarding configuration. 987af75078fSIntel */ 988af75078fSIntel static void 989af75078fSIntel launch_packet_forwarding(lcore_function_t *pkt_fwd_on_lcore) 990af75078fSIntel { 991af75078fSIntel port_fwd_begin_t port_fwd_begin; 992af75078fSIntel unsigned int i; 993af75078fSIntel unsigned int lc_id; 994af75078fSIntel int diag; 995af75078fSIntel 996af75078fSIntel port_fwd_begin = cur_fwd_config.fwd_eng->port_fwd_begin; 997af75078fSIntel if (port_fwd_begin != NULL) { 998af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) 999af75078fSIntel (*port_fwd_begin)(fwd_ports_ids[i]); 1000af75078fSIntel } 1001af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_lcores; i++) { 1002af75078fSIntel lc_id = fwd_lcores_cpuids[i]; 1003af75078fSIntel if ((interactive == 0) || (lc_id != rte_lcore_id())) { 1004af75078fSIntel fwd_lcores[i]->stopped = 0; 1005af75078fSIntel diag = rte_eal_remote_launch(pkt_fwd_on_lcore, 1006af75078fSIntel fwd_lcores[i], lc_id); 1007af75078fSIntel if (diag != 0) 1008af75078fSIntel printf("launch lcore %u failed - diag=%d\n", 1009af75078fSIntel lc_id, diag); 1010af75078fSIntel } 1011af75078fSIntel } 1012af75078fSIntel } 1013af75078fSIntel 1014af75078fSIntel /* 1015af75078fSIntel * Launch packet forwarding configuration. 1016af75078fSIntel */ 1017af75078fSIntel void 1018af75078fSIntel start_packet_forwarding(int with_tx_first) 1019af75078fSIntel { 1020af75078fSIntel port_fwd_begin_t port_fwd_begin; 1021af75078fSIntel port_fwd_end_t port_fwd_end; 1022af75078fSIntel struct rte_port *port; 1023af75078fSIntel unsigned int i; 1024af75078fSIntel portid_t pt_id; 1025af75078fSIntel streamid_t sm_id; 1026af75078fSIntel 1027ce8d5614SIntel if (all_ports_started() == 0) { 1028ce8d5614SIntel printf("Not all ports were started\n"); 1029ce8d5614SIntel return; 1030ce8d5614SIntel } 1031af75078fSIntel if (test_done == 0) { 1032af75078fSIntel printf("Packet forwarding already started\n"); 1033af75078fSIntel return; 1034af75078fSIntel } 10357741e4cfSIntel if(dcb_test) { 10367741e4cfSIntel for (i = 0; i < nb_fwd_ports; i++) { 10377741e4cfSIntel pt_id = fwd_ports_ids[i]; 10387741e4cfSIntel port = &ports[pt_id]; 10397741e4cfSIntel if (!port->dcb_flag) { 10407741e4cfSIntel printf("In DCB mode, all forwarding ports must " 10417741e4cfSIntel "be configured in this mode.\n"); 1042013af9b6SIntel return; 1043013af9b6SIntel } 10447741e4cfSIntel } 10457741e4cfSIntel if (nb_fwd_lcores == 1) { 10467741e4cfSIntel printf("In DCB mode,the nb forwarding cores " 10477741e4cfSIntel "should be larger than 1.\n"); 10487741e4cfSIntel return; 10497741e4cfSIntel } 10507741e4cfSIntel } 1051af75078fSIntel test_done = 0; 10527741e4cfSIntel 10537741e4cfSIntel if(!no_flush_rx) 10547741e4cfSIntel flush_fwd_rx_queues(); 10557741e4cfSIntel 1056af75078fSIntel fwd_config_setup(); 1057af75078fSIntel rxtx_config_display(); 1058af75078fSIntel 1059af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) { 1060af75078fSIntel pt_id = fwd_ports_ids[i]; 1061af75078fSIntel port = &ports[pt_id]; 1062af75078fSIntel rte_eth_stats_get(pt_id, &port->stats); 1063af75078fSIntel port->tx_dropped = 0; 1064013af9b6SIntel 1065013af9b6SIntel map_port_queue_stats_mapping_registers(pt_id, port); 1066af75078fSIntel } 1067af75078fSIntel for (sm_id = 0; sm_id < cur_fwd_config.nb_fwd_streams; sm_id++) { 1068af75078fSIntel fwd_streams[sm_id]->rx_packets = 0; 1069af75078fSIntel fwd_streams[sm_id]->tx_packets = 0; 1070af75078fSIntel fwd_streams[sm_id]->fwd_dropped = 0; 1071af75078fSIntel fwd_streams[sm_id]->rx_bad_ip_csum = 0; 1072af75078fSIntel fwd_streams[sm_id]->rx_bad_l4_csum = 0; 1073af75078fSIntel 1074af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 1075af75078fSIntel memset(&fwd_streams[sm_id]->rx_burst_stats, 0, 1076af75078fSIntel sizeof(fwd_streams[sm_id]->rx_burst_stats)); 1077af75078fSIntel memset(&fwd_streams[sm_id]->tx_burst_stats, 0, 1078af75078fSIntel sizeof(fwd_streams[sm_id]->tx_burst_stats)); 1079af75078fSIntel #endif 1080af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 1081af75078fSIntel fwd_streams[sm_id]->core_cycles = 0; 1082af75078fSIntel #endif 1083af75078fSIntel } 1084af75078fSIntel if (with_tx_first) { 1085af75078fSIntel port_fwd_begin = tx_only_engine.port_fwd_begin; 1086af75078fSIntel if (port_fwd_begin != NULL) { 1087af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) 1088af75078fSIntel (*port_fwd_begin)(fwd_ports_ids[i]); 1089af75078fSIntel } 1090af75078fSIntel launch_packet_forwarding(run_one_txonly_burst_on_core); 1091af75078fSIntel rte_eal_mp_wait_lcore(); 1092af75078fSIntel port_fwd_end = tx_only_engine.port_fwd_end; 1093af75078fSIntel if (port_fwd_end != NULL) { 1094af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) 1095af75078fSIntel (*port_fwd_end)(fwd_ports_ids[i]); 1096af75078fSIntel } 1097af75078fSIntel } 1098af75078fSIntel launch_packet_forwarding(start_pkt_forward_on_core); 1099af75078fSIntel } 1100af75078fSIntel 1101af75078fSIntel void 1102af75078fSIntel stop_packet_forwarding(void) 1103af75078fSIntel { 1104af75078fSIntel struct rte_eth_stats stats; 1105af75078fSIntel struct rte_port *port; 1106af75078fSIntel port_fwd_end_t port_fwd_end; 1107af75078fSIntel int i; 1108af75078fSIntel portid_t pt_id; 1109af75078fSIntel streamid_t sm_id; 1110af75078fSIntel lcoreid_t lc_id; 1111af75078fSIntel uint64_t total_recv; 1112af75078fSIntel uint64_t total_xmit; 1113af75078fSIntel uint64_t total_rx_dropped; 1114af75078fSIntel uint64_t total_tx_dropped; 1115af75078fSIntel uint64_t total_rx_nombuf; 1116af75078fSIntel uint64_t tx_dropped; 1117af75078fSIntel uint64_t rx_bad_ip_csum; 1118af75078fSIntel uint64_t rx_bad_l4_csum; 1119af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 1120af75078fSIntel uint64_t fwd_cycles; 1121af75078fSIntel #endif 1122af75078fSIntel static const char *acc_stats_border = "+++++++++++++++"; 1123af75078fSIntel 1124ce8d5614SIntel if (all_ports_started() == 0) { 1125ce8d5614SIntel printf("Not all ports were started\n"); 1126ce8d5614SIntel return; 1127ce8d5614SIntel } 1128af75078fSIntel if (test_done) { 1129af75078fSIntel printf("Packet forwarding not started\n"); 1130af75078fSIntel return; 1131af75078fSIntel } 1132af75078fSIntel printf("Telling cores to stop..."); 1133af75078fSIntel for (lc_id = 0; lc_id < cur_fwd_config.nb_fwd_lcores; lc_id++) 1134af75078fSIntel fwd_lcores[lc_id]->stopped = 1; 1135af75078fSIntel printf("\nWaiting for lcores to finish...\n"); 1136af75078fSIntel rte_eal_mp_wait_lcore(); 1137af75078fSIntel port_fwd_end = cur_fwd_config.fwd_eng->port_fwd_end; 1138af75078fSIntel if (port_fwd_end != NULL) { 1139af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) { 1140af75078fSIntel pt_id = fwd_ports_ids[i]; 1141af75078fSIntel (*port_fwd_end)(pt_id); 1142af75078fSIntel } 1143af75078fSIntel } 1144af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 1145af75078fSIntel fwd_cycles = 0; 1146af75078fSIntel #endif 1147af75078fSIntel for (sm_id = 0; sm_id < cur_fwd_config.nb_fwd_streams; sm_id++) { 1148af75078fSIntel if (cur_fwd_config.nb_fwd_streams > 1149af75078fSIntel cur_fwd_config.nb_fwd_ports) { 1150af75078fSIntel fwd_stream_stats_display(sm_id); 1151af75078fSIntel ports[fwd_streams[sm_id]->tx_port].tx_stream = NULL; 1152af75078fSIntel ports[fwd_streams[sm_id]->rx_port].rx_stream = NULL; 1153af75078fSIntel } else { 1154af75078fSIntel ports[fwd_streams[sm_id]->tx_port].tx_stream = 1155af75078fSIntel fwd_streams[sm_id]; 1156af75078fSIntel ports[fwd_streams[sm_id]->rx_port].rx_stream = 1157af75078fSIntel fwd_streams[sm_id]; 1158af75078fSIntel } 1159af75078fSIntel tx_dropped = ports[fwd_streams[sm_id]->tx_port].tx_dropped; 1160af75078fSIntel tx_dropped = (uint64_t) (tx_dropped + 1161af75078fSIntel fwd_streams[sm_id]->fwd_dropped); 1162af75078fSIntel ports[fwd_streams[sm_id]->tx_port].tx_dropped = tx_dropped; 1163af75078fSIntel 1164013af9b6SIntel rx_bad_ip_csum = 1165013af9b6SIntel ports[fwd_streams[sm_id]->rx_port].rx_bad_ip_csum; 1166af75078fSIntel rx_bad_ip_csum = (uint64_t) (rx_bad_ip_csum + 1167af75078fSIntel fwd_streams[sm_id]->rx_bad_ip_csum); 1168013af9b6SIntel ports[fwd_streams[sm_id]->rx_port].rx_bad_ip_csum = 1169013af9b6SIntel rx_bad_ip_csum; 1170af75078fSIntel 1171013af9b6SIntel rx_bad_l4_csum = 1172013af9b6SIntel ports[fwd_streams[sm_id]->rx_port].rx_bad_l4_csum; 1173af75078fSIntel rx_bad_l4_csum = (uint64_t) (rx_bad_l4_csum + 1174af75078fSIntel fwd_streams[sm_id]->rx_bad_l4_csum); 1175013af9b6SIntel ports[fwd_streams[sm_id]->rx_port].rx_bad_l4_csum = 1176013af9b6SIntel rx_bad_l4_csum; 1177af75078fSIntel 1178af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 1179af75078fSIntel fwd_cycles = (uint64_t) (fwd_cycles + 1180af75078fSIntel fwd_streams[sm_id]->core_cycles); 1181af75078fSIntel #endif 1182af75078fSIntel } 1183af75078fSIntel total_recv = 0; 1184af75078fSIntel total_xmit = 0; 1185af75078fSIntel total_rx_dropped = 0; 1186af75078fSIntel total_tx_dropped = 0; 1187af75078fSIntel total_rx_nombuf = 0; 11887741e4cfSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) { 1189af75078fSIntel pt_id = fwd_ports_ids[i]; 1190af75078fSIntel 1191af75078fSIntel port = &ports[pt_id]; 1192af75078fSIntel rte_eth_stats_get(pt_id, &stats); 1193af75078fSIntel stats.ipackets -= port->stats.ipackets; 1194af75078fSIntel port->stats.ipackets = 0; 1195af75078fSIntel stats.opackets -= port->stats.opackets; 1196af75078fSIntel port->stats.opackets = 0; 1197af75078fSIntel stats.ibytes -= port->stats.ibytes; 1198af75078fSIntel port->stats.ibytes = 0; 1199af75078fSIntel stats.obytes -= port->stats.obytes; 1200af75078fSIntel port->stats.obytes = 0; 120170bdb186SIvan Boule stats.imissed -= port->stats.imissed; 120270bdb186SIvan Boule port->stats.imissed = 0; 1203af75078fSIntel stats.oerrors -= port->stats.oerrors; 1204af75078fSIntel port->stats.oerrors = 0; 1205af75078fSIntel stats.rx_nombuf -= port->stats.rx_nombuf; 1206af75078fSIntel port->stats.rx_nombuf = 0; 1207af75078fSIntel stats.fdirmatch -= port->stats.fdirmatch; 1208af75078fSIntel port->stats.rx_nombuf = 0; 1209af75078fSIntel stats.fdirmiss -= port->stats.fdirmiss; 1210af75078fSIntel port->stats.rx_nombuf = 0; 1211af75078fSIntel 1212af75078fSIntel total_recv += stats.ipackets; 1213af75078fSIntel total_xmit += stats.opackets; 121470bdb186SIvan Boule total_rx_dropped += stats.imissed; 1215af75078fSIntel total_tx_dropped += port->tx_dropped; 1216af75078fSIntel total_rx_nombuf += stats.rx_nombuf; 1217af75078fSIntel 1218af75078fSIntel fwd_port_stats_display(pt_id, &stats); 1219af75078fSIntel } 1220af75078fSIntel printf("\n %s Accumulated forward statistics for all ports" 1221af75078fSIntel "%s\n", 1222af75078fSIntel acc_stats_border, acc_stats_border); 1223af75078fSIntel printf(" RX-packets: %-14"PRIu64" RX-dropped: %-14"PRIu64"RX-total: " 1224af75078fSIntel "%-"PRIu64"\n" 1225af75078fSIntel " TX-packets: %-14"PRIu64" TX-dropped: %-14"PRIu64"TX-total: " 1226af75078fSIntel "%-"PRIu64"\n", 1227af75078fSIntel total_recv, total_rx_dropped, total_recv + total_rx_dropped, 1228af75078fSIntel total_xmit, total_tx_dropped, total_xmit + total_tx_dropped); 1229af75078fSIntel if (total_rx_nombuf > 0) 1230af75078fSIntel printf(" RX-nombufs: %-14"PRIu64"\n", total_rx_nombuf); 1231af75078fSIntel printf(" %s++++++++++++++++++++++++++++++++++++++++++++++" 1232af75078fSIntel "%s\n", 1233af75078fSIntel acc_stats_border, acc_stats_border); 1234af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 1235af75078fSIntel if (total_recv > 0) 1236af75078fSIntel printf("\n CPU cycles/packet=%u (total cycles=" 1237af75078fSIntel "%"PRIu64" / total RX packets=%"PRIu64")\n", 1238af75078fSIntel (unsigned int)(fwd_cycles / total_recv), 1239af75078fSIntel fwd_cycles, total_recv); 1240af75078fSIntel #endif 1241af75078fSIntel printf("\nDone.\n"); 1242af75078fSIntel test_done = 1; 1243af75078fSIntel } 1244af75078fSIntel 1245cfae07fdSOuyang Changchun void 1246cfae07fdSOuyang Changchun dev_set_link_up(portid_t pid) 1247cfae07fdSOuyang Changchun { 1248cfae07fdSOuyang Changchun if (rte_eth_dev_set_link_up((uint8_t)pid) < 0) 1249cfae07fdSOuyang Changchun printf("\nSet link up fail.\n"); 1250cfae07fdSOuyang Changchun } 1251cfae07fdSOuyang Changchun 1252cfae07fdSOuyang Changchun void 1253cfae07fdSOuyang Changchun dev_set_link_down(portid_t pid) 1254cfae07fdSOuyang Changchun { 1255cfae07fdSOuyang Changchun if (rte_eth_dev_set_link_down((uint8_t)pid) < 0) 1256cfae07fdSOuyang Changchun printf("\nSet link down fail.\n"); 1257cfae07fdSOuyang Changchun } 1258cfae07fdSOuyang Changchun 1259ce8d5614SIntel static int 1260ce8d5614SIntel all_ports_started(void) 1261ce8d5614SIntel { 1262ce8d5614SIntel portid_t pi; 1263ce8d5614SIntel struct rte_port *port; 1264ce8d5614SIntel 1265edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 1266ce8d5614SIntel port = &ports[pi]; 1267ce8d5614SIntel /* Check if there is a port which is not started */ 1268ce8d5614SIntel if (port->port_status != RTE_PORT_STARTED) 1269ce8d5614SIntel return 0; 1270ce8d5614SIntel } 1271ce8d5614SIntel 1272ce8d5614SIntel /* No port is not started */ 1273ce8d5614SIntel return 1; 1274ce8d5614SIntel } 1275ce8d5614SIntel 1276148f963fSBruce Richardson int 1277edab33b1STetsuya Mukawa all_ports_stopped(void) 1278edab33b1STetsuya Mukawa { 1279edab33b1STetsuya Mukawa portid_t pi; 1280edab33b1STetsuya Mukawa struct rte_port *port; 1281edab33b1STetsuya Mukawa 1282edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 1283edab33b1STetsuya Mukawa port = &ports[pi]; 1284edab33b1STetsuya Mukawa if (port->port_status != RTE_PORT_STOPPED) 1285edab33b1STetsuya Mukawa return 0; 1286edab33b1STetsuya Mukawa } 1287edab33b1STetsuya Mukawa 1288edab33b1STetsuya Mukawa return 1; 1289edab33b1STetsuya Mukawa } 1290edab33b1STetsuya Mukawa 1291edab33b1STetsuya Mukawa int 1292edab33b1STetsuya Mukawa port_is_started(portid_t port_id) 1293edab33b1STetsuya Mukawa { 1294edab33b1STetsuya Mukawa if (port_id_is_invalid(port_id, ENABLED_WARN)) 1295edab33b1STetsuya Mukawa return 0; 1296edab33b1STetsuya Mukawa 1297edab33b1STetsuya Mukawa if (ports[port_id].port_status != RTE_PORT_STARTED) 1298edab33b1STetsuya Mukawa return 0; 1299edab33b1STetsuya Mukawa 1300edab33b1STetsuya Mukawa return 1; 1301edab33b1STetsuya Mukawa } 1302edab33b1STetsuya Mukawa 1303edab33b1STetsuya Mukawa static int 1304edab33b1STetsuya Mukawa port_is_closed(portid_t port_id) 1305edab33b1STetsuya Mukawa { 1306edab33b1STetsuya Mukawa if (port_id_is_invalid(port_id, ENABLED_WARN)) 1307edab33b1STetsuya Mukawa return 0; 1308edab33b1STetsuya Mukawa 1309edab33b1STetsuya Mukawa if (ports[port_id].port_status != RTE_PORT_CLOSED) 1310edab33b1STetsuya Mukawa return 0; 1311edab33b1STetsuya Mukawa 1312edab33b1STetsuya Mukawa return 1; 1313edab33b1STetsuya Mukawa } 1314edab33b1STetsuya Mukawa 1315edab33b1STetsuya Mukawa int 1316ce8d5614SIntel start_port(portid_t pid) 1317ce8d5614SIntel { 1318ce8d5614SIntel int diag, need_check_link_status = 0; 1319ce8d5614SIntel portid_t pi; 1320ce8d5614SIntel queueid_t qi; 1321ce8d5614SIntel struct rte_port *port; 13222950a769SDeclan Doherty struct ether_addr mac_addr; 1323ce8d5614SIntel 1324ce8d5614SIntel if (test_done == 0) { 1325ce8d5614SIntel printf("Please stop forwarding first\n"); 1326148f963fSBruce Richardson return -1; 1327ce8d5614SIntel } 1328ce8d5614SIntel 1329ce8d5614SIntel if (init_fwd_streams() < 0) { 1330ce8d5614SIntel printf("Fail from init_fwd_streams()\n"); 1331148f963fSBruce Richardson return -1; 1332ce8d5614SIntel } 1333ce8d5614SIntel 1334ce8d5614SIntel if(dcb_config) 1335ce8d5614SIntel dcb_test = 1; 1336edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 1337edab33b1STetsuya Mukawa if (pid != pi && pid != (portid_t)RTE_PORT_ALL) 1338ce8d5614SIntel continue; 1339ce8d5614SIntel 1340ce8d5614SIntel port = &ports[pi]; 1341ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), RTE_PORT_STOPPED, 1342ce8d5614SIntel RTE_PORT_HANDLING) == 0) { 1343ce8d5614SIntel printf("Port %d is now not stopped\n", pi); 1344ce8d5614SIntel continue; 1345ce8d5614SIntel } 1346ce8d5614SIntel 1347ce8d5614SIntel if (port->need_reconfig > 0) { 1348ce8d5614SIntel port->need_reconfig = 0; 1349ce8d5614SIntel 13505706de65SJulien Cretin printf("Configuring Port %d (socket %u)\n", pi, 135120a0286fSLiu Xiaofeng port->socket_id); 1352ce8d5614SIntel /* configure port */ 1353ce8d5614SIntel diag = rte_eth_dev_configure(pi, nb_rxq, nb_txq, 1354ce8d5614SIntel &(port->dev_conf)); 1355ce8d5614SIntel if (diag != 0) { 1356ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1357ce8d5614SIntel RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0) 1358ce8d5614SIntel printf("Port %d can not be set back " 1359ce8d5614SIntel "to stopped\n", pi); 1360ce8d5614SIntel printf("Fail to configure port %d\n", pi); 1361ce8d5614SIntel /* try to reconfigure port next time */ 1362ce8d5614SIntel port->need_reconfig = 1; 1363148f963fSBruce Richardson return -1; 1364ce8d5614SIntel } 1365ce8d5614SIntel } 1366ce8d5614SIntel if (port->need_reconfig_queues > 0) { 1367ce8d5614SIntel port->need_reconfig_queues = 0; 1368ce8d5614SIntel /* setup tx queues */ 1369ce8d5614SIntel for (qi = 0; qi < nb_txq; qi++) { 1370b6ea6408SIntel if ((numa_support) && 1371b6ea6408SIntel (txring_numa[pi] != NUMA_NO_CONFIG)) 1372b6ea6408SIntel diag = rte_eth_tx_queue_setup(pi, qi, 1373b6ea6408SIntel nb_txd,txring_numa[pi], 1374b6ea6408SIntel &(port->tx_conf)); 1375b6ea6408SIntel else 1376b6ea6408SIntel diag = rte_eth_tx_queue_setup(pi, qi, 1377b6ea6408SIntel nb_txd,port->socket_id, 1378b6ea6408SIntel &(port->tx_conf)); 1379b6ea6408SIntel 1380ce8d5614SIntel if (diag == 0) 1381ce8d5614SIntel continue; 1382ce8d5614SIntel 1383ce8d5614SIntel /* Fail to setup tx queue, return */ 1384ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1385ce8d5614SIntel RTE_PORT_HANDLING, 1386ce8d5614SIntel RTE_PORT_STOPPED) == 0) 1387ce8d5614SIntel printf("Port %d can not be set back " 1388ce8d5614SIntel "to stopped\n", pi); 1389ce8d5614SIntel printf("Fail to configure port %d tx queues\n", pi); 1390ce8d5614SIntel /* try to reconfigure queues next time */ 1391ce8d5614SIntel port->need_reconfig_queues = 1; 1392148f963fSBruce Richardson return -1; 1393ce8d5614SIntel } 1394ce8d5614SIntel /* setup rx queues */ 1395ce8d5614SIntel for (qi = 0; qi < nb_rxq; qi++) { 1396b6ea6408SIntel if ((numa_support) && 1397b6ea6408SIntel (rxring_numa[pi] != NUMA_NO_CONFIG)) { 1398b6ea6408SIntel struct rte_mempool * mp = 1399b6ea6408SIntel mbuf_pool_find(rxring_numa[pi]); 1400b6ea6408SIntel if (mp == NULL) { 1401b6ea6408SIntel printf("Failed to setup RX queue:" 1402b6ea6408SIntel "No mempool allocation" 1403b6ea6408SIntel "on the socket %d\n", 1404b6ea6408SIntel rxring_numa[pi]); 1405148f963fSBruce Richardson return -1; 1406b6ea6408SIntel } 1407b6ea6408SIntel 1408b6ea6408SIntel diag = rte_eth_rx_queue_setup(pi, qi, 1409b6ea6408SIntel nb_rxd,rxring_numa[pi], 1410b6ea6408SIntel &(port->rx_conf),mp); 1411b6ea6408SIntel } 1412b6ea6408SIntel else 1413b6ea6408SIntel diag = rte_eth_rx_queue_setup(pi, qi, 1414b6ea6408SIntel nb_rxd,port->socket_id, 1415b6ea6408SIntel &(port->rx_conf), 1416ce8d5614SIntel mbuf_pool_find(port->socket_id)); 1417b6ea6408SIntel 1418ce8d5614SIntel if (diag == 0) 1419ce8d5614SIntel continue; 1420ce8d5614SIntel 1421b6ea6408SIntel 1422ce8d5614SIntel /* Fail to setup rx queue, return */ 1423ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1424ce8d5614SIntel RTE_PORT_HANDLING, 1425ce8d5614SIntel RTE_PORT_STOPPED) == 0) 1426ce8d5614SIntel printf("Port %d can not be set back " 1427ce8d5614SIntel "to stopped\n", pi); 1428ce8d5614SIntel printf("Fail to configure port %d rx queues\n", pi); 1429ce8d5614SIntel /* try to reconfigure queues next time */ 1430ce8d5614SIntel port->need_reconfig_queues = 1; 1431148f963fSBruce Richardson return -1; 1432ce8d5614SIntel } 1433ce8d5614SIntel } 1434ce8d5614SIntel /* start port */ 1435ce8d5614SIntel if (rte_eth_dev_start(pi) < 0) { 1436ce8d5614SIntel printf("Fail to start port %d\n", pi); 1437ce8d5614SIntel 1438ce8d5614SIntel /* Fail to setup rx queue, return */ 1439ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1440ce8d5614SIntel RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0) 1441ce8d5614SIntel printf("Port %d can not be set back to " 1442ce8d5614SIntel "stopped\n", pi); 1443ce8d5614SIntel continue; 1444ce8d5614SIntel } 1445ce8d5614SIntel 1446ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1447ce8d5614SIntel RTE_PORT_HANDLING, RTE_PORT_STARTED) == 0) 1448ce8d5614SIntel printf("Port %d can not be set into started\n", pi); 1449ce8d5614SIntel 14502950a769SDeclan Doherty rte_eth_macaddr_get(pi, &mac_addr); 1451d8c89163SZijie Pan printf("Port %d: %02X:%02X:%02X:%02X:%02X:%02X\n", pi, 14522950a769SDeclan Doherty mac_addr.addr_bytes[0], mac_addr.addr_bytes[1], 14532950a769SDeclan Doherty mac_addr.addr_bytes[2], mac_addr.addr_bytes[3], 14542950a769SDeclan Doherty mac_addr.addr_bytes[4], mac_addr.addr_bytes[5]); 1455d8c89163SZijie Pan 1456ce8d5614SIntel /* at least one port started, need checking link status */ 1457ce8d5614SIntel need_check_link_status = 1; 1458ce8d5614SIntel } 1459ce8d5614SIntel 1460bc202406SDavid Marchand if (need_check_link_status && !no_link_check) 1461edab33b1STetsuya Mukawa check_all_ports_link_status(RTE_PORT_ALL); 1462ce8d5614SIntel else 1463ce8d5614SIntel printf("Please stop the ports first\n"); 1464ce8d5614SIntel 1465ce8d5614SIntel printf("Done\n"); 1466148f963fSBruce Richardson return 0; 1467ce8d5614SIntel } 1468ce8d5614SIntel 1469ce8d5614SIntel void 1470ce8d5614SIntel stop_port(portid_t pid) 1471ce8d5614SIntel { 1472ce8d5614SIntel portid_t pi; 1473ce8d5614SIntel struct rte_port *port; 1474ce8d5614SIntel int need_check_link_status = 0; 1475ce8d5614SIntel 1476ce8d5614SIntel if (test_done == 0) { 1477ce8d5614SIntel printf("Please stop forwarding first\n"); 1478ce8d5614SIntel return; 1479ce8d5614SIntel } 1480ce8d5614SIntel if (dcb_test) { 1481ce8d5614SIntel dcb_test = 0; 1482ce8d5614SIntel dcb_config = 0; 1483ce8d5614SIntel } 1484ce8d5614SIntel printf("Stopping ports...\n"); 1485ce8d5614SIntel 1486edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 1487edab33b1STetsuya Mukawa if (!port_id_is_invalid(pid, DISABLED_WARN) && pid != pi) 1488ce8d5614SIntel continue; 1489ce8d5614SIntel 1490ce8d5614SIntel port = &ports[pi]; 1491ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), RTE_PORT_STARTED, 1492ce8d5614SIntel RTE_PORT_HANDLING) == 0) 1493ce8d5614SIntel continue; 1494ce8d5614SIntel 1495ce8d5614SIntel rte_eth_dev_stop(pi); 1496ce8d5614SIntel 1497ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1498ce8d5614SIntel RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0) 1499ce8d5614SIntel printf("Port %d can not be set into stopped\n", pi); 1500ce8d5614SIntel need_check_link_status = 1; 1501ce8d5614SIntel } 1502bc202406SDavid Marchand if (need_check_link_status && !no_link_check) 1503edab33b1STetsuya Mukawa check_all_ports_link_status(RTE_PORT_ALL); 1504ce8d5614SIntel 1505ce8d5614SIntel printf("Done\n"); 1506ce8d5614SIntel } 1507ce8d5614SIntel 1508ce8d5614SIntel void 1509ce8d5614SIntel close_port(portid_t pid) 1510ce8d5614SIntel { 1511ce8d5614SIntel portid_t pi; 1512ce8d5614SIntel struct rte_port *port; 1513ce8d5614SIntel 1514ce8d5614SIntel if (test_done == 0) { 1515ce8d5614SIntel printf("Please stop forwarding first\n"); 1516ce8d5614SIntel return; 1517ce8d5614SIntel } 1518ce8d5614SIntel 1519ce8d5614SIntel printf("Closing ports...\n"); 1520ce8d5614SIntel 1521edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 1522edab33b1STetsuya Mukawa if (!port_id_is_invalid(pid, DISABLED_WARN) && pid != pi) 1523ce8d5614SIntel continue; 1524ce8d5614SIntel 1525ce8d5614SIntel port = &ports[pi]; 1526ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1527ce8d5614SIntel RTE_PORT_STOPPED, RTE_PORT_HANDLING) == 0) { 1528ce8d5614SIntel printf("Port %d is now not stopped\n", pi); 1529ce8d5614SIntel continue; 1530ce8d5614SIntel } 1531ce8d5614SIntel 1532ce8d5614SIntel rte_eth_dev_close(pi); 1533ce8d5614SIntel 1534ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1535ce8d5614SIntel RTE_PORT_HANDLING, RTE_PORT_CLOSED) == 0) 1536ce8d5614SIntel printf("Port %d can not be set into stopped\n", pi); 1537ce8d5614SIntel } 1538ce8d5614SIntel 1539ce8d5614SIntel printf("Done\n"); 1540ce8d5614SIntel } 1541ce8d5614SIntel 1542edab33b1STetsuya Mukawa void 1543edab33b1STetsuya Mukawa attach_port(char *identifier) 1544ce8d5614SIntel { 1545edab33b1STetsuya Mukawa portid_t i, j, pi = 0; 1546ce8d5614SIntel 1547edab33b1STetsuya Mukawa printf("Attaching a new port...\n"); 1548edab33b1STetsuya Mukawa 1549edab33b1STetsuya Mukawa if (identifier == NULL) { 1550edab33b1STetsuya Mukawa printf("Invalid parameters are specified\n"); 1551edab33b1STetsuya Mukawa return; 1552ce8d5614SIntel } 1553ce8d5614SIntel 1554edab33b1STetsuya Mukawa if (test_done == 0) { 1555edab33b1STetsuya Mukawa printf("Please stop forwarding first\n"); 1556edab33b1STetsuya Mukawa return; 1557ce8d5614SIntel } 1558ce8d5614SIntel 1559edab33b1STetsuya Mukawa if (rte_eth_dev_attach(identifier, &pi)) 1560edab33b1STetsuya Mukawa return; 1561edab33b1STetsuya Mukawa 1562edab33b1STetsuya Mukawa ports[pi].enabled = 1; 1563edab33b1STetsuya Mukawa reconfig(pi, rte_eth_dev_socket_id(pi)); 1564edab33b1STetsuya Mukawa rte_eth_promiscuous_enable(pi); 1565edab33b1STetsuya Mukawa 1566edab33b1STetsuya Mukawa nb_ports = rte_eth_dev_count(); 1567edab33b1STetsuya Mukawa 1568edab33b1STetsuya Mukawa /* set_default_fwd_ports_config(); */ 1569edab33b1STetsuya Mukawa bzero(fwd_ports_ids, sizeof(fwd_ports_ids)); 1570edab33b1STetsuya Mukawa i = 0; 1571edab33b1STetsuya Mukawa FOREACH_PORT(j, ports) { 1572edab33b1STetsuya Mukawa fwd_ports_ids[i] = j; 1573edab33b1STetsuya Mukawa i++; 1574edab33b1STetsuya Mukawa } 1575edab33b1STetsuya Mukawa nb_cfg_ports = nb_ports; 1576edab33b1STetsuya Mukawa nb_fwd_ports++; 1577edab33b1STetsuya Mukawa 1578edab33b1STetsuya Mukawa ports[pi].port_status = RTE_PORT_STOPPED; 1579edab33b1STetsuya Mukawa 1580edab33b1STetsuya Mukawa printf("Port %d is attached. Now total ports is %d\n", pi, nb_ports); 1581edab33b1STetsuya Mukawa printf("Done\n"); 1582edab33b1STetsuya Mukawa } 1583edab33b1STetsuya Mukawa 1584edab33b1STetsuya Mukawa void 1585edab33b1STetsuya Mukawa detach_port(uint8_t port_id) 15865f4ec54fSChen Jing D(Mark) { 1587edab33b1STetsuya Mukawa portid_t i, pi = 0; 1588edab33b1STetsuya Mukawa char name[RTE_ETH_NAME_MAX_LEN]; 15895f4ec54fSChen Jing D(Mark) 1590edab33b1STetsuya Mukawa printf("Detaching a port...\n"); 15915f4ec54fSChen Jing D(Mark) 1592edab33b1STetsuya Mukawa if (!port_is_closed(port_id)) { 1593edab33b1STetsuya Mukawa printf("Please close port first\n"); 1594edab33b1STetsuya Mukawa return; 1595edab33b1STetsuya Mukawa } 1596edab33b1STetsuya Mukawa 1597edab33b1STetsuya Mukawa rte_eth_promiscuous_disable(port_id); 1598edab33b1STetsuya Mukawa 1599edab33b1STetsuya Mukawa if (rte_eth_dev_detach(port_id, name)) 1600edab33b1STetsuya Mukawa return; 1601edab33b1STetsuya Mukawa 1602edab33b1STetsuya Mukawa ports[port_id].enabled = 0; 1603edab33b1STetsuya Mukawa nb_ports = rte_eth_dev_count(); 1604edab33b1STetsuya Mukawa 1605edab33b1STetsuya Mukawa /* set_default_fwd_ports_config(); */ 1606edab33b1STetsuya Mukawa bzero(fwd_ports_ids, sizeof(fwd_ports_ids)); 1607edab33b1STetsuya Mukawa i = 0; 1608edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 1609edab33b1STetsuya Mukawa fwd_ports_ids[i] = pi; 1610edab33b1STetsuya Mukawa i++; 1611edab33b1STetsuya Mukawa } 1612edab33b1STetsuya Mukawa nb_cfg_ports = nb_ports; 1613edab33b1STetsuya Mukawa nb_fwd_ports--; 1614edab33b1STetsuya Mukawa 1615edab33b1STetsuya Mukawa printf("Port '%s' is detached. Now total ports is %d\n", 1616edab33b1STetsuya Mukawa name, nb_ports); 1617edab33b1STetsuya Mukawa printf("Done\n"); 1618edab33b1STetsuya Mukawa return; 16195f4ec54fSChen Jing D(Mark) } 16205f4ec54fSChen Jing D(Mark) 1621af75078fSIntel void 1622af75078fSIntel pmd_test_exit(void) 1623af75078fSIntel { 1624af75078fSIntel portid_t pt_id; 1625af75078fSIntel 1626edab33b1STetsuya Mukawa FOREACH_PORT(pt_id, ports) { 1627af75078fSIntel printf("Stopping port %d...", pt_id); 1628af75078fSIntel fflush(stdout); 1629af75078fSIntel rte_eth_dev_close(pt_id); 1630af75078fSIntel printf("done\n"); 1631af75078fSIntel } 1632af75078fSIntel printf("bye...\n"); 1633af75078fSIntel } 1634af75078fSIntel 1635af75078fSIntel typedef void (*cmd_func_t)(void); 1636af75078fSIntel struct pmd_test_command { 1637af75078fSIntel const char *cmd_name; 1638af75078fSIntel cmd_func_t cmd_func; 1639af75078fSIntel }; 1640af75078fSIntel 1641af75078fSIntel #define PMD_TEST_CMD_NB (sizeof(pmd_test_menu) / sizeof(pmd_test_menu[0])) 1642af75078fSIntel 1643ce8d5614SIntel /* Check the link status of all ports in up to 9s, and print them finally */ 1644af75078fSIntel static void 1645edab33b1STetsuya Mukawa check_all_ports_link_status(uint32_t port_mask) 1646af75078fSIntel { 1647ce8d5614SIntel #define CHECK_INTERVAL 100 /* 100ms */ 1648ce8d5614SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 1649ce8d5614SIntel uint8_t portid, count, all_ports_up, print_flag = 0; 1650ce8d5614SIntel struct rte_eth_link link; 1651ce8d5614SIntel 1652ce8d5614SIntel printf("Checking link statuses...\n"); 1653ce8d5614SIntel fflush(stdout); 1654ce8d5614SIntel for (count = 0; count <= MAX_CHECK_TIME; count++) { 1655ce8d5614SIntel all_ports_up = 1; 1656edab33b1STetsuya Mukawa FOREACH_PORT(portid, ports) { 1657ce8d5614SIntel if ((port_mask & (1 << portid)) == 0) 1658ce8d5614SIntel continue; 1659ce8d5614SIntel memset(&link, 0, sizeof(link)); 1660ce8d5614SIntel rte_eth_link_get_nowait(portid, &link); 1661ce8d5614SIntel /* print link status if flag set */ 1662ce8d5614SIntel if (print_flag == 1) { 1663ce8d5614SIntel if (link.link_status) 1664ce8d5614SIntel printf("Port %d Link Up - speed %u " 1665ce8d5614SIntel "Mbps - %s\n", (uint8_t)portid, 1666ce8d5614SIntel (unsigned)link.link_speed, 1667ce8d5614SIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 1668ce8d5614SIntel ("full-duplex") : ("half-duplex\n")); 1669ce8d5614SIntel else 1670ce8d5614SIntel printf("Port %d Link Down\n", 1671ce8d5614SIntel (uint8_t)portid); 1672ce8d5614SIntel continue; 1673ce8d5614SIntel } 1674ce8d5614SIntel /* clear all_ports_up flag if any link down */ 1675ce8d5614SIntel if (link.link_status == 0) { 1676ce8d5614SIntel all_ports_up = 0; 1677ce8d5614SIntel break; 1678ce8d5614SIntel } 1679ce8d5614SIntel } 1680ce8d5614SIntel /* after finally printing all link status, get out */ 1681ce8d5614SIntel if (print_flag == 1) 1682ce8d5614SIntel break; 1683ce8d5614SIntel 1684ce8d5614SIntel if (all_ports_up == 0) { 1685ce8d5614SIntel fflush(stdout); 1686ce8d5614SIntel rte_delay_ms(CHECK_INTERVAL); 1687ce8d5614SIntel } 1688ce8d5614SIntel 1689ce8d5614SIntel /* set the print_flag if all ports up or timeout */ 1690ce8d5614SIntel if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) { 1691ce8d5614SIntel print_flag = 1; 1692ce8d5614SIntel } 1693ce8d5614SIntel } 1694af75078fSIntel } 1695af75078fSIntel 1696013af9b6SIntel static int 1697013af9b6SIntel set_tx_queue_stats_mapping_registers(uint8_t port_id, struct rte_port *port) 1698af75078fSIntel { 1699013af9b6SIntel uint16_t i; 1700af75078fSIntel int diag; 1701013af9b6SIntel uint8_t mapping_found = 0; 1702af75078fSIntel 1703013af9b6SIntel for (i = 0; i < nb_tx_queue_stats_mappings; i++) { 1704013af9b6SIntel if ((tx_queue_stats_mappings[i].port_id == port_id) && 1705013af9b6SIntel (tx_queue_stats_mappings[i].queue_id < nb_txq )) { 1706013af9b6SIntel diag = rte_eth_dev_set_tx_queue_stats_mapping(port_id, 1707013af9b6SIntel tx_queue_stats_mappings[i].queue_id, 1708013af9b6SIntel tx_queue_stats_mappings[i].stats_counter_id); 1709013af9b6SIntel if (diag != 0) 1710013af9b6SIntel return diag; 1711013af9b6SIntel mapping_found = 1; 1712af75078fSIntel } 1713013af9b6SIntel } 1714013af9b6SIntel if (mapping_found) 1715013af9b6SIntel port->tx_queue_stats_mapping_enabled = 1; 1716013af9b6SIntel return 0; 1717013af9b6SIntel } 1718013af9b6SIntel 1719013af9b6SIntel static int 1720013af9b6SIntel set_rx_queue_stats_mapping_registers(uint8_t port_id, struct rte_port *port) 1721013af9b6SIntel { 1722013af9b6SIntel uint16_t i; 1723013af9b6SIntel int diag; 1724013af9b6SIntel uint8_t mapping_found = 0; 1725013af9b6SIntel 1726013af9b6SIntel for (i = 0; i < nb_rx_queue_stats_mappings; i++) { 1727013af9b6SIntel if ((rx_queue_stats_mappings[i].port_id == port_id) && 1728013af9b6SIntel (rx_queue_stats_mappings[i].queue_id < nb_rxq )) { 1729013af9b6SIntel diag = rte_eth_dev_set_rx_queue_stats_mapping(port_id, 1730013af9b6SIntel rx_queue_stats_mappings[i].queue_id, 1731013af9b6SIntel rx_queue_stats_mappings[i].stats_counter_id); 1732013af9b6SIntel if (diag != 0) 1733013af9b6SIntel return diag; 1734013af9b6SIntel mapping_found = 1; 1735013af9b6SIntel } 1736013af9b6SIntel } 1737013af9b6SIntel if (mapping_found) 1738013af9b6SIntel port->rx_queue_stats_mapping_enabled = 1; 1739013af9b6SIntel return 0; 1740013af9b6SIntel } 1741013af9b6SIntel 1742013af9b6SIntel static void 1743013af9b6SIntel map_port_queue_stats_mapping_registers(uint8_t pi, struct rte_port *port) 1744013af9b6SIntel { 1745013af9b6SIntel int diag = 0; 1746013af9b6SIntel 1747013af9b6SIntel diag = set_tx_queue_stats_mapping_registers(pi, port); 1748af75078fSIntel if (diag != 0) { 1749013af9b6SIntel if (diag == -ENOTSUP) { 1750013af9b6SIntel port->tx_queue_stats_mapping_enabled = 0; 1751013af9b6SIntel printf("TX queue stats mapping not supported port id=%d\n", pi); 1752013af9b6SIntel } 1753013af9b6SIntel else 1754013af9b6SIntel rte_exit(EXIT_FAILURE, 1755013af9b6SIntel "set_tx_queue_stats_mapping_registers " 1756013af9b6SIntel "failed for port id=%d diag=%d\n", 1757af75078fSIntel pi, diag); 1758af75078fSIntel } 1759013af9b6SIntel 1760013af9b6SIntel diag = set_rx_queue_stats_mapping_registers(pi, port); 1761af75078fSIntel if (diag != 0) { 1762013af9b6SIntel if (diag == -ENOTSUP) { 1763013af9b6SIntel port->rx_queue_stats_mapping_enabled = 0; 1764013af9b6SIntel printf("RX queue stats mapping not supported port id=%d\n", pi); 1765013af9b6SIntel } 1766013af9b6SIntel else 1767013af9b6SIntel rte_exit(EXIT_FAILURE, 1768013af9b6SIntel "set_rx_queue_stats_mapping_registers " 1769013af9b6SIntel "failed for port id=%d diag=%d\n", 1770af75078fSIntel pi, diag); 1771af75078fSIntel } 1772af75078fSIntel } 1773af75078fSIntel 1774f2c5125aSPablo de Lara static void 1775f2c5125aSPablo de Lara rxtx_port_config(struct rte_port *port) 1776f2c5125aSPablo de Lara { 1777f2c5125aSPablo de Lara port->rx_conf = port->dev_info.default_rxconf; 1778f2c5125aSPablo de Lara port->tx_conf = port->dev_info.default_txconf; 1779f2c5125aSPablo de Lara 1780f2c5125aSPablo de Lara /* Check if any RX/TX parameters have been passed */ 1781f2c5125aSPablo de Lara if (rx_pthresh != RTE_PMD_PARAM_UNSET) 1782f2c5125aSPablo de Lara port->rx_conf.rx_thresh.pthresh = rx_pthresh; 1783f2c5125aSPablo de Lara 1784f2c5125aSPablo de Lara if (rx_hthresh != RTE_PMD_PARAM_UNSET) 1785f2c5125aSPablo de Lara port->rx_conf.rx_thresh.hthresh = rx_hthresh; 1786f2c5125aSPablo de Lara 1787f2c5125aSPablo de Lara if (rx_wthresh != RTE_PMD_PARAM_UNSET) 1788f2c5125aSPablo de Lara port->rx_conf.rx_thresh.wthresh = rx_wthresh; 1789f2c5125aSPablo de Lara 1790f2c5125aSPablo de Lara if (rx_free_thresh != RTE_PMD_PARAM_UNSET) 1791f2c5125aSPablo de Lara port->rx_conf.rx_free_thresh = rx_free_thresh; 1792f2c5125aSPablo de Lara 1793f2c5125aSPablo de Lara if (rx_drop_en != RTE_PMD_PARAM_UNSET) 1794f2c5125aSPablo de Lara port->rx_conf.rx_drop_en = rx_drop_en; 1795f2c5125aSPablo de Lara 1796f2c5125aSPablo de Lara if (tx_pthresh != RTE_PMD_PARAM_UNSET) 1797f2c5125aSPablo de Lara port->tx_conf.tx_thresh.pthresh = tx_pthresh; 1798f2c5125aSPablo de Lara 1799f2c5125aSPablo de Lara if (tx_hthresh != RTE_PMD_PARAM_UNSET) 1800f2c5125aSPablo de Lara port->tx_conf.tx_thresh.hthresh = tx_hthresh; 1801f2c5125aSPablo de Lara 1802f2c5125aSPablo de Lara if (tx_wthresh != RTE_PMD_PARAM_UNSET) 1803f2c5125aSPablo de Lara port->tx_conf.tx_thresh.wthresh = tx_wthresh; 1804f2c5125aSPablo de Lara 1805f2c5125aSPablo de Lara if (tx_rs_thresh != RTE_PMD_PARAM_UNSET) 1806f2c5125aSPablo de Lara port->tx_conf.tx_rs_thresh = tx_rs_thresh; 1807f2c5125aSPablo de Lara 1808f2c5125aSPablo de Lara if (tx_free_thresh != RTE_PMD_PARAM_UNSET) 1809f2c5125aSPablo de Lara port->tx_conf.tx_free_thresh = tx_free_thresh; 1810f2c5125aSPablo de Lara 1811f2c5125aSPablo de Lara if (txq_flags != RTE_PMD_PARAM_UNSET) 1812f2c5125aSPablo de Lara port->tx_conf.txq_flags = txq_flags; 1813f2c5125aSPablo de Lara } 1814f2c5125aSPablo de Lara 1815013af9b6SIntel void 1816013af9b6SIntel init_port_config(void) 1817013af9b6SIntel { 1818013af9b6SIntel portid_t pid; 1819013af9b6SIntel struct rte_port *port; 1820013af9b6SIntel 1821edab33b1STetsuya Mukawa FOREACH_PORT(pid, ports) { 1822013af9b6SIntel port = &ports[pid]; 1823013af9b6SIntel port->dev_conf.rxmode = rx_mode; 1824013af9b6SIntel port->dev_conf.fdir_conf = fdir_conf; 18253ce690d3SBruce Richardson if (nb_rxq > 1) { 1826013af9b6SIntel port->dev_conf.rx_adv_conf.rss_conf.rss_key = NULL; 1827013af9b6SIntel port->dev_conf.rx_adv_conf.rss_conf.rss_hf = rss_hf; 1828af75078fSIntel } else { 1829013af9b6SIntel port->dev_conf.rx_adv_conf.rss_conf.rss_key = NULL; 1830013af9b6SIntel port->dev_conf.rx_adv_conf.rss_conf.rss_hf = 0; 1831af75078fSIntel } 18323ce690d3SBruce Richardson 18333ce690d3SBruce Richardson if (port->dcb_flag == 0 && port->dev_info.max_vfs == 0) { 18343ce690d3SBruce Richardson if( port->dev_conf.rx_adv_conf.rss_conf.rss_hf != 0) 18353ce690d3SBruce Richardson port->dev_conf.rxmode.mq_mode = ETH_MQ_RX_RSS; 18363ce690d3SBruce Richardson else 18373ce690d3SBruce Richardson port->dev_conf.rxmode.mq_mode = ETH_MQ_RX_NONE; 18383ce690d3SBruce Richardson } 18393ce690d3SBruce Richardson 1840a30979f6SOuyang Changchun if (port->dev_info.max_vfs != 0) { 1841a30979f6SOuyang Changchun if (port->dev_conf.rx_adv_conf.rss_conf.rss_hf != 0) 1842a30979f6SOuyang Changchun port->dev_conf.rxmode.mq_mode = 1843a30979f6SOuyang Changchun ETH_MQ_RX_VMDQ_RSS; 1844a30979f6SOuyang Changchun else 1845a30979f6SOuyang Changchun port->dev_conf.rxmode.mq_mode = 1846a30979f6SOuyang Changchun ETH_MQ_RX_NONE; 1847a30979f6SOuyang Changchun 1848a30979f6SOuyang Changchun port->dev_conf.txmode.mq_mode = ETH_MQ_TX_NONE; 1849a30979f6SOuyang Changchun } 1850a30979f6SOuyang Changchun 1851f2c5125aSPablo de Lara rxtx_port_config(port); 1852013af9b6SIntel 1853013af9b6SIntel rte_eth_macaddr_get(pid, &port->eth_addr); 1854013af9b6SIntel 1855013af9b6SIntel map_port_queue_stats_mapping_registers(pid, port); 18567b7e5ba7SIntel #ifdef RTE_NIC_BYPASS 18577b7e5ba7SIntel rte_eth_dev_bypass_init(pid); 18587b7e5ba7SIntel #endif 1859013af9b6SIntel } 1860013af9b6SIntel } 1861013af9b6SIntel 1862013af9b6SIntel const uint16_t vlan_tags[] = { 1863013af9b6SIntel 0, 1, 2, 3, 4, 5, 6, 7, 1864013af9b6SIntel 8, 9, 10, 11, 12, 13, 14, 15, 1865013af9b6SIntel 16, 17, 18, 19, 20, 21, 22, 23, 1866013af9b6SIntel 24, 25, 26, 27, 28, 29, 30, 31 1867013af9b6SIntel }; 1868013af9b6SIntel 1869013af9b6SIntel static int 1870013af9b6SIntel get_eth_dcb_conf(struct rte_eth_conf *eth_conf, struct dcb_config *dcb_conf) 1871013af9b6SIntel { 1872013af9b6SIntel uint8_t i; 1873af75078fSIntel 1874af75078fSIntel /* 1875013af9b6SIntel * Builds up the correct configuration for dcb+vt based on the vlan tags array 1876013af9b6SIntel * given above, and the number of traffic classes available for use. 1877af75078fSIntel */ 1878013af9b6SIntel if (dcb_conf->dcb_mode == DCB_VT_ENABLED) { 1879013af9b6SIntel struct rte_eth_vmdq_dcb_conf vmdq_rx_conf; 1880013af9b6SIntel struct rte_eth_vmdq_dcb_tx_conf vmdq_tx_conf; 1881013af9b6SIntel 1882013af9b6SIntel /* VMDQ+DCB RX and TX configrations */ 1883013af9b6SIntel vmdq_rx_conf.enable_default_pool = 0; 1884013af9b6SIntel vmdq_rx_conf.default_pool = 0; 1885013af9b6SIntel vmdq_rx_conf.nb_queue_pools = 1886013af9b6SIntel (dcb_conf->num_tcs == ETH_4_TCS ? ETH_32_POOLS : ETH_16_POOLS); 1887013af9b6SIntel vmdq_tx_conf.nb_queue_pools = 1888013af9b6SIntel (dcb_conf->num_tcs == ETH_4_TCS ? ETH_32_POOLS : ETH_16_POOLS); 1889013af9b6SIntel 1890013af9b6SIntel vmdq_rx_conf.nb_pool_maps = sizeof( vlan_tags )/sizeof( vlan_tags[ 0 ]); 1891013af9b6SIntel for (i = 0; i < vmdq_rx_conf.nb_pool_maps; i++) { 1892013af9b6SIntel vmdq_rx_conf.pool_map[i].vlan_id = vlan_tags[ i ]; 1893013af9b6SIntel vmdq_rx_conf.pool_map[i].pools = 1 << (i % vmdq_rx_conf.nb_queue_pools); 1894af75078fSIntel } 1895013af9b6SIntel for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) { 1896013af9b6SIntel vmdq_rx_conf.dcb_queue[i] = i; 1897013af9b6SIntel vmdq_tx_conf.dcb_queue[i] = i; 1898013af9b6SIntel } 1899013af9b6SIntel 1900013af9b6SIntel /*set DCB mode of RX and TX of multiple queues*/ 190132e7aa0bSIntel eth_conf->rxmode.mq_mode = ETH_MQ_RX_VMDQ_DCB; 190232e7aa0bSIntel eth_conf->txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 1903013af9b6SIntel if (dcb_conf->pfc_en) 1904013af9b6SIntel eth_conf->dcb_capability_en = ETH_DCB_PG_SUPPORT|ETH_DCB_PFC_SUPPORT; 1905013af9b6SIntel else 1906013af9b6SIntel eth_conf->dcb_capability_en = ETH_DCB_PG_SUPPORT; 1907013af9b6SIntel 1908013af9b6SIntel (void)(rte_memcpy(ð_conf->rx_adv_conf.vmdq_dcb_conf, &vmdq_rx_conf, 1909013af9b6SIntel sizeof(struct rte_eth_vmdq_dcb_conf))); 1910013af9b6SIntel (void)(rte_memcpy(ð_conf->tx_adv_conf.vmdq_dcb_tx_conf, &vmdq_tx_conf, 1911013af9b6SIntel sizeof(struct rte_eth_vmdq_dcb_tx_conf))); 1912013af9b6SIntel } 1913013af9b6SIntel else { 1914013af9b6SIntel struct rte_eth_dcb_rx_conf rx_conf; 1915013af9b6SIntel struct rte_eth_dcb_tx_conf tx_conf; 1916013af9b6SIntel 1917013af9b6SIntel /* queue mapping configuration of DCB RX and TX */ 1918013af9b6SIntel if (dcb_conf->num_tcs == ETH_4_TCS) 1919013af9b6SIntel dcb_q_mapping = DCB_4_TCS_Q_MAPPING; 1920013af9b6SIntel else 1921013af9b6SIntel dcb_q_mapping = DCB_8_TCS_Q_MAPPING; 1922013af9b6SIntel 1923013af9b6SIntel rx_conf.nb_tcs = dcb_conf->num_tcs; 1924013af9b6SIntel tx_conf.nb_tcs = dcb_conf->num_tcs; 1925013af9b6SIntel 1926013af9b6SIntel for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++){ 1927013af9b6SIntel rx_conf.dcb_queue[i] = i; 1928013af9b6SIntel tx_conf.dcb_queue[i] = i; 1929013af9b6SIntel } 193032e7aa0bSIntel eth_conf->rxmode.mq_mode = ETH_MQ_RX_DCB; 193132e7aa0bSIntel eth_conf->txmode.mq_mode = ETH_MQ_TX_DCB; 1932013af9b6SIntel if (dcb_conf->pfc_en) 1933013af9b6SIntel eth_conf->dcb_capability_en = ETH_DCB_PG_SUPPORT|ETH_DCB_PFC_SUPPORT; 1934013af9b6SIntel else 1935013af9b6SIntel eth_conf->dcb_capability_en = ETH_DCB_PG_SUPPORT; 1936013af9b6SIntel 1937013af9b6SIntel (void)(rte_memcpy(ð_conf->rx_adv_conf.dcb_rx_conf, &rx_conf, 1938013af9b6SIntel sizeof(struct rte_eth_dcb_rx_conf))); 1939013af9b6SIntel (void)(rte_memcpy(ð_conf->tx_adv_conf.dcb_tx_conf, &tx_conf, 1940013af9b6SIntel sizeof(struct rte_eth_dcb_tx_conf))); 1941013af9b6SIntel } 1942013af9b6SIntel 1943013af9b6SIntel return 0; 1944013af9b6SIntel } 1945013af9b6SIntel 1946013af9b6SIntel int 1947013af9b6SIntel init_port_dcb_config(portid_t pid,struct dcb_config *dcb_conf) 1948013af9b6SIntel { 1949013af9b6SIntel struct rte_eth_conf port_conf; 1950013af9b6SIntel struct rte_port *rte_port; 1951013af9b6SIntel int retval; 1952013af9b6SIntel uint16_t nb_vlan; 1953013af9b6SIntel uint16_t i; 1954013af9b6SIntel 1955013af9b6SIntel /* rxq and txq configuration in dcb mode */ 1956013af9b6SIntel nb_rxq = 128; 1957013af9b6SIntel nb_txq = 128; 1958013af9b6SIntel rx_free_thresh = 64; 1959013af9b6SIntel 1960013af9b6SIntel memset(&port_conf,0,sizeof(struct rte_eth_conf)); 1961013af9b6SIntel /* Enter DCB configuration status */ 1962013af9b6SIntel dcb_config = 1; 1963013af9b6SIntel 1964013af9b6SIntel nb_vlan = sizeof( vlan_tags )/sizeof( vlan_tags[ 0 ]); 1965013af9b6SIntel /*set configuration of DCB in vt mode and DCB in non-vt mode*/ 1966013af9b6SIntel retval = get_eth_dcb_conf(&port_conf, dcb_conf); 1967013af9b6SIntel if (retval < 0) 1968013af9b6SIntel return retval; 1969013af9b6SIntel 1970013af9b6SIntel rte_port = &ports[pid]; 1971013af9b6SIntel memcpy(&rte_port->dev_conf, &port_conf,sizeof(struct rte_eth_conf)); 1972013af9b6SIntel 1973f2c5125aSPablo de Lara rxtx_port_config(rte_port); 1974013af9b6SIntel /* VLAN filter */ 1975013af9b6SIntel rte_port->dev_conf.rxmode.hw_vlan_filter = 1; 1976013af9b6SIntel for (i = 0; i < nb_vlan; i++){ 1977013af9b6SIntel rx_vft_set(pid, vlan_tags[i], 1); 1978013af9b6SIntel } 1979013af9b6SIntel 1980013af9b6SIntel rte_eth_macaddr_get(pid, &rte_port->eth_addr); 1981013af9b6SIntel map_port_queue_stats_mapping_registers(pid, rte_port); 1982013af9b6SIntel 19837741e4cfSIntel rte_port->dcb_flag = 1; 19847741e4cfSIntel 1985013af9b6SIntel return 0; 1986af75078fSIntel } 1987af75078fSIntel 1988*ffc468ffSTetsuya Mukawa static void 1989*ffc468ffSTetsuya Mukawa init_port(void) 1990*ffc468ffSTetsuya Mukawa { 1991*ffc468ffSTetsuya Mukawa portid_t pid; 1992*ffc468ffSTetsuya Mukawa 1993*ffc468ffSTetsuya Mukawa /* Configuration of Ethernet ports. */ 1994*ffc468ffSTetsuya Mukawa ports = rte_zmalloc("testpmd: ports", 1995*ffc468ffSTetsuya Mukawa sizeof(struct rte_port) * RTE_MAX_ETHPORTS, 1996*ffc468ffSTetsuya Mukawa RTE_CACHE_LINE_SIZE); 1997*ffc468ffSTetsuya Mukawa if (ports == NULL) { 1998*ffc468ffSTetsuya Mukawa rte_exit(EXIT_FAILURE, 1999*ffc468ffSTetsuya Mukawa "rte_zmalloc(%d struct rte_port) failed\n", 2000*ffc468ffSTetsuya Mukawa RTE_MAX_ETHPORTS); 2001*ffc468ffSTetsuya Mukawa } 2002*ffc468ffSTetsuya Mukawa 2003*ffc468ffSTetsuya Mukawa /* enabled allocated ports */ 2004*ffc468ffSTetsuya Mukawa for (pid = 0; pid < nb_ports; pid++) 2005*ffc468ffSTetsuya Mukawa ports[pid].enabled = 1; 2006*ffc468ffSTetsuya Mukawa } 2007*ffc468ffSTetsuya Mukawa 2008af75078fSIntel int 2009af75078fSIntel main(int argc, char** argv) 2010af75078fSIntel { 2011af75078fSIntel int diag; 2012013af9b6SIntel uint8_t port_id; 2013af75078fSIntel 2014af75078fSIntel diag = rte_eal_init(argc, argv); 2015af75078fSIntel if (diag < 0) 2016af75078fSIntel rte_panic("Cannot init EAL\n"); 2017af75078fSIntel 2018af75078fSIntel nb_ports = (portid_t) rte_eth_dev_count(); 2019af75078fSIntel if (nb_ports == 0) 2020edab33b1STetsuya Mukawa RTE_LOG(WARNING, EAL, "No probed ethernet devices\n"); 2021af75078fSIntel 2022*ffc468ffSTetsuya Mukawa /* allocate port structures, and init them */ 2023*ffc468ffSTetsuya Mukawa init_port(); 2024*ffc468ffSTetsuya Mukawa 2025af75078fSIntel set_def_fwd_config(); 2026af75078fSIntel if (nb_lcores == 0) 2027af75078fSIntel rte_panic("Empty set of forwarding logical cores - check the " 2028af75078fSIntel "core mask supplied in the command parameters\n"); 2029af75078fSIntel 2030af75078fSIntel argc -= diag; 2031af75078fSIntel argv += diag; 2032af75078fSIntel if (argc > 1) 2033af75078fSIntel launch_args_parse(argc, argv); 2034af75078fSIntel 2035af75078fSIntel if (nb_rxq > nb_txq) 2036af75078fSIntel printf("Warning: nb_rxq=%d enables RSS configuration, " 2037af75078fSIntel "but nb_txq=%d will prevent to fully test it.\n", 2038af75078fSIntel nb_rxq, nb_txq); 2039af75078fSIntel 2040af75078fSIntel init_config(); 2041148f963fSBruce Richardson if (start_port(RTE_PORT_ALL) != 0) 2042148f963fSBruce Richardson rte_exit(EXIT_FAILURE, "Start ports failed\n"); 2043af75078fSIntel 2044ce8d5614SIntel /* set all ports to promiscuous mode by default */ 2045edab33b1STetsuya Mukawa FOREACH_PORT(port_id, ports) 2046ce8d5614SIntel rte_eth_promiscuous_enable(port_id); 2047af75078fSIntel 20480d56cb81SThomas Monjalon #ifdef RTE_LIBRTE_CMDLINE 2049ca7feb22SCyril Chemparathy if (interactive == 1) { 2050ca7feb22SCyril Chemparathy if (auto_start) { 2051ca7feb22SCyril Chemparathy printf("Start automatic packet forwarding\n"); 2052ca7feb22SCyril Chemparathy start_packet_forwarding(0); 2053ca7feb22SCyril Chemparathy } 2054af75078fSIntel prompt(); 2055ca7feb22SCyril Chemparathy } else 20560d56cb81SThomas Monjalon #endif 20570d56cb81SThomas Monjalon { 2058af75078fSIntel char c; 2059af75078fSIntel int rc; 2060af75078fSIntel 2061af75078fSIntel printf("No commandline core given, start packet forwarding\n"); 2062af75078fSIntel start_packet_forwarding(0); 2063af75078fSIntel printf("Press enter to exit\n"); 2064af75078fSIntel rc = read(0, &c, 1); 2065af75078fSIntel if (rc < 0) 2066af75078fSIntel return 1; 2067af75078fSIntel } 2068af75078fSIntel 2069af75078fSIntel return 0; 2070af75078fSIntel } 2071