1af75078fSIntel /*- 2af75078fSIntel * BSD LICENSE 3af75078fSIntel * 420718201SBernard Iremonger * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. 5af75078fSIntel * All rights reserved. 6af75078fSIntel * 7af75078fSIntel * Redistribution and use in source and binary forms, with or without 8af75078fSIntel * modification, are permitted provided that the following conditions 9af75078fSIntel * are met: 10af75078fSIntel * 11af75078fSIntel * * Redistributions of source code must retain the above copyright 12af75078fSIntel * notice, this list of conditions and the following disclaimer. 13af75078fSIntel * * Redistributions in binary form must reproduce the above copyright 14af75078fSIntel * notice, this list of conditions and the following disclaimer in 15af75078fSIntel * the documentation and/or other materials provided with the 16af75078fSIntel * distribution. 17af75078fSIntel * * Neither the name of Intel Corporation nor the names of its 18af75078fSIntel * contributors may be used to endorse or promote products derived 19af75078fSIntel * from this software without specific prior written permission. 20af75078fSIntel * 21af75078fSIntel * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22af75078fSIntel * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23af75078fSIntel * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24af75078fSIntel * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25af75078fSIntel * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26af75078fSIntel * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27af75078fSIntel * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28af75078fSIntel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29af75078fSIntel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30af75078fSIntel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31af75078fSIntel * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32af75078fSIntel */ 33af75078fSIntel 34af75078fSIntel #include <stdarg.h> 35af75078fSIntel #include <stdio.h> 36af75078fSIntel #include <stdlib.h> 37af75078fSIntel #include <signal.h> 38af75078fSIntel #include <string.h> 39af75078fSIntel #include <time.h> 40af75078fSIntel #include <fcntl.h> 41af75078fSIntel #include <sys/types.h> 42af75078fSIntel #include <errno.h> 43af75078fSIntel 44af75078fSIntel #include <sys/queue.h> 45af75078fSIntel #include <sys/stat.h> 46af75078fSIntel 47af75078fSIntel #include <stdint.h> 48af75078fSIntel #include <unistd.h> 49af75078fSIntel #include <inttypes.h> 50af75078fSIntel 51af75078fSIntel #include <rte_common.h> 52af75078fSIntel #include <rte_byteorder.h> 53af75078fSIntel #include <rte_log.h> 54af75078fSIntel #include <rte_debug.h> 55af75078fSIntel #include <rte_cycles.h> 56af75078fSIntel #include <rte_memory.h> 57af75078fSIntel #include <rte_memcpy.h> 58af75078fSIntel #include <rte_memzone.h> 59af75078fSIntel #include <rte_launch.h> 60af75078fSIntel #include <rte_eal.h> 61af75078fSIntel #include <rte_per_lcore.h> 62af75078fSIntel #include <rte_lcore.h> 63af75078fSIntel #include <rte_atomic.h> 64af75078fSIntel #include <rte_branch_prediction.h> 65af75078fSIntel #include <rte_ring.h> 66af75078fSIntel #include <rte_mempool.h> 67af75078fSIntel #include <rte_malloc.h> 68af75078fSIntel #include <rte_mbuf.h> 69af75078fSIntel #include <rte_interrupts.h> 70af75078fSIntel #include <rte_pci.h> 71af75078fSIntel #include <rte_ether.h> 72af75078fSIntel #include <rte_ethdev.h> 73edab33b1STetsuya Mukawa #include <rte_dev.h> 74af75078fSIntel #include <rte_string_fns.h> 75148f963fSBruce Richardson #ifdef RTE_LIBRTE_PMD_XENVIRT 76148f963fSBruce Richardson #include <rte_eth_xenvirt.h> 77148f963fSBruce Richardson #endif 78af75078fSIntel 79af75078fSIntel #include "testpmd.h" 80148f963fSBruce Richardson #include "mempool_osdep.h" 81af75078fSIntel 82af75078fSIntel uint16_t verbose_level = 0; /**< Silent by default. */ 83af75078fSIntel 84af75078fSIntel /* use master core for command line ? */ 85af75078fSIntel uint8_t interactive = 0; 86ca7feb22SCyril Chemparathy uint8_t auto_start = 0; 87af75078fSIntel 88af75078fSIntel /* 89af75078fSIntel * NUMA support configuration. 90af75078fSIntel * When set, the NUMA support attempts to dispatch the allocation of the 91af75078fSIntel * RX and TX memory rings, and of the DMA memory buffers (mbufs) for the 92af75078fSIntel * probed ports among the CPU sockets 0 and 1. 93af75078fSIntel * Otherwise, all memory is allocated from CPU socket 0. 94af75078fSIntel */ 95af75078fSIntel uint8_t numa_support = 0; /**< No numa support by default */ 96af75078fSIntel 97af75078fSIntel /* 98b6ea6408SIntel * In UMA mode,all memory is allocated from socket 0 if --socket-num is 99b6ea6408SIntel * not configured. 100b6ea6408SIntel */ 101b6ea6408SIntel uint8_t socket_num = UMA_NO_CONFIG; 102b6ea6408SIntel 103b6ea6408SIntel /* 104148f963fSBruce Richardson * Use ANONYMOUS mapped memory (might be not physically continuous) for mbufs. 105148f963fSBruce Richardson */ 106148f963fSBruce Richardson uint8_t mp_anon = 0; 107148f963fSBruce Richardson 108148f963fSBruce Richardson /* 109af75078fSIntel * Record the Ethernet address of peer target ports to which packets are 110af75078fSIntel * forwarded. 111af75078fSIntel * Must be instanciated with the ethernet addresses of peer traffic generator 112af75078fSIntel * ports. 113af75078fSIntel */ 114af75078fSIntel struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS]; 115af75078fSIntel portid_t nb_peer_eth_addrs = 0; 116af75078fSIntel 117af75078fSIntel /* 118af75078fSIntel * Probed Target Environment. 119af75078fSIntel */ 120af75078fSIntel struct rte_port *ports; /**< For all probed ethernet ports. */ 121af75078fSIntel portid_t nb_ports; /**< Number of probed ethernet ports. */ 122af75078fSIntel struct fwd_lcore **fwd_lcores; /**< For all probed logical cores. */ 123af75078fSIntel lcoreid_t nb_lcores; /**< Number of probed logical cores. */ 124af75078fSIntel 125af75078fSIntel /* 126af75078fSIntel * Test Forwarding Configuration. 127af75078fSIntel * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores 128af75078fSIntel * nb_fwd_ports <= nb_cfg_ports <= nb_ports 129af75078fSIntel */ 130af75078fSIntel lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */ 131af75078fSIntel lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */ 132af75078fSIntel portid_t nb_cfg_ports; /**< Number of configured ports. */ 133af75078fSIntel portid_t nb_fwd_ports; /**< Number of forwarding ports. */ 134af75078fSIntel 135af75078fSIntel unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE]; /**< CPU ids configuration. */ 136af75078fSIntel portid_t fwd_ports_ids[RTE_MAX_ETHPORTS]; /**< Port ids configuration. */ 137af75078fSIntel 138af75078fSIntel struct fwd_stream **fwd_streams; /**< For each RX queue of each port. */ 139af75078fSIntel streamid_t nb_fwd_streams; /**< Is equal to (nb_ports * nb_rxq). */ 140af75078fSIntel 141af75078fSIntel /* 142af75078fSIntel * Forwarding engines. 143af75078fSIntel */ 144af75078fSIntel struct fwd_engine * fwd_engines[] = { 145af75078fSIntel &io_fwd_engine, 146af75078fSIntel &mac_fwd_engine, 14757e85242SBruce Richardson &mac_retry_fwd_engine, 148d47388f1SCyril Chemparathy &mac_swap_engine, 149e9e23a61SCyril Chemparathy &flow_gen_engine, 150af75078fSIntel &rx_only_engine, 151af75078fSIntel &tx_only_engine, 152af75078fSIntel &csum_fwd_engine, 153168dfa61SIvan Boule &icmp_echo_engine, 154af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588 155af75078fSIntel &ieee1588_fwd_engine, 156af75078fSIntel #endif 157af75078fSIntel NULL, 158af75078fSIntel }; 159af75078fSIntel 160af75078fSIntel struct fwd_config cur_fwd_config; 161af75078fSIntel struct fwd_engine *cur_fwd_eng = &io_fwd_engine; /**< IO mode by default. */ 162af75078fSIntel 163af75078fSIntel uint16_t mbuf_data_size = DEFAULT_MBUF_DATA_SIZE; /**< Mbuf data space size. */ 164c8798818SIntel uint32_t param_total_num_mbufs = 0; /**< number of mbufs in all pools - if 165c8798818SIntel * specified on command-line. */ 166af75078fSIntel 167af75078fSIntel /* 168af75078fSIntel * Configuration of packet segments used by the "txonly" processing engine. 169af75078fSIntel */ 170af75078fSIntel uint16_t tx_pkt_length = TXONLY_DEF_PACKET_LEN; /**< TXONLY packet length. */ 171af75078fSIntel uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT] = { 172af75078fSIntel TXONLY_DEF_PACKET_LEN, 173af75078fSIntel }; 174af75078fSIntel uint8_t tx_pkt_nb_segs = 1; /**< Number of segments in TXONLY packets */ 175af75078fSIntel 17679bec05bSKonstantin Ananyev enum tx_pkt_split tx_pkt_split = TX_PKT_SPLIT_OFF; 17779bec05bSKonstantin Ananyev /**< Split policy for packets to TX. */ 17879bec05bSKonstantin Ananyev 179af75078fSIntel uint16_t nb_pkt_per_burst = DEF_PKT_BURST; /**< Number of packets per burst. */ 180e9378bbcSCunming Liang uint16_t mb_mempool_cache = DEF_MBUF_CACHE; /**< Size of mbuf mempool cache. */ 181af75078fSIntel 182900550deSIntel /* current configuration is in DCB or not,0 means it is not in DCB mode */ 183900550deSIntel uint8_t dcb_config = 0; 184900550deSIntel 185900550deSIntel /* Whether the dcb is in testing status */ 186900550deSIntel uint8_t dcb_test = 0; 187900550deSIntel 188af75078fSIntel /* 189af75078fSIntel * Configurable number of RX/TX queues. 190af75078fSIntel */ 191af75078fSIntel queueid_t nb_rxq = 1; /**< Number of RX queues per port. */ 192af75078fSIntel queueid_t nb_txq = 1; /**< Number of TX queues per port. */ 193af75078fSIntel 194af75078fSIntel /* 195af75078fSIntel * Configurable number of RX/TX ring descriptors. 196af75078fSIntel */ 197af75078fSIntel #define RTE_TEST_RX_DESC_DEFAULT 128 198af75078fSIntel #define RTE_TEST_TX_DESC_DEFAULT 512 199af75078fSIntel uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT; /**< Number of RX descriptors. */ 200af75078fSIntel uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT; /**< Number of TX descriptors. */ 201af75078fSIntel 202f2c5125aSPablo de Lara #define RTE_PMD_PARAM_UNSET -1 203af75078fSIntel /* 204af75078fSIntel * Configurable values of RX and TX ring threshold registers. 205af75078fSIntel */ 206af75078fSIntel 207f2c5125aSPablo de Lara int8_t rx_pthresh = RTE_PMD_PARAM_UNSET; 208f2c5125aSPablo de Lara int8_t rx_hthresh = RTE_PMD_PARAM_UNSET; 209f2c5125aSPablo de Lara int8_t rx_wthresh = RTE_PMD_PARAM_UNSET; 210af75078fSIntel 211f2c5125aSPablo de Lara int8_t tx_pthresh = RTE_PMD_PARAM_UNSET; 212f2c5125aSPablo de Lara int8_t tx_hthresh = RTE_PMD_PARAM_UNSET; 213f2c5125aSPablo de Lara int8_t tx_wthresh = RTE_PMD_PARAM_UNSET; 214af75078fSIntel 215af75078fSIntel /* 216af75078fSIntel * Configurable value of RX free threshold. 217af75078fSIntel */ 218f2c5125aSPablo de Lara int16_t rx_free_thresh = RTE_PMD_PARAM_UNSET; 219af75078fSIntel 220af75078fSIntel /* 221ce8d5614SIntel * Configurable value of RX drop enable. 222ce8d5614SIntel */ 223f2c5125aSPablo de Lara int8_t rx_drop_en = RTE_PMD_PARAM_UNSET; 224ce8d5614SIntel 225ce8d5614SIntel /* 226af75078fSIntel * Configurable value of TX free threshold. 227af75078fSIntel */ 228f2c5125aSPablo de Lara int16_t tx_free_thresh = RTE_PMD_PARAM_UNSET; 229af75078fSIntel 230af75078fSIntel /* 231af75078fSIntel * Configurable value of TX RS bit threshold. 232af75078fSIntel */ 233f2c5125aSPablo de Lara int16_t tx_rs_thresh = RTE_PMD_PARAM_UNSET; 234af75078fSIntel 235af75078fSIntel /* 236ce8d5614SIntel * Configurable value of TX queue flags. 237ce8d5614SIntel */ 238f2c5125aSPablo de Lara int32_t txq_flags = RTE_PMD_PARAM_UNSET; 239ce8d5614SIntel 240ce8d5614SIntel /* 241af75078fSIntel * Receive Side Scaling (RSS) configuration. 242af75078fSIntel */ 2438a387fa8SHelin Zhang uint64_t rss_hf = ETH_RSS_IP; /* RSS IP by default. */ 244af75078fSIntel 245af75078fSIntel /* 246af75078fSIntel * Port topology configuration 247af75078fSIntel */ 248af75078fSIntel uint16_t port_topology = PORT_TOPOLOGY_PAIRED; /* Ports are paired by default */ 249af75078fSIntel 2507741e4cfSIntel /* 2517741e4cfSIntel * Avoids to flush all the RX streams before starts forwarding. 2527741e4cfSIntel */ 2537741e4cfSIntel uint8_t no_flush_rx = 0; /* flush by default */ 2547741e4cfSIntel 255af75078fSIntel /* 256bc202406SDavid Marchand * Avoids to check link status when starting/stopping a port. 257bc202406SDavid Marchand */ 258bc202406SDavid Marchand uint8_t no_link_check = 0; /* check by default */ 259bc202406SDavid Marchand 260bc202406SDavid Marchand /* 2617b7e5ba7SIntel * NIC bypass mode configuration options. 2627b7e5ba7SIntel */ 2637b7e5ba7SIntel #ifdef RTE_NIC_BYPASS 2647b7e5ba7SIntel 2657b7e5ba7SIntel /* The NIC bypass watchdog timeout. */ 2667b7e5ba7SIntel uint32_t bypass_timeout = RTE_BYPASS_TMT_OFF; 2677b7e5ba7SIntel 2687b7e5ba7SIntel #endif 2697b7e5ba7SIntel 2707b7e5ba7SIntel /* 271af75078fSIntel * Ethernet device configuration. 272af75078fSIntel */ 273af75078fSIntel struct rte_eth_rxmode rx_mode = { 274af75078fSIntel .max_rx_pkt_len = ETHER_MAX_LEN, /**< Default maximum frame length. */ 275af75078fSIntel .split_hdr_size = 0, 276af75078fSIntel .header_split = 0, /**< Header Split disabled. */ 277af75078fSIntel .hw_ip_checksum = 0, /**< IP checksum offload disabled. */ 278af75078fSIntel .hw_vlan_filter = 1, /**< VLAN filtering enabled. */ 279a47aa8b9SIntel .hw_vlan_strip = 1, /**< VLAN strip enabled. */ 280a47aa8b9SIntel .hw_vlan_extend = 0, /**< Extended VLAN disabled. */ 281af75078fSIntel .jumbo_frame = 0, /**< Jumbo Frame Support disabled. */ 282af75078fSIntel .hw_strip_crc = 0, /**< CRC stripping by hardware disabled. */ 283af75078fSIntel }; 284af75078fSIntel 285af75078fSIntel struct rte_fdir_conf fdir_conf = { 286af75078fSIntel .mode = RTE_FDIR_MODE_NONE, 287af75078fSIntel .pballoc = RTE_FDIR_PBALLOC_64K, 288af75078fSIntel .status = RTE_FDIR_REPORT_STATUS, 289d9d5e6f2SJingjing Wu .mask = { 290d9d5e6f2SJingjing Wu .vlan_tci_mask = 0x0, 291d9d5e6f2SJingjing Wu .ipv4_mask = { 292d9d5e6f2SJingjing Wu .src_ip = 0xFFFFFFFF, 293d9d5e6f2SJingjing Wu .dst_ip = 0xFFFFFFFF, 294d9d5e6f2SJingjing Wu }, 295d9d5e6f2SJingjing Wu .ipv6_mask = { 296d9d5e6f2SJingjing Wu .src_ip = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 297d9d5e6f2SJingjing Wu .dst_ip = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, 298d9d5e6f2SJingjing Wu }, 299d9d5e6f2SJingjing Wu .src_port_mask = 0xFFFF, 300d9d5e6f2SJingjing Wu .dst_port_mask = 0xFFFF, 30147b3ac6bSWenzhuo Lu .mac_addr_byte_mask = 0xFF, 30247b3ac6bSWenzhuo Lu .tunnel_type_mask = 1, 30347b3ac6bSWenzhuo Lu .tunnel_id_mask = 0xFFFFFFFF, 304d9d5e6f2SJingjing Wu }, 305af75078fSIntel .drop_queue = 127, 306af75078fSIntel }; 307af75078fSIntel 3082950a769SDeclan Doherty volatile int test_done = 1; /* stop packet forwarding when set to 1. */ 309af75078fSIntel 310ed30d9b6SIntel struct queue_stats_mappings tx_queue_stats_mappings_array[MAX_TX_QUEUE_STATS_MAPPINGS]; 311ed30d9b6SIntel struct queue_stats_mappings rx_queue_stats_mappings_array[MAX_RX_QUEUE_STATS_MAPPINGS]; 312ed30d9b6SIntel 313ed30d9b6SIntel struct queue_stats_mappings *tx_queue_stats_mappings = tx_queue_stats_mappings_array; 314ed30d9b6SIntel struct queue_stats_mappings *rx_queue_stats_mappings = rx_queue_stats_mappings_array; 315ed30d9b6SIntel 316ed30d9b6SIntel uint16_t nb_tx_queue_stats_mappings = 0; 317ed30d9b6SIntel uint16_t nb_rx_queue_stats_mappings = 0; 318ed30d9b6SIntel 3197acf894dSStephen Hurd unsigned max_socket = 0; 3207acf894dSStephen Hurd 321ed30d9b6SIntel /* Forward function declarations */ 322ed30d9b6SIntel static void map_port_queue_stats_mapping_registers(uint8_t pi, struct rte_port *port); 323edab33b1STetsuya Mukawa static void check_all_ports_link_status(uint32_t port_mask); 324ce8d5614SIntel 325ce8d5614SIntel /* 326ce8d5614SIntel * Check if all the ports are started. 327ce8d5614SIntel * If yes, return positive value. If not, return zero. 328ce8d5614SIntel */ 329ce8d5614SIntel static int all_ports_started(void); 330ed30d9b6SIntel 331af75078fSIntel /* 332edab33b1STetsuya Mukawa * Find next enabled port 333edab33b1STetsuya Mukawa */ 334edab33b1STetsuya Mukawa portid_t 335edab33b1STetsuya Mukawa find_next_port(portid_t p, struct rte_port *ports, int size) 336edab33b1STetsuya Mukawa { 337edab33b1STetsuya Mukawa if (ports == NULL) 338edab33b1STetsuya Mukawa rte_exit(-EINVAL, "failed to find a next port id\n"); 339edab33b1STetsuya Mukawa 34012a8e30fSJulien Cretin while ((p < size) && (ports[p].enabled == 0)) 341edab33b1STetsuya Mukawa p++; 342edab33b1STetsuya Mukawa return p; 343edab33b1STetsuya Mukawa } 344edab33b1STetsuya Mukawa 345edab33b1STetsuya Mukawa /* 346af75078fSIntel * Setup default configuration. 347af75078fSIntel */ 348af75078fSIntel static void 349af75078fSIntel set_default_fwd_lcores_config(void) 350af75078fSIntel { 351af75078fSIntel unsigned int i; 352af75078fSIntel unsigned int nb_lc; 3537acf894dSStephen Hurd unsigned int sock_num; 354af75078fSIntel 355af75078fSIntel nb_lc = 0; 356af75078fSIntel for (i = 0; i < RTE_MAX_LCORE; i++) { 3577acf894dSStephen Hurd sock_num = rte_lcore_to_socket_id(i) + 1; 3587acf894dSStephen Hurd if (sock_num > max_socket) { 3597acf894dSStephen Hurd if (sock_num > RTE_MAX_NUMA_NODES) 3607acf894dSStephen Hurd rte_exit(EXIT_FAILURE, "Total sockets greater than %u\n", RTE_MAX_NUMA_NODES); 3617acf894dSStephen Hurd max_socket = sock_num; 3627acf894dSStephen Hurd } 363*f54fe5eeSStephen Hurd if (!rte_lcore_is_enabled(i)) 364*f54fe5eeSStephen Hurd continue; 365*f54fe5eeSStephen Hurd if (i == rte_get_master_lcore()) 366*f54fe5eeSStephen Hurd continue; 367*f54fe5eeSStephen Hurd fwd_lcores_cpuids[nb_lc++] = i; 368af75078fSIntel } 369af75078fSIntel nb_lcores = (lcoreid_t) nb_lc; 370af75078fSIntel nb_cfg_lcores = nb_lcores; 371af75078fSIntel nb_fwd_lcores = 1; 372af75078fSIntel } 373af75078fSIntel 374af75078fSIntel static void 375af75078fSIntel set_def_peer_eth_addrs(void) 376af75078fSIntel { 377af75078fSIntel portid_t i; 378af75078fSIntel 379af75078fSIntel for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 380af75078fSIntel peer_eth_addrs[i].addr_bytes[0] = ETHER_LOCAL_ADMIN_ADDR; 381af75078fSIntel peer_eth_addrs[i].addr_bytes[5] = i; 382af75078fSIntel } 383af75078fSIntel } 384af75078fSIntel 385af75078fSIntel static void 386af75078fSIntel set_default_fwd_ports_config(void) 387af75078fSIntel { 388af75078fSIntel portid_t pt_id; 389af75078fSIntel 390af75078fSIntel for (pt_id = 0; pt_id < nb_ports; pt_id++) 391af75078fSIntel fwd_ports_ids[pt_id] = pt_id; 392af75078fSIntel 393af75078fSIntel nb_cfg_ports = nb_ports; 394af75078fSIntel nb_fwd_ports = nb_ports; 395af75078fSIntel } 396af75078fSIntel 397af75078fSIntel void 398af75078fSIntel set_def_fwd_config(void) 399af75078fSIntel { 400af75078fSIntel set_default_fwd_lcores_config(); 401af75078fSIntel set_def_peer_eth_addrs(); 402af75078fSIntel set_default_fwd_ports_config(); 403af75078fSIntel } 404af75078fSIntel 405af75078fSIntel /* 406af75078fSIntel * Configuration initialisation done once at init time. 407af75078fSIntel */ 408af75078fSIntel static void 409af75078fSIntel mbuf_pool_create(uint16_t mbuf_seg_size, unsigned nb_mbuf, 410af75078fSIntel unsigned int socket_id) 411af75078fSIntel { 412af75078fSIntel char pool_name[RTE_MEMPOOL_NAMESIZE]; 413af75078fSIntel struct rte_mempool *rte_mp; 414af75078fSIntel uint32_t mb_size; 415af75078fSIntel 416dfb03bbeSOlivier Matz mb_size = sizeof(struct rte_mbuf) + mbuf_seg_size; 417af75078fSIntel mbuf_poolname_build(socket_id, pool_name, sizeof(pool_name)); 418148f963fSBruce Richardson 419148f963fSBruce Richardson #ifdef RTE_LIBRTE_PMD_XENVIRT 420148f963fSBruce Richardson rte_mp = rte_mempool_gntalloc_create(pool_name, nb_mbuf, mb_size, 421af75078fSIntel (unsigned) mb_mempool_cache, 422af75078fSIntel sizeof(struct rte_pktmbuf_pool_private), 423dfb03bbeSOlivier Matz rte_pktmbuf_pool_init, NULL, 424dfb03bbeSOlivier Matz rte_pktmbuf_init, NULL, 425af75078fSIntel socket_id, 0); 426148f963fSBruce Richardson 427148f963fSBruce Richardson 428148f963fSBruce Richardson 429148f963fSBruce Richardson #else 430148f963fSBruce Richardson if (mp_anon != 0) 431148f963fSBruce Richardson rte_mp = mempool_anon_create(pool_name, nb_mbuf, mb_size, 432148f963fSBruce Richardson (unsigned) mb_mempool_cache, 433148f963fSBruce Richardson sizeof(struct rte_pktmbuf_pool_private), 434dfb03bbeSOlivier Matz rte_pktmbuf_pool_init, NULL, 435dfb03bbeSOlivier Matz rte_pktmbuf_init, NULL, 436148f963fSBruce Richardson socket_id, 0); 437148f963fSBruce Richardson else 438ea0c20eaSOlivier Matz /* wrapper to rte_mempool_create() */ 439ea0c20eaSOlivier Matz rte_mp = rte_pktmbuf_pool_create(pool_name, nb_mbuf, 440ea0c20eaSOlivier Matz mb_mempool_cache, 0, mbuf_seg_size, socket_id); 441148f963fSBruce Richardson 442148f963fSBruce Richardson #endif 443148f963fSBruce Richardson 444af75078fSIntel if (rte_mp == NULL) { 445ce8d5614SIntel rte_exit(EXIT_FAILURE, "Creation of mbuf pool for socket %u " 446ce8d5614SIntel "failed\n", socket_id); 447148f963fSBruce Richardson } else if (verbose_level > 0) { 448591a9d79SStephen Hemminger rte_mempool_dump(stdout, rte_mp); 449af75078fSIntel } 450af75078fSIntel } 451af75078fSIntel 45220a0286fSLiu Xiaofeng /* 45320a0286fSLiu Xiaofeng * Check given socket id is valid or not with NUMA mode, 45420a0286fSLiu Xiaofeng * if valid, return 0, else return -1 45520a0286fSLiu Xiaofeng */ 45620a0286fSLiu Xiaofeng static int 45720a0286fSLiu Xiaofeng check_socket_id(const unsigned int socket_id) 45820a0286fSLiu Xiaofeng { 45920a0286fSLiu Xiaofeng static int warning_once = 0; 46020a0286fSLiu Xiaofeng 4617acf894dSStephen Hurd if (socket_id >= max_socket) { 46220a0286fSLiu Xiaofeng if (!warning_once && numa_support) 46320a0286fSLiu Xiaofeng printf("Warning: NUMA should be configured manually by" 46420a0286fSLiu Xiaofeng " using --port-numa-config and" 46520a0286fSLiu Xiaofeng " --ring-numa-config parameters along with" 46620a0286fSLiu Xiaofeng " --numa.\n"); 46720a0286fSLiu Xiaofeng warning_once = 1; 46820a0286fSLiu Xiaofeng return -1; 46920a0286fSLiu Xiaofeng } 47020a0286fSLiu Xiaofeng return 0; 47120a0286fSLiu Xiaofeng } 47220a0286fSLiu Xiaofeng 473af75078fSIntel static void 474af75078fSIntel init_config(void) 475af75078fSIntel { 476ce8d5614SIntel portid_t pid; 477af75078fSIntel struct rte_port *port; 478af75078fSIntel struct rte_mempool *mbp; 479af75078fSIntel unsigned int nb_mbuf_per_pool; 480af75078fSIntel lcoreid_t lc_id; 4817acf894dSStephen Hurd uint8_t port_per_socket[RTE_MAX_NUMA_NODES]; 482af75078fSIntel 4837acf894dSStephen Hurd memset(port_per_socket,0,RTE_MAX_NUMA_NODES); 484af75078fSIntel /* Configuration of logical cores. */ 485af75078fSIntel fwd_lcores = rte_zmalloc("testpmd: fwd_lcores", 486af75078fSIntel sizeof(struct fwd_lcore *) * nb_lcores, 487fdf20fa7SSergio Gonzalez Monroy RTE_CACHE_LINE_SIZE); 488af75078fSIntel if (fwd_lcores == NULL) { 489ce8d5614SIntel rte_exit(EXIT_FAILURE, "rte_zmalloc(%d (struct fwd_lcore *)) " 490ce8d5614SIntel "failed\n", nb_lcores); 491af75078fSIntel } 492af75078fSIntel for (lc_id = 0; lc_id < nb_lcores; lc_id++) { 493af75078fSIntel fwd_lcores[lc_id] = rte_zmalloc("testpmd: struct fwd_lcore", 494af75078fSIntel sizeof(struct fwd_lcore), 495fdf20fa7SSergio Gonzalez Monroy RTE_CACHE_LINE_SIZE); 496af75078fSIntel if (fwd_lcores[lc_id] == NULL) { 497ce8d5614SIntel rte_exit(EXIT_FAILURE, "rte_zmalloc(struct fwd_lcore) " 498ce8d5614SIntel "failed\n"); 499af75078fSIntel } 500af75078fSIntel fwd_lcores[lc_id]->cpuid_idx = lc_id; 501af75078fSIntel } 502af75078fSIntel 503af75078fSIntel /* 504af75078fSIntel * Create pools of mbuf. 505af75078fSIntel * If NUMA support is disabled, create a single pool of mbuf in 506b6ea6408SIntel * socket 0 memory by default. 507af75078fSIntel * Otherwise, create a pool of mbuf in the memory of sockets 0 and 1. 508c8798818SIntel * 509c8798818SIntel * Use the maximum value of nb_rxd and nb_txd here, then nb_rxd and 510c8798818SIntel * nb_txd can be configured at run time. 511af75078fSIntel */ 512c8798818SIntel if (param_total_num_mbufs) 513c8798818SIntel nb_mbuf_per_pool = param_total_num_mbufs; 514c8798818SIntel else { 515c8798818SIntel nb_mbuf_per_pool = RTE_TEST_RX_DESC_MAX + (nb_lcores * mb_mempool_cache) 516c8798818SIntel + RTE_TEST_TX_DESC_MAX + MAX_PKT_BURST; 517b6ea6408SIntel 518b6ea6408SIntel if (!numa_support) 519edab33b1STetsuya Mukawa nb_mbuf_per_pool = 520edab33b1STetsuya Mukawa (nb_mbuf_per_pool * RTE_MAX_ETHPORTS); 521c8798818SIntel } 522af75078fSIntel 523b6ea6408SIntel if (!numa_support) { 524b6ea6408SIntel if (socket_num == UMA_NO_CONFIG) 525b6ea6408SIntel mbuf_pool_create(mbuf_data_size, nb_mbuf_per_pool, 0); 526b6ea6408SIntel else 527b6ea6408SIntel mbuf_pool_create(mbuf_data_size, nb_mbuf_per_pool, 528b6ea6408SIntel socket_num); 529b6ea6408SIntel } 530af75078fSIntel 531edab33b1STetsuya Mukawa FOREACH_PORT(pid, ports) { 532ce8d5614SIntel port = &ports[pid]; 533ce8d5614SIntel rte_eth_dev_info_get(pid, &port->dev_info); 534ce8d5614SIntel 535b6ea6408SIntel if (numa_support) { 536b6ea6408SIntel if (port_numa[pid] != NUMA_NO_CONFIG) 537b6ea6408SIntel port_per_socket[port_numa[pid]]++; 538b6ea6408SIntel else { 539b6ea6408SIntel uint32_t socket_id = rte_eth_dev_socket_id(pid); 54020a0286fSLiu Xiaofeng 54120a0286fSLiu Xiaofeng /* if socket_id is invalid, set to 0 */ 54220a0286fSLiu Xiaofeng if (check_socket_id(socket_id) < 0) 54320a0286fSLiu Xiaofeng socket_id = 0; 544b6ea6408SIntel port_per_socket[socket_id]++; 545b6ea6408SIntel } 546b6ea6408SIntel } 547b6ea6408SIntel 548ce8d5614SIntel /* set flag to initialize port/queue */ 549ce8d5614SIntel port->need_reconfig = 1; 550ce8d5614SIntel port->need_reconfig_queues = 1; 551ce8d5614SIntel } 552ce8d5614SIntel 553b6ea6408SIntel if (numa_support) { 554b6ea6408SIntel uint8_t i; 555b6ea6408SIntel unsigned int nb_mbuf; 556ce8d5614SIntel 557b6ea6408SIntel if (param_total_num_mbufs) 558b6ea6408SIntel nb_mbuf_per_pool = nb_mbuf_per_pool/nb_ports; 559b6ea6408SIntel 5607acf894dSStephen Hurd for (i = 0; i < max_socket; i++) { 561edab33b1STetsuya Mukawa nb_mbuf = (nb_mbuf_per_pool * RTE_MAX_ETHPORTS); 562b6ea6408SIntel if (nb_mbuf) 563b6ea6408SIntel mbuf_pool_create(mbuf_data_size, 564b6ea6408SIntel nb_mbuf,i); 565b6ea6408SIntel } 566b6ea6408SIntel } 567b6ea6408SIntel init_port_config(); 5685886ae07SAdrien Mazarguil 5695886ae07SAdrien Mazarguil /* 5705886ae07SAdrien Mazarguil * Records which Mbuf pool to use by each logical core, if needed. 5715886ae07SAdrien Mazarguil */ 5725886ae07SAdrien Mazarguil for (lc_id = 0; lc_id < nb_lcores; lc_id++) { 5738fd8bebcSAdrien Mazarguil mbp = mbuf_pool_find( 5748fd8bebcSAdrien Mazarguil rte_lcore_to_socket_id(fwd_lcores_cpuids[lc_id])); 5758fd8bebcSAdrien Mazarguil 5765886ae07SAdrien Mazarguil if (mbp == NULL) 5775886ae07SAdrien Mazarguil mbp = mbuf_pool_find(0); 5785886ae07SAdrien Mazarguil fwd_lcores[lc_id]->mbp = mbp; 5795886ae07SAdrien Mazarguil } 5805886ae07SAdrien Mazarguil 581ce8d5614SIntel /* Configuration of packet forwarding streams. */ 582ce8d5614SIntel if (init_fwd_streams() < 0) 583ce8d5614SIntel rte_exit(EXIT_FAILURE, "FAIL from init_fwd_streams()\n"); 584ce8d5614SIntel } 585ce8d5614SIntel 5862950a769SDeclan Doherty 5872950a769SDeclan Doherty void 588a21d5a4bSDeclan Doherty reconfig(portid_t new_port_id, unsigned socket_id) 5892950a769SDeclan Doherty { 5902950a769SDeclan Doherty struct rte_port *port; 5912950a769SDeclan Doherty 5922950a769SDeclan Doherty /* Reconfiguration of Ethernet ports. */ 5932950a769SDeclan Doherty port = &ports[new_port_id]; 5942950a769SDeclan Doherty rte_eth_dev_info_get(new_port_id, &port->dev_info); 5952950a769SDeclan Doherty 5962950a769SDeclan Doherty /* set flag to initialize port/queue */ 5972950a769SDeclan Doherty port->need_reconfig = 1; 5982950a769SDeclan Doherty port->need_reconfig_queues = 1; 599a21d5a4bSDeclan Doherty port->socket_id = socket_id; 6002950a769SDeclan Doherty 6012950a769SDeclan Doherty init_port_config(); 6022950a769SDeclan Doherty } 6032950a769SDeclan Doherty 6042950a769SDeclan Doherty 605ce8d5614SIntel int 606ce8d5614SIntel init_fwd_streams(void) 607ce8d5614SIntel { 608ce8d5614SIntel portid_t pid; 609ce8d5614SIntel struct rte_port *port; 610ce8d5614SIntel streamid_t sm_id, nb_fwd_streams_new; 611ce8d5614SIntel 612ce8d5614SIntel /* set socket id according to numa or not */ 613edab33b1STetsuya Mukawa FOREACH_PORT(pid, ports) { 614ce8d5614SIntel port = &ports[pid]; 615ce8d5614SIntel if (nb_rxq > port->dev_info.max_rx_queues) { 616ce8d5614SIntel printf("Fail: nb_rxq(%d) is greater than " 617ce8d5614SIntel "max_rx_queues(%d)\n", nb_rxq, 618ce8d5614SIntel port->dev_info.max_rx_queues); 619ce8d5614SIntel return -1; 620ce8d5614SIntel } 621ce8d5614SIntel if (nb_txq > port->dev_info.max_tx_queues) { 622ce8d5614SIntel printf("Fail: nb_txq(%d) is greater than " 623ce8d5614SIntel "max_tx_queues(%d)\n", nb_txq, 624ce8d5614SIntel port->dev_info.max_tx_queues); 625ce8d5614SIntel return -1; 626ce8d5614SIntel } 62720a0286fSLiu Xiaofeng if (numa_support) { 62820a0286fSLiu Xiaofeng if (port_numa[pid] != NUMA_NO_CONFIG) 62920a0286fSLiu Xiaofeng port->socket_id = port_numa[pid]; 63020a0286fSLiu Xiaofeng else { 631b6ea6408SIntel port->socket_id = rte_eth_dev_socket_id(pid); 63220a0286fSLiu Xiaofeng 63320a0286fSLiu Xiaofeng /* if socket_id is invalid, set to 0 */ 63420a0286fSLiu Xiaofeng if (check_socket_id(port->socket_id) < 0) 63520a0286fSLiu Xiaofeng port->socket_id = 0; 63620a0286fSLiu Xiaofeng } 63720a0286fSLiu Xiaofeng } 638b6ea6408SIntel else { 639b6ea6408SIntel if (socket_num == UMA_NO_CONFIG) 640af75078fSIntel port->socket_id = 0; 641b6ea6408SIntel else 642b6ea6408SIntel port->socket_id = socket_num; 643b6ea6408SIntel } 644af75078fSIntel } 645af75078fSIntel 646ce8d5614SIntel nb_fwd_streams_new = (streamid_t)(nb_ports * nb_rxq); 647ce8d5614SIntel if (nb_fwd_streams_new == nb_fwd_streams) 648ce8d5614SIntel return 0; 649ce8d5614SIntel /* clear the old */ 650ce8d5614SIntel if (fwd_streams != NULL) { 651ce8d5614SIntel for (sm_id = 0; sm_id < nb_fwd_streams; sm_id++) { 652ce8d5614SIntel if (fwd_streams[sm_id] == NULL) 653ce8d5614SIntel continue; 654ce8d5614SIntel rte_free(fwd_streams[sm_id]); 655ce8d5614SIntel fwd_streams[sm_id] = NULL; 656af75078fSIntel } 657ce8d5614SIntel rte_free(fwd_streams); 658ce8d5614SIntel fwd_streams = NULL; 659ce8d5614SIntel } 660ce8d5614SIntel 661ce8d5614SIntel /* init new */ 662ce8d5614SIntel nb_fwd_streams = nb_fwd_streams_new; 663ce8d5614SIntel fwd_streams = rte_zmalloc("testpmd: fwd_streams", 664fdf20fa7SSergio Gonzalez Monroy sizeof(struct fwd_stream *) * nb_fwd_streams, RTE_CACHE_LINE_SIZE); 665ce8d5614SIntel if (fwd_streams == NULL) 666ce8d5614SIntel rte_exit(EXIT_FAILURE, "rte_zmalloc(%d (struct fwd_stream *)) " 667ce8d5614SIntel "failed\n", nb_fwd_streams); 668ce8d5614SIntel 669af75078fSIntel for (sm_id = 0; sm_id < nb_fwd_streams; sm_id++) { 670af75078fSIntel fwd_streams[sm_id] = rte_zmalloc("testpmd: struct fwd_stream", 671fdf20fa7SSergio Gonzalez Monroy sizeof(struct fwd_stream), RTE_CACHE_LINE_SIZE); 672ce8d5614SIntel if (fwd_streams[sm_id] == NULL) 673ce8d5614SIntel rte_exit(EXIT_FAILURE, "rte_zmalloc(struct fwd_stream)" 674ce8d5614SIntel " failed\n"); 675af75078fSIntel } 676ce8d5614SIntel 677ce8d5614SIntel return 0; 678af75078fSIntel } 679af75078fSIntel 680af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 681af75078fSIntel static void 682af75078fSIntel pkt_burst_stats_display(const char *rx_tx, struct pkt_burst_stats *pbs) 683af75078fSIntel { 684af75078fSIntel unsigned int total_burst; 685af75078fSIntel unsigned int nb_burst; 686af75078fSIntel unsigned int burst_stats[3]; 687af75078fSIntel uint16_t pktnb_stats[3]; 688af75078fSIntel uint16_t nb_pkt; 689af75078fSIntel int burst_percent[3]; 690af75078fSIntel 691af75078fSIntel /* 692af75078fSIntel * First compute the total number of packet bursts and the 693af75078fSIntel * two highest numbers of bursts of the same number of packets. 694af75078fSIntel */ 695af75078fSIntel total_burst = 0; 696af75078fSIntel burst_stats[0] = burst_stats[1] = burst_stats[2] = 0; 697af75078fSIntel pktnb_stats[0] = pktnb_stats[1] = pktnb_stats[2] = 0; 698af75078fSIntel for (nb_pkt = 0; nb_pkt < MAX_PKT_BURST; nb_pkt++) { 699af75078fSIntel nb_burst = pbs->pkt_burst_spread[nb_pkt]; 700af75078fSIntel if (nb_burst == 0) 701af75078fSIntel continue; 702af75078fSIntel total_burst += nb_burst; 703af75078fSIntel if (nb_burst > burst_stats[0]) { 704af75078fSIntel burst_stats[1] = burst_stats[0]; 705af75078fSIntel pktnb_stats[1] = pktnb_stats[0]; 706af75078fSIntel burst_stats[0] = nb_burst; 707af75078fSIntel pktnb_stats[0] = nb_pkt; 708af75078fSIntel } 709af75078fSIntel } 710af75078fSIntel if (total_burst == 0) 711af75078fSIntel return; 712af75078fSIntel burst_percent[0] = (burst_stats[0] * 100) / total_burst; 713af75078fSIntel printf(" %s-bursts : %u [%d%% of %d pkts", rx_tx, total_burst, 714af75078fSIntel burst_percent[0], (int) pktnb_stats[0]); 715af75078fSIntel if (burst_stats[0] == total_burst) { 716af75078fSIntel printf("]\n"); 717af75078fSIntel return; 718af75078fSIntel } 719af75078fSIntel if (burst_stats[0] + burst_stats[1] == total_burst) { 720af75078fSIntel printf(" + %d%% of %d pkts]\n", 721af75078fSIntel 100 - burst_percent[0], pktnb_stats[1]); 722af75078fSIntel return; 723af75078fSIntel } 724af75078fSIntel burst_percent[1] = (burst_stats[1] * 100) / total_burst; 725af75078fSIntel burst_percent[2] = 100 - (burst_percent[0] + burst_percent[1]); 726af75078fSIntel if ((burst_percent[1] == 0) || (burst_percent[2] == 0)) { 727af75078fSIntel printf(" + %d%% of others]\n", 100 - burst_percent[0]); 728af75078fSIntel return; 729af75078fSIntel } 730af75078fSIntel printf(" + %d%% of %d pkts + %d%% of others]\n", 731af75078fSIntel burst_percent[1], (int) pktnb_stats[1], burst_percent[2]); 732af75078fSIntel } 733af75078fSIntel #endif /* RTE_TEST_PMD_RECORD_BURST_STATS */ 734af75078fSIntel 735af75078fSIntel static void 736af75078fSIntel fwd_port_stats_display(portid_t port_id, struct rte_eth_stats *stats) 737af75078fSIntel { 738af75078fSIntel struct rte_port *port; 739013af9b6SIntel uint8_t i; 740af75078fSIntel 741af75078fSIntel static const char *fwd_stats_border = "----------------------"; 742af75078fSIntel 743af75078fSIntel port = &ports[port_id]; 744af75078fSIntel printf("\n %s Forward statistics for port %-2d %s\n", 745af75078fSIntel fwd_stats_border, port_id, fwd_stats_border); 746013af9b6SIntel 747013af9b6SIntel if ((!port->rx_queue_stats_mapping_enabled) && (!port->tx_queue_stats_mapping_enabled)) { 748af75078fSIntel printf(" RX-packets: %-14"PRIu64" RX-dropped: %-14"PRIu64"RX-total: " 749af75078fSIntel "%-"PRIu64"\n", 75070bdb186SIvan Boule stats->ipackets, stats->imissed, 75170bdb186SIvan Boule (uint64_t) (stats->ipackets + stats->imissed)); 752af75078fSIntel 753af75078fSIntel if (cur_fwd_eng == &csum_fwd_engine) 754af75078fSIntel printf(" Bad-ipcsum: %-14"PRIu64" Bad-l4csum: %-14"PRIu64" \n", 755af75078fSIntel port->rx_bad_ip_csum, port->rx_bad_l4_csum); 75670bdb186SIvan Boule if (((stats->ierrors - stats->imissed) + stats->rx_nombuf) > 0) { 757f72a0fa6SStephen Hemminger printf(" RX-error: %-"PRIu64"\n", stats->ierrors); 75870bdb186SIvan Boule printf(" RX-nombufs: %-14"PRIu64"\n", stats->rx_nombuf); 75970bdb186SIvan Boule } 760af75078fSIntel 761af75078fSIntel printf(" TX-packets: %-14"PRIu64" TX-dropped: %-14"PRIu64"TX-total: " 762af75078fSIntel "%-"PRIu64"\n", 763af75078fSIntel stats->opackets, port->tx_dropped, 764af75078fSIntel (uint64_t) (stats->opackets + port->tx_dropped)); 765013af9b6SIntel } 766013af9b6SIntel else { 767013af9b6SIntel printf(" RX-packets: %14"PRIu64" RX-dropped:%14"PRIu64" RX-total:" 768013af9b6SIntel "%14"PRIu64"\n", 76970bdb186SIvan Boule stats->ipackets, stats->imissed, 77070bdb186SIvan Boule (uint64_t) (stats->ipackets + stats->imissed)); 771013af9b6SIntel 772013af9b6SIntel if (cur_fwd_eng == &csum_fwd_engine) 773013af9b6SIntel printf(" Bad-ipcsum:%14"PRIu64" Bad-l4csum:%14"PRIu64"\n", 774013af9b6SIntel port->rx_bad_ip_csum, port->rx_bad_l4_csum); 77570bdb186SIvan Boule if (((stats->ierrors - stats->imissed) + stats->rx_nombuf) > 0) { 776f72a0fa6SStephen Hemminger printf(" RX-error:%"PRIu64"\n", stats->ierrors); 77770bdb186SIvan Boule printf(" RX-nombufs: %14"PRIu64"\n", 77870bdb186SIvan Boule stats->rx_nombuf); 77970bdb186SIvan Boule } 780013af9b6SIntel 781013af9b6SIntel printf(" TX-packets: %14"PRIu64" TX-dropped:%14"PRIu64" TX-total:" 782013af9b6SIntel "%14"PRIu64"\n", 783013af9b6SIntel stats->opackets, port->tx_dropped, 784013af9b6SIntel (uint64_t) (stats->opackets + port->tx_dropped)); 785013af9b6SIntel } 786e659b6b4SIvan Boule 787af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 788af75078fSIntel if (port->rx_stream) 789013af9b6SIntel pkt_burst_stats_display("RX", 790013af9b6SIntel &port->rx_stream->rx_burst_stats); 791af75078fSIntel if (port->tx_stream) 792013af9b6SIntel pkt_burst_stats_display("TX", 793013af9b6SIntel &port->tx_stream->tx_burst_stats); 794af75078fSIntel #endif 795af75078fSIntel 796013af9b6SIntel if (port->rx_queue_stats_mapping_enabled) { 797013af9b6SIntel printf("\n"); 798013af9b6SIntel for (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) { 799013af9b6SIntel printf(" Stats reg %2d RX-packets:%14"PRIu64 800013af9b6SIntel " RX-errors:%14"PRIu64 801013af9b6SIntel " RX-bytes:%14"PRIu64"\n", 802013af9b6SIntel i, stats->q_ipackets[i], stats->q_errors[i], stats->q_ibytes[i]); 803013af9b6SIntel } 804013af9b6SIntel printf("\n"); 805013af9b6SIntel } 806013af9b6SIntel if (port->tx_queue_stats_mapping_enabled) { 807013af9b6SIntel for (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) { 808013af9b6SIntel printf(" Stats reg %2d TX-packets:%14"PRIu64 809013af9b6SIntel " TX-bytes:%14"PRIu64"\n", 810013af9b6SIntel i, stats->q_opackets[i], stats->q_obytes[i]); 811013af9b6SIntel } 812013af9b6SIntel } 813013af9b6SIntel 814af75078fSIntel printf(" %s--------------------------------%s\n", 815af75078fSIntel fwd_stats_border, fwd_stats_border); 816af75078fSIntel } 817af75078fSIntel 818af75078fSIntel static void 819af75078fSIntel fwd_stream_stats_display(streamid_t stream_id) 820af75078fSIntel { 821af75078fSIntel struct fwd_stream *fs; 822af75078fSIntel static const char *fwd_top_stats_border = "-------"; 823af75078fSIntel 824af75078fSIntel fs = fwd_streams[stream_id]; 825af75078fSIntel if ((fs->rx_packets == 0) && (fs->tx_packets == 0) && 826af75078fSIntel (fs->fwd_dropped == 0)) 827af75078fSIntel return; 828af75078fSIntel printf("\n %s Forward Stats for RX Port=%2d/Queue=%2d -> " 829af75078fSIntel "TX Port=%2d/Queue=%2d %s\n", 830af75078fSIntel fwd_top_stats_border, fs->rx_port, fs->rx_queue, 831af75078fSIntel fs->tx_port, fs->tx_queue, fwd_top_stats_border); 832af75078fSIntel printf(" RX-packets: %-14u TX-packets: %-14u TX-dropped: %-14u", 833af75078fSIntel fs->rx_packets, fs->tx_packets, fs->fwd_dropped); 834af75078fSIntel 835af75078fSIntel /* if checksum mode */ 836af75078fSIntel if (cur_fwd_eng == &csum_fwd_engine) { 837013af9b6SIntel printf(" RX- bad IP checksum: %-14u Rx- bad L4 checksum: " 838013af9b6SIntel "%-14u\n", fs->rx_bad_ip_csum, fs->rx_bad_l4_csum); 839af75078fSIntel } 840af75078fSIntel 841af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 842af75078fSIntel pkt_burst_stats_display("RX", &fs->rx_burst_stats); 843af75078fSIntel pkt_burst_stats_display("TX", &fs->tx_burst_stats); 844af75078fSIntel #endif 845af75078fSIntel } 846af75078fSIntel 847af75078fSIntel static void 8487741e4cfSIntel flush_fwd_rx_queues(void) 849af75078fSIntel { 850af75078fSIntel struct rte_mbuf *pkts_burst[MAX_PKT_BURST]; 851af75078fSIntel portid_t rxp; 8527741e4cfSIntel portid_t port_id; 853af75078fSIntel queueid_t rxq; 854af75078fSIntel uint16_t nb_rx; 855af75078fSIntel uint16_t i; 856af75078fSIntel uint8_t j; 857af75078fSIntel 858af75078fSIntel for (j = 0; j < 2; j++) { 8597741e4cfSIntel for (rxp = 0; rxp < cur_fwd_config.nb_fwd_ports; rxp++) { 860af75078fSIntel for (rxq = 0; rxq < nb_rxq; rxq++) { 8617741e4cfSIntel port_id = fwd_ports_ids[rxp]; 862af75078fSIntel do { 8637741e4cfSIntel nb_rx = rte_eth_rx_burst(port_id, rxq, 864013af9b6SIntel pkts_burst, MAX_PKT_BURST); 865af75078fSIntel for (i = 0; i < nb_rx; i++) 866af75078fSIntel rte_pktmbuf_free(pkts_burst[i]); 867af75078fSIntel } while (nb_rx > 0); 868af75078fSIntel } 869af75078fSIntel } 870af75078fSIntel rte_delay_ms(10); /* wait 10 milli-seconds before retrying */ 871af75078fSIntel } 872af75078fSIntel } 873af75078fSIntel 874af75078fSIntel static void 875af75078fSIntel run_pkt_fwd_on_lcore(struct fwd_lcore *fc, packet_fwd_t pkt_fwd) 876af75078fSIntel { 877af75078fSIntel struct fwd_stream **fsm; 878af75078fSIntel streamid_t nb_fs; 879af75078fSIntel streamid_t sm_id; 880af75078fSIntel 881af75078fSIntel fsm = &fwd_streams[fc->stream_idx]; 882af75078fSIntel nb_fs = fc->stream_nb; 883af75078fSIntel do { 884af75078fSIntel for (sm_id = 0; sm_id < nb_fs; sm_id++) 885af75078fSIntel (*pkt_fwd)(fsm[sm_id]); 886af75078fSIntel } while (! fc->stopped); 887af75078fSIntel } 888af75078fSIntel 889af75078fSIntel static int 890af75078fSIntel start_pkt_forward_on_core(void *fwd_arg) 891af75078fSIntel { 892af75078fSIntel run_pkt_fwd_on_lcore((struct fwd_lcore *) fwd_arg, 893af75078fSIntel cur_fwd_config.fwd_eng->packet_fwd); 894af75078fSIntel return 0; 895af75078fSIntel } 896af75078fSIntel 897af75078fSIntel /* 898af75078fSIntel * Run the TXONLY packet forwarding engine to send a single burst of packets. 899af75078fSIntel * Used to start communication flows in network loopback test configurations. 900af75078fSIntel */ 901af75078fSIntel static int 902af75078fSIntel run_one_txonly_burst_on_core(void *fwd_arg) 903af75078fSIntel { 904af75078fSIntel struct fwd_lcore *fwd_lc; 905af75078fSIntel struct fwd_lcore tmp_lcore; 906af75078fSIntel 907af75078fSIntel fwd_lc = (struct fwd_lcore *) fwd_arg; 908af75078fSIntel tmp_lcore = *fwd_lc; 909af75078fSIntel tmp_lcore.stopped = 1; 910af75078fSIntel run_pkt_fwd_on_lcore(&tmp_lcore, tx_only_engine.packet_fwd); 911af75078fSIntel return 0; 912af75078fSIntel } 913af75078fSIntel 914af75078fSIntel /* 915af75078fSIntel * Launch packet forwarding: 916af75078fSIntel * - Setup per-port forwarding context. 917af75078fSIntel * - launch logical cores with their forwarding configuration. 918af75078fSIntel */ 919af75078fSIntel static void 920af75078fSIntel launch_packet_forwarding(lcore_function_t *pkt_fwd_on_lcore) 921af75078fSIntel { 922af75078fSIntel port_fwd_begin_t port_fwd_begin; 923af75078fSIntel unsigned int i; 924af75078fSIntel unsigned int lc_id; 925af75078fSIntel int diag; 926af75078fSIntel 927af75078fSIntel port_fwd_begin = cur_fwd_config.fwd_eng->port_fwd_begin; 928af75078fSIntel if (port_fwd_begin != NULL) { 929af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) 930af75078fSIntel (*port_fwd_begin)(fwd_ports_ids[i]); 931af75078fSIntel } 932af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_lcores; i++) { 933af75078fSIntel lc_id = fwd_lcores_cpuids[i]; 934af75078fSIntel if ((interactive == 0) || (lc_id != rte_lcore_id())) { 935af75078fSIntel fwd_lcores[i]->stopped = 0; 936af75078fSIntel diag = rte_eal_remote_launch(pkt_fwd_on_lcore, 937af75078fSIntel fwd_lcores[i], lc_id); 938af75078fSIntel if (diag != 0) 939af75078fSIntel printf("launch lcore %u failed - diag=%d\n", 940af75078fSIntel lc_id, diag); 941af75078fSIntel } 942af75078fSIntel } 943af75078fSIntel } 944af75078fSIntel 945af75078fSIntel /* 946af75078fSIntel * Launch packet forwarding configuration. 947af75078fSIntel */ 948af75078fSIntel void 949af75078fSIntel start_packet_forwarding(int with_tx_first) 950af75078fSIntel { 951af75078fSIntel port_fwd_begin_t port_fwd_begin; 952af75078fSIntel port_fwd_end_t port_fwd_end; 953af75078fSIntel struct rte_port *port; 954af75078fSIntel unsigned int i; 955af75078fSIntel portid_t pt_id; 956af75078fSIntel streamid_t sm_id; 957af75078fSIntel 958ce8d5614SIntel if (all_ports_started() == 0) { 959ce8d5614SIntel printf("Not all ports were started\n"); 960ce8d5614SIntel return; 961ce8d5614SIntel } 962af75078fSIntel if (test_done == 0) { 963af75078fSIntel printf("Packet forwarding already started\n"); 964af75078fSIntel return; 965af75078fSIntel } 9667741e4cfSIntel if(dcb_test) { 9677741e4cfSIntel for (i = 0; i < nb_fwd_ports; i++) { 9687741e4cfSIntel pt_id = fwd_ports_ids[i]; 9697741e4cfSIntel port = &ports[pt_id]; 9707741e4cfSIntel if (!port->dcb_flag) { 9717741e4cfSIntel printf("In DCB mode, all forwarding ports must " 9727741e4cfSIntel "be configured in this mode.\n"); 973013af9b6SIntel return; 974013af9b6SIntel } 9757741e4cfSIntel } 9767741e4cfSIntel if (nb_fwd_lcores == 1) { 9777741e4cfSIntel printf("In DCB mode,the nb forwarding cores " 9787741e4cfSIntel "should be larger than 1.\n"); 9797741e4cfSIntel return; 9807741e4cfSIntel } 9817741e4cfSIntel } 982af75078fSIntel test_done = 0; 9837741e4cfSIntel 9847741e4cfSIntel if(!no_flush_rx) 9857741e4cfSIntel flush_fwd_rx_queues(); 9867741e4cfSIntel 987af75078fSIntel fwd_config_setup(); 988af75078fSIntel rxtx_config_display(); 989af75078fSIntel 990af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) { 991af75078fSIntel pt_id = fwd_ports_ids[i]; 992af75078fSIntel port = &ports[pt_id]; 993af75078fSIntel rte_eth_stats_get(pt_id, &port->stats); 994af75078fSIntel port->tx_dropped = 0; 995013af9b6SIntel 996013af9b6SIntel map_port_queue_stats_mapping_registers(pt_id, port); 997af75078fSIntel } 998af75078fSIntel for (sm_id = 0; sm_id < cur_fwd_config.nb_fwd_streams; sm_id++) { 999af75078fSIntel fwd_streams[sm_id]->rx_packets = 0; 1000af75078fSIntel fwd_streams[sm_id]->tx_packets = 0; 1001af75078fSIntel fwd_streams[sm_id]->fwd_dropped = 0; 1002af75078fSIntel fwd_streams[sm_id]->rx_bad_ip_csum = 0; 1003af75078fSIntel fwd_streams[sm_id]->rx_bad_l4_csum = 0; 1004af75078fSIntel 1005af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 1006af75078fSIntel memset(&fwd_streams[sm_id]->rx_burst_stats, 0, 1007af75078fSIntel sizeof(fwd_streams[sm_id]->rx_burst_stats)); 1008af75078fSIntel memset(&fwd_streams[sm_id]->tx_burst_stats, 0, 1009af75078fSIntel sizeof(fwd_streams[sm_id]->tx_burst_stats)); 1010af75078fSIntel #endif 1011af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 1012af75078fSIntel fwd_streams[sm_id]->core_cycles = 0; 1013af75078fSIntel #endif 1014af75078fSIntel } 1015af75078fSIntel if (with_tx_first) { 1016af75078fSIntel port_fwd_begin = tx_only_engine.port_fwd_begin; 1017af75078fSIntel if (port_fwd_begin != NULL) { 1018af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) 1019af75078fSIntel (*port_fwd_begin)(fwd_ports_ids[i]); 1020af75078fSIntel } 1021af75078fSIntel launch_packet_forwarding(run_one_txonly_burst_on_core); 1022af75078fSIntel rte_eal_mp_wait_lcore(); 1023af75078fSIntel port_fwd_end = tx_only_engine.port_fwd_end; 1024af75078fSIntel if (port_fwd_end != NULL) { 1025af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) 1026af75078fSIntel (*port_fwd_end)(fwd_ports_ids[i]); 1027af75078fSIntel } 1028af75078fSIntel } 1029af75078fSIntel launch_packet_forwarding(start_pkt_forward_on_core); 1030af75078fSIntel } 1031af75078fSIntel 1032af75078fSIntel void 1033af75078fSIntel stop_packet_forwarding(void) 1034af75078fSIntel { 1035af75078fSIntel struct rte_eth_stats stats; 1036af75078fSIntel struct rte_port *port; 1037af75078fSIntel port_fwd_end_t port_fwd_end; 1038af75078fSIntel int i; 1039af75078fSIntel portid_t pt_id; 1040af75078fSIntel streamid_t sm_id; 1041af75078fSIntel lcoreid_t lc_id; 1042af75078fSIntel uint64_t total_recv; 1043af75078fSIntel uint64_t total_xmit; 1044af75078fSIntel uint64_t total_rx_dropped; 1045af75078fSIntel uint64_t total_tx_dropped; 1046af75078fSIntel uint64_t total_rx_nombuf; 1047af75078fSIntel uint64_t tx_dropped; 1048af75078fSIntel uint64_t rx_bad_ip_csum; 1049af75078fSIntel uint64_t rx_bad_l4_csum; 1050af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 1051af75078fSIntel uint64_t fwd_cycles; 1052af75078fSIntel #endif 1053af75078fSIntel static const char *acc_stats_border = "+++++++++++++++"; 1054af75078fSIntel 1055ce8d5614SIntel if (all_ports_started() == 0) { 1056ce8d5614SIntel printf("Not all ports were started\n"); 1057ce8d5614SIntel return; 1058ce8d5614SIntel } 1059af75078fSIntel if (test_done) { 1060af75078fSIntel printf("Packet forwarding not started\n"); 1061af75078fSIntel return; 1062af75078fSIntel } 1063af75078fSIntel printf("Telling cores to stop..."); 1064af75078fSIntel for (lc_id = 0; lc_id < cur_fwd_config.nb_fwd_lcores; lc_id++) 1065af75078fSIntel fwd_lcores[lc_id]->stopped = 1; 1066af75078fSIntel printf("\nWaiting for lcores to finish...\n"); 1067af75078fSIntel rte_eal_mp_wait_lcore(); 1068af75078fSIntel port_fwd_end = cur_fwd_config.fwd_eng->port_fwd_end; 1069af75078fSIntel if (port_fwd_end != NULL) { 1070af75078fSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) { 1071af75078fSIntel pt_id = fwd_ports_ids[i]; 1072af75078fSIntel (*port_fwd_end)(pt_id); 1073af75078fSIntel } 1074af75078fSIntel } 1075af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 1076af75078fSIntel fwd_cycles = 0; 1077af75078fSIntel #endif 1078af75078fSIntel for (sm_id = 0; sm_id < cur_fwd_config.nb_fwd_streams; sm_id++) { 1079af75078fSIntel if (cur_fwd_config.nb_fwd_streams > 1080af75078fSIntel cur_fwd_config.nb_fwd_ports) { 1081af75078fSIntel fwd_stream_stats_display(sm_id); 1082af75078fSIntel ports[fwd_streams[sm_id]->tx_port].tx_stream = NULL; 1083af75078fSIntel ports[fwd_streams[sm_id]->rx_port].rx_stream = NULL; 1084af75078fSIntel } else { 1085af75078fSIntel ports[fwd_streams[sm_id]->tx_port].tx_stream = 1086af75078fSIntel fwd_streams[sm_id]; 1087af75078fSIntel ports[fwd_streams[sm_id]->rx_port].rx_stream = 1088af75078fSIntel fwd_streams[sm_id]; 1089af75078fSIntel } 1090af75078fSIntel tx_dropped = ports[fwd_streams[sm_id]->tx_port].tx_dropped; 1091af75078fSIntel tx_dropped = (uint64_t) (tx_dropped + 1092af75078fSIntel fwd_streams[sm_id]->fwd_dropped); 1093af75078fSIntel ports[fwd_streams[sm_id]->tx_port].tx_dropped = tx_dropped; 1094af75078fSIntel 1095013af9b6SIntel rx_bad_ip_csum = 1096013af9b6SIntel ports[fwd_streams[sm_id]->rx_port].rx_bad_ip_csum; 1097af75078fSIntel rx_bad_ip_csum = (uint64_t) (rx_bad_ip_csum + 1098af75078fSIntel fwd_streams[sm_id]->rx_bad_ip_csum); 1099013af9b6SIntel ports[fwd_streams[sm_id]->rx_port].rx_bad_ip_csum = 1100013af9b6SIntel rx_bad_ip_csum; 1101af75078fSIntel 1102013af9b6SIntel rx_bad_l4_csum = 1103013af9b6SIntel ports[fwd_streams[sm_id]->rx_port].rx_bad_l4_csum; 1104af75078fSIntel rx_bad_l4_csum = (uint64_t) (rx_bad_l4_csum + 1105af75078fSIntel fwd_streams[sm_id]->rx_bad_l4_csum); 1106013af9b6SIntel ports[fwd_streams[sm_id]->rx_port].rx_bad_l4_csum = 1107013af9b6SIntel rx_bad_l4_csum; 1108af75078fSIntel 1109af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 1110af75078fSIntel fwd_cycles = (uint64_t) (fwd_cycles + 1111af75078fSIntel fwd_streams[sm_id]->core_cycles); 1112af75078fSIntel #endif 1113af75078fSIntel } 1114af75078fSIntel total_recv = 0; 1115af75078fSIntel total_xmit = 0; 1116af75078fSIntel total_rx_dropped = 0; 1117af75078fSIntel total_tx_dropped = 0; 1118af75078fSIntel total_rx_nombuf = 0; 11197741e4cfSIntel for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) { 1120af75078fSIntel pt_id = fwd_ports_ids[i]; 1121af75078fSIntel 1122af75078fSIntel port = &ports[pt_id]; 1123af75078fSIntel rte_eth_stats_get(pt_id, &stats); 1124af75078fSIntel stats.ipackets -= port->stats.ipackets; 1125af75078fSIntel port->stats.ipackets = 0; 1126af75078fSIntel stats.opackets -= port->stats.opackets; 1127af75078fSIntel port->stats.opackets = 0; 1128af75078fSIntel stats.ibytes -= port->stats.ibytes; 1129af75078fSIntel port->stats.ibytes = 0; 1130af75078fSIntel stats.obytes -= port->stats.obytes; 1131af75078fSIntel port->stats.obytes = 0; 113270bdb186SIvan Boule stats.imissed -= port->stats.imissed; 113370bdb186SIvan Boule port->stats.imissed = 0; 1134af75078fSIntel stats.oerrors -= port->stats.oerrors; 1135af75078fSIntel port->stats.oerrors = 0; 1136af75078fSIntel stats.rx_nombuf -= port->stats.rx_nombuf; 1137af75078fSIntel port->stats.rx_nombuf = 0; 1138af75078fSIntel 1139af75078fSIntel total_recv += stats.ipackets; 1140af75078fSIntel total_xmit += stats.opackets; 114170bdb186SIvan Boule total_rx_dropped += stats.imissed; 1142af75078fSIntel total_tx_dropped += port->tx_dropped; 1143af75078fSIntel total_rx_nombuf += stats.rx_nombuf; 1144af75078fSIntel 1145af75078fSIntel fwd_port_stats_display(pt_id, &stats); 1146af75078fSIntel } 1147af75078fSIntel printf("\n %s Accumulated forward statistics for all ports" 1148af75078fSIntel "%s\n", 1149af75078fSIntel acc_stats_border, acc_stats_border); 1150af75078fSIntel printf(" RX-packets: %-14"PRIu64" RX-dropped: %-14"PRIu64"RX-total: " 1151af75078fSIntel "%-"PRIu64"\n" 1152af75078fSIntel " TX-packets: %-14"PRIu64" TX-dropped: %-14"PRIu64"TX-total: " 1153af75078fSIntel "%-"PRIu64"\n", 1154af75078fSIntel total_recv, total_rx_dropped, total_recv + total_rx_dropped, 1155af75078fSIntel total_xmit, total_tx_dropped, total_xmit + total_tx_dropped); 1156af75078fSIntel if (total_rx_nombuf > 0) 1157af75078fSIntel printf(" RX-nombufs: %-14"PRIu64"\n", total_rx_nombuf); 1158af75078fSIntel printf(" %s++++++++++++++++++++++++++++++++++++++++++++++" 1159af75078fSIntel "%s\n", 1160af75078fSIntel acc_stats_border, acc_stats_border); 1161af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 1162af75078fSIntel if (total_recv > 0) 1163af75078fSIntel printf("\n CPU cycles/packet=%u (total cycles=" 1164af75078fSIntel "%"PRIu64" / total RX packets=%"PRIu64")\n", 1165af75078fSIntel (unsigned int)(fwd_cycles / total_recv), 1166af75078fSIntel fwd_cycles, total_recv); 1167af75078fSIntel #endif 1168af75078fSIntel printf("\nDone.\n"); 1169af75078fSIntel test_done = 1; 1170af75078fSIntel } 1171af75078fSIntel 1172cfae07fdSOuyang Changchun void 1173cfae07fdSOuyang Changchun dev_set_link_up(portid_t pid) 1174cfae07fdSOuyang Changchun { 1175cfae07fdSOuyang Changchun if (rte_eth_dev_set_link_up((uint8_t)pid) < 0) 1176cfae07fdSOuyang Changchun printf("\nSet link up fail.\n"); 1177cfae07fdSOuyang Changchun } 1178cfae07fdSOuyang Changchun 1179cfae07fdSOuyang Changchun void 1180cfae07fdSOuyang Changchun dev_set_link_down(portid_t pid) 1181cfae07fdSOuyang Changchun { 1182cfae07fdSOuyang Changchun if (rte_eth_dev_set_link_down((uint8_t)pid) < 0) 1183cfae07fdSOuyang Changchun printf("\nSet link down fail.\n"); 1184cfae07fdSOuyang Changchun } 1185cfae07fdSOuyang Changchun 1186ce8d5614SIntel static int 1187ce8d5614SIntel all_ports_started(void) 1188ce8d5614SIntel { 1189ce8d5614SIntel portid_t pi; 1190ce8d5614SIntel struct rte_port *port; 1191ce8d5614SIntel 1192edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 1193ce8d5614SIntel port = &ports[pi]; 1194ce8d5614SIntel /* Check if there is a port which is not started */ 119541b05095SBernard Iremonger if ((port->port_status != RTE_PORT_STARTED) && 119641b05095SBernard Iremonger (port->slave_flag == 0)) 1197ce8d5614SIntel return 0; 1198ce8d5614SIntel } 1199ce8d5614SIntel 1200ce8d5614SIntel /* No port is not started */ 1201ce8d5614SIntel return 1; 1202ce8d5614SIntel } 1203ce8d5614SIntel 1204148f963fSBruce Richardson int 1205edab33b1STetsuya Mukawa all_ports_stopped(void) 1206edab33b1STetsuya Mukawa { 1207edab33b1STetsuya Mukawa portid_t pi; 1208edab33b1STetsuya Mukawa struct rte_port *port; 1209edab33b1STetsuya Mukawa 1210edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 1211edab33b1STetsuya Mukawa port = &ports[pi]; 121241b05095SBernard Iremonger if ((port->port_status != RTE_PORT_STOPPED) && 121341b05095SBernard Iremonger (port->slave_flag == 0)) 1214edab33b1STetsuya Mukawa return 0; 1215edab33b1STetsuya Mukawa } 1216edab33b1STetsuya Mukawa 1217edab33b1STetsuya Mukawa return 1; 1218edab33b1STetsuya Mukawa } 1219edab33b1STetsuya Mukawa 1220edab33b1STetsuya Mukawa int 1221edab33b1STetsuya Mukawa port_is_started(portid_t port_id) 1222edab33b1STetsuya Mukawa { 1223edab33b1STetsuya Mukawa if (port_id_is_invalid(port_id, ENABLED_WARN)) 1224edab33b1STetsuya Mukawa return 0; 1225edab33b1STetsuya Mukawa 1226edab33b1STetsuya Mukawa if (ports[port_id].port_status != RTE_PORT_STARTED) 1227edab33b1STetsuya Mukawa return 0; 1228edab33b1STetsuya Mukawa 1229edab33b1STetsuya Mukawa return 1; 1230edab33b1STetsuya Mukawa } 1231edab33b1STetsuya Mukawa 1232edab33b1STetsuya Mukawa static int 1233edab33b1STetsuya Mukawa port_is_closed(portid_t port_id) 1234edab33b1STetsuya Mukawa { 1235edab33b1STetsuya Mukawa if (port_id_is_invalid(port_id, ENABLED_WARN)) 1236edab33b1STetsuya Mukawa return 0; 1237edab33b1STetsuya Mukawa 1238edab33b1STetsuya Mukawa if (ports[port_id].port_status != RTE_PORT_CLOSED) 1239edab33b1STetsuya Mukawa return 0; 1240edab33b1STetsuya Mukawa 1241edab33b1STetsuya Mukawa return 1; 1242edab33b1STetsuya Mukawa } 1243edab33b1STetsuya Mukawa 1244edab33b1STetsuya Mukawa int 1245ce8d5614SIntel start_port(portid_t pid) 1246ce8d5614SIntel { 124792d2703eSMichael Qiu int diag, need_check_link_status = -1; 1248ce8d5614SIntel portid_t pi; 1249ce8d5614SIntel queueid_t qi; 1250ce8d5614SIntel struct rte_port *port; 12512950a769SDeclan Doherty struct ether_addr mac_addr; 1252ce8d5614SIntel 1253ce8d5614SIntel if (test_done == 0) { 1254ce8d5614SIntel printf("Please stop forwarding first\n"); 1255148f963fSBruce Richardson return -1; 1256ce8d5614SIntel } 1257ce8d5614SIntel 12584468635fSMichael Qiu if (port_id_is_invalid(pid, ENABLED_WARN)) 12594468635fSMichael Qiu return 0; 12604468635fSMichael Qiu 1261ce8d5614SIntel if (init_fwd_streams() < 0) { 1262ce8d5614SIntel printf("Fail from init_fwd_streams()\n"); 1263148f963fSBruce Richardson return -1; 1264ce8d5614SIntel } 1265ce8d5614SIntel 1266ce8d5614SIntel if(dcb_config) 1267ce8d5614SIntel dcb_test = 1; 1268edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 1269edab33b1STetsuya Mukawa if (pid != pi && pid != (portid_t)RTE_PORT_ALL) 1270ce8d5614SIntel continue; 1271ce8d5614SIntel 127292d2703eSMichael Qiu need_check_link_status = 0; 1273ce8d5614SIntel port = &ports[pi]; 1274ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), RTE_PORT_STOPPED, 1275ce8d5614SIntel RTE_PORT_HANDLING) == 0) { 1276ce8d5614SIntel printf("Port %d is now not stopped\n", pi); 1277ce8d5614SIntel continue; 1278ce8d5614SIntel } 1279ce8d5614SIntel 1280ce8d5614SIntel if (port->need_reconfig > 0) { 1281ce8d5614SIntel port->need_reconfig = 0; 1282ce8d5614SIntel 12835706de65SJulien Cretin printf("Configuring Port %d (socket %u)\n", pi, 128420a0286fSLiu Xiaofeng port->socket_id); 1285ce8d5614SIntel /* configure port */ 1286ce8d5614SIntel diag = rte_eth_dev_configure(pi, nb_rxq, nb_txq, 1287ce8d5614SIntel &(port->dev_conf)); 1288ce8d5614SIntel if (diag != 0) { 1289ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1290ce8d5614SIntel RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0) 1291ce8d5614SIntel printf("Port %d can not be set back " 1292ce8d5614SIntel "to stopped\n", pi); 1293ce8d5614SIntel printf("Fail to configure port %d\n", pi); 1294ce8d5614SIntel /* try to reconfigure port next time */ 1295ce8d5614SIntel port->need_reconfig = 1; 1296148f963fSBruce Richardson return -1; 1297ce8d5614SIntel } 1298ce8d5614SIntel } 1299ce8d5614SIntel if (port->need_reconfig_queues > 0) { 1300ce8d5614SIntel port->need_reconfig_queues = 0; 1301ce8d5614SIntel /* setup tx queues */ 1302ce8d5614SIntel for (qi = 0; qi < nb_txq; qi++) { 1303b6ea6408SIntel if ((numa_support) && 1304b6ea6408SIntel (txring_numa[pi] != NUMA_NO_CONFIG)) 1305b6ea6408SIntel diag = rte_eth_tx_queue_setup(pi, qi, 1306b6ea6408SIntel nb_txd,txring_numa[pi], 1307b6ea6408SIntel &(port->tx_conf)); 1308b6ea6408SIntel else 1309b6ea6408SIntel diag = rte_eth_tx_queue_setup(pi, qi, 1310b6ea6408SIntel nb_txd,port->socket_id, 1311b6ea6408SIntel &(port->tx_conf)); 1312b6ea6408SIntel 1313ce8d5614SIntel if (diag == 0) 1314ce8d5614SIntel continue; 1315ce8d5614SIntel 1316ce8d5614SIntel /* Fail to setup tx queue, return */ 1317ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1318ce8d5614SIntel RTE_PORT_HANDLING, 1319ce8d5614SIntel RTE_PORT_STOPPED) == 0) 1320ce8d5614SIntel printf("Port %d can not be set back " 1321ce8d5614SIntel "to stopped\n", pi); 1322ce8d5614SIntel printf("Fail to configure port %d tx queues\n", pi); 1323ce8d5614SIntel /* try to reconfigure queues next time */ 1324ce8d5614SIntel port->need_reconfig_queues = 1; 1325148f963fSBruce Richardson return -1; 1326ce8d5614SIntel } 1327ce8d5614SIntel /* setup rx queues */ 1328ce8d5614SIntel for (qi = 0; qi < nb_rxq; qi++) { 1329b6ea6408SIntel if ((numa_support) && 1330b6ea6408SIntel (rxring_numa[pi] != NUMA_NO_CONFIG)) { 1331b6ea6408SIntel struct rte_mempool * mp = 1332b6ea6408SIntel mbuf_pool_find(rxring_numa[pi]); 1333b6ea6408SIntel if (mp == NULL) { 1334b6ea6408SIntel printf("Failed to setup RX queue:" 1335b6ea6408SIntel "No mempool allocation" 1336b6ea6408SIntel "on the socket %d\n", 1337b6ea6408SIntel rxring_numa[pi]); 1338148f963fSBruce Richardson return -1; 1339b6ea6408SIntel } 1340b6ea6408SIntel 1341b6ea6408SIntel diag = rte_eth_rx_queue_setup(pi, qi, 1342b6ea6408SIntel nb_rxd,rxring_numa[pi], 1343b6ea6408SIntel &(port->rx_conf),mp); 1344b6ea6408SIntel } 1345b6ea6408SIntel else 1346b6ea6408SIntel diag = rte_eth_rx_queue_setup(pi, qi, 1347b6ea6408SIntel nb_rxd,port->socket_id, 1348b6ea6408SIntel &(port->rx_conf), 1349ce8d5614SIntel mbuf_pool_find(port->socket_id)); 1350b6ea6408SIntel 1351ce8d5614SIntel if (diag == 0) 1352ce8d5614SIntel continue; 1353ce8d5614SIntel 1354b6ea6408SIntel 1355ce8d5614SIntel /* Fail to setup rx queue, return */ 1356ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1357ce8d5614SIntel RTE_PORT_HANDLING, 1358ce8d5614SIntel RTE_PORT_STOPPED) == 0) 1359ce8d5614SIntel printf("Port %d can not be set back " 1360ce8d5614SIntel "to stopped\n", pi); 1361ce8d5614SIntel printf("Fail to configure port %d rx queues\n", pi); 1362ce8d5614SIntel /* try to reconfigure queues next time */ 1363ce8d5614SIntel port->need_reconfig_queues = 1; 1364148f963fSBruce Richardson return -1; 1365ce8d5614SIntel } 1366ce8d5614SIntel } 1367ce8d5614SIntel /* start port */ 1368ce8d5614SIntel if (rte_eth_dev_start(pi) < 0) { 1369ce8d5614SIntel printf("Fail to start port %d\n", pi); 1370ce8d5614SIntel 1371ce8d5614SIntel /* Fail to setup rx queue, return */ 1372ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1373ce8d5614SIntel RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0) 1374ce8d5614SIntel printf("Port %d can not be set back to " 1375ce8d5614SIntel "stopped\n", pi); 1376ce8d5614SIntel continue; 1377ce8d5614SIntel } 1378ce8d5614SIntel 1379ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1380ce8d5614SIntel RTE_PORT_HANDLING, RTE_PORT_STARTED) == 0) 1381ce8d5614SIntel printf("Port %d can not be set into started\n", pi); 1382ce8d5614SIntel 13832950a769SDeclan Doherty rte_eth_macaddr_get(pi, &mac_addr); 1384d8c89163SZijie Pan printf("Port %d: %02X:%02X:%02X:%02X:%02X:%02X\n", pi, 13852950a769SDeclan Doherty mac_addr.addr_bytes[0], mac_addr.addr_bytes[1], 13862950a769SDeclan Doherty mac_addr.addr_bytes[2], mac_addr.addr_bytes[3], 13872950a769SDeclan Doherty mac_addr.addr_bytes[4], mac_addr.addr_bytes[5]); 1388d8c89163SZijie Pan 1389ce8d5614SIntel /* at least one port started, need checking link status */ 1390ce8d5614SIntel need_check_link_status = 1; 1391ce8d5614SIntel } 1392ce8d5614SIntel 139392d2703eSMichael Qiu if (need_check_link_status == 1 && !no_link_check) 1394edab33b1STetsuya Mukawa check_all_ports_link_status(RTE_PORT_ALL); 139592d2703eSMichael Qiu else if (need_check_link_status == 0) 1396ce8d5614SIntel printf("Please stop the ports first\n"); 1397ce8d5614SIntel 1398ce8d5614SIntel printf("Done\n"); 1399148f963fSBruce Richardson return 0; 1400ce8d5614SIntel } 1401ce8d5614SIntel 1402ce8d5614SIntel void 1403ce8d5614SIntel stop_port(portid_t pid) 1404ce8d5614SIntel { 1405ce8d5614SIntel portid_t pi; 1406ce8d5614SIntel struct rte_port *port; 1407ce8d5614SIntel int need_check_link_status = 0; 1408ce8d5614SIntel 1409ce8d5614SIntel if (test_done == 0) { 1410ce8d5614SIntel printf("Please stop forwarding first\n"); 1411ce8d5614SIntel return; 1412ce8d5614SIntel } 1413ce8d5614SIntel if (dcb_test) { 1414ce8d5614SIntel dcb_test = 0; 1415ce8d5614SIntel dcb_config = 0; 1416ce8d5614SIntel } 14174468635fSMichael Qiu 14184468635fSMichael Qiu if (port_id_is_invalid(pid, ENABLED_WARN)) 14194468635fSMichael Qiu return; 14204468635fSMichael Qiu 1421ce8d5614SIntel printf("Stopping ports...\n"); 1422ce8d5614SIntel 1423edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 14244468635fSMichael Qiu if (pid != pi && pid != (portid_t)RTE_PORT_ALL) 1425ce8d5614SIntel continue; 1426ce8d5614SIntel 1427ce8d5614SIntel port = &ports[pi]; 1428ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), RTE_PORT_STARTED, 1429ce8d5614SIntel RTE_PORT_HANDLING) == 0) 1430ce8d5614SIntel continue; 1431ce8d5614SIntel 1432ce8d5614SIntel rte_eth_dev_stop(pi); 1433ce8d5614SIntel 1434ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1435ce8d5614SIntel RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0) 1436ce8d5614SIntel printf("Port %d can not be set into stopped\n", pi); 1437ce8d5614SIntel need_check_link_status = 1; 1438ce8d5614SIntel } 1439bc202406SDavid Marchand if (need_check_link_status && !no_link_check) 1440edab33b1STetsuya Mukawa check_all_ports_link_status(RTE_PORT_ALL); 1441ce8d5614SIntel 1442ce8d5614SIntel printf("Done\n"); 1443ce8d5614SIntel } 1444ce8d5614SIntel 1445ce8d5614SIntel void 1446ce8d5614SIntel close_port(portid_t pid) 1447ce8d5614SIntel { 1448ce8d5614SIntel portid_t pi; 1449ce8d5614SIntel struct rte_port *port; 1450ce8d5614SIntel 1451ce8d5614SIntel if (test_done == 0) { 1452ce8d5614SIntel printf("Please stop forwarding first\n"); 1453ce8d5614SIntel return; 1454ce8d5614SIntel } 1455ce8d5614SIntel 14564468635fSMichael Qiu if (port_id_is_invalid(pid, ENABLED_WARN)) 14574468635fSMichael Qiu return; 14584468635fSMichael Qiu 1459ce8d5614SIntel printf("Closing ports...\n"); 1460ce8d5614SIntel 1461edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 14624468635fSMichael Qiu if (pid != pi && pid != (portid_t)RTE_PORT_ALL) 1463ce8d5614SIntel continue; 1464ce8d5614SIntel 1465ce8d5614SIntel port = &ports[pi]; 1466ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1467d4e8ad64SMichael Qiu RTE_PORT_CLOSED, RTE_PORT_CLOSED) == 1) { 1468d4e8ad64SMichael Qiu printf("Port %d is already closed\n", pi); 1469d4e8ad64SMichael Qiu continue; 1470d4e8ad64SMichael Qiu } 1471d4e8ad64SMichael Qiu 1472d4e8ad64SMichael Qiu if (rte_atomic16_cmpset(&(port->port_status), 1473ce8d5614SIntel RTE_PORT_STOPPED, RTE_PORT_HANDLING) == 0) { 1474ce8d5614SIntel printf("Port %d is now not stopped\n", pi); 1475ce8d5614SIntel continue; 1476ce8d5614SIntel } 1477ce8d5614SIntel 1478ce8d5614SIntel rte_eth_dev_close(pi); 1479ce8d5614SIntel 1480ce8d5614SIntel if (rte_atomic16_cmpset(&(port->port_status), 1481ce8d5614SIntel RTE_PORT_HANDLING, RTE_PORT_CLOSED) == 0) 1482ce8d5614SIntel printf("Port %d can not be set into stopped\n", pi); 1483ce8d5614SIntel } 1484ce8d5614SIntel 1485ce8d5614SIntel printf("Done\n"); 1486ce8d5614SIntel } 1487ce8d5614SIntel 1488edab33b1STetsuya Mukawa void 1489edab33b1STetsuya Mukawa attach_port(char *identifier) 1490ce8d5614SIntel { 1491edab33b1STetsuya Mukawa portid_t i, j, pi = 0; 1492ce8d5614SIntel 1493edab33b1STetsuya Mukawa printf("Attaching a new port...\n"); 1494edab33b1STetsuya Mukawa 1495edab33b1STetsuya Mukawa if (identifier == NULL) { 1496edab33b1STetsuya Mukawa printf("Invalid parameters are specified\n"); 1497edab33b1STetsuya Mukawa return; 1498ce8d5614SIntel } 1499ce8d5614SIntel 1500edab33b1STetsuya Mukawa if (test_done == 0) { 1501edab33b1STetsuya Mukawa printf("Please stop forwarding first\n"); 1502edab33b1STetsuya Mukawa return; 1503ce8d5614SIntel } 1504ce8d5614SIntel 1505edab33b1STetsuya Mukawa if (rte_eth_dev_attach(identifier, &pi)) 1506edab33b1STetsuya Mukawa return; 1507edab33b1STetsuya Mukawa 1508edab33b1STetsuya Mukawa ports[pi].enabled = 1; 1509edab33b1STetsuya Mukawa reconfig(pi, rte_eth_dev_socket_id(pi)); 1510edab33b1STetsuya Mukawa rte_eth_promiscuous_enable(pi); 1511edab33b1STetsuya Mukawa 1512edab33b1STetsuya Mukawa nb_ports = rte_eth_dev_count(); 1513edab33b1STetsuya Mukawa 1514edab33b1STetsuya Mukawa /* set_default_fwd_ports_config(); */ 15156c76533cSStephen Hemminger memset(fwd_ports_ids, 0, sizeof(fwd_ports_ids)); 1516edab33b1STetsuya Mukawa i = 0; 1517edab33b1STetsuya Mukawa FOREACH_PORT(j, ports) { 1518edab33b1STetsuya Mukawa fwd_ports_ids[i] = j; 1519edab33b1STetsuya Mukawa i++; 1520edab33b1STetsuya Mukawa } 1521edab33b1STetsuya Mukawa nb_cfg_ports = nb_ports; 1522edab33b1STetsuya Mukawa nb_fwd_ports++; 1523edab33b1STetsuya Mukawa 1524edab33b1STetsuya Mukawa ports[pi].port_status = RTE_PORT_STOPPED; 1525edab33b1STetsuya Mukawa 1526edab33b1STetsuya Mukawa printf("Port %d is attached. Now total ports is %d\n", pi, nb_ports); 1527edab33b1STetsuya Mukawa printf("Done\n"); 1528edab33b1STetsuya Mukawa } 1529edab33b1STetsuya Mukawa 1530edab33b1STetsuya Mukawa void 1531edab33b1STetsuya Mukawa detach_port(uint8_t port_id) 15325f4ec54fSChen Jing D(Mark) { 1533edab33b1STetsuya Mukawa portid_t i, pi = 0; 1534edab33b1STetsuya Mukawa char name[RTE_ETH_NAME_MAX_LEN]; 15355f4ec54fSChen Jing D(Mark) 1536edab33b1STetsuya Mukawa printf("Detaching a port...\n"); 15375f4ec54fSChen Jing D(Mark) 1538edab33b1STetsuya Mukawa if (!port_is_closed(port_id)) { 1539edab33b1STetsuya Mukawa printf("Please close port first\n"); 1540edab33b1STetsuya Mukawa return; 1541edab33b1STetsuya Mukawa } 1542edab33b1STetsuya Mukawa 1543edab33b1STetsuya Mukawa if (rte_eth_dev_detach(port_id, name)) 1544edab33b1STetsuya Mukawa return; 1545edab33b1STetsuya Mukawa 1546edab33b1STetsuya Mukawa ports[port_id].enabled = 0; 1547edab33b1STetsuya Mukawa nb_ports = rte_eth_dev_count(); 1548edab33b1STetsuya Mukawa 1549edab33b1STetsuya Mukawa /* set_default_fwd_ports_config(); */ 15506c76533cSStephen Hemminger memset(fwd_ports_ids, 0, sizeof(fwd_ports_ids)); 1551edab33b1STetsuya Mukawa i = 0; 1552edab33b1STetsuya Mukawa FOREACH_PORT(pi, ports) { 1553edab33b1STetsuya Mukawa fwd_ports_ids[i] = pi; 1554edab33b1STetsuya Mukawa i++; 1555edab33b1STetsuya Mukawa } 1556edab33b1STetsuya Mukawa nb_cfg_ports = nb_ports; 1557edab33b1STetsuya Mukawa nb_fwd_ports--; 1558edab33b1STetsuya Mukawa 1559edab33b1STetsuya Mukawa printf("Port '%s' is detached. Now total ports is %d\n", 1560edab33b1STetsuya Mukawa name, nb_ports); 1561edab33b1STetsuya Mukawa printf("Done\n"); 1562edab33b1STetsuya Mukawa return; 15635f4ec54fSChen Jing D(Mark) } 15645f4ec54fSChen Jing D(Mark) 1565af75078fSIntel void 1566af75078fSIntel pmd_test_exit(void) 1567af75078fSIntel { 1568af75078fSIntel portid_t pt_id; 1569af75078fSIntel 15708210ec25SPablo de Lara if (test_done == 0) 15718210ec25SPablo de Lara stop_packet_forwarding(); 15728210ec25SPablo de Lara 1573d3a274ceSZhihong Wang if (ports != NULL) { 1574d3a274ceSZhihong Wang no_link_check = 1; 1575edab33b1STetsuya Mukawa FOREACH_PORT(pt_id, ports) { 1576d3a274ceSZhihong Wang printf("\nShutting down port %d...\n", pt_id); 1577af75078fSIntel fflush(stdout); 1578d3a274ceSZhihong Wang stop_port(pt_id); 1579d3a274ceSZhihong Wang close_port(pt_id); 1580af75078fSIntel } 1581d3a274ceSZhihong Wang } 1582d3a274ceSZhihong Wang printf("\nBye...\n"); 1583af75078fSIntel } 1584af75078fSIntel 1585af75078fSIntel typedef void (*cmd_func_t)(void); 1586af75078fSIntel struct pmd_test_command { 1587af75078fSIntel const char *cmd_name; 1588af75078fSIntel cmd_func_t cmd_func; 1589af75078fSIntel }; 1590af75078fSIntel 1591af75078fSIntel #define PMD_TEST_CMD_NB (sizeof(pmd_test_menu) / sizeof(pmd_test_menu[0])) 1592af75078fSIntel 1593ce8d5614SIntel /* Check the link status of all ports in up to 9s, and print them finally */ 1594af75078fSIntel static void 1595edab33b1STetsuya Mukawa check_all_ports_link_status(uint32_t port_mask) 1596af75078fSIntel { 1597ce8d5614SIntel #define CHECK_INTERVAL 100 /* 100ms */ 1598ce8d5614SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 1599ce8d5614SIntel uint8_t portid, count, all_ports_up, print_flag = 0; 1600ce8d5614SIntel struct rte_eth_link link; 1601ce8d5614SIntel 1602ce8d5614SIntel printf("Checking link statuses...\n"); 1603ce8d5614SIntel fflush(stdout); 1604ce8d5614SIntel for (count = 0; count <= MAX_CHECK_TIME; count++) { 1605ce8d5614SIntel all_ports_up = 1; 1606edab33b1STetsuya Mukawa FOREACH_PORT(portid, ports) { 1607ce8d5614SIntel if ((port_mask & (1 << portid)) == 0) 1608ce8d5614SIntel continue; 1609ce8d5614SIntel memset(&link, 0, sizeof(link)); 1610ce8d5614SIntel rte_eth_link_get_nowait(portid, &link); 1611ce8d5614SIntel /* print link status if flag set */ 1612ce8d5614SIntel if (print_flag == 1) { 1613ce8d5614SIntel if (link.link_status) 1614ce8d5614SIntel printf("Port %d Link Up - speed %u " 1615ce8d5614SIntel "Mbps - %s\n", (uint8_t)portid, 1616ce8d5614SIntel (unsigned)link.link_speed, 1617ce8d5614SIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 1618ce8d5614SIntel ("full-duplex") : ("half-duplex\n")); 1619ce8d5614SIntel else 1620ce8d5614SIntel printf("Port %d Link Down\n", 1621ce8d5614SIntel (uint8_t)portid); 1622ce8d5614SIntel continue; 1623ce8d5614SIntel } 1624ce8d5614SIntel /* clear all_ports_up flag if any link down */ 1625ce8d5614SIntel if (link.link_status == 0) { 1626ce8d5614SIntel all_ports_up = 0; 1627ce8d5614SIntel break; 1628ce8d5614SIntel } 1629ce8d5614SIntel } 1630ce8d5614SIntel /* after finally printing all link status, get out */ 1631ce8d5614SIntel if (print_flag == 1) 1632ce8d5614SIntel break; 1633ce8d5614SIntel 1634ce8d5614SIntel if (all_ports_up == 0) { 1635ce8d5614SIntel fflush(stdout); 1636ce8d5614SIntel rte_delay_ms(CHECK_INTERVAL); 1637ce8d5614SIntel } 1638ce8d5614SIntel 1639ce8d5614SIntel /* set the print_flag if all ports up or timeout */ 1640ce8d5614SIntel if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) { 1641ce8d5614SIntel print_flag = 1; 1642ce8d5614SIntel } 1643ce8d5614SIntel } 1644af75078fSIntel } 1645af75078fSIntel 1646013af9b6SIntel static int 1647013af9b6SIntel set_tx_queue_stats_mapping_registers(uint8_t port_id, struct rte_port *port) 1648af75078fSIntel { 1649013af9b6SIntel uint16_t i; 1650af75078fSIntel int diag; 1651013af9b6SIntel uint8_t mapping_found = 0; 1652af75078fSIntel 1653013af9b6SIntel for (i = 0; i < nb_tx_queue_stats_mappings; i++) { 1654013af9b6SIntel if ((tx_queue_stats_mappings[i].port_id == port_id) && 1655013af9b6SIntel (tx_queue_stats_mappings[i].queue_id < nb_txq )) { 1656013af9b6SIntel diag = rte_eth_dev_set_tx_queue_stats_mapping(port_id, 1657013af9b6SIntel tx_queue_stats_mappings[i].queue_id, 1658013af9b6SIntel tx_queue_stats_mappings[i].stats_counter_id); 1659013af9b6SIntel if (diag != 0) 1660013af9b6SIntel return diag; 1661013af9b6SIntel mapping_found = 1; 1662af75078fSIntel } 1663013af9b6SIntel } 1664013af9b6SIntel if (mapping_found) 1665013af9b6SIntel port->tx_queue_stats_mapping_enabled = 1; 1666013af9b6SIntel return 0; 1667013af9b6SIntel } 1668013af9b6SIntel 1669013af9b6SIntel static int 1670013af9b6SIntel set_rx_queue_stats_mapping_registers(uint8_t port_id, struct rte_port *port) 1671013af9b6SIntel { 1672013af9b6SIntel uint16_t i; 1673013af9b6SIntel int diag; 1674013af9b6SIntel uint8_t mapping_found = 0; 1675013af9b6SIntel 1676013af9b6SIntel for (i = 0; i < nb_rx_queue_stats_mappings; i++) { 1677013af9b6SIntel if ((rx_queue_stats_mappings[i].port_id == port_id) && 1678013af9b6SIntel (rx_queue_stats_mappings[i].queue_id < nb_rxq )) { 1679013af9b6SIntel diag = rte_eth_dev_set_rx_queue_stats_mapping(port_id, 1680013af9b6SIntel rx_queue_stats_mappings[i].queue_id, 1681013af9b6SIntel rx_queue_stats_mappings[i].stats_counter_id); 1682013af9b6SIntel if (diag != 0) 1683013af9b6SIntel return diag; 1684013af9b6SIntel mapping_found = 1; 1685013af9b6SIntel } 1686013af9b6SIntel } 1687013af9b6SIntel if (mapping_found) 1688013af9b6SIntel port->rx_queue_stats_mapping_enabled = 1; 1689013af9b6SIntel return 0; 1690013af9b6SIntel } 1691013af9b6SIntel 1692013af9b6SIntel static void 1693013af9b6SIntel map_port_queue_stats_mapping_registers(uint8_t pi, struct rte_port *port) 1694013af9b6SIntel { 1695013af9b6SIntel int diag = 0; 1696013af9b6SIntel 1697013af9b6SIntel diag = set_tx_queue_stats_mapping_registers(pi, port); 1698af75078fSIntel if (diag != 0) { 1699013af9b6SIntel if (diag == -ENOTSUP) { 1700013af9b6SIntel port->tx_queue_stats_mapping_enabled = 0; 1701013af9b6SIntel printf("TX queue stats mapping not supported port id=%d\n", pi); 1702013af9b6SIntel } 1703013af9b6SIntel else 1704013af9b6SIntel rte_exit(EXIT_FAILURE, 1705013af9b6SIntel "set_tx_queue_stats_mapping_registers " 1706013af9b6SIntel "failed for port id=%d diag=%d\n", 1707af75078fSIntel pi, diag); 1708af75078fSIntel } 1709013af9b6SIntel 1710013af9b6SIntel diag = set_rx_queue_stats_mapping_registers(pi, port); 1711af75078fSIntel if (diag != 0) { 1712013af9b6SIntel if (diag == -ENOTSUP) { 1713013af9b6SIntel port->rx_queue_stats_mapping_enabled = 0; 1714013af9b6SIntel printf("RX queue stats mapping not supported port id=%d\n", pi); 1715013af9b6SIntel } 1716013af9b6SIntel else 1717013af9b6SIntel rte_exit(EXIT_FAILURE, 1718013af9b6SIntel "set_rx_queue_stats_mapping_registers " 1719013af9b6SIntel "failed for port id=%d diag=%d\n", 1720af75078fSIntel pi, diag); 1721af75078fSIntel } 1722af75078fSIntel } 1723af75078fSIntel 1724f2c5125aSPablo de Lara static void 1725f2c5125aSPablo de Lara rxtx_port_config(struct rte_port *port) 1726f2c5125aSPablo de Lara { 1727f2c5125aSPablo de Lara port->rx_conf = port->dev_info.default_rxconf; 1728f2c5125aSPablo de Lara port->tx_conf = port->dev_info.default_txconf; 1729f2c5125aSPablo de Lara 1730f2c5125aSPablo de Lara /* Check if any RX/TX parameters have been passed */ 1731f2c5125aSPablo de Lara if (rx_pthresh != RTE_PMD_PARAM_UNSET) 1732f2c5125aSPablo de Lara port->rx_conf.rx_thresh.pthresh = rx_pthresh; 1733f2c5125aSPablo de Lara 1734f2c5125aSPablo de Lara if (rx_hthresh != RTE_PMD_PARAM_UNSET) 1735f2c5125aSPablo de Lara port->rx_conf.rx_thresh.hthresh = rx_hthresh; 1736f2c5125aSPablo de Lara 1737f2c5125aSPablo de Lara if (rx_wthresh != RTE_PMD_PARAM_UNSET) 1738f2c5125aSPablo de Lara port->rx_conf.rx_thresh.wthresh = rx_wthresh; 1739f2c5125aSPablo de Lara 1740f2c5125aSPablo de Lara if (rx_free_thresh != RTE_PMD_PARAM_UNSET) 1741f2c5125aSPablo de Lara port->rx_conf.rx_free_thresh = rx_free_thresh; 1742f2c5125aSPablo de Lara 1743f2c5125aSPablo de Lara if (rx_drop_en != RTE_PMD_PARAM_UNSET) 1744f2c5125aSPablo de Lara port->rx_conf.rx_drop_en = rx_drop_en; 1745f2c5125aSPablo de Lara 1746f2c5125aSPablo de Lara if (tx_pthresh != RTE_PMD_PARAM_UNSET) 1747f2c5125aSPablo de Lara port->tx_conf.tx_thresh.pthresh = tx_pthresh; 1748f2c5125aSPablo de Lara 1749f2c5125aSPablo de Lara if (tx_hthresh != RTE_PMD_PARAM_UNSET) 1750f2c5125aSPablo de Lara port->tx_conf.tx_thresh.hthresh = tx_hthresh; 1751f2c5125aSPablo de Lara 1752f2c5125aSPablo de Lara if (tx_wthresh != RTE_PMD_PARAM_UNSET) 1753f2c5125aSPablo de Lara port->tx_conf.tx_thresh.wthresh = tx_wthresh; 1754f2c5125aSPablo de Lara 1755f2c5125aSPablo de Lara if (tx_rs_thresh != RTE_PMD_PARAM_UNSET) 1756f2c5125aSPablo de Lara port->tx_conf.tx_rs_thresh = tx_rs_thresh; 1757f2c5125aSPablo de Lara 1758f2c5125aSPablo de Lara if (tx_free_thresh != RTE_PMD_PARAM_UNSET) 1759f2c5125aSPablo de Lara port->tx_conf.tx_free_thresh = tx_free_thresh; 1760f2c5125aSPablo de Lara 1761f2c5125aSPablo de Lara if (txq_flags != RTE_PMD_PARAM_UNSET) 1762f2c5125aSPablo de Lara port->tx_conf.txq_flags = txq_flags; 1763f2c5125aSPablo de Lara } 1764f2c5125aSPablo de Lara 1765013af9b6SIntel void 1766013af9b6SIntel init_port_config(void) 1767013af9b6SIntel { 1768013af9b6SIntel portid_t pid; 1769013af9b6SIntel struct rte_port *port; 1770013af9b6SIntel 1771edab33b1STetsuya Mukawa FOREACH_PORT(pid, ports) { 1772013af9b6SIntel port = &ports[pid]; 1773013af9b6SIntel port->dev_conf.rxmode = rx_mode; 1774013af9b6SIntel port->dev_conf.fdir_conf = fdir_conf; 17753ce690d3SBruce Richardson if (nb_rxq > 1) { 1776013af9b6SIntel port->dev_conf.rx_adv_conf.rss_conf.rss_key = NULL; 1777013af9b6SIntel port->dev_conf.rx_adv_conf.rss_conf.rss_hf = rss_hf; 1778af75078fSIntel } else { 1779013af9b6SIntel port->dev_conf.rx_adv_conf.rss_conf.rss_key = NULL; 1780013af9b6SIntel port->dev_conf.rx_adv_conf.rss_conf.rss_hf = 0; 1781af75078fSIntel } 17823ce690d3SBruce Richardson 17833ce690d3SBruce Richardson if (port->dcb_flag == 0 && port->dev_info.max_vfs == 0) { 17843ce690d3SBruce Richardson if( port->dev_conf.rx_adv_conf.rss_conf.rss_hf != 0) 17853ce690d3SBruce Richardson port->dev_conf.rxmode.mq_mode = ETH_MQ_RX_RSS; 17863ce690d3SBruce Richardson else 17873ce690d3SBruce Richardson port->dev_conf.rxmode.mq_mode = ETH_MQ_RX_NONE; 17883ce690d3SBruce Richardson } 17893ce690d3SBruce Richardson 1790a30979f6SOuyang Changchun if (port->dev_info.max_vfs != 0) { 1791a30979f6SOuyang Changchun if (port->dev_conf.rx_adv_conf.rss_conf.rss_hf != 0) 1792a30979f6SOuyang Changchun port->dev_conf.rxmode.mq_mode = 1793a30979f6SOuyang Changchun ETH_MQ_RX_VMDQ_RSS; 1794a30979f6SOuyang Changchun else 1795a30979f6SOuyang Changchun port->dev_conf.rxmode.mq_mode = 1796a30979f6SOuyang Changchun ETH_MQ_RX_NONE; 1797a30979f6SOuyang Changchun 1798a30979f6SOuyang Changchun port->dev_conf.txmode.mq_mode = ETH_MQ_TX_NONE; 1799a30979f6SOuyang Changchun } 1800a30979f6SOuyang Changchun 1801f2c5125aSPablo de Lara rxtx_port_config(port); 1802013af9b6SIntel 1803013af9b6SIntel rte_eth_macaddr_get(pid, &port->eth_addr); 1804013af9b6SIntel 1805013af9b6SIntel map_port_queue_stats_mapping_registers(pid, port); 18067b7e5ba7SIntel #ifdef RTE_NIC_BYPASS 18077b7e5ba7SIntel rte_eth_dev_bypass_init(pid); 18087b7e5ba7SIntel #endif 1809013af9b6SIntel } 1810013af9b6SIntel } 1811013af9b6SIntel 181241b05095SBernard Iremonger void set_port_slave_flag(portid_t slave_pid) 181341b05095SBernard Iremonger { 181441b05095SBernard Iremonger struct rte_port *port; 181541b05095SBernard Iremonger 181641b05095SBernard Iremonger port = &ports[slave_pid]; 181741b05095SBernard Iremonger port->slave_flag = 1; 181841b05095SBernard Iremonger } 181941b05095SBernard Iremonger 182041b05095SBernard Iremonger void clear_port_slave_flag(portid_t slave_pid) 182141b05095SBernard Iremonger { 182241b05095SBernard Iremonger struct rte_port *port; 182341b05095SBernard Iremonger 182441b05095SBernard Iremonger port = &ports[slave_pid]; 182541b05095SBernard Iremonger port->slave_flag = 0; 182641b05095SBernard Iremonger } 182741b05095SBernard Iremonger 1828013af9b6SIntel const uint16_t vlan_tags[] = { 1829013af9b6SIntel 0, 1, 2, 3, 4, 5, 6, 7, 1830013af9b6SIntel 8, 9, 10, 11, 12, 13, 14, 15, 1831013af9b6SIntel 16, 17, 18, 19, 20, 21, 22, 23, 1832013af9b6SIntel 24, 25, 26, 27, 28, 29, 30, 31 1833013af9b6SIntel }; 1834013af9b6SIntel 1835013af9b6SIntel static int 18361a572499SJingjing Wu get_eth_dcb_conf(struct rte_eth_conf *eth_conf, 18371a572499SJingjing Wu enum dcb_mode_enable dcb_mode, 18381a572499SJingjing Wu enum rte_eth_nb_tcs num_tcs, 18391a572499SJingjing Wu uint8_t pfc_en) 1840013af9b6SIntel { 1841013af9b6SIntel uint8_t i; 1842af75078fSIntel 1843af75078fSIntel /* 1844013af9b6SIntel * Builds up the correct configuration for dcb+vt based on the vlan tags array 1845013af9b6SIntel * given above, and the number of traffic classes available for use. 1846af75078fSIntel */ 18471a572499SJingjing Wu if (dcb_mode == DCB_VT_ENABLED) { 18481a572499SJingjing Wu struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 18491a572499SJingjing Wu ð_conf->rx_adv_conf.vmdq_dcb_conf; 18501a572499SJingjing Wu struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf = 18511a572499SJingjing Wu ð_conf->tx_adv_conf.vmdq_dcb_tx_conf; 1852013af9b6SIntel 1853013af9b6SIntel /* VMDQ+DCB RX and TX configrations */ 18541a572499SJingjing Wu vmdq_rx_conf->enable_default_pool = 0; 18551a572499SJingjing Wu vmdq_rx_conf->default_pool = 0; 18561a572499SJingjing Wu vmdq_rx_conf->nb_queue_pools = 18571a572499SJingjing Wu (num_tcs == ETH_4_TCS ? ETH_32_POOLS : ETH_16_POOLS); 18581a572499SJingjing Wu vmdq_tx_conf->nb_queue_pools = 18591a572499SJingjing Wu (num_tcs == ETH_4_TCS ? ETH_32_POOLS : ETH_16_POOLS); 1860013af9b6SIntel 18611a572499SJingjing Wu vmdq_rx_conf->nb_pool_maps = vmdq_rx_conf->nb_queue_pools; 18621a572499SJingjing Wu for (i = 0; i < vmdq_rx_conf->nb_pool_maps; i++) { 18631a572499SJingjing Wu vmdq_rx_conf->pool_map[i].vlan_id = vlan_tags[i]; 18641a572499SJingjing Wu vmdq_rx_conf->pool_map[i].pools = 18651a572499SJingjing Wu 1 << (i % vmdq_rx_conf->nb_queue_pools); 1866af75078fSIntel } 1867013af9b6SIntel for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) { 18681a572499SJingjing Wu vmdq_rx_conf->dcb_tc[i] = i; 18691a572499SJingjing Wu vmdq_tx_conf->dcb_tc[i] = i; 1870013af9b6SIntel } 1871013af9b6SIntel 1872013af9b6SIntel /* set DCB mode of RX and TX of multiple queues */ 187332e7aa0bSIntel eth_conf->rxmode.mq_mode = ETH_MQ_RX_VMDQ_DCB; 187432e7aa0bSIntel eth_conf->txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 18751a572499SJingjing Wu } else { 18761a572499SJingjing Wu struct rte_eth_dcb_rx_conf *rx_conf = 18771a572499SJingjing Wu ð_conf->rx_adv_conf.dcb_rx_conf; 18781a572499SJingjing Wu struct rte_eth_dcb_tx_conf *tx_conf = 18791a572499SJingjing Wu ð_conf->tx_adv_conf.dcb_tx_conf; 1880013af9b6SIntel 18811a572499SJingjing Wu rx_conf->nb_tcs = num_tcs; 18821a572499SJingjing Wu tx_conf->nb_tcs = num_tcs; 18831a572499SJingjing Wu 18841a572499SJingjing Wu for (i = 0; i < num_tcs; i++) { 18851a572499SJingjing Wu rx_conf->dcb_tc[i] = i; 18861a572499SJingjing Wu tx_conf->dcb_tc[i] = i; 1887013af9b6SIntel } 18881a572499SJingjing Wu eth_conf->rxmode.mq_mode = ETH_MQ_RX_DCB_RSS; 18891a572499SJingjing Wu eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_hf; 189032e7aa0bSIntel eth_conf->txmode.mq_mode = ETH_MQ_TX_DCB; 18911a572499SJingjing Wu } 18921a572499SJingjing Wu 18931a572499SJingjing Wu if (pfc_en) 18941a572499SJingjing Wu eth_conf->dcb_capability_en = 18951a572499SJingjing Wu ETH_DCB_PG_SUPPORT | ETH_DCB_PFC_SUPPORT; 1896013af9b6SIntel else 1897013af9b6SIntel eth_conf->dcb_capability_en = ETH_DCB_PG_SUPPORT; 1898013af9b6SIntel 1899013af9b6SIntel return 0; 1900013af9b6SIntel } 1901013af9b6SIntel 1902013af9b6SIntel int 19031a572499SJingjing Wu init_port_dcb_config(portid_t pid, 19041a572499SJingjing Wu enum dcb_mode_enable dcb_mode, 19051a572499SJingjing Wu enum rte_eth_nb_tcs num_tcs, 19061a572499SJingjing Wu uint8_t pfc_en) 1907013af9b6SIntel { 1908013af9b6SIntel struct rte_eth_conf port_conf; 19091a572499SJingjing Wu struct rte_eth_dev_info dev_info; 1910013af9b6SIntel struct rte_port *rte_port; 1911013af9b6SIntel int retval; 1912013af9b6SIntel uint16_t i; 1913013af9b6SIntel 19141a572499SJingjing Wu rte_eth_dev_info_get(pid, &dev_info); 19151a572499SJingjing Wu 19161a572499SJingjing Wu /* If dev_info.vmdq_pool_base is greater than 0, 19171a572499SJingjing Wu * the queue id of vmdq pools is started after pf queues. 19181a572499SJingjing Wu */ 19191a572499SJingjing Wu if (dcb_mode == DCB_VT_ENABLED && dev_info.vmdq_pool_base > 0) { 19201a572499SJingjing Wu printf("VMDQ_DCB multi-queue mode is nonsensical" 19211a572499SJingjing Wu " for port %d.", pid); 19221a572499SJingjing Wu return -1; 19231a572499SJingjing Wu } 19241a572499SJingjing Wu 19251a572499SJingjing Wu /* Assume the ports in testpmd have the same dcb capability 19261a572499SJingjing Wu * and has the same number of rxq and txq in dcb mode 19271a572499SJingjing Wu */ 19281a572499SJingjing Wu if (dcb_mode == DCB_VT_ENABLED) { 19291a572499SJingjing Wu nb_rxq = dev_info.max_rx_queues; 19301a572499SJingjing Wu nb_txq = dev_info.max_tx_queues; 19311a572499SJingjing Wu } else { 19321a572499SJingjing Wu /*if vt is disabled, use all pf queues */ 19331a572499SJingjing Wu if (dev_info.vmdq_pool_base == 0) { 19341a572499SJingjing Wu nb_rxq = dev_info.max_rx_queues; 19351a572499SJingjing Wu nb_txq = dev_info.max_tx_queues; 19361a572499SJingjing Wu } else { 19371a572499SJingjing Wu nb_rxq = (queueid_t)num_tcs; 19381a572499SJingjing Wu nb_txq = (queueid_t)num_tcs; 19391a572499SJingjing Wu 19401a572499SJingjing Wu } 19411a572499SJingjing Wu } 1942013af9b6SIntel rx_free_thresh = 64; 1943013af9b6SIntel 1944013af9b6SIntel memset(&port_conf, 0, sizeof(struct rte_eth_conf)); 1945013af9b6SIntel /* Enter DCB configuration status */ 1946013af9b6SIntel dcb_config = 1; 1947013af9b6SIntel 1948013af9b6SIntel /*set configuration of DCB in vt mode and DCB in non-vt mode*/ 19491a572499SJingjing Wu retval = get_eth_dcb_conf(&port_conf, dcb_mode, num_tcs, pfc_en); 1950013af9b6SIntel if (retval < 0) 1951013af9b6SIntel return retval; 1952013af9b6SIntel 1953013af9b6SIntel rte_port = &ports[pid]; 1954013af9b6SIntel memcpy(&rte_port->dev_conf, &port_conf, sizeof(struct rte_eth_conf)); 1955013af9b6SIntel 1956f2c5125aSPablo de Lara rxtx_port_config(rte_port); 1957013af9b6SIntel /* VLAN filter */ 1958013af9b6SIntel rte_port->dev_conf.rxmode.hw_vlan_filter = 1; 19591a572499SJingjing Wu for (i = 0; i < RTE_DIM(vlan_tags); i++) 1960013af9b6SIntel rx_vft_set(pid, vlan_tags[i], 1); 1961013af9b6SIntel 1962013af9b6SIntel rte_eth_macaddr_get(pid, &rte_port->eth_addr); 1963013af9b6SIntel map_port_queue_stats_mapping_registers(pid, rte_port); 1964013af9b6SIntel 19657741e4cfSIntel rte_port->dcb_flag = 1; 19667741e4cfSIntel 1967013af9b6SIntel return 0; 1968af75078fSIntel } 1969af75078fSIntel 1970ffc468ffSTetsuya Mukawa static void 1971ffc468ffSTetsuya Mukawa init_port(void) 1972ffc468ffSTetsuya Mukawa { 1973ffc468ffSTetsuya Mukawa portid_t pid; 1974ffc468ffSTetsuya Mukawa 1975ffc468ffSTetsuya Mukawa /* Configuration of Ethernet ports. */ 1976ffc468ffSTetsuya Mukawa ports = rte_zmalloc("testpmd: ports", 1977ffc468ffSTetsuya Mukawa sizeof(struct rte_port) * RTE_MAX_ETHPORTS, 1978ffc468ffSTetsuya Mukawa RTE_CACHE_LINE_SIZE); 1979ffc468ffSTetsuya Mukawa if (ports == NULL) { 1980ffc468ffSTetsuya Mukawa rte_exit(EXIT_FAILURE, 1981ffc468ffSTetsuya Mukawa "rte_zmalloc(%d struct rte_port) failed\n", 1982ffc468ffSTetsuya Mukawa RTE_MAX_ETHPORTS); 1983ffc468ffSTetsuya Mukawa } 1984ffc468ffSTetsuya Mukawa 1985ffc468ffSTetsuya Mukawa /* enabled allocated ports */ 1986ffc468ffSTetsuya Mukawa for (pid = 0; pid < nb_ports; pid++) 1987ffc468ffSTetsuya Mukawa ports[pid].enabled = 1; 1988ffc468ffSTetsuya Mukawa } 1989ffc468ffSTetsuya Mukawa 1990d3a274ceSZhihong Wang static void 1991d3a274ceSZhihong Wang force_quit(void) 1992d3a274ceSZhihong Wang { 1993d3a274ceSZhihong Wang pmd_test_exit(); 1994d3a274ceSZhihong Wang prompt_exit(); 1995d3a274ceSZhihong Wang } 1996d3a274ceSZhihong Wang 1997d3a274ceSZhihong Wang static void 1998d3a274ceSZhihong Wang signal_handler(int signum) 1999d3a274ceSZhihong Wang { 2000d3a274ceSZhihong Wang if (signum == SIGINT || signum == SIGTERM) { 2001d3a274ceSZhihong Wang printf("\nSignal %d received, preparing to exit...\n", 2002d3a274ceSZhihong Wang signum); 2003d3a274ceSZhihong Wang force_quit(); 2004d3a274ceSZhihong Wang /* exit with the expected status */ 2005d3a274ceSZhihong Wang signal(signum, SIG_DFL); 2006d3a274ceSZhihong Wang kill(getpid(), signum); 2007d3a274ceSZhihong Wang } 2008d3a274ceSZhihong Wang } 2009d3a274ceSZhihong Wang 2010af75078fSIntel int 2011af75078fSIntel main(int argc, char** argv) 2012af75078fSIntel { 2013af75078fSIntel int diag; 2014013af9b6SIntel uint8_t port_id; 2015af75078fSIntel 2016d3a274ceSZhihong Wang signal(SIGINT, signal_handler); 2017d3a274ceSZhihong Wang signal(SIGTERM, signal_handler); 2018d3a274ceSZhihong Wang 2019af75078fSIntel diag = rte_eal_init(argc, argv); 2020af75078fSIntel if (diag < 0) 2021af75078fSIntel rte_panic("Cannot init EAL\n"); 2022af75078fSIntel 2023af75078fSIntel nb_ports = (portid_t) rte_eth_dev_count(); 2024af75078fSIntel if (nb_ports == 0) 2025edab33b1STetsuya Mukawa RTE_LOG(WARNING, EAL, "No probed ethernet devices\n"); 2026af75078fSIntel 2027ffc468ffSTetsuya Mukawa /* allocate port structures, and init them */ 2028ffc468ffSTetsuya Mukawa init_port(); 2029ffc468ffSTetsuya Mukawa 2030af75078fSIntel set_def_fwd_config(); 2031af75078fSIntel if (nb_lcores == 0) 2032af75078fSIntel rte_panic("Empty set of forwarding logical cores - check the " 2033af75078fSIntel "core mask supplied in the command parameters\n"); 2034af75078fSIntel 2035af75078fSIntel argc -= diag; 2036af75078fSIntel argv += diag; 2037af75078fSIntel if (argc > 1) 2038af75078fSIntel launch_args_parse(argc, argv); 2039af75078fSIntel 2040af75078fSIntel if (nb_rxq > nb_txq) 2041af75078fSIntel printf("Warning: nb_rxq=%d enables RSS configuration, " 2042af75078fSIntel "but nb_txq=%d will prevent to fully test it.\n", 2043af75078fSIntel nb_rxq, nb_txq); 2044af75078fSIntel 2045af75078fSIntel init_config(); 2046148f963fSBruce Richardson if (start_port(RTE_PORT_ALL) != 0) 2047148f963fSBruce Richardson rte_exit(EXIT_FAILURE, "Start ports failed\n"); 2048af75078fSIntel 2049ce8d5614SIntel /* set all ports to promiscuous mode by default */ 2050edab33b1STetsuya Mukawa FOREACH_PORT(port_id, ports) 2051ce8d5614SIntel rte_eth_promiscuous_enable(port_id); 2052af75078fSIntel 20530d56cb81SThomas Monjalon #ifdef RTE_LIBRTE_CMDLINE 2054ca7feb22SCyril Chemparathy if (interactive == 1) { 2055ca7feb22SCyril Chemparathy if (auto_start) { 2056ca7feb22SCyril Chemparathy printf("Start automatic packet forwarding\n"); 2057ca7feb22SCyril Chemparathy start_packet_forwarding(0); 2058ca7feb22SCyril Chemparathy } 2059af75078fSIntel prompt(); 2060ca7feb22SCyril Chemparathy } else 20610d56cb81SThomas Monjalon #endif 20620d56cb81SThomas Monjalon { 2063af75078fSIntel char c; 2064af75078fSIntel int rc; 2065af75078fSIntel 2066af75078fSIntel printf("No commandline core given, start packet forwarding\n"); 2067af75078fSIntel start_packet_forwarding(0); 2068af75078fSIntel printf("Press enter to exit\n"); 2069af75078fSIntel rc = read(0, &c, 1); 2070d3a274ceSZhihong Wang pmd_test_exit(); 2071af75078fSIntel if (rc < 0) 2072af75078fSIntel return 1; 2073af75078fSIntel } 2074af75078fSIntel 2075af75078fSIntel return 0; 2076af75078fSIntel } 2077