xref: /dpdk/app/test-pmd/testpmd.c (revision 23ea57a2a0cecbb904a5feeb0650db116585ee28)
1174a1631SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
2174a1631SBruce Richardson  * Copyright(c) 2010-2017 Intel Corporation
3af75078fSIntel  */
4af75078fSIntel 
5af75078fSIntel #include <stdarg.h>
6af75078fSIntel #include <stdio.h>
7af75078fSIntel #include <stdlib.h>
8af75078fSIntel #include <signal.h>
9af75078fSIntel #include <string.h>
10af75078fSIntel #include <time.h>
11af75078fSIntel #include <fcntl.h>
121c036b16SEelco Chaudron #include <sys/mman.h>
13af75078fSIntel #include <sys/types.h>
14af75078fSIntel #include <errno.h>
15fb73e096SJeff Guo #include <stdbool.h>
16af75078fSIntel 
17af75078fSIntel #include <sys/queue.h>
18af75078fSIntel #include <sys/stat.h>
19af75078fSIntel 
20af75078fSIntel #include <stdint.h>
21af75078fSIntel #include <unistd.h>
22af75078fSIntel #include <inttypes.h>
23af75078fSIntel 
24af75078fSIntel #include <rte_common.h>
25d1eb542eSOlivier Matz #include <rte_errno.h>
26af75078fSIntel #include <rte_byteorder.h>
27af75078fSIntel #include <rte_log.h>
28af75078fSIntel #include <rte_debug.h>
29af75078fSIntel #include <rte_cycles.h>
30c7f5dba7SAnatoly Burakov #include <rte_malloc_heap.h>
31af75078fSIntel #include <rte_memory.h>
32af75078fSIntel #include <rte_memcpy.h>
33af75078fSIntel #include <rte_launch.h>
34af75078fSIntel #include <rte_eal.h>
35284c908cSGaetan Rivet #include <rte_alarm.h>
36af75078fSIntel #include <rte_per_lcore.h>
37af75078fSIntel #include <rte_lcore.h>
38af75078fSIntel #include <rte_atomic.h>
39af75078fSIntel #include <rte_branch_prediction.h>
40af75078fSIntel #include <rte_mempool.h>
41af75078fSIntel #include <rte_malloc.h>
42af75078fSIntel #include <rte_mbuf.h>
430e798567SPavan Nikhilesh #include <rte_mbuf_pool_ops.h>
44af75078fSIntel #include <rte_interrupts.h>
45af75078fSIntel #include <rte_pci.h>
46af75078fSIntel #include <rte_ether.h>
47af75078fSIntel #include <rte_ethdev.h>
48edab33b1STetsuya Mukawa #include <rte_dev.h>
49af75078fSIntel #include <rte_string_fns.h>
50e261265eSRadu Nicolau #ifdef RTE_LIBRTE_IXGBE_PMD
51e261265eSRadu Nicolau #include <rte_pmd_ixgbe.h>
52e261265eSRadu Nicolau #endif
53102b7329SReshma Pattan #ifdef RTE_LIBRTE_PDUMP
54102b7329SReshma Pattan #include <rte_pdump.h>
55102b7329SReshma Pattan #endif
56938a184aSAdrien Mazarguil #include <rte_flow.h>
577e4441c8SRemy Horton #include <rte_metrics.h>
587e4441c8SRemy Horton #ifdef RTE_LIBRTE_BITRATE
597e4441c8SRemy Horton #include <rte_bitrate.h>
607e4441c8SRemy Horton #endif
6162d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS
6262d3216dSReshma Pattan #include <rte_latencystats.h>
6362d3216dSReshma Pattan #endif
64af75078fSIntel 
65af75078fSIntel #include "testpmd.h"
66af75078fSIntel 
67c7f5dba7SAnatoly Burakov #ifndef MAP_HUGETLB
68c7f5dba7SAnatoly Burakov /* FreeBSD may not have MAP_HUGETLB (in fact, it probably doesn't) */
69c7f5dba7SAnatoly Burakov #define HUGE_FLAG (0x40000)
70c7f5dba7SAnatoly Burakov #else
71c7f5dba7SAnatoly Burakov #define HUGE_FLAG MAP_HUGETLB
72c7f5dba7SAnatoly Burakov #endif
73c7f5dba7SAnatoly Burakov 
74c7f5dba7SAnatoly Burakov #ifndef MAP_HUGE_SHIFT
75c7f5dba7SAnatoly Burakov /* older kernels (or FreeBSD) will not have this define */
76c7f5dba7SAnatoly Burakov #define HUGE_SHIFT (26)
77c7f5dba7SAnatoly Burakov #else
78c7f5dba7SAnatoly Burakov #define HUGE_SHIFT MAP_HUGE_SHIFT
79c7f5dba7SAnatoly Burakov #endif
80c7f5dba7SAnatoly Burakov 
81c7f5dba7SAnatoly Burakov #define EXTMEM_HEAP_NAME "extmem"
82c7f5dba7SAnatoly Burakov 
83af75078fSIntel uint16_t verbose_level = 0; /**< Silent by default. */
84285fd101SOlivier Matz int testpmd_logtype; /**< Log type for testpmd logs */
85af75078fSIntel 
86af75078fSIntel /* use master core for command line ? */
87af75078fSIntel uint8_t interactive = 0;
88ca7feb22SCyril Chemparathy uint8_t auto_start = 0;
8999cabef0SPablo de Lara uint8_t tx_first;
9081ef862bSAllain Legacy char cmdline_filename[PATH_MAX] = {0};
91af75078fSIntel 
92af75078fSIntel /*
93af75078fSIntel  * NUMA support configuration.
94af75078fSIntel  * When set, the NUMA support attempts to dispatch the allocation of the
95af75078fSIntel  * RX and TX memory rings, and of the DMA memory buffers (mbufs) for the
96af75078fSIntel  * probed ports among the CPU sockets 0 and 1.
97af75078fSIntel  * Otherwise, all memory is allocated from CPU socket 0.
98af75078fSIntel  */
99999b2ee0SBruce Richardson uint8_t numa_support = 1; /**< numa enabled by default */
100af75078fSIntel 
101af75078fSIntel /*
102b6ea6408SIntel  * In UMA mode,all memory is allocated from socket 0 if --socket-num is
103b6ea6408SIntel  * not configured.
104b6ea6408SIntel  */
105b6ea6408SIntel uint8_t socket_num = UMA_NO_CONFIG;
106b6ea6408SIntel 
107b6ea6408SIntel /*
108c7f5dba7SAnatoly Burakov  * Select mempool allocation type:
109c7f5dba7SAnatoly Burakov  * - native: use regular DPDK memory
110c7f5dba7SAnatoly Burakov  * - anon: use regular DPDK memory to create mempool, but populate using
111c7f5dba7SAnatoly Burakov  *         anonymous memory (may not be IOVA-contiguous)
112c7f5dba7SAnatoly Burakov  * - xmem: use externally allocated hugepage memory
113148f963fSBruce Richardson  */
114c7f5dba7SAnatoly Burakov uint8_t mp_alloc_type = MP_ALLOC_NATIVE;
115148f963fSBruce Richardson 
116148f963fSBruce Richardson /*
11763531389SGeorgios Katsikas  * Store specified sockets on which memory pool to be used by ports
11863531389SGeorgios Katsikas  * is allocated.
11963531389SGeorgios Katsikas  */
12063531389SGeorgios Katsikas uint8_t port_numa[RTE_MAX_ETHPORTS];
12163531389SGeorgios Katsikas 
12263531389SGeorgios Katsikas /*
12363531389SGeorgios Katsikas  * Store specified sockets on which RX ring to be used by ports
12463531389SGeorgios Katsikas  * is allocated.
12563531389SGeorgios Katsikas  */
12663531389SGeorgios Katsikas uint8_t rxring_numa[RTE_MAX_ETHPORTS];
12763531389SGeorgios Katsikas 
12863531389SGeorgios Katsikas /*
12963531389SGeorgios Katsikas  * Store specified sockets on which TX ring to be used by ports
13063531389SGeorgios Katsikas  * is allocated.
13163531389SGeorgios Katsikas  */
13263531389SGeorgios Katsikas uint8_t txring_numa[RTE_MAX_ETHPORTS];
13363531389SGeorgios Katsikas 
13463531389SGeorgios Katsikas /*
135af75078fSIntel  * Record the Ethernet address of peer target ports to which packets are
136af75078fSIntel  * forwarded.
137547d946cSNirmoy Das  * Must be instantiated with the ethernet addresses of peer traffic generator
138af75078fSIntel  * ports.
139af75078fSIntel  */
140af75078fSIntel struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS];
141af75078fSIntel portid_t nb_peer_eth_addrs = 0;
142af75078fSIntel 
143af75078fSIntel /*
144af75078fSIntel  * Probed Target Environment.
145af75078fSIntel  */
146af75078fSIntel struct rte_port *ports;	       /**< For all probed ethernet ports. */
147af75078fSIntel portid_t nb_ports;             /**< Number of probed ethernet ports. */
148af75078fSIntel struct fwd_lcore **fwd_lcores; /**< For all probed logical cores. */
149af75078fSIntel lcoreid_t nb_lcores;           /**< Number of probed logical cores. */
150af75078fSIntel 
1514918a357SXiaoyun Li portid_t ports_ids[RTE_MAX_ETHPORTS]; /**< Store all port ids. */
1524918a357SXiaoyun Li 
153af75078fSIntel /*
154af75078fSIntel  * Test Forwarding Configuration.
155af75078fSIntel  *    nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores
156af75078fSIntel  *    nb_fwd_ports  <= nb_cfg_ports  <= nb_ports
157af75078fSIntel  */
158af75078fSIntel lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */
159af75078fSIntel lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */
160af75078fSIntel portid_t  nb_cfg_ports;  /**< Number of configured ports. */
161af75078fSIntel portid_t  nb_fwd_ports;  /**< Number of forwarding ports. */
162af75078fSIntel 
163af75078fSIntel unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE]; /**< CPU ids configuration. */
164af75078fSIntel portid_t fwd_ports_ids[RTE_MAX_ETHPORTS];      /**< Port ids configuration. */
165af75078fSIntel 
166af75078fSIntel struct fwd_stream **fwd_streams; /**< For each RX queue of each port. */
167af75078fSIntel streamid_t nb_fwd_streams;       /**< Is equal to (nb_ports * nb_rxq). */
168af75078fSIntel 
169af75078fSIntel /*
170af75078fSIntel  * Forwarding engines.
171af75078fSIntel  */
172af75078fSIntel struct fwd_engine * fwd_engines[] = {
173af75078fSIntel 	&io_fwd_engine,
174af75078fSIntel 	&mac_fwd_engine,
175d47388f1SCyril Chemparathy 	&mac_swap_engine,
176e9e23a61SCyril Chemparathy 	&flow_gen_engine,
177af75078fSIntel 	&rx_only_engine,
178af75078fSIntel 	&tx_only_engine,
179af75078fSIntel 	&csum_fwd_engine,
180168dfa61SIvan Boule 	&icmp_echo_engine,
1813c156061SJens Freimann 	&noisy_vnf_engine,
1820ad778b3SJasvinder Singh #if defined RTE_LIBRTE_PMD_SOFTNIC
1830ad778b3SJasvinder Singh 	&softnic_fwd_engine,
1845b590fbeSJasvinder Singh #endif
185af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588
186af75078fSIntel 	&ieee1588_fwd_engine,
187af75078fSIntel #endif
188af75078fSIntel 	NULL,
189af75078fSIntel };
190af75078fSIntel 
191af75078fSIntel struct fwd_config cur_fwd_config;
192af75078fSIntel struct fwd_engine *cur_fwd_eng = &io_fwd_engine; /**< IO mode by default. */
193bf56fce1SZhihong Wang uint32_t retry_enabled;
194bf56fce1SZhihong Wang uint32_t burst_tx_delay_time = BURST_TX_WAIT_US;
195bf56fce1SZhihong Wang uint32_t burst_tx_retry_num = BURST_TX_RETRIES;
196af75078fSIntel 
197af75078fSIntel uint16_t mbuf_data_size = DEFAULT_MBUF_DATA_SIZE; /**< Mbuf data space size. */
198c8798818SIntel uint32_t param_total_num_mbufs = 0;  /**< number of mbufs in all pools - if
199c8798818SIntel                                       * specified on command-line. */
200cfea1f30SPablo de Lara uint16_t stats_period; /**< Period to show statistics (disabled by default) */
201d9a191a0SPhil Yang 
202d9a191a0SPhil Yang /*
203d9a191a0SPhil Yang  * In container, it cannot terminate the process which running with 'stats-period'
204d9a191a0SPhil Yang  * option. Set flag to exit stats period loop after received SIGINT/SIGTERM.
205d9a191a0SPhil Yang  */
206d9a191a0SPhil Yang uint8_t f_quit;
207d9a191a0SPhil Yang 
208af75078fSIntel /*
209af75078fSIntel  * Configuration of packet segments used by the "txonly" processing engine.
210af75078fSIntel  */
211af75078fSIntel uint16_t tx_pkt_length = TXONLY_DEF_PACKET_LEN; /**< TXONLY packet length. */
212af75078fSIntel uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT] = {
213af75078fSIntel 	TXONLY_DEF_PACKET_LEN,
214af75078fSIntel };
215af75078fSIntel uint8_t  tx_pkt_nb_segs = 1; /**< Number of segments in TXONLY packets */
216af75078fSIntel 
21779bec05bSKonstantin Ananyev enum tx_pkt_split tx_pkt_split = TX_PKT_SPLIT_OFF;
21879bec05bSKonstantin Ananyev /**< Split policy for packets to TX. */
21979bec05bSKonstantin Ananyev 
220af75078fSIntel uint16_t nb_pkt_per_burst = DEF_PKT_BURST; /**< Number of packets per burst. */
221e9378bbcSCunming Liang uint16_t mb_mempool_cache = DEF_MBUF_CACHE; /**< Size of mbuf mempool cache. */
222af75078fSIntel 
223900550deSIntel /* current configuration is in DCB or not,0 means it is not in DCB mode */
224900550deSIntel uint8_t dcb_config = 0;
225900550deSIntel 
226900550deSIntel /* Whether the dcb is in testing status */
227900550deSIntel uint8_t dcb_test = 0;
228900550deSIntel 
229af75078fSIntel /*
230af75078fSIntel  * Configurable number of RX/TX queues.
231af75078fSIntel  */
232af75078fSIntel queueid_t nb_rxq = 1; /**< Number of RX queues per port. */
233af75078fSIntel queueid_t nb_txq = 1; /**< Number of TX queues per port. */
234af75078fSIntel 
235af75078fSIntel /*
236af75078fSIntel  * Configurable number of RX/TX ring descriptors.
2378599ed31SRemy Horton  * Defaults are supplied by drivers via ethdev.
238af75078fSIntel  */
2398599ed31SRemy Horton #define RTE_TEST_RX_DESC_DEFAULT 0
2408599ed31SRemy Horton #define RTE_TEST_TX_DESC_DEFAULT 0
241af75078fSIntel uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT; /**< Number of RX descriptors. */
242af75078fSIntel uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT; /**< Number of TX descriptors. */
243af75078fSIntel 
244f2c5125aSPablo de Lara #define RTE_PMD_PARAM_UNSET -1
245af75078fSIntel /*
246af75078fSIntel  * Configurable values of RX and TX ring threshold registers.
247af75078fSIntel  */
248af75078fSIntel 
249f2c5125aSPablo de Lara int8_t rx_pthresh = RTE_PMD_PARAM_UNSET;
250f2c5125aSPablo de Lara int8_t rx_hthresh = RTE_PMD_PARAM_UNSET;
251f2c5125aSPablo de Lara int8_t rx_wthresh = RTE_PMD_PARAM_UNSET;
252af75078fSIntel 
253f2c5125aSPablo de Lara int8_t tx_pthresh = RTE_PMD_PARAM_UNSET;
254f2c5125aSPablo de Lara int8_t tx_hthresh = RTE_PMD_PARAM_UNSET;
255f2c5125aSPablo de Lara int8_t tx_wthresh = RTE_PMD_PARAM_UNSET;
256af75078fSIntel 
257af75078fSIntel /*
258af75078fSIntel  * Configurable value of RX free threshold.
259af75078fSIntel  */
260f2c5125aSPablo de Lara int16_t rx_free_thresh = RTE_PMD_PARAM_UNSET;
261af75078fSIntel 
262af75078fSIntel /*
263ce8d5614SIntel  * Configurable value of RX drop enable.
264ce8d5614SIntel  */
265f2c5125aSPablo de Lara int8_t rx_drop_en = RTE_PMD_PARAM_UNSET;
266ce8d5614SIntel 
267ce8d5614SIntel /*
268af75078fSIntel  * Configurable value of TX free threshold.
269af75078fSIntel  */
270f2c5125aSPablo de Lara int16_t tx_free_thresh = RTE_PMD_PARAM_UNSET;
271af75078fSIntel 
272af75078fSIntel /*
273af75078fSIntel  * Configurable value of TX RS bit threshold.
274af75078fSIntel  */
275f2c5125aSPablo de Lara int16_t tx_rs_thresh = RTE_PMD_PARAM_UNSET;
276af75078fSIntel 
277af75078fSIntel /*
2783c156061SJens Freimann  * Configurable value of buffered packets before sending.
2793c156061SJens Freimann  */
2803c156061SJens Freimann uint16_t noisy_tx_sw_bufsz;
2813c156061SJens Freimann 
2823c156061SJens Freimann /*
2833c156061SJens Freimann  * Configurable value of packet buffer timeout.
2843c156061SJens Freimann  */
2853c156061SJens Freimann uint16_t noisy_tx_sw_buf_flush_time;
2863c156061SJens Freimann 
2873c156061SJens Freimann /*
2883c156061SJens Freimann  * Configurable value for size of VNF internal memory area
2893c156061SJens Freimann  * used for simulating noisy neighbour behaviour
2903c156061SJens Freimann  */
2913c156061SJens Freimann uint64_t noisy_lkup_mem_sz;
2923c156061SJens Freimann 
2933c156061SJens Freimann /*
2943c156061SJens Freimann  * Configurable value of number of random writes done in
2953c156061SJens Freimann  * VNF simulation memory area.
2963c156061SJens Freimann  */
2973c156061SJens Freimann uint64_t noisy_lkup_num_writes;
2983c156061SJens Freimann 
2993c156061SJens Freimann /*
3003c156061SJens Freimann  * Configurable value of number of random reads done in
3013c156061SJens Freimann  * VNF simulation memory area.
3023c156061SJens Freimann  */
3033c156061SJens Freimann uint64_t noisy_lkup_num_reads;
3043c156061SJens Freimann 
3053c156061SJens Freimann /*
3063c156061SJens Freimann  * Configurable value of number of random reads/writes done in
3073c156061SJens Freimann  * VNF simulation memory area.
3083c156061SJens Freimann  */
3093c156061SJens Freimann uint64_t noisy_lkup_num_reads_writes;
3103c156061SJens Freimann 
3113c156061SJens Freimann /*
312af75078fSIntel  * Receive Side Scaling (RSS) configuration.
313af75078fSIntel  */
3148a387fa8SHelin Zhang uint64_t rss_hf = ETH_RSS_IP; /* RSS IP by default. */
315af75078fSIntel 
316af75078fSIntel /*
317af75078fSIntel  * Port topology configuration
318af75078fSIntel  */
319af75078fSIntel uint16_t port_topology = PORT_TOPOLOGY_PAIRED; /* Ports are paired by default */
320af75078fSIntel 
3217741e4cfSIntel /*
3227741e4cfSIntel  * Avoids to flush all the RX streams before starts forwarding.
3237741e4cfSIntel  */
3247741e4cfSIntel uint8_t no_flush_rx = 0; /* flush by default */
3257741e4cfSIntel 
326af75078fSIntel /*
3277ee3e944SVasily Philipov  * Flow API isolated mode.
3287ee3e944SVasily Philipov  */
3297ee3e944SVasily Philipov uint8_t flow_isolate_all;
3307ee3e944SVasily Philipov 
3317ee3e944SVasily Philipov /*
332bc202406SDavid Marchand  * Avoids to check link status when starting/stopping a port.
333bc202406SDavid Marchand  */
334bc202406SDavid Marchand uint8_t no_link_check = 0; /* check by default */
335bc202406SDavid Marchand 
336bc202406SDavid Marchand /*
3378ea656f8SGaetan Rivet  * Enable link status change notification
3388ea656f8SGaetan Rivet  */
3398ea656f8SGaetan Rivet uint8_t lsc_interrupt = 1; /* enabled by default */
3408ea656f8SGaetan Rivet 
3418ea656f8SGaetan Rivet /*
342284c908cSGaetan Rivet  * Enable device removal notification.
343284c908cSGaetan Rivet  */
344284c908cSGaetan Rivet uint8_t rmv_interrupt = 1; /* enabled by default */
345284c908cSGaetan Rivet 
346fb73e096SJeff Guo uint8_t hot_plug = 0; /**< hotplug disabled by default. */
347fb73e096SJeff Guo 
348284c908cSGaetan Rivet /*
3493af72783SGaetan Rivet  * Display or mask ether events
3503af72783SGaetan Rivet  * Default to all events except VF_MBOX
3513af72783SGaetan Rivet  */
3523af72783SGaetan Rivet uint32_t event_print_mask = (UINT32_C(1) << RTE_ETH_EVENT_UNKNOWN) |
3533af72783SGaetan Rivet 			    (UINT32_C(1) << RTE_ETH_EVENT_INTR_LSC) |
3543af72783SGaetan Rivet 			    (UINT32_C(1) << RTE_ETH_EVENT_QUEUE_STATE) |
3553af72783SGaetan Rivet 			    (UINT32_C(1) << RTE_ETH_EVENT_INTR_RESET) |
356badb87c1SAnoob Joseph 			    (UINT32_C(1) << RTE_ETH_EVENT_IPSEC) |
3573af72783SGaetan Rivet 			    (UINT32_C(1) << RTE_ETH_EVENT_MACSEC) |
3583af72783SGaetan Rivet 			    (UINT32_C(1) << RTE_ETH_EVENT_INTR_RMV);
359e505d84cSAnatoly Burakov /*
360e505d84cSAnatoly Burakov  * Decide if all memory are locked for performance.
361e505d84cSAnatoly Burakov  */
362e505d84cSAnatoly Burakov int do_mlockall = 0;
3633af72783SGaetan Rivet 
3643af72783SGaetan Rivet /*
3657b7e5ba7SIntel  * NIC bypass mode configuration options.
3667b7e5ba7SIntel  */
3677b7e5ba7SIntel 
36850c4440eSThomas Monjalon #if defined RTE_LIBRTE_IXGBE_PMD && defined RTE_LIBRTE_IXGBE_BYPASS
3697b7e5ba7SIntel /* The NIC bypass watchdog timeout. */
370e261265eSRadu Nicolau uint32_t bypass_timeout = RTE_PMD_IXGBE_BYPASS_TMT_OFF;
3717b7e5ba7SIntel #endif
3727b7e5ba7SIntel 
373e261265eSRadu Nicolau 
37462d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS
37562d3216dSReshma Pattan 
37662d3216dSReshma Pattan /*
37762d3216dSReshma Pattan  * Set when latency stats is enabled in the commandline
37862d3216dSReshma Pattan  */
37962d3216dSReshma Pattan uint8_t latencystats_enabled;
38062d3216dSReshma Pattan 
38162d3216dSReshma Pattan /*
38262d3216dSReshma Pattan  * Lcore ID to serive latency statistics.
38362d3216dSReshma Pattan  */
38462d3216dSReshma Pattan lcoreid_t latencystats_lcore_id = -1;
38562d3216dSReshma Pattan 
38662d3216dSReshma Pattan #endif
38762d3216dSReshma Pattan 
3887b7e5ba7SIntel /*
389af75078fSIntel  * Ethernet device configuration.
390af75078fSIntel  */
391af75078fSIntel struct rte_eth_rxmode rx_mode = {
392af75078fSIntel 	.max_rx_pkt_len = ETHER_MAX_LEN, /**< Default maximum frame length. */
393af75078fSIntel };
394af75078fSIntel 
39507e5f7bdSShahaf Shuler struct rte_eth_txmode tx_mode = {
39607e5f7bdSShahaf Shuler 	.offloads = DEV_TX_OFFLOAD_MBUF_FAST_FREE,
39707e5f7bdSShahaf Shuler };
398fd8c20aaSShahaf Shuler 
399af75078fSIntel struct rte_fdir_conf fdir_conf = {
400af75078fSIntel 	.mode = RTE_FDIR_MODE_NONE,
401af75078fSIntel 	.pballoc = RTE_FDIR_PBALLOC_64K,
402af75078fSIntel 	.status = RTE_FDIR_REPORT_STATUS,
403d9d5e6f2SJingjing Wu 	.mask = {
40426f579aaSWei Zhao 		.vlan_tci_mask = 0xFFEF,
405d9d5e6f2SJingjing Wu 		.ipv4_mask     = {
406d9d5e6f2SJingjing Wu 			.src_ip = 0xFFFFFFFF,
407d9d5e6f2SJingjing Wu 			.dst_ip = 0xFFFFFFFF,
408d9d5e6f2SJingjing Wu 		},
409d9d5e6f2SJingjing Wu 		.ipv6_mask     = {
410d9d5e6f2SJingjing Wu 			.src_ip = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
411d9d5e6f2SJingjing Wu 			.dst_ip = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
412d9d5e6f2SJingjing Wu 		},
413d9d5e6f2SJingjing Wu 		.src_port_mask = 0xFFFF,
414d9d5e6f2SJingjing Wu 		.dst_port_mask = 0xFFFF,
41547b3ac6bSWenzhuo Lu 		.mac_addr_byte_mask = 0xFF,
41647b3ac6bSWenzhuo Lu 		.tunnel_type_mask = 1,
41747b3ac6bSWenzhuo Lu 		.tunnel_id_mask = 0xFFFFFFFF,
418d9d5e6f2SJingjing Wu 	},
419af75078fSIntel 	.drop_queue = 127,
420af75078fSIntel };
421af75078fSIntel 
4222950a769SDeclan Doherty volatile int test_done = 1; /* stop packet forwarding when set to 1. */
423af75078fSIntel 
424ed30d9b6SIntel struct queue_stats_mappings tx_queue_stats_mappings_array[MAX_TX_QUEUE_STATS_MAPPINGS];
425ed30d9b6SIntel struct queue_stats_mappings rx_queue_stats_mappings_array[MAX_RX_QUEUE_STATS_MAPPINGS];
426ed30d9b6SIntel 
427ed30d9b6SIntel struct queue_stats_mappings *tx_queue_stats_mappings = tx_queue_stats_mappings_array;
428ed30d9b6SIntel struct queue_stats_mappings *rx_queue_stats_mappings = rx_queue_stats_mappings_array;
429ed30d9b6SIntel 
430ed30d9b6SIntel uint16_t nb_tx_queue_stats_mappings = 0;
431ed30d9b6SIntel uint16_t nb_rx_queue_stats_mappings = 0;
432ed30d9b6SIntel 
433a4fd5eeeSElza Mathew /*
434a4fd5eeeSElza Mathew  * Display zero values by default for xstats
435a4fd5eeeSElza Mathew  */
436a4fd5eeeSElza Mathew uint8_t xstats_hide_zero;
437a4fd5eeeSElza Mathew 
438c9cafcc8SShahaf Shuler unsigned int num_sockets = 0;
439c9cafcc8SShahaf Shuler unsigned int socket_ids[RTE_MAX_NUMA_NODES];
4407acf894dSStephen Hurd 
441e25e6c70SRemy Horton #ifdef RTE_LIBRTE_BITRATE
4427e4441c8SRemy Horton /* Bitrate statistics */
4437e4441c8SRemy Horton struct rte_stats_bitrates *bitrate_data;
444e25e6c70SRemy Horton lcoreid_t bitrate_lcore_id;
445e25e6c70SRemy Horton uint8_t bitrate_enabled;
446e25e6c70SRemy Horton #endif
4477e4441c8SRemy Horton 
448b40f8d78SJiayu Hu struct gro_status gro_ports[RTE_MAX_ETHPORTS];
449b7091f1dSJiayu Hu uint8_t gro_flush_cycles = GRO_DEFAULT_FLUSH_CYCLES;
450b40f8d78SJiayu Hu 
4511960be7dSNelio Laranjeiro struct vxlan_encap_conf vxlan_encap_conf = {
4521960be7dSNelio Laranjeiro 	.select_ipv4 = 1,
4531960be7dSNelio Laranjeiro 	.select_vlan = 0,
4541960be7dSNelio Laranjeiro 	.vni = "\x00\x00\x00",
4551960be7dSNelio Laranjeiro 	.udp_src = 0,
4561960be7dSNelio Laranjeiro 	.udp_dst = RTE_BE16(4789),
4571960be7dSNelio Laranjeiro 	.ipv4_src = IPv4(127, 0, 0, 1),
4581960be7dSNelio Laranjeiro 	.ipv4_dst = IPv4(255, 255, 255, 255),
4591960be7dSNelio Laranjeiro 	.ipv6_src = "\x00\x00\x00\x00\x00\x00\x00\x00"
4601960be7dSNelio Laranjeiro 		"\x00\x00\x00\x00\x00\x00\x00\x01",
4611960be7dSNelio Laranjeiro 	.ipv6_dst = "\x00\x00\x00\x00\x00\x00\x00\x00"
4621960be7dSNelio Laranjeiro 		"\x00\x00\x00\x00\x00\x00\x11\x11",
4631960be7dSNelio Laranjeiro 	.vlan_tci = 0,
4641960be7dSNelio Laranjeiro 	.eth_src = "\x00\x00\x00\x00\x00\x00",
4651960be7dSNelio Laranjeiro 	.eth_dst = "\xff\xff\xff\xff\xff\xff",
4661960be7dSNelio Laranjeiro };
4671960be7dSNelio Laranjeiro 
468dcd962fcSNelio Laranjeiro struct nvgre_encap_conf nvgre_encap_conf = {
469dcd962fcSNelio Laranjeiro 	.select_ipv4 = 1,
470dcd962fcSNelio Laranjeiro 	.select_vlan = 0,
471dcd962fcSNelio Laranjeiro 	.tni = "\x00\x00\x00",
472dcd962fcSNelio Laranjeiro 	.ipv4_src = IPv4(127, 0, 0, 1),
473dcd962fcSNelio Laranjeiro 	.ipv4_dst = IPv4(255, 255, 255, 255),
474dcd962fcSNelio Laranjeiro 	.ipv6_src = "\x00\x00\x00\x00\x00\x00\x00\x00"
475dcd962fcSNelio Laranjeiro 		"\x00\x00\x00\x00\x00\x00\x00\x01",
476dcd962fcSNelio Laranjeiro 	.ipv6_dst = "\x00\x00\x00\x00\x00\x00\x00\x00"
477dcd962fcSNelio Laranjeiro 		"\x00\x00\x00\x00\x00\x00\x11\x11",
478dcd962fcSNelio Laranjeiro 	.vlan_tci = 0,
479dcd962fcSNelio Laranjeiro 	.eth_src = "\x00\x00\x00\x00\x00\x00",
480dcd962fcSNelio Laranjeiro 	.eth_dst = "\xff\xff\xff\xff\xff\xff",
481dcd962fcSNelio Laranjeiro };
482dcd962fcSNelio Laranjeiro 
483ed30d9b6SIntel /* Forward function declarations */
48428caa76aSZhiyong Yang static void map_port_queue_stats_mapping_registers(portid_t pi,
48528caa76aSZhiyong Yang 						   struct rte_port *port);
486edab33b1STetsuya Mukawa static void check_all_ports_link_status(uint32_t port_mask);
487f8244c63SZhiyong Yang static int eth_event_callback(portid_t port_id,
48876ad4a2dSGaetan Rivet 			      enum rte_eth_event_type type,
489d6af1a13SBernard Iremonger 			      void *param, void *ret_param);
49089ecd110SJeff Guo static void eth_dev_event_callback(const char *device_name,
491fb73e096SJeff Guo 				enum rte_dev_event_type type,
492fb73e096SJeff Guo 				void *param);
493ce8d5614SIntel 
494ce8d5614SIntel /*
495ce8d5614SIntel  * Check if all the ports are started.
496ce8d5614SIntel  * If yes, return positive value. If not, return zero.
497ce8d5614SIntel  */
498ce8d5614SIntel static int all_ports_started(void);
499ed30d9b6SIntel 
50052f38a20SJiayu Hu struct gso_status gso_ports[RTE_MAX_ETHPORTS];
50152f38a20SJiayu Hu uint16_t gso_max_segment_size = ETHER_MAX_LEN - ETHER_CRC_LEN;
50252f38a20SJiayu Hu 
503af75078fSIntel /*
50498a7ea33SJerin Jacob  * Helper function to check if socket is already discovered.
505c9cafcc8SShahaf Shuler  * If yes, return positive value. If not, return zero.
506c9cafcc8SShahaf Shuler  */
507c9cafcc8SShahaf Shuler int
508c9cafcc8SShahaf Shuler new_socket_id(unsigned int socket_id)
509c9cafcc8SShahaf Shuler {
510c9cafcc8SShahaf Shuler 	unsigned int i;
511c9cafcc8SShahaf Shuler 
512c9cafcc8SShahaf Shuler 	for (i = 0; i < num_sockets; i++) {
513c9cafcc8SShahaf Shuler 		if (socket_ids[i] == socket_id)
514c9cafcc8SShahaf Shuler 			return 0;
515c9cafcc8SShahaf Shuler 	}
516c9cafcc8SShahaf Shuler 	return 1;
517c9cafcc8SShahaf Shuler }
518c9cafcc8SShahaf Shuler 
519c9cafcc8SShahaf Shuler /*
520af75078fSIntel  * Setup default configuration.
521af75078fSIntel  */
522af75078fSIntel static void
523af75078fSIntel set_default_fwd_lcores_config(void)
524af75078fSIntel {
525af75078fSIntel 	unsigned int i;
526af75078fSIntel 	unsigned int nb_lc;
5277acf894dSStephen Hurd 	unsigned int sock_num;
528af75078fSIntel 
529af75078fSIntel 	nb_lc = 0;
530af75078fSIntel 	for (i = 0; i < RTE_MAX_LCORE; i++) {
531dbfb8ec7SPhil Yang 		if (!rte_lcore_is_enabled(i))
532dbfb8ec7SPhil Yang 			continue;
533c9cafcc8SShahaf Shuler 		sock_num = rte_lcore_to_socket_id(i);
534c9cafcc8SShahaf Shuler 		if (new_socket_id(sock_num)) {
535c9cafcc8SShahaf Shuler 			if (num_sockets >= RTE_MAX_NUMA_NODES) {
536c9cafcc8SShahaf Shuler 				rte_exit(EXIT_FAILURE,
537c9cafcc8SShahaf Shuler 					 "Total sockets greater than %u\n",
538c9cafcc8SShahaf Shuler 					 RTE_MAX_NUMA_NODES);
539c9cafcc8SShahaf Shuler 			}
540c9cafcc8SShahaf Shuler 			socket_ids[num_sockets++] = sock_num;
5417acf894dSStephen Hurd 		}
542f54fe5eeSStephen Hurd 		if (i == rte_get_master_lcore())
543f54fe5eeSStephen Hurd 			continue;
544f54fe5eeSStephen Hurd 		fwd_lcores_cpuids[nb_lc++] = i;
545af75078fSIntel 	}
546af75078fSIntel 	nb_lcores = (lcoreid_t) nb_lc;
547af75078fSIntel 	nb_cfg_lcores = nb_lcores;
548af75078fSIntel 	nb_fwd_lcores = 1;
549af75078fSIntel }
550af75078fSIntel 
551af75078fSIntel static void
552af75078fSIntel set_def_peer_eth_addrs(void)
553af75078fSIntel {
554af75078fSIntel 	portid_t i;
555af75078fSIntel 
556af75078fSIntel 	for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
557af75078fSIntel 		peer_eth_addrs[i].addr_bytes[0] = ETHER_LOCAL_ADMIN_ADDR;
558af75078fSIntel 		peer_eth_addrs[i].addr_bytes[5] = i;
559af75078fSIntel 	}
560af75078fSIntel }
561af75078fSIntel 
562af75078fSIntel static void
563af75078fSIntel set_default_fwd_ports_config(void)
564af75078fSIntel {
565af75078fSIntel 	portid_t pt_id;
56665a7360cSMatan Azrad 	int i = 0;
567af75078fSIntel 
568effdb8bbSPhil Yang 	RTE_ETH_FOREACH_DEV(pt_id) {
56965a7360cSMatan Azrad 		fwd_ports_ids[i++] = pt_id;
570af75078fSIntel 
571effdb8bbSPhil Yang 		/* Update sockets info according to the attached device */
572effdb8bbSPhil Yang 		int socket_id = rte_eth_dev_socket_id(pt_id);
573effdb8bbSPhil Yang 		if (socket_id >= 0 && new_socket_id(socket_id)) {
574effdb8bbSPhil Yang 			if (num_sockets >= RTE_MAX_NUMA_NODES) {
575effdb8bbSPhil Yang 				rte_exit(EXIT_FAILURE,
576effdb8bbSPhil Yang 					 "Total sockets greater than %u\n",
577effdb8bbSPhil Yang 					 RTE_MAX_NUMA_NODES);
578effdb8bbSPhil Yang 			}
579effdb8bbSPhil Yang 			socket_ids[num_sockets++] = socket_id;
580effdb8bbSPhil Yang 		}
581effdb8bbSPhil Yang 	}
582effdb8bbSPhil Yang 
583af75078fSIntel 	nb_cfg_ports = nb_ports;
584af75078fSIntel 	nb_fwd_ports = nb_ports;
585af75078fSIntel }
586af75078fSIntel 
587af75078fSIntel void
588af75078fSIntel set_def_fwd_config(void)
589af75078fSIntel {
590af75078fSIntel 	set_default_fwd_lcores_config();
591af75078fSIntel 	set_def_peer_eth_addrs();
592af75078fSIntel 	set_default_fwd_ports_config();
593af75078fSIntel }
594af75078fSIntel 
595c7f5dba7SAnatoly Burakov /* extremely pessimistic estimation of memory required to create a mempool */
596c7f5dba7SAnatoly Burakov static int
597c7f5dba7SAnatoly Burakov calc_mem_size(uint32_t nb_mbufs, uint32_t mbuf_sz, size_t pgsz, size_t *out)
598c7f5dba7SAnatoly Burakov {
599c7f5dba7SAnatoly Burakov 	unsigned int n_pages, mbuf_per_pg, leftover;
600c7f5dba7SAnatoly Burakov 	uint64_t total_mem, mbuf_mem, obj_sz;
601c7f5dba7SAnatoly Burakov 
602c7f5dba7SAnatoly Burakov 	/* there is no good way to predict how much space the mempool will
603c7f5dba7SAnatoly Burakov 	 * occupy because it will allocate chunks on the fly, and some of those
604c7f5dba7SAnatoly Burakov 	 * will come from default DPDK memory while some will come from our
605c7f5dba7SAnatoly Burakov 	 * external memory, so just assume 128MB will be enough for everyone.
606c7f5dba7SAnatoly Burakov 	 */
607c7f5dba7SAnatoly Burakov 	uint64_t hdr_mem = 128 << 20;
608c7f5dba7SAnatoly Burakov 
609c7f5dba7SAnatoly Burakov 	/* account for possible non-contiguousness */
610c7f5dba7SAnatoly Burakov 	obj_sz = rte_mempool_calc_obj_size(mbuf_sz, 0, NULL);
611c7f5dba7SAnatoly Burakov 	if (obj_sz > pgsz) {
612c7f5dba7SAnatoly Burakov 		TESTPMD_LOG(ERR, "Object size is bigger than page size\n");
613c7f5dba7SAnatoly Burakov 		return -1;
614c7f5dba7SAnatoly Burakov 	}
615c7f5dba7SAnatoly Burakov 
616c7f5dba7SAnatoly Burakov 	mbuf_per_pg = pgsz / obj_sz;
617c7f5dba7SAnatoly Burakov 	leftover = (nb_mbufs % mbuf_per_pg) > 0;
618c7f5dba7SAnatoly Burakov 	n_pages = (nb_mbufs / mbuf_per_pg) + leftover;
619c7f5dba7SAnatoly Burakov 
620c7f5dba7SAnatoly Burakov 	mbuf_mem = n_pages * pgsz;
621c7f5dba7SAnatoly Burakov 
622c7f5dba7SAnatoly Burakov 	total_mem = RTE_ALIGN(hdr_mem + mbuf_mem, pgsz);
623c7f5dba7SAnatoly Burakov 
624c7f5dba7SAnatoly Burakov 	if (total_mem > SIZE_MAX) {
625c7f5dba7SAnatoly Burakov 		TESTPMD_LOG(ERR, "Memory size too big\n");
626c7f5dba7SAnatoly Burakov 		return -1;
627c7f5dba7SAnatoly Burakov 	}
628c7f5dba7SAnatoly Burakov 	*out = (size_t)total_mem;
629c7f5dba7SAnatoly Burakov 
630c7f5dba7SAnatoly Burakov 	return 0;
631c7f5dba7SAnatoly Burakov }
632c7f5dba7SAnatoly Burakov 
633c7f5dba7SAnatoly Burakov static inline uint32_t
634c7f5dba7SAnatoly Burakov bsf64(uint64_t v)
635c7f5dba7SAnatoly Burakov {
636c7f5dba7SAnatoly Burakov 	return (uint32_t)__builtin_ctzll(v);
637c7f5dba7SAnatoly Burakov }
638c7f5dba7SAnatoly Burakov 
639c7f5dba7SAnatoly Burakov static inline uint32_t
640c7f5dba7SAnatoly Burakov log2_u64(uint64_t v)
641c7f5dba7SAnatoly Burakov {
642c7f5dba7SAnatoly Burakov 	if (v == 0)
643c7f5dba7SAnatoly Burakov 		return 0;
644c7f5dba7SAnatoly Burakov 	v = rte_align64pow2(v);
645c7f5dba7SAnatoly Burakov 	return bsf64(v);
646c7f5dba7SAnatoly Burakov }
647c7f5dba7SAnatoly Burakov 
648c7f5dba7SAnatoly Burakov static int
649c7f5dba7SAnatoly Burakov pagesz_flags(uint64_t page_sz)
650c7f5dba7SAnatoly Burakov {
651c7f5dba7SAnatoly Burakov 	/* as per mmap() manpage, all page sizes are log2 of page size
652c7f5dba7SAnatoly Burakov 	 * shifted by MAP_HUGE_SHIFT
653c7f5dba7SAnatoly Burakov 	 */
654c7f5dba7SAnatoly Burakov 	int log2 = log2_u64(page_sz);
655c7f5dba7SAnatoly Burakov 
656c7f5dba7SAnatoly Burakov 	return (log2 << HUGE_SHIFT);
657c7f5dba7SAnatoly Burakov }
658c7f5dba7SAnatoly Burakov 
659c7f5dba7SAnatoly Burakov static void *
660c7f5dba7SAnatoly Burakov alloc_mem(size_t memsz, size_t pgsz, bool huge)
661c7f5dba7SAnatoly Burakov {
662c7f5dba7SAnatoly Burakov 	void *addr;
663c7f5dba7SAnatoly Burakov 	int flags;
664c7f5dba7SAnatoly Burakov 
665c7f5dba7SAnatoly Burakov 	/* allocate anonymous hugepages */
666c7f5dba7SAnatoly Burakov 	flags = MAP_ANONYMOUS | MAP_PRIVATE;
667c7f5dba7SAnatoly Burakov 	if (huge)
668c7f5dba7SAnatoly Burakov 		flags |= HUGE_FLAG | pagesz_flags(pgsz);
669c7f5dba7SAnatoly Burakov 
670c7f5dba7SAnatoly Burakov 	addr = mmap(NULL, memsz, PROT_READ | PROT_WRITE, flags, -1, 0);
671c7f5dba7SAnatoly Burakov 	if (addr == MAP_FAILED)
672c7f5dba7SAnatoly Burakov 		return NULL;
673c7f5dba7SAnatoly Burakov 
674c7f5dba7SAnatoly Burakov 	return addr;
675c7f5dba7SAnatoly Burakov }
676c7f5dba7SAnatoly Burakov 
677c7f5dba7SAnatoly Burakov struct extmem_param {
678c7f5dba7SAnatoly Burakov 	void *addr;
679c7f5dba7SAnatoly Burakov 	size_t len;
680c7f5dba7SAnatoly Burakov 	size_t pgsz;
681c7f5dba7SAnatoly Burakov 	rte_iova_t *iova_table;
682c7f5dba7SAnatoly Burakov 	unsigned int iova_table_len;
683c7f5dba7SAnatoly Burakov };
684c7f5dba7SAnatoly Burakov 
685c7f5dba7SAnatoly Burakov static int
686c7f5dba7SAnatoly Burakov create_extmem(uint32_t nb_mbufs, uint32_t mbuf_sz, struct extmem_param *param,
687c7f5dba7SAnatoly Burakov 		bool huge)
688c7f5dba7SAnatoly Burakov {
689c7f5dba7SAnatoly Burakov 	uint64_t pgsizes[] = {RTE_PGSIZE_2M, RTE_PGSIZE_1G, /* x86_64, ARM */
690c7f5dba7SAnatoly Burakov 			RTE_PGSIZE_16M, RTE_PGSIZE_16G};    /* POWER */
691c7f5dba7SAnatoly Burakov 	unsigned int cur_page, n_pages, pgsz_idx;
692c7f5dba7SAnatoly Burakov 	size_t mem_sz, cur_pgsz;
693c7f5dba7SAnatoly Burakov 	rte_iova_t *iovas = NULL;
694c7f5dba7SAnatoly Burakov 	void *addr;
695c7f5dba7SAnatoly Burakov 	int ret;
696c7f5dba7SAnatoly Burakov 
697c7f5dba7SAnatoly Burakov 	for (pgsz_idx = 0; pgsz_idx < RTE_DIM(pgsizes); pgsz_idx++) {
698c7f5dba7SAnatoly Burakov 		/* skip anything that is too big */
699c7f5dba7SAnatoly Burakov 		if (pgsizes[pgsz_idx] > SIZE_MAX)
700c7f5dba7SAnatoly Burakov 			continue;
701c7f5dba7SAnatoly Burakov 
702c7f5dba7SAnatoly Burakov 		cur_pgsz = pgsizes[pgsz_idx];
703c7f5dba7SAnatoly Burakov 
704c7f5dba7SAnatoly Burakov 		/* if we were told not to allocate hugepages, override */
705c7f5dba7SAnatoly Burakov 		if (!huge)
706c7f5dba7SAnatoly Burakov 			cur_pgsz = sysconf(_SC_PAGESIZE);
707c7f5dba7SAnatoly Burakov 
708c7f5dba7SAnatoly Burakov 		ret = calc_mem_size(nb_mbufs, mbuf_sz, cur_pgsz, &mem_sz);
709c7f5dba7SAnatoly Burakov 		if (ret < 0) {
710c7f5dba7SAnatoly Burakov 			TESTPMD_LOG(ERR, "Cannot calculate memory size\n");
711c7f5dba7SAnatoly Burakov 			return -1;
712c7f5dba7SAnatoly Burakov 		}
713c7f5dba7SAnatoly Burakov 
714c7f5dba7SAnatoly Burakov 		/* allocate our memory */
715c7f5dba7SAnatoly Burakov 		addr = alloc_mem(mem_sz, cur_pgsz, huge);
716c7f5dba7SAnatoly Burakov 
717c7f5dba7SAnatoly Burakov 		/* if we couldn't allocate memory with a specified page size,
718c7f5dba7SAnatoly Burakov 		 * that doesn't mean we can't do it with other page sizes, so
719c7f5dba7SAnatoly Burakov 		 * try another one.
720c7f5dba7SAnatoly Burakov 		 */
721c7f5dba7SAnatoly Burakov 		if (addr == NULL)
722c7f5dba7SAnatoly Burakov 			continue;
723c7f5dba7SAnatoly Burakov 
724c7f5dba7SAnatoly Burakov 		/* store IOVA addresses for every page in this memory area */
725c7f5dba7SAnatoly Burakov 		n_pages = mem_sz / cur_pgsz;
726c7f5dba7SAnatoly Burakov 
727c7f5dba7SAnatoly Burakov 		iovas = malloc(sizeof(*iovas) * n_pages);
728c7f5dba7SAnatoly Burakov 
729c7f5dba7SAnatoly Burakov 		if (iovas == NULL) {
730c7f5dba7SAnatoly Burakov 			TESTPMD_LOG(ERR, "Cannot allocate memory for iova addresses\n");
731c7f5dba7SAnatoly Burakov 			goto fail;
732c7f5dba7SAnatoly Burakov 		}
733c7f5dba7SAnatoly Burakov 		/* lock memory if it's not huge pages */
734c7f5dba7SAnatoly Burakov 		if (!huge)
735c7f5dba7SAnatoly Burakov 			mlock(addr, mem_sz);
736c7f5dba7SAnatoly Burakov 
737c7f5dba7SAnatoly Burakov 		/* populate IOVA addresses */
738c7f5dba7SAnatoly Burakov 		for (cur_page = 0; cur_page < n_pages; cur_page++) {
739c7f5dba7SAnatoly Burakov 			rte_iova_t iova;
740c7f5dba7SAnatoly Burakov 			size_t offset;
741c7f5dba7SAnatoly Burakov 			void *cur;
742c7f5dba7SAnatoly Burakov 
743c7f5dba7SAnatoly Burakov 			offset = cur_pgsz * cur_page;
744c7f5dba7SAnatoly Burakov 			cur = RTE_PTR_ADD(addr, offset);
745c7f5dba7SAnatoly Burakov 
746c7f5dba7SAnatoly Burakov 			/* touch the page before getting its IOVA */
747c7f5dba7SAnatoly Burakov 			*(volatile char *)cur = 0;
748c7f5dba7SAnatoly Burakov 
749c7f5dba7SAnatoly Burakov 			iova = rte_mem_virt2iova(cur);
750c7f5dba7SAnatoly Burakov 
751c7f5dba7SAnatoly Burakov 			iovas[cur_page] = iova;
752c7f5dba7SAnatoly Burakov 		}
753c7f5dba7SAnatoly Burakov 
754c7f5dba7SAnatoly Burakov 		break;
755c7f5dba7SAnatoly Burakov 	}
756c7f5dba7SAnatoly Burakov 	/* if we couldn't allocate anything */
757c7f5dba7SAnatoly Burakov 	if (iovas == NULL)
758c7f5dba7SAnatoly Burakov 		return -1;
759c7f5dba7SAnatoly Burakov 
760c7f5dba7SAnatoly Burakov 	param->addr = addr;
761c7f5dba7SAnatoly Burakov 	param->len = mem_sz;
762c7f5dba7SAnatoly Burakov 	param->pgsz = cur_pgsz;
763c7f5dba7SAnatoly Burakov 	param->iova_table = iovas;
764c7f5dba7SAnatoly Burakov 	param->iova_table_len = n_pages;
765c7f5dba7SAnatoly Burakov 
766c7f5dba7SAnatoly Burakov 	return 0;
767c7f5dba7SAnatoly Burakov fail:
768c7f5dba7SAnatoly Burakov 	if (iovas)
769c7f5dba7SAnatoly Burakov 		free(iovas);
770c7f5dba7SAnatoly Burakov 	if (addr)
771c7f5dba7SAnatoly Burakov 		munmap(addr, mem_sz);
772c7f5dba7SAnatoly Burakov 
773c7f5dba7SAnatoly Burakov 	return -1;
774c7f5dba7SAnatoly Burakov }
775c7f5dba7SAnatoly Burakov 
776c7f5dba7SAnatoly Burakov static int
777c7f5dba7SAnatoly Burakov setup_extmem(uint32_t nb_mbufs, uint32_t mbuf_sz, bool huge)
778c7f5dba7SAnatoly Burakov {
779c7f5dba7SAnatoly Burakov 	struct extmem_param param;
780c7f5dba7SAnatoly Burakov 	int socket_id, ret;
781c7f5dba7SAnatoly Burakov 
782c7f5dba7SAnatoly Burakov 	memset(&param, 0, sizeof(param));
783c7f5dba7SAnatoly Burakov 
784c7f5dba7SAnatoly Burakov 	/* check if our heap exists */
785c7f5dba7SAnatoly Burakov 	socket_id = rte_malloc_heap_get_socket(EXTMEM_HEAP_NAME);
786c7f5dba7SAnatoly Burakov 	if (socket_id < 0) {
787c7f5dba7SAnatoly Burakov 		/* create our heap */
788c7f5dba7SAnatoly Burakov 		ret = rte_malloc_heap_create(EXTMEM_HEAP_NAME);
789c7f5dba7SAnatoly Burakov 		if (ret < 0) {
790c7f5dba7SAnatoly Burakov 			TESTPMD_LOG(ERR, "Cannot create heap\n");
791c7f5dba7SAnatoly Burakov 			return -1;
792c7f5dba7SAnatoly Burakov 		}
793c7f5dba7SAnatoly Burakov 	}
794c7f5dba7SAnatoly Burakov 
795c7f5dba7SAnatoly Burakov 	ret = create_extmem(nb_mbufs, mbuf_sz, &param, huge);
796c7f5dba7SAnatoly Burakov 	if (ret < 0) {
797c7f5dba7SAnatoly Burakov 		TESTPMD_LOG(ERR, "Cannot create memory area\n");
798c7f5dba7SAnatoly Burakov 		return -1;
799c7f5dba7SAnatoly Burakov 	}
800c7f5dba7SAnatoly Burakov 
801c7f5dba7SAnatoly Burakov 	/* we now have a valid memory area, so add it to heap */
802c7f5dba7SAnatoly Burakov 	ret = rte_malloc_heap_memory_add(EXTMEM_HEAP_NAME,
803c7f5dba7SAnatoly Burakov 			param.addr, param.len, param.iova_table,
804c7f5dba7SAnatoly Burakov 			param.iova_table_len, param.pgsz);
805c7f5dba7SAnatoly Burakov 
806c7f5dba7SAnatoly Burakov 	/* when using VFIO, memory is automatically mapped for DMA by EAL */
807c7f5dba7SAnatoly Burakov 
808c7f5dba7SAnatoly Burakov 	/* not needed any more */
809c7f5dba7SAnatoly Burakov 	free(param.iova_table);
810c7f5dba7SAnatoly Burakov 
811c7f5dba7SAnatoly Burakov 	if (ret < 0) {
812c7f5dba7SAnatoly Burakov 		TESTPMD_LOG(ERR, "Cannot add memory to heap\n");
813c7f5dba7SAnatoly Burakov 		munmap(param.addr, param.len);
814c7f5dba7SAnatoly Burakov 		return -1;
815c7f5dba7SAnatoly Burakov 	}
816c7f5dba7SAnatoly Burakov 
817c7f5dba7SAnatoly Burakov 	/* success */
818c7f5dba7SAnatoly Burakov 
819c7f5dba7SAnatoly Burakov 	TESTPMD_LOG(DEBUG, "Allocated %zuMB of external memory\n",
820c7f5dba7SAnatoly Burakov 			param.len >> 20);
821c7f5dba7SAnatoly Burakov 
822c7f5dba7SAnatoly Burakov 	return 0;
823c7f5dba7SAnatoly Burakov }
824c7f5dba7SAnatoly Burakov 
825af75078fSIntel /*
826af75078fSIntel  * Configuration initialisation done once at init time.
827af75078fSIntel  */
828af75078fSIntel static void
829af75078fSIntel mbuf_pool_create(uint16_t mbuf_seg_size, unsigned nb_mbuf,
830af75078fSIntel 		 unsigned int socket_id)
831af75078fSIntel {
832af75078fSIntel 	char pool_name[RTE_MEMPOOL_NAMESIZE];
833bece7b6cSChristian Ehrhardt 	struct rte_mempool *rte_mp = NULL;
834af75078fSIntel 	uint32_t mb_size;
835af75078fSIntel 
836dfb03bbeSOlivier Matz 	mb_size = sizeof(struct rte_mbuf) + mbuf_seg_size;
837af75078fSIntel 	mbuf_poolname_build(socket_id, pool_name, sizeof(pool_name));
838148f963fSBruce Richardson 
839285fd101SOlivier Matz 	TESTPMD_LOG(INFO,
840d1eb542eSOlivier Matz 		"create a new mbuf pool <%s>: n=%u, size=%u, socket=%u\n",
841d1eb542eSOlivier Matz 		pool_name, nb_mbuf, mbuf_seg_size, socket_id);
842d1eb542eSOlivier Matz 
843c7f5dba7SAnatoly Burakov 	switch (mp_alloc_type) {
844c7f5dba7SAnatoly Burakov 	case MP_ALLOC_NATIVE:
845c7f5dba7SAnatoly Burakov 		{
846c7f5dba7SAnatoly Burakov 			/* wrapper to rte_mempool_create() */
847c7f5dba7SAnatoly Burakov 			TESTPMD_LOG(INFO, "preferred mempool ops selected: %s\n",
848c7f5dba7SAnatoly Burakov 					rte_mbuf_best_mempool_ops());
849c7f5dba7SAnatoly Burakov 			rte_mp = rte_pktmbuf_pool_create(pool_name, nb_mbuf,
850c7f5dba7SAnatoly Burakov 				mb_mempool_cache, 0, mbuf_seg_size, socket_id);
851c7f5dba7SAnatoly Burakov 			break;
852c7f5dba7SAnatoly Burakov 		}
853c7f5dba7SAnatoly Burakov 	case MP_ALLOC_ANON:
854c7f5dba7SAnatoly Burakov 		{
855b19a0c75SOlivier Matz 			rte_mp = rte_mempool_create_empty(pool_name, nb_mbuf,
856c7f5dba7SAnatoly Burakov 				mb_size, (unsigned int) mb_mempool_cache,
857148f963fSBruce Richardson 				sizeof(struct rte_pktmbuf_pool_private),
858148f963fSBruce Richardson 				socket_id, 0);
85924427bb9SOlivier Matz 			if (rte_mp == NULL)
86024427bb9SOlivier Matz 				goto err;
861b19a0c75SOlivier Matz 
862b19a0c75SOlivier Matz 			if (rte_mempool_populate_anon(rte_mp) == 0) {
863b19a0c75SOlivier Matz 				rte_mempool_free(rte_mp);
864b19a0c75SOlivier Matz 				rte_mp = NULL;
86524427bb9SOlivier Matz 				goto err;
866b19a0c75SOlivier Matz 			}
867b19a0c75SOlivier Matz 			rte_pktmbuf_pool_init(rte_mp, NULL);
868b19a0c75SOlivier Matz 			rte_mempool_obj_iter(rte_mp, rte_pktmbuf_init, NULL);
869c7f5dba7SAnatoly Burakov 			break;
870c7f5dba7SAnatoly Burakov 		}
871c7f5dba7SAnatoly Burakov 	case MP_ALLOC_XMEM:
872c7f5dba7SAnatoly Burakov 	case MP_ALLOC_XMEM_HUGE:
873c7f5dba7SAnatoly Burakov 		{
874c7f5dba7SAnatoly Burakov 			int heap_socket;
875c7f5dba7SAnatoly Burakov 			bool huge = mp_alloc_type == MP_ALLOC_XMEM_HUGE;
876c7f5dba7SAnatoly Burakov 
877c7f5dba7SAnatoly Burakov 			if (setup_extmem(nb_mbuf, mbuf_seg_size, huge) < 0)
878c7f5dba7SAnatoly Burakov 				rte_exit(EXIT_FAILURE, "Could not create external memory\n");
879c7f5dba7SAnatoly Burakov 
880c7f5dba7SAnatoly Burakov 			heap_socket =
881c7f5dba7SAnatoly Burakov 				rte_malloc_heap_get_socket(EXTMEM_HEAP_NAME);
882c7f5dba7SAnatoly Burakov 			if (heap_socket < 0)
883c7f5dba7SAnatoly Burakov 				rte_exit(EXIT_FAILURE, "Could not get external memory socket ID\n");
884c7f5dba7SAnatoly Burakov 
8850e798567SPavan Nikhilesh 			TESTPMD_LOG(INFO, "preferred mempool ops selected: %s\n",
8860e798567SPavan Nikhilesh 					rte_mbuf_best_mempool_ops());
887ea0c20eaSOlivier Matz 			rte_mp = rte_pktmbuf_pool_create(pool_name, nb_mbuf,
888c7f5dba7SAnatoly Burakov 					mb_mempool_cache, 0, mbuf_seg_size,
889c7f5dba7SAnatoly Burakov 					heap_socket);
890c7f5dba7SAnatoly Burakov 			break;
891c7f5dba7SAnatoly Burakov 		}
892c7f5dba7SAnatoly Burakov 	default:
893c7f5dba7SAnatoly Burakov 		{
894c7f5dba7SAnatoly Burakov 			rte_exit(EXIT_FAILURE, "Invalid mempool creation mode\n");
895c7f5dba7SAnatoly Burakov 		}
896bece7b6cSChristian Ehrhardt 	}
897148f963fSBruce Richardson 
89824427bb9SOlivier Matz err:
899af75078fSIntel 	if (rte_mp == NULL) {
900d1eb542eSOlivier Matz 		rte_exit(EXIT_FAILURE,
901d1eb542eSOlivier Matz 			"Creation of mbuf pool for socket %u failed: %s\n",
902d1eb542eSOlivier Matz 			socket_id, rte_strerror(rte_errno));
903148f963fSBruce Richardson 	} else if (verbose_level > 0) {
904591a9d79SStephen Hemminger 		rte_mempool_dump(stdout, rte_mp);
905af75078fSIntel 	}
906af75078fSIntel }
907af75078fSIntel 
90820a0286fSLiu Xiaofeng /*
90920a0286fSLiu Xiaofeng  * Check given socket id is valid or not with NUMA mode,
91020a0286fSLiu Xiaofeng  * if valid, return 0, else return -1
91120a0286fSLiu Xiaofeng  */
91220a0286fSLiu Xiaofeng static int
91320a0286fSLiu Xiaofeng check_socket_id(const unsigned int socket_id)
91420a0286fSLiu Xiaofeng {
91520a0286fSLiu Xiaofeng 	static int warning_once = 0;
91620a0286fSLiu Xiaofeng 
917c9cafcc8SShahaf Shuler 	if (new_socket_id(socket_id)) {
91820a0286fSLiu Xiaofeng 		if (!warning_once && numa_support)
91920a0286fSLiu Xiaofeng 			printf("Warning: NUMA should be configured manually by"
92020a0286fSLiu Xiaofeng 			       " using --port-numa-config and"
92120a0286fSLiu Xiaofeng 			       " --ring-numa-config parameters along with"
92220a0286fSLiu Xiaofeng 			       " --numa.\n");
92320a0286fSLiu Xiaofeng 		warning_once = 1;
92420a0286fSLiu Xiaofeng 		return -1;
92520a0286fSLiu Xiaofeng 	}
92620a0286fSLiu Xiaofeng 	return 0;
92720a0286fSLiu Xiaofeng }
92820a0286fSLiu Xiaofeng 
9293f7311baSWei Dai /*
9303f7311baSWei Dai  * Get the allowed maximum number of RX queues.
9313f7311baSWei Dai  * *pid return the port id which has minimal value of
9323f7311baSWei Dai  * max_rx_queues in all ports.
9333f7311baSWei Dai  */
9343f7311baSWei Dai queueid_t
9353f7311baSWei Dai get_allowed_max_nb_rxq(portid_t *pid)
9363f7311baSWei Dai {
9373f7311baSWei Dai 	queueid_t allowed_max_rxq = MAX_QUEUE_ID;
9383f7311baSWei Dai 	portid_t pi;
9393f7311baSWei Dai 	struct rte_eth_dev_info dev_info;
9403f7311baSWei Dai 
9413f7311baSWei Dai 	RTE_ETH_FOREACH_DEV(pi) {
9423f7311baSWei Dai 		rte_eth_dev_info_get(pi, &dev_info);
9433f7311baSWei Dai 		if (dev_info.max_rx_queues < allowed_max_rxq) {
9443f7311baSWei Dai 			allowed_max_rxq = dev_info.max_rx_queues;
9453f7311baSWei Dai 			*pid = pi;
9463f7311baSWei Dai 		}
9473f7311baSWei Dai 	}
9483f7311baSWei Dai 	return allowed_max_rxq;
9493f7311baSWei Dai }
9503f7311baSWei Dai 
9513f7311baSWei Dai /*
9523f7311baSWei Dai  * Check input rxq is valid or not.
9533f7311baSWei Dai  * If input rxq is not greater than any of maximum number
9543f7311baSWei Dai  * of RX queues of all ports, it is valid.
9553f7311baSWei Dai  * if valid, return 0, else return -1
9563f7311baSWei Dai  */
9573f7311baSWei Dai int
9583f7311baSWei Dai check_nb_rxq(queueid_t rxq)
9593f7311baSWei Dai {
9603f7311baSWei Dai 	queueid_t allowed_max_rxq;
9613f7311baSWei Dai 	portid_t pid = 0;
9623f7311baSWei Dai 
9633f7311baSWei Dai 	allowed_max_rxq = get_allowed_max_nb_rxq(&pid);
9643f7311baSWei Dai 	if (rxq > allowed_max_rxq) {
9653f7311baSWei Dai 		printf("Fail: input rxq (%u) can't be greater "
9663f7311baSWei Dai 		       "than max_rx_queues (%u) of port %u\n",
9673f7311baSWei Dai 		       rxq,
9683f7311baSWei Dai 		       allowed_max_rxq,
9693f7311baSWei Dai 		       pid);
9703f7311baSWei Dai 		return -1;
9713f7311baSWei Dai 	}
9723f7311baSWei Dai 	return 0;
9733f7311baSWei Dai }
9743f7311baSWei Dai 
97536db4f6cSWei Dai /*
97636db4f6cSWei Dai  * Get the allowed maximum number of TX queues.
97736db4f6cSWei Dai  * *pid return the port id which has minimal value of
97836db4f6cSWei Dai  * max_tx_queues in all ports.
97936db4f6cSWei Dai  */
98036db4f6cSWei Dai queueid_t
98136db4f6cSWei Dai get_allowed_max_nb_txq(portid_t *pid)
98236db4f6cSWei Dai {
98336db4f6cSWei Dai 	queueid_t allowed_max_txq = MAX_QUEUE_ID;
98436db4f6cSWei Dai 	portid_t pi;
98536db4f6cSWei Dai 	struct rte_eth_dev_info dev_info;
98636db4f6cSWei Dai 
98736db4f6cSWei Dai 	RTE_ETH_FOREACH_DEV(pi) {
98836db4f6cSWei Dai 		rte_eth_dev_info_get(pi, &dev_info);
98936db4f6cSWei Dai 		if (dev_info.max_tx_queues < allowed_max_txq) {
99036db4f6cSWei Dai 			allowed_max_txq = dev_info.max_tx_queues;
99136db4f6cSWei Dai 			*pid = pi;
99236db4f6cSWei Dai 		}
99336db4f6cSWei Dai 	}
99436db4f6cSWei Dai 	return allowed_max_txq;
99536db4f6cSWei Dai }
99636db4f6cSWei Dai 
99736db4f6cSWei Dai /*
99836db4f6cSWei Dai  * Check input txq is valid or not.
99936db4f6cSWei Dai  * If input txq is not greater than any of maximum number
100036db4f6cSWei Dai  * of TX queues of all ports, it is valid.
100136db4f6cSWei Dai  * if valid, return 0, else return -1
100236db4f6cSWei Dai  */
100336db4f6cSWei Dai int
100436db4f6cSWei Dai check_nb_txq(queueid_t txq)
100536db4f6cSWei Dai {
100636db4f6cSWei Dai 	queueid_t allowed_max_txq;
100736db4f6cSWei Dai 	portid_t pid = 0;
100836db4f6cSWei Dai 
100936db4f6cSWei Dai 	allowed_max_txq = get_allowed_max_nb_txq(&pid);
101036db4f6cSWei Dai 	if (txq > allowed_max_txq) {
101136db4f6cSWei Dai 		printf("Fail: input txq (%u) can't be greater "
101236db4f6cSWei Dai 		       "than max_tx_queues (%u) of port %u\n",
101336db4f6cSWei Dai 		       txq,
101436db4f6cSWei Dai 		       allowed_max_txq,
101536db4f6cSWei Dai 		       pid);
101636db4f6cSWei Dai 		return -1;
101736db4f6cSWei Dai 	}
101836db4f6cSWei Dai 	return 0;
101936db4f6cSWei Dai }
102036db4f6cSWei Dai 
1021af75078fSIntel static void
1022af75078fSIntel init_config(void)
1023af75078fSIntel {
1024ce8d5614SIntel 	portid_t pid;
1025af75078fSIntel 	struct rte_port *port;
1026af75078fSIntel 	struct rte_mempool *mbp;
1027af75078fSIntel 	unsigned int nb_mbuf_per_pool;
1028af75078fSIntel 	lcoreid_t  lc_id;
10297acf894dSStephen Hurd 	uint8_t port_per_socket[RTE_MAX_NUMA_NODES];
1030b7091f1dSJiayu Hu 	struct rte_gro_param gro_param;
103152f38a20SJiayu Hu 	uint32_t gso_types;
1032c73a9071SWei Dai 	int k;
1033af75078fSIntel 
10347acf894dSStephen Hurd 	memset(port_per_socket,0,RTE_MAX_NUMA_NODES);
1035487f9a59SYulong Pei 
1036af75078fSIntel 	/* Configuration of logical cores. */
1037af75078fSIntel 	fwd_lcores = rte_zmalloc("testpmd: fwd_lcores",
1038af75078fSIntel 				sizeof(struct fwd_lcore *) * nb_lcores,
1039fdf20fa7SSergio Gonzalez Monroy 				RTE_CACHE_LINE_SIZE);
1040af75078fSIntel 	if (fwd_lcores == NULL) {
1041ce8d5614SIntel 		rte_exit(EXIT_FAILURE, "rte_zmalloc(%d (struct fwd_lcore *)) "
1042ce8d5614SIntel 							"failed\n", nb_lcores);
1043af75078fSIntel 	}
1044af75078fSIntel 	for (lc_id = 0; lc_id < nb_lcores; lc_id++) {
1045af75078fSIntel 		fwd_lcores[lc_id] = rte_zmalloc("testpmd: struct fwd_lcore",
1046af75078fSIntel 					       sizeof(struct fwd_lcore),
1047fdf20fa7SSergio Gonzalez Monroy 					       RTE_CACHE_LINE_SIZE);
1048af75078fSIntel 		if (fwd_lcores[lc_id] == NULL) {
1049ce8d5614SIntel 			rte_exit(EXIT_FAILURE, "rte_zmalloc(struct fwd_lcore) "
1050ce8d5614SIntel 								"failed\n");
1051af75078fSIntel 		}
1052af75078fSIntel 		fwd_lcores[lc_id]->cpuid_idx = lc_id;
1053af75078fSIntel 	}
1054af75078fSIntel 
10557d89b261SGaetan Rivet 	RTE_ETH_FOREACH_DEV(pid) {
1056ce8d5614SIntel 		port = &ports[pid];
10578b9bd0efSMoti Haimovsky 		/* Apply default TxRx configuration for all ports */
1058fd8c20aaSShahaf Shuler 		port->dev_conf.txmode = tx_mode;
1059384161e0SShahaf Shuler 		port->dev_conf.rxmode = rx_mode;
1060ce8d5614SIntel 		rte_eth_dev_info_get(pid, &port->dev_info);
10617c45f6c0SFerruh Yigit 
106207e5f7bdSShahaf Shuler 		if (!(port->dev_info.tx_offload_capa &
106307e5f7bdSShahaf Shuler 		      DEV_TX_OFFLOAD_MBUF_FAST_FREE))
106407e5f7bdSShahaf Shuler 			port->dev_conf.txmode.offloads &=
106507e5f7bdSShahaf Shuler 				~DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1066b6ea6408SIntel 		if (numa_support) {
1067b6ea6408SIntel 			if (port_numa[pid] != NUMA_NO_CONFIG)
1068b6ea6408SIntel 				port_per_socket[port_numa[pid]]++;
1069b6ea6408SIntel 			else {
1070b6ea6408SIntel 				uint32_t socket_id = rte_eth_dev_socket_id(pid);
107120a0286fSLiu Xiaofeng 
107229841336SPhil Yang 				/*
107329841336SPhil Yang 				 * if socket_id is invalid,
107429841336SPhil Yang 				 * set to the first available socket.
107529841336SPhil Yang 				 */
107620a0286fSLiu Xiaofeng 				if (check_socket_id(socket_id) < 0)
107729841336SPhil Yang 					socket_id = socket_ids[0];
1078b6ea6408SIntel 				port_per_socket[socket_id]++;
1079b6ea6408SIntel 			}
1080b6ea6408SIntel 		}
1081b6ea6408SIntel 
1082c73a9071SWei Dai 		/* Apply Rx offloads configuration */
1083c73a9071SWei Dai 		for (k = 0; k < port->dev_info.max_rx_queues; k++)
1084c73a9071SWei Dai 			port->rx_conf[k].offloads =
1085c73a9071SWei Dai 				port->dev_conf.rxmode.offloads;
1086c73a9071SWei Dai 		/* Apply Tx offloads configuration */
1087c73a9071SWei Dai 		for (k = 0; k < port->dev_info.max_tx_queues; k++)
1088c73a9071SWei Dai 			port->tx_conf[k].offloads =
1089c73a9071SWei Dai 				port->dev_conf.txmode.offloads;
1090c73a9071SWei Dai 
1091ce8d5614SIntel 		/* set flag to initialize port/queue */
1092ce8d5614SIntel 		port->need_reconfig = 1;
1093ce8d5614SIntel 		port->need_reconfig_queues = 1;
1094ce8d5614SIntel 	}
1095ce8d5614SIntel 
10963ab64341SOlivier Matz 	/*
10973ab64341SOlivier Matz 	 * Create pools of mbuf.
10983ab64341SOlivier Matz 	 * If NUMA support is disabled, create a single pool of mbuf in
10993ab64341SOlivier Matz 	 * socket 0 memory by default.
11003ab64341SOlivier Matz 	 * Otherwise, create a pool of mbuf in the memory of sockets 0 and 1.
11013ab64341SOlivier Matz 	 *
11023ab64341SOlivier Matz 	 * Use the maximum value of nb_rxd and nb_txd here, then nb_rxd and
11033ab64341SOlivier Matz 	 * nb_txd can be configured at run time.
11043ab64341SOlivier Matz 	 */
11053ab64341SOlivier Matz 	if (param_total_num_mbufs)
11063ab64341SOlivier Matz 		nb_mbuf_per_pool = param_total_num_mbufs;
11073ab64341SOlivier Matz 	else {
11083ab64341SOlivier Matz 		nb_mbuf_per_pool = RTE_TEST_RX_DESC_MAX +
11093ab64341SOlivier Matz 			(nb_lcores * mb_mempool_cache) +
11103ab64341SOlivier Matz 			RTE_TEST_TX_DESC_MAX + MAX_PKT_BURST;
11113ab64341SOlivier Matz 		nb_mbuf_per_pool *= RTE_MAX_ETHPORTS;
11123ab64341SOlivier Matz 	}
11133ab64341SOlivier Matz 
1114b6ea6408SIntel 	if (numa_support) {
1115b6ea6408SIntel 		uint8_t i;
1116ce8d5614SIntel 
1117c9cafcc8SShahaf Shuler 		for (i = 0; i < num_sockets; i++)
1118c9cafcc8SShahaf Shuler 			mbuf_pool_create(mbuf_data_size, nb_mbuf_per_pool,
1119c9cafcc8SShahaf Shuler 					 socket_ids[i]);
11203ab64341SOlivier Matz 	} else {
11213ab64341SOlivier Matz 		if (socket_num == UMA_NO_CONFIG)
11223ab64341SOlivier Matz 			mbuf_pool_create(mbuf_data_size, nb_mbuf_per_pool, 0);
11233ab64341SOlivier Matz 		else
11243ab64341SOlivier Matz 			mbuf_pool_create(mbuf_data_size, nb_mbuf_per_pool,
11253ab64341SOlivier Matz 						 socket_num);
11263ab64341SOlivier Matz 	}
1127b6ea6408SIntel 
1128b6ea6408SIntel 	init_port_config();
11295886ae07SAdrien Mazarguil 
113052f38a20SJiayu Hu 	gso_types = DEV_TX_OFFLOAD_TCP_TSO | DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1131aaacd052SJiayu Hu 		DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_UDP_TSO;
11325886ae07SAdrien Mazarguil 	/*
11335886ae07SAdrien Mazarguil 	 * Records which Mbuf pool to use by each logical core, if needed.
11345886ae07SAdrien Mazarguil 	 */
11355886ae07SAdrien Mazarguil 	for (lc_id = 0; lc_id < nb_lcores; lc_id++) {
11368fd8bebcSAdrien Mazarguil 		mbp = mbuf_pool_find(
11378fd8bebcSAdrien Mazarguil 			rte_lcore_to_socket_id(fwd_lcores_cpuids[lc_id]));
11388fd8bebcSAdrien Mazarguil 
11395886ae07SAdrien Mazarguil 		if (mbp == NULL)
11405886ae07SAdrien Mazarguil 			mbp = mbuf_pool_find(0);
11415886ae07SAdrien Mazarguil 		fwd_lcores[lc_id]->mbp = mbp;
114252f38a20SJiayu Hu 		/* initialize GSO context */
114352f38a20SJiayu Hu 		fwd_lcores[lc_id]->gso_ctx.direct_pool = mbp;
114452f38a20SJiayu Hu 		fwd_lcores[lc_id]->gso_ctx.indirect_pool = mbp;
114552f38a20SJiayu Hu 		fwd_lcores[lc_id]->gso_ctx.gso_types = gso_types;
114652f38a20SJiayu Hu 		fwd_lcores[lc_id]->gso_ctx.gso_size = ETHER_MAX_LEN -
114752f38a20SJiayu Hu 			ETHER_CRC_LEN;
114852f38a20SJiayu Hu 		fwd_lcores[lc_id]->gso_ctx.flag = 0;
11495886ae07SAdrien Mazarguil 	}
11505886ae07SAdrien Mazarguil 
1151ce8d5614SIntel 	/* Configuration of packet forwarding streams. */
1152ce8d5614SIntel 	if (init_fwd_streams() < 0)
1153ce8d5614SIntel 		rte_exit(EXIT_FAILURE, "FAIL from init_fwd_streams()\n");
11540c0db76fSBernard Iremonger 
11550c0db76fSBernard Iremonger 	fwd_config_setup();
1156b7091f1dSJiayu Hu 
1157b7091f1dSJiayu Hu 	/* create a gro context for each lcore */
1158b7091f1dSJiayu Hu 	gro_param.gro_types = RTE_GRO_TCP_IPV4;
1159b7091f1dSJiayu Hu 	gro_param.max_flow_num = GRO_MAX_FLUSH_CYCLES;
1160b7091f1dSJiayu Hu 	gro_param.max_item_per_flow = MAX_PKT_BURST;
1161b7091f1dSJiayu Hu 	for (lc_id = 0; lc_id < nb_lcores; lc_id++) {
1162b7091f1dSJiayu Hu 		gro_param.socket_id = rte_lcore_to_socket_id(
1163b7091f1dSJiayu Hu 				fwd_lcores_cpuids[lc_id]);
1164b7091f1dSJiayu Hu 		fwd_lcores[lc_id]->gro_ctx = rte_gro_ctx_create(&gro_param);
1165b7091f1dSJiayu Hu 		if (fwd_lcores[lc_id]->gro_ctx == NULL) {
1166b7091f1dSJiayu Hu 			rte_exit(EXIT_FAILURE,
1167b7091f1dSJiayu Hu 					"rte_gro_ctx_create() failed\n");
1168b7091f1dSJiayu Hu 		}
1169b7091f1dSJiayu Hu 	}
11700ad778b3SJasvinder Singh 
11710ad778b3SJasvinder Singh #if defined RTE_LIBRTE_PMD_SOFTNIC
11720ad778b3SJasvinder Singh 	if (strcmp(cur_fwd_eng->fwd_mode_name, "softnic") == 0) {
11730ad778b3SJasvinder Singh 		RTE_ETH_FOREACH_DEV(pid) {
11740ad778b3SJasvinder Singh 			port = &ports[pid];
11750ad778b3SJasvinder Singh 			const char *driver = port->dev_info.driver_name;
11760ad778b3SJasvinder Singh 
11770ad778b3SJasvinder Singh 			if (strcmp(driver, "net_softnic") == 0)
11780ad778b3SJasvinder Singh 				port->softport.fwd_lcore_arg = fwd_lcores;
11790ad778b3SJasvinder Singh 		}
11800ad778b3SJasvinder Singh 	}
11810ad778b3SJasvinder Singh #endif
11820ad778b3SJasvinder Singh 
1183ce8d5614SIntel }
1184ce8d5614SIntel 
11852950a769SDeclan Doherty 
11862950a769SDeclan Doherty void
1187a21d5a4bSDeclan Doherty reconfig(portid_t new_port_id, unsigned socket_id)
11882950a769SDeclan Doherty {
11892950a769SDeclan Doherty 	struct rte_port *port;
11902950a769SDeclan Doherty 
11912950a769SDeclan Doherty 	/* Reconfiguration of Ethernet ports. */
11922950a769SDeclan Doherty 	port = &ports[new_port_id];
11932950a769SDeclan Doherty 	rte_eth_dev_info_get(new_port_id, &port->dev_info);
11942950a769SDeclan Doherty 
11952950a769SDeclan Doherty 	/* set flag to initialize port/queue */
11962950a769SDeclan Doherty 	port->need_reconfig = 1;
11972950a769SDeclan Doherty 	port->need_reconfig_queues = 1;
1198a21d5a4bSDeclan Doherty 	port->socket_id = socket_id;
11992950a769SDeclan Doherty 
12002950a769SDeclan Doherty 	init_port_config();
12012950a769SDeclan Doherty }
12022950a769SDeclan Doherty 
12032950a769SDeclan Doherty 
1204ce8d5614SIntel int
1205ce8d5614SIntel init_fwd_streams(void)
1206ce8d5614SIntel {
1207ce8d5614SIntel 	portid_t pid;
1208ce8d5614SIntel 	struct rte_port *port;
1209ce8d5614SIntel 	streamid_t sm_id, nb_fwd_streams_new;
12105a8fb55cSReshma Pattan 	queueid_t q;
1211ce8d5614SIntel 
1212ce8d5614SIntel 	/* set socket id according to numa or not */
12137d89b261SGaetan Rivet 	RTE_ETH_FOREACH_DEV(pid) {
1214ce8d5614SIntel 		port = &ports[pid];
1215ce8d5614SIntel 		if (nb_rxq > port->dev_info.max_rx_queues) {
1216ce8d5614SIntel 			printf("Fail: nb_rxq(%d) is greater than "
1217ce8d5614SIntel 				"max_rx_queues(%d)\n", nb_rxq,
1218ce8d5614SIntel 				port->dev_info.max_rx_queues);
1219ce8d5614SIntel 			return -1;
1220ce8d5614SIntel 		}
1221ce8d5614SIntel 		if (nb_txq > port->dev_info.max_tx_queues) {
1222ce8d5614SIntel 			printf("Fail: nb_txq(%d) is greater than "
1223ce8d5614SIntel 				"max_tx_queues(%d)\n", nb_txq,
1224ce8d5614SIntel 				port->dev_info.max_tx_queues);
1225ce8d5614SIntel 			return -1;
1226ce8d5614SIntel 		}
122720a0286fSLiu Xiaofeng 		if (numa_support) {
122820a0286fSLiu Xiaofeng 			if (port_numa[pid] != NUMA_NO_CONFIG)
122920a0286fSLiu Xiaofeng 				port->socket_id = port_numa[pid];
123020a0286fSLiu Xiaofeng 			else {
1231b6ea6408SIntel 				port->socket_id = rte_eth_dev_socket_id(pid);
123220a0286fSLiu Xiaofeng 
123329841336SPhil Yang 				/*
123429841336SPhil Yang 				 * if socket_id is invalid,
123529841336SPhil Yang 				 * set to the first available socket.
123629841336SPhil Yang 				 */
123720a0286fSLiu Xiaofeng 				if (check_socket_id(port->socket_id) < 0)
123829841336SPhil Yang 					port->socket_id = socket_ids[0];
123920a0286fSLiu Xiaofeng 			}
124020a0286fSLiu Xiaofeng 		}
1241b6ea6408SIntel 		else {
1242b6ea6408SIntel 			if (socket_num == UMA_NO_CONFIG)
1243af75078fSIntel 				port->socket_id = 0;
1244b6ea6408SIntel 			else
1245b6ea6408SIntel 				port->socket_id = socket_num;
1246b6ea6408SIntel 		}
1247af75078fSIntel 	}
1248af75078fSIntel 
12495a8fb55cSReshma Pattan 	q = RTE_MAX(nb_rxq, nb_txq);
12505a8fb55cSReshma Pattan 	if (q == 0) {
12515a8fb55cSReshma Pattan 		printf("Fail: Cannot allocate fwd streams as number of queues is 0\n");
12525a8fb55cSReshma Pattan 		return -1;
12535a8fb55cSReshma Pattan 	}
12545a8fb55cSReshma Pattan 	nb_fwd_streams_new = (streamid_t)(nb_ports * q);
1255ce8d5614SIntel 	if (nb_fwd_streams_new == nb_fwd_streams)
1256ce8d5614SIntel 		return 0;
1257ce8d5614SIntel 	/* clear the old */
1258ce8d5614SIntel 	if (fwd_streams != NULL) {
1259ce8d5614SIntel 		for (sm_id = 0; sm_id < nb_fwd_streams; sm_id++) {
1260ce8d5614SIntel 			if (fwd_streams[sm_id] == NULL)
1261ce8d5614SIntel 				continue;
1262ce8d5614SIntel 			rte_free(fwd_streams[sm_id]);
1263ce8d5614SIntel 			fwd_streams[sm_id] = NULL;
1264af75078fSIntel 		}
1265ce8d5614SIntel 		rte_free(fwd_streams);
1266ce8d5614SIntel 		fwd_streams = NULL;
1267ce8d5614SIntel 	}
1268ce8d5614SIntel 
1269ce8d5614SIntel 	/* init new */
1270ce8d5614SIntel 	nb_fwd_streams = nb_fwd_streams_new;
12711f84c469SMatan Azrad 	if (nb_fwd_streams) {
1272ce8d5614SIntel 		fwd_streams = rte_zmalloc("testpmd: fwd_streams",
12731f84c469SMatan Azrad 			sizeof(struct fwd_stream *) * nb_fwd_streams,
12741f84c469SMatan Azrad 			RTE_CACHE_LINE_SIZE);
1275ce8d5614SIntel 		if (fwd_streams == NULL)
12761f84c469SMatan Azrad 			rte_exit(EXIT_FAILURE, "rte_zmalloc(%d"
12771f84c469SMatan Azrad 				 " (struct fwd_stream *)) failed\n",
12781f84c469SMatan Azrad 				 nb_fwd_streams);
1279ce8d5614SIntel 
1280af75078fSIntel 		for (sm_id = 0; sm_id < nb_fwd_streams; sm_id++) {
12811f84c469SMatan Azrad 			fwd_streams[sm_id] = rte_zmalloc("testpmd:"
12821f84c469SMatan Azrad 				" struct fwd_stream", sizeof(struct fwd_stream),
12831f84c469SMatan Azrad 				RTE_CACHE_LINE_SIZE);
1284ce8d5614SIntel 			if (fwd_streams[sm_id] == NULL)
12851f84c469SMatan Azrad 				rte_exit(EXIT_FAILURE, "rte_zmalloc"
12861f84c469SMatan Azrad 					 "(struct fwd_stream) failed\n");
12871f84c469SMatan Azrad 		}
1288af75078fSIntel 	}
1289ce8d5614SIntel 
1290ce8d5614SIntel 	return 0;
1291af75078fSIntel }
1292af75078fSIntel 
1293af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
1294af75078fSIntel static void
1295af75078fSIntel pkt_burst_stats_display(const char *rx_tx, struct pkt_burst_stats *pbs)
1296af75078fSIntel {
1297af75078fSIntel 	unsigned int total_burst;
1298af75078fSIntel 	unsigned int nb_burst;
1299af75078fSIntel 	unsigned int burst_stats[3];
1300af75078fSIntel 	uint16_t pktnb_stats[3];
1301af75078fSIntel 	uint16_t nb_pkt;
1302af75078fSIntel 	int burst_percent[3];
1303af75078fSIntel 
1304af75078fSIntel 	/*
1305af75078fSIntel 	 * First compute the total number of packet bursts and the
1306af75078fSIntel 	 * two highest numbers of bursts of the same number of packets.
1307af75078fSIntel 	 */
1308af75078fSIntel 	total_burst = 0;
1309af75078fSIntel 	burst_stats[0] = burst_stats[1] = burst_stats[2] = 0;
1310af75078fSIntel 	pktnb_stats[0] = pktnb_stats[1] = pktnb_stats[2] = 0;
1311af75078fSIntel 	for (nb_pkt = 0; nb_pkt < MAX_PKT_BURST; nb_pkt++) {
1312af75078fSIntel 		nb_burst = pbs->pkt_burst_spread[nb_pkt];
1313af75078fSIntel 		if (nb_burst == 0)
1314af75078fSIntel 			continue;
1315af75078fSIntel 		total_burst += nb_burst;
1316af75078fSIntel 		if (nb_burst > burst_stats[0]) {
1317af75078fSIntel 			burst_stats[1] = burst_stats[0];
1318af75078fSIntel 			pktnb_stats[1] = pktnb_stats[0];
1319af75078fSIntel 			burst_stats[0] = nb_burst;
1320af75078fSIntel 			pktnb_stats[0] = nb_pkt;
1321fe613657SDaniel Shelepov 		} else if (nb_burst > burst_stats[1]) {
1322fe613657SDaniel Shelepov 			burst_stats[1] = nb_burst;
1323fe613657SDaniel Shelepov 			pktnb_stats[1] = nb_pkt;
1324af75078fSIntel 		}
1325af75078fSIntel 	}
1326af75078fSIntel 	if (total_burst == 0)
1327af75078fSIntel 		return;
1328af75078fSIntel 	burst_percent[0] = (burst_stats[0] * 100) / total_burst;
1329af75078fSIntel 	printf("  %s-bursts : %u [%d%% of %d pkts", rx_tx, total_burst,
1330af75078fSIntel 	       burst_percent[0], (int) pktnb_stats[0]);
1331af75078fSIntel 	if (burst_stats[0] == total_burst) {
1332af75078fSIntel 		printf("]\n");
1333af75078fSIntel 		return;
1334af75078fSIntel 	}
1335af75078fSIntel 	if (burst_stats[0] + burst_stats[1] == total_burst) {
1336af75078fSIntel 		printf(" + %d%% of %d pkts]\n",
1337af75078fSIntel 		       100 - burst_percent[0], pktnb_stats[1]);
1338af75078fSIntel 		return;
1339af75078fSIntel 	}
1340af75078fSIntel 	burst_percent[1] = (burst_stats[1] * 100) / total_burst;
1341af75078fSIntel 	burst_percent[2] = 100 - (burst_percent[0] + burst_percent[1]);
1342af75078fSIntel 	if ((burst_percent[1] == 0) || (burst_percent[2] == 0)) {
1343af75078fSIntel 		printf(" + %d%% of others]\n", 100 - burst_percent[0]);
1344af75078fSIntel 		return;
1345af75078fSIntel 	}
1346af75078fSIntel 	printf(" + %d%% of %d pkts + %d%% of others]\n",
1347af75078fSIntel 	       burst_percent[1], (int) pktnb_stats[1], burst_percent[2]);
1348af75078fSIntel }
1349af75078fSIntel #endif /* RTE_TEST_PMD_RECORD_BURST_STATS */
1350af75078fSIntel 
1351af75078fSIntel static void
1352af75078fSIntel fwd_port_stats_display(portid_t port_id, struct rte_eth_stats *stats)
1353af75078fSIntel {
1354af75078fSIntel 	struct rte_port *port;
1355013af9b6SIntel 	uint8_t i;
1356af75078fSIntel 
1357af75078fSIntel 	static const char *fwd_stats_border = "----------------------";
1358af75078fSIntel 
1359af75078fSIntel 	port = &ports[port_id];
1360af75078fSIntel 	printf("\n  %s Forward statistics for port %-2d %s\n",
1361af75078fSIntel 	       fwd_stats_border, port_id, fwd_stats_border);
1362013af9b6SIntel 
1363013af9b6SIntel 	if ((!port->rx_queue_stats_mapping_enabled) && (!port->tx_queue_stats_mapping_enabled)) {
1364af75078fSIntel 		printf("  RX-packets: %-14"PRIu64" RX-dropped: %-14"PRIu64"RX-total: "
1365af75078fSIntel 		       "%-"PRIu64"\n",
136670bdb186SIvan Boule 		       stats->ipackets, stats->imissed,
136770bdb186SIvan Boule 		       (uint64_t) (stats->ipackets + stats->imissed));
1368af75078fSIntel 
1369af75078fSIntel 		if (cur_fwd_eng == &csum_fwd_engine)
137058d475b7SJerin Jacob 			printf("  Bad-ipcsum: %-14"PRIu64" Bad-l4csum: %-14"PRIu64"Bad-outer-l4csum: %-14"PRIu64"\n",
137158d475b7SJerin Jacob 			       port->rx_bad_ip_csum, port->rx_bad_l4_csum,
137258d475b7SJerin Jacob 			       port->rx_bad_outer_l4_csum);
137386057c99SIgor Ryzhov 		if ((stats->ierrors + stats->rx_nombuf) > 0) {
1374f72a0fa6SStephen Hemminger 			printf("  RX-error: %-"PRIu64"\n",  stats->ierrors);
137570bdb186SIvan Boule 			printf("  RX-nombufs: %-14"PRIu64"\n", stats->rx_nombuf);
137670bdb186SIvan Boule 		}
1377af75078fSIntel 
1378af75078fSIntel 		printf("  TX-packets: %-14"PRIu64" TX-dropped: %-14"PRIu64"TX-total: "
1379af75078fSIntel 		       "%-"PRIu64"\n",
1380af75078fSIntel 		       stats->opackets, port->tx_dropped,
1381af75078fSIntel 		       (uint64_t) (stats->opackets + port->tx_dropped));
1382013af9b6SIntel 	}
1383013af9b6SIntel 	else {
1384013af9b6SIntel 		printf("  RX-packets:             %14"PRIu64"    RX-dropped:%14"PRIu64"    RX-total:"
1385013af9b6SIntel 		       "%14"PRIu64"\n",
138670bdb186SIvan Boule 		       stats->ipackets, stats->imissed,
138770bdb186SIvan Boule 		       (uint64_t) (stats->ipackets + stats->imissed));
1388013af9b6SIntel 
1389013af9b6SIntel 		if (cur_fwd_eng == &csum_fwd_engine)
139058d475b7SJerin Jacob 			printf("  Bad-ipcsum:%14"PRIu64"    Bad-l4csum:%14"PRIu64"    Bad-outer-l4csum: %-14"PRIu64"\n",
139158d475b7SJerin Jacob 			       port->rx_bad_ip_csum, port->rx_bad_l4_csum,
139258d475b7SJerin Jacob 			       port->rx_bad_outer_l4_csum);
139386057c99SIgor Ryzhov 		if ((stats->ierrors + stats->rx_nombuf) > 0) {
1394f72a0fa6SStephen Hemminger 			printf("  RX-error:%"PRIu64"\n", stats->ierrors);
139570bdb186SIvan Boule 			printf("  RX-nombufs:             %14"PRIu64"\n",
139670bdb186SIvan Boule 			       stats->rx_nombuf);
139770bdb186SIvan Boule 		}
1398013af9b6SIntel 
1399013af9b6SIntel 		printf("  TX-packets:             %14"PRIu64"    TX-dropped:%14"PRIu64"    TX-total:"
1400013af9b6SIntel 		       "%14"PRIu64"\n",
1401013af9b6SIntel 		       stats->opackets, port->tx_dropped,
1402013af9b6SIntel 		       (uint64_t) (stats->opackets + port->tx_dropped));
1403013af9b6SIntel 	}
1404e659b6b4SIvan Boule 
1405af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
1406af75078fSIntel 	if (port->rx_stream)
1407013af9b6SIntel 		pkt_burst_stats_display("RX",
1408013af9b6SIntel 			&port->rx_stream->rx_burst_stats);
1409af75078fSIntel 	if (port->tx_stream)
1410013af9b6SIntel 		pkt_burst_stats_display("TX",
1411013af9b6SIntel 			&port->tx_stream->tx_burst_stats);
1412af75078fSIntel #endif
1413af75078fSIntel 
1414013af9b6SIntel 	if (port->rx_queue_stats_mapping_enabled) {
1415013af9b6SIntel 		printf("\n");
1416013af9b6SIntel 		for (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {
1417013af9b6SIntel 			printf("  Stats reg %2d RX-packets:%14"PRIu64
1418013af9b6SIntel 			       "     RX-errors:%14"PRIu64
1419013af9b6SIntel 			       "    RX-bytes:%14"PRIu64"\n",
1420013af9b6SIntel 			       i, stats->q_ipackets[i], stats->q_errors[i], stats->q_ibytes[i]);
1421013af9b6SIntel 		}
1422013af9b6SIntel 		printf("\n");
1423013af9b6SIntel 	}
1424013af9b6SIntel 	if (port->tx_queue_stats_mapping_enabled) {
1425013af9b6SIntel 		for (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {
1426013af9b6SIntel 			printf("  Stats reg %2d TX-packets:%14"PRIu64
1427013af9b6SIntel 			       "                                 TX-bytes:%14"PRIu64"\n",
1428013af9b6SIntel 			       i, stats->q_opackets[i], stats->q_obytes[i]);
1429013af9b6SIntel 		}
1430013af9b6SIntel 	}
1431013af9b6SIntel 
1432af75078fSIntel 	printf("  %s--------------------------------%s\n",
1433af75078fSIntel 	       fwd_stats_border, fwd_stats_border);
1434af75078fSIntel }
1435af75078fSIntel 
1436af75078fSIntel static void
1437af75078fSIntel fwd_stream_stats_display(streamid_t stream_id)
1438af75078fSIntel {
1439af75078fSIntel 	struct fwd_stream *fs;
1440af75078fSIntel 	static const char *fwd_top_stats_border = "-------";
1441af75078fSIntel 
1442af75078fSIntel 	fs = fwd_streams[stream_id];
1443af75078fSIntel 	if ((fs->rx_packets == 0) && (fs->tx_packets == 0) &&
1444af75078fSIntel 	    (fs->fwd_dropped == 0))
1445af75078fSIntel 		return;
1446af75078fSIntel 	printf("\n  %s Forward Stats for RX Port=%2d/Queue=%2d -> "
1447af75078fSIntel 	       "TX Port=%2d/Queue=%2d %s\n",
1448af75078fSIntel 	       fwd_top_stats_border, fs->rx_port, fs->rx_queue,
1449af75078fSIntel 	       fs->tx_port, fs->tx_queue, fwd_top_stats_border);
1450af75078fSIntel 	printf("  RX-packets: %-14u TX-packets: %-14u TX-dropped: %-14u",
1451af75078fSIntel 	       fs->rx_packets, fs->tx_packets, fs->fwd_dropped);
1452af75078fSIntel 
1453af75078fSIntel 	/* if checksum mode */
1454af75078fSIntel 	if (cur_fwd_eng == &csum_fwd_engine) {
1455013af9b6SIntel 	       printf("  RX- bad IP checksum: %-14u  Rx- bad L4 checksum: "
145658d475b7SJerin Jacob 			"%-14u Rx- bad outer L4 checksum: %-14u\n",
145758d475b7SJerin Jacob 			fs->rx_bad_ip_csum, fs->rx_bad_l4_csum,
145858d475b7SJerin Jacob 			fs->rx_bad_outer_l4_csum);
1459af75078fSIntel 	}
1460af75078fSIntel 
1461af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
1462af75078fSIntel 	pkt_burst_stats_display("RX", &fs->rx_burst_stats);
1463af75078fSIntel 	pkt_burst_stats_display("TX", &fs->tx_burst_stats);
1464af75078fSIntel #endif
1465af75078fSIntel }
1466af75078fSIntel 
1467af75078fSIntel static void
14687741e4cfSIntel flush_fwd_rx_queues(void)
1469af75078fSIntel {
1470af75078fSIntel 	struct rte_mbuf *pkts_burst[MAX_PKT_BURST];
1471af75078fSIntel 	portid_t  rxp;
14727741e4cfSIntel 	portid_t port_id;
1473af75078fSIntel 	queueid_t rxq;
1474af75078fSIntel 	uint16_t  nb_rx;
1475af75078fSIntel 	uint16_t  i;
1476af75078fSIntel 	uint8_t   j;
1477f487715fSReshma Pattan 	uint64_t prev_tsc = 0, diff_tsc, cur_tsc, timer_tsc = 0;
1478594302c7SJames Poole 	uint64_t timer_period;
1479f487715fSReshma Pattan 
1480f487715fSReshma Pattan 	/* convert to number of cycles */
1481594302c7SJames Poole 	timer_period = rte_get_timer_hz(); /* 1 second timeout */
1482af75078fSIntel 
1483af75078fSIntel 	for (j = 0; j < 2; j++) {
14847741e4cfSIntel 		for (rxp = 0; rxp < cur_fwd_config.nb_fwd_ports; rxp++) {
1485af75078fSIntel 			for (rxq = 0; rxq < nb_rxq; rxq++) {
14867741e4cfSIntel 				port_id = fwd_ports_ids[rxp];
1487f487715fSReshma Pattan 				/**
1488f487715fSReshma Pattan 				* testpmd can stuck in the below do while loop
1489f487715fSReshma Pattan 				* if rte_eth_rx_burst() always returns nonzero
1490f487715fSReshma Pattan 				* packets. So timer is added to exit this loop
1491f487715fSReshma Pattan 				* after 1sec timer expiry.
1492f487715fSReshma Pattan 				*/
1493f487715fSReshma Pattan 				prev_tsc = rte_rdtsc();
1494af75078fSIntel 				do {
14957741e4cfSIntel 					nb_rx = rte_eth_rx_burst(port_id, rxq,
1496013af9b6SIntel 						pkts_burst, MAX_PKT_BURST);
1497af75078fSIntel 					for (i = 0; i < nb_rx; i++)
1498af75078fSIntel 						rte_pktmbuf_free(pkts_burst[i]);
1499f487715fSReshma Pattan 
1500f487715fSReshma Pattan 					cur_tsc = rte_rdtsc();
1501f487715fSReshma Pattan 					diff_tsc = cur_tsc - prev_tsc;
1502f487715fSReshma Pattan 					timer_tsc += diff_tsc;
1503f487715fSReshma Pattan 				} while ((nb_rx > 0) &&
1504f487715fSReshma Pattan 					(timer_tsc < timer_period));
1505f487715fSReshma Pattan 				timer_tsc = 0;
1506af75078fSIntel 			}
1507af75078fSIntel 		}
1508af75078fSIntel 		rte_delay_ms(10); /* wait 10 milli-seconds before retrying */
1509af75078fSIntel 	}
1510af75078fSIntel }
1511af75078fSIntel 
1512af75078fSIntel static void
1513af75078fSIntel run_pkt_fwd_on_lcore(struct fwd_lcore *fc, packet_fwd_t pkt_fwd)
1514af75078fSIntel {
1515af75078fSIntel 	struct fwd_stream **fsm;
1516af75078fSIntel 	streamid_t nb_fs;
1517af75078fSIntel 	streamid_t sm_id;
15187e4441c8SRemy Horton #ifdef RTE_LIBRTE_BITRATE
15197e4441c8SRemy Horton 	uint64_t tics_per_1sec;
15207e4441c8SRemy Horton 	uint64_t tics_datum;
15217e4441c8SRemy Horton 	uint64_t tics_current;
15224918a357SXiaoyun Li 	uint16_t i, cnt_ports;
1523af75078fSIntel 
15244918a357SXiaoyun Li 	cnt_ports = nb_ports;
15257e4441c8SRemy Horton 	tics_datum = rte_rdtsc();
15267e4441c8SRemy Horton 	tics_per_1sec = rte_get_timer_hz();
15277e4441c8SRemy Horton #endif
1528af75078fSIntel 	fsm = &fwd_streams[fc->stream_idx];
1529af75078fSIntel 	nb_fs = fc->stream_nb;
1530af75078fSIntel 	do {
1531af75078fSIntel 		for (sm_id = 0; sm_id < nb_fs; sm_id++)
1532af75078fSIntel 			(*pkt_fwd)(fsm[sm_id]);
15337e4441c8SRemy Horton #ifdef RTE_LIBRTE_BITRATE
1534e25e6c70SRemy Horton 		if (bitrate_enabled != 0 &&
1535e25e6c70SRemy Horton 				bitrate_lcore_id == rte_lcore_id()) {
15367e4441c8SRemy Horton 			tics_current = rte_rdtsc();
15377e4441c8SRemy Horton 			if (tics_current - tics_datum >= tics_per_1sec) {
15387e4441c8SRemy Horton 				/* Periodic bitrate calculation */
15394918a357SXiaoyun Li 				for (i = 0; i < cnt_ports; i++)
1540e25e6c70SRemy Horton 					rte_stats_bitrate_calc(bitrate_data,
15414918a357SXiaoyun Li 						ports_ids[i]);
15427e4441c8SRemy Horton 				tics_datum = tics_current;
15437e4441c8SRemy Horton 			}
1544e25e6c70SRemy Horton 		}
15457e4441c8SRemy Horton #endif
154662d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS
154765eb1e54SPablo de Lara 		if (latencystats_enabled != 0 &&
154865eb1e54SPablo de Lara 				latencystats_lcore_id == rte_lcore_id())
154962d3216dSReshma Pattan 			rte_latencystats_update();
155062d3216dSReshma Pattan #endif
155162d3216dSReshma Pattan 
1552af75078fSIntel 	} while (! fc->stopped);
1553af75078fSIntel }
1554af75078fSIntel 
1555af75078fSIntel static int
1556af75078fSIntel start_pkt_forward_on_core(void *fwd_arg)
1557af75078fSIntel {
1558af75078fSIntel 	run_pkt_fwd_on_lcore((struct fwd_lcore *) fwd_arg,
1559af75078fSIntel 			     cur_fwd_config.fwd_eng->packet_fwd);
1560af75078fSIntel 	return 0;
1561af75078fSIntel }
1562af75078fSIntel 
1563af75078fSIntel /*
1564af75078fSIntel  * Run the TXONLY packet forwarding engine to send a single burst of packets.
1565af75078fSIntel  * Used to start communication flows in network loopback test configurations.
1566af75078fSIntel  */
1567af75078fSIntel static int
1568af75078fSIntel run_one_txonly_burst_on_core(void *fwd_arg)
1569af75078fSIntel {
1570af75078fSIntel 	struct fwd_lcore *fwd_lc;
1571af75078fSIntel 	struct fwd_lcore tmp_lcore;
1572af75078fSIntel 
1573af75078fSIntel 	fwd_lc = (struct fwd_lcore *) fwd_arg;
1574af75078fSIntel 	tmp_lcore = *fwd_lc;
1575af75078fSIntel 	tmp_lcore.stopped = 1;
1576af75078fSIntel 	run_pkt_fwd_on_lcore(&tmp_lcore, tx_only_engine.packet_fwd);
1577af75078fSIntel 	return 0;
1578af75078fSIntel }
1579af75078fSIntel 
1580af75078fSIntel /*
1581af75078fSIntel  * Launch packet forwarding:
1582af75078fSIntel  *     - Setup per-port forwarding context.
1583af75078fSIntel  *     - launch logical cores with their forwarding configuration.
1584af75078fSIntel  */
1585af75078fSIntel static void
1586af75078fSIntel launch_packet_forwarding(lcore_function_t *pkt_fwd_on_lcore)
1587af75078fSIntel {
1588af75078fSIntel 	port_fwd_begin_t port_fwd_begin;
1589af75078fSIntel 	unsigned int i;
1590af75078fSIntel 	unsigned int lc_id;
1591af75078fSIntel 	int diag;
1592af75078fSIntel 
1593af75078fSIntel 	port_fwd_begin = cur_fwd_config.fwd_eng->port_fwd_begin;
1594af75078fSIntel 	if (port_fwd_begin != NULL) {
1595af75078fSIntel 		for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++)
1596af75078fSIntel 			(*port_fwd_begin)(fwd_ports_ids[i]);
1597af75078fSIntel 	}
1598af75078fSIntel 	for (i = 0; i < cur_fwd_config.nb_fwd_lcores; i++) {
1599af75078fSIntel 		lc_id = fwd_lcores_cpuids[i];
1600af75078fSIntel 		if ((interactive == 0) || (lc_id != rte_lcore_id())) {
1601af75078fSIntel 			fwd_lcores[i]->stopped = 0;
1602af75078fSIntel 			diag = rte_eal_remote_launch(pkt_fwd_on_lcore,
1603af75078fSIntel 						     fwd_lcores[i], lc_id);
1604af75078fSIntel 			if (diag != 0)
1605af75078fSIntel 				printf("launch lcore %u failed - diag=%d\n",
1606af75078fSIntel 				       lc_id, diag);
1607af75078fSIntel 		}
1608af75078fSIntel 	}
1609af75078fSIntel }
1610af75078fSIntel 
1611af75078fSIntel /*
161203ce2c53SMatan Azrad  * Update the forward ports list.
161303ce2c53SMatan Azrad  */
161403ce2c53SMatan Azrad void
161503ce2c53SMatan Azrad update_fwd_ports(portid_t new_pid)
161603ce2c53SMatan Azrad {
161703ce2c53SMatan Azrad 	unsigned int i;
161803ce2c53SMatan Azrad 	unsigned int new_nb_fwd_ports = 0;
161903ce2c53SMatan Azrad 	int move = 0;
162003ce2c53SMatan Azrad 
162103ce2c53SMatan Azrad 	for (i = 0; i < nb_fwd_ports; ++i) {
162203ce2c53SMatan Azrad 		if (port_id_is_invalid(fwd_ports_ids[i], DISABLED_WARN))
162303ce2c53SMatan Azrad 			move = 1;
162403ce2c53SMatan Azrad 		else if (move)
162503ce2c53SMatan Azrad 			fwd_ports_ids[new_nb_fwd_ports++] = fwd_ports_ids[i];
162603ce2c53SMatan Azrad 		else
162703ce2c53SMatan Azrad 			new_nb_fwd_ports++;
162803ce2c53SMatan Azrad 	}
162903ce2c53SMatan Azrad 	if (new_pid < RTE_MAX_ETHPORTS)
163003ce2c53SMatan Azrad 		fwd_ports_ids[new_nb_fwd_ports++] = new_pid;
163103ce2c53SMatan Azrad 
163203ce2c53SMatan Azrad 	nb_fwd_ports = new_nb_fwd_ports;
163303ce2c53SMatan Azrad 	nb_cfg_ports = new_nb_fwd_ports;
163403ce2c53SMatan Azrad }
163503ce2c53SMatan Azrad 
163603ce2c53SMatan Azrad /*
1637af75078fSIntel  * Launch packet forwarding configuration.
1638af75078fSIntel  */
1639af75078fSIntel void
1640af75078fSIntel start_packet_forwarding(int with_tx_first)
1641af75078fSIntel {
1642af75078fSIntel 	port_fwd_begin_t port_fwd_begin;
1643af75078fSIntel 	port_fwd_end_t  port_fwd_end;
1644af75078fSIntel 	struct rte_port *port;
1645af75078fSIntel 	unsigned int i;
1646af75078fSIntel 	portid_t   pt_id;
1647af75078fSIntel 	streamid_t sm_id;
1648af75078fSIntel 
16495a8fb55cSReshma Pattan 	if (strcmp(cur_fwd_eng->fwd_mode_name, "rxonly") == 0 && !nb_rxq)
16505a8fb55cSReshma Pattan 		rte_exit(EXIT_FAILURE, "rxq are 0, cannot use rxonly fwd mode\n");
16515a8fb55cSReshma Pattan 
16525a8fb55cSReshma Pattan 	if (strcmp(cur_fwd_eng->fwd_mode_name, "txonly") == 0 && !nb_txq)
16535a8fb55cSReshma Pattan 		rte_exit(EXIT_FAILURE, "txq are 0, cannot use txonly fwd mode\n");
16545a8fb55cSReshma Pattan 
16555a8fb55cSReshma Pattan 	if ((strcmp(cur_fwd_eng->fwd_mode_name, "rxonly") != 0 &&
16565a8fb55cSReshma Pattan 		strcmp(cur_fwd_eng->fwd_mode_name, "txonly") != 0) &&
16575a8fb55cSReshma Pattan 		(!nb_rxq || !nb_txq))
16585a8fb55cSReshma Pattan 		rte_exit(EXIT_FAILURE,
16595a8fb55cSReshma Pattan 			"Either rxq or txq are 0, cannot use %s fwd mode\n",
16605a8fb55cSReshma Pattan 			cur_fwd_eng->fwd_mode_name);
16615a8fb55cSReshma Pattan 
1662ce8d5614SIntel 	if (all_ports_started() == 0) {
1663ce8d5614SIntel 		printf("Not all ports were started\n");
1664ce8d5614SIntel 		return;
1665ce8d5614SIntel 	}
1666af75078fSIntel 	if (test_done == 0) {
1667af75078fSIntel 		printf("Packet forwarding already started\n");
1668af75078fSIntel 		return;
1669af75078fSIntel 	}
1670edf87b4aSBernard Iremonger 
1671edf87b4aSBernard Iremonger 
16727741e4cfSIntel 	if(dcb_test) {
16737741e4cfSIntel 		for (i = 0; i < nb_fwd_ports; i++) {
16747741e4cfSIntel 			pt_id = fwd_ports_ids[i];
16757741e4cfSIntel 			port = &ports[pt_id];
16767741e4cfSIntel 			if (!port->dcb_flag) {
16777741e4cfSIntel 				printf("In DCB mode, all forwarding ports must "
16787741e4cfSIntel                                        "be configured in this mode.\n");
1679013af9b6SIntel 				return;
1680013af9b6SIntel 			}
16817741e4cfSIntel 		}
16827741e4cfSIntel 		if (nb_fwd_lcores == 1) {
16837741e4cfSIntel 			printf("In DCB mode,the nb forwarding cores "
16847741e4cfSIntel                                "should be larger than 1.\n");
16857741e4cfSIntel 			return;
16867741e4cfSIntel 		}
16877741e4cfSIntel 	}
1688af75078fSIntel 	test_done = 0;
16897741e4cfSIntel 
169047a767b2SMatan Azrad 	fwd_config_setup();
169147a767b2SMatan Azrad 
16927741e4cfSIntel 	if(!no_flush_rx)
16937741e4cfSIntel 		flush_fwd_rx_queues();
16947741e4cfSIntel 
1695933617d8SZhihong Wang 	pkt_fwd_config_display(&cur_fwd_config);
1696af75078fSIntel 	rxtx_config_display();
1697af75078fSIntel 
1698af75078fSIntel 	for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) {
1699af75078fSIntel 		pt_id = fwd_ports_ids[i];
1700af75078fSIntel 		port = &ports[pt_id];
1701af75078fSIntel 		rte_eth_stats_get(pt_id, &port->stats);
1702af75078fSIntel 		port->tx_dropped = 0;
1703013af9b6SIntel 
1704013af9b6SIntel 		map_port_queue_stats_mapping_registers(pt_id, port);
1705af75078fSIntel 	}
1706af75078fSIntel 	for (sm_id = 0; sm_id < cur_fwd_config.nb_fwd_streams; sm_id++) {
1707af75078fSIntel 		fwd_streams[sm_id]->rx_packets = 0;
1708af75078fSIntel 		fwd_streams[sm_id]->tx_packets = 0;
1709af75078fSIntel 		fwd_streams[sm_id]->fwd_dropped = 0;
1710af75078fSIntel 		fwd_streams[sm_id]->rx_bad_ip_csum = 0;
1711af75078fSIntel 		fwd_streams[sm_id]->rx_bad_l4_csum = 0;
171258d475b7SJerin Jacob 		fwd_streams[sm_id]->rx_bad_outer_l4_csum = 0;
1713af75078fSIntel 
1714af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
1715af75078fSIntel 		memset(&fwd_streams[sm_id]->rx_burst_stats, 0,
1716af75078fSIntel 		       sizeof(fwd_streams[sm_id]->rx_burst_stats));
1717af75078fSIntel 		memset(&fwd_streams[sm_id]->tx_burst_stats, 0,
1718af75078fSIntel 		       sizeof(fwd_streams[sm_id]->tx_burst_stats));
1719af75078fSIntel #endif
1720af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
1721af75078fSIntel 		fwd_streams[sm_id]->core_cycles = 0;
1722af75078fSIntel #endif
1723af75078fSIntel 	}
1724af75078fSIntel 	if (with_tx_first) {
1725af75078fSIntel 		port_fwd_begin = tx_only_engine.port_fwd_begin;
1726af75078fSIntel 		if (port_fwd_begin != NULL) {
1727af75078fSIntel 			for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++)
1728af75078fSIntel 				(*port_fwd_begin)(fwd_ports_ids[i]);
1729af75078fSIntel 		}
1730acbf77a6SZhihong Wang 		while (with_tx_first--) {
1731acbf77a6SZhihong Wang 			launch_packet_forwarding(
1732acbf77a6SZhihong Wang 					run_one_txonly_burst_on_core);
1733af75078fSIntel 			rte_eal_mp_wait_lcore();
1734acbf77a6SZhihong Wang 		}
1735af75078fSIntel 		port_fwd_end = tx_only_engine.port_fwd_end;
1736af75078fSIntel 		if (port_fwd_end != NULL) {
1737af75078fSIntel 			for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++)
1738af75078fSIntel 				(*port_fwd_end)(fwd_ports_ids[i]);
1739af75078fSIntel 		}
1740af75078fSIntel 	}
1741af75078fSIntel 	launch_packet_forwarding(start_pkt_forward_on_core);
1742af75078fSIntel }
1743af75078fSIntel 
1744af75078fSIntel void
1745af75078fSIntel stop_packet_forwarding(void)
1746af75078fSIntel {
1747af75078fSIntel 	struct rte_eth_stats stats;
1748af75078fSIntel 	struct rte_port *port;
1749af75078fSIntel 	port_fwd_end_t  port_fwd_end;
1750af75078fSIntel 	int i;
1751af75078fSIntel 	portid_t   pt_id;
1752af75078fSIntel 	streamid_t sm_id;
1753af75078fSIntel 	lcoreid_t  lc_id;
1754af75078fSIntel 	uint64_t total_recv;
1755af75078fSIntel 	uint64_t total_xmit;
1756af75078fSIntel 	uint64_t total_rx_dropped;
1757af75078fSIntel 	uint64_t total_tx_dropped;
1758af75078fSIntel 	uint64_t total_rx_nombuf;
1759af75078fSIntel 	uint64_t tx_dropped;
1760af75078fSIntel 	uint64_t rx_bad_ip_csum;
1761af75078fSIntel 	uint64_t rx_bad_l4_csum;
1762af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
1763af75078fSIntel 	uint64_t fwd_cycles;
1764af75078fSIntel #endif
1765b7091f1dSJiayu Hu 
1766af75078fSIntel 	static const char *acc_stats_border = "+++++++++++++++";
1767af75078fSIntel 
1768af75078fSIntel 	if (test_done) {
1769af75078fSIntel 		printf("Packet forwarding not started\n");
1770af75078fSIntel 		return;
1771af75078fSIntel 	}
1772af75078fSIntel 	printf("Telling cores to stop...");
1773af75078fSIntel 	for (lc_id = 0; lc_id < cur_fwd_config.nb_fwd_lcores; lc_id++)
1774af75078fSIntel 		fwd_lcores[lc_id]->stopped = 1;
1775af75078fSIntel 	printf("\nWaiting for lcores to finish...\n");
1776af75078fSIntel 	rte_eal_mp_wait_lcore();
1777af75078fSIntel 	port_fwd_end = cur_fwd_config.fwd_eng->port_fwd_end;
1778af75078fSIntel 	if (port_fwd_end != NULL) {
1779af75078fSIntel 		for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) {
1780af75078fSIntel 			pt_id = fwd_ports_ids[i];
1781af75078fSIntel 			(*port_fwd_end)(pt_id);
1782af75078fSIntel 		}
1783af75078fSIntel 	}
1784af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
1785af75078fSIntel 	fwd_cycles = 0;
1786af75078fSIntel #endif
1787af75078fSIntel 	for (sm_id = 0; sm_id < cur_fwd_config.nb_fwd_streams; sm_id++) {
1788af75078fSIntel 		if (cur_fwd_config.nb_fwd_streams >
1789af75078fSIntel 		    cur_fwd_config.nb_fwd_ports) {
1790af75078fSIntel 			fwd_stream_stats_display(sm_id);
1791af75078fSIntel 			ports[fwd_streams[sm_id]->tx_port].tx_stream = NULL;
1792af75078fSIntel 			ports[fwd_streams[sm_id]->rx_port].rx_stream = NULL;
1793af75078fSIntel 		} else {
1794af75078fSIntel 			ports[fwd_streams[sm_id]->tx_port].tx_stream =
1795af75078fSIntel 				fwd_streams[sm_id];
1796af75078fSIntel 			ports[fwd_streams[sm_id]->rx_port].rx_stream =
1797af75078fSIntel 				fwd_streams[sm_id];
1798af75078fSIntel 		}
1799af75078fSIntel 		tx_dropped = ports[fwd_streams[sm_id]->tx_port].tx_dropped;
1800af75078fSIntel 		tx_dropped = (uint64_t) (tx_dropped +
1801af75078fSIntel 					 fwd_streams[sm_id]->fwd_dropped);
1802af75078fSIntel 		ports[fwd_streams[sm_id]->tx_port].tx_dropped = tx_dropped;
1803af75078fSIntel 
1804013af9b6SIntel 		rx_bad_ip_csum =
1805013af9b6SIntel 			ports[fwd_streams[sm_id]->rx_port].rx_bad_ip_csum;
1806af75078fSIntel 		rx_bad_ip_csum = (uint64_t) (rx_bad_ip_csum +
1807af75078fSIntel 					 fwd_streams[sm_id]->rx_bad_ip_csum);
1808013af9b6SIntel 		ports[fwd_streams[sm_id]->rx_port].rx_bad_ip_csum =
1809013af9b6SIntel 							rx_bad_ip_csum;
1810af75078fSIntel 
1811013af9b6SIntel 		rx_bad_l4_csum =
1812013af9b6SIntel 			ports[fwd_streams[sm_id]->rx_port].rx_bad_l4_csum;
1813af75078fSIntel 		rx_bad_l4_csum = (uint64_t) (rx_bad_l4_csum +
1814af75078fSIntel 					 fwd_streams[sm_id]->rx_bad_l4_csum);
1815013af9b6SIntel 		ports[fwd_streams[sm_id]->rx_port].rx_bad_l4_csum =
1816013af9b6SIntel 							rx_bad_l4_csum;
1817af75078fSIntel 
181858d475b7SJerin Jacob 		ports[fwd_streams[sm_id]->rx_port].rx_bad_outer_l4_csum +=
181958d475b7SJerin Jacob 				fwd_streams[sm_id]->rx_bad_outer_l4_csum;
182058d475b7SJerin Jacob 
1821af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
1822af75078fSIntel 		fwd_cycles = (uint64_t) (fwd_cycles +
1823af75078fSIntel 					 fwd_streams[sm_id]->core_cycles);
1824af75078fSIntel #endif
1825af75078fSIntel 	}
1826af75078fSIntel 	total_recv = 0;
1827af75078fSIntel 	total_xmit = 0;
1828af75078fSIntel 	total_rx_dropped = 0;
1829af75078fSIntel 	total_tx_dropped = 0;
1830af75078fSIntel 	total_rx_nombuf  = 0;
18317741e4cfSIntel 	for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) {
1832af75078fSIntel 		pt_id = fwd_ports_ids[i];
1833af75078fSIntel 
1834af75078fSIntel 		port = &ports[pt_id];
1835af75078fSIntel 		rte_eth_stats_get(pt_id, &stats);
1836af75078fSIntel 		stats.ipackets -= port->stats.ipackets;
1837af75078fSIntel 		port->stats.ipackets = 0;
1838af75078fSIntel 		stats.opackets -= port->stats.opackets;
1839af75078fSIntel 		port->stats.opackets = 0;
1840af75078fSIntel 		stats.ibytes   -= port->stats.ibytes;
1841af75078fSIntel 		port->stats.ibytes = 0;
1842af75078fSIntel 		stats.obytes   -= port->stats.obytes;
1843af75078fSIntel 		port->stats.obytes = 0;
184470bdb186SIvan Boule 		stats.imissed  -= port->stats.imissed;
184570bdb186SIvan Boule 		port->stats.imissed = 0;
1846af75078fSIntel 		stats.oerrors  -= port->stats.oerrors;
1847af75078fSIntel 		port->stats.oerrors = 0;
1848af75078fSIntel 		stats.rx_nombuf -= port->stats.rx_nombuf;
1849af75078fSIntel 		port->stats.rx_nombuf = 0;
1850af75078fSIntel 
1851af75078fSIntel 		total_recv += stats.ipackets;
1852af75078fSIntel 		total_xmit += stats.opackets;
185370bdb186SIvan Boule 		total_rx_dropped += stats.imissed;
1854af75078fSIntel 		total_tx_dropped += port->tx_dropped;
1855af75078fSIntel 		total_rx_nombuf  += stats.rx_nombuf;
1856af75078fSIntel 
1857af75078fSIntel 		fwd_port_stats_display(pt_id, &stats);
1858af75078fSIntel 	}
1859b7091f1dSJiayu Hu 
1860af75078fSIntel 	printf("\n  %s Accumulated forward statistics for all ports"
1861af75078fSIntel 	       "%s\n",
1862af75078fSIntel 	       acc_stats_border, acc_stats_border);
1863af75078fSIntel 	printf("  RX-packets: %-14"PRIu64" RX-dropped: %-14"PRIu64"RX-total: "
1864af75078fSIntel 	       "%-"PRIu64"\n"
1865af75078fSIntel 	       "  TX-packets: %-14"PRIu64" TX-dropped: %-14"PRIu64"TX-total: "
1866af75078fSIntel 	       "%-"PRIu64"\n",
1867af75078fSIntel 	       total_recv, total_rx_dropped, total_recv + total_rx_dropped,
1868af75078fSIntel 	       total_xmit, total_tx_dropped, total_xmit + total_tx_dropped);
1869af75078fSIntel 	if (total_rx_nombuf > 0)
1870af75078fSIntel 		printf("  RX-nombufs: %-14"PRIu64"\n", total_rx_nombuf);
1871af75078fSIntel 	printf("  %s++++++++++++++++++++++++++++++++++++++++++++++"
1872af75078fSIntel 	       "%s\n",
1873af75078fSIntel 	       acc_stats_border, acc_stats_border);
1874af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
1875af75078fSIntel 	if (total_recv > 0)
1876af75078fSIntel 		printf("\n  CPU cycles/packet=%u (total cycles="
1877af75078fSIntel 		       "%"PRIu64" / total RX packets=%"PRIu64")\n",
1878af75078fSIntel 		       (unsigned int)(fwd_cycles / total_recv),
1879af75078fSIntel 		       fwd_cycles, total_recv);
1880af75078fSIntel #endif
1881af75078fSIntel 	printf("\nDone.\n");
1882af75078fSIntel 	test_done = 1;
1883af75078fSIntel }
1884af75078fSIntel 
1885cfae07fdSOuyang Changchun void
1886cfae07fdSOuyang Changchun dev_set_link_up(portid_t pid)
1887cfae07fdSOuyang Changchun {
1888492ab604SZhiyong Yang 	if (rte_eth_dev_set_link_up(pid) < 0)
1889cfae07fdSOuyang Changchun 		printf("\nSet link up fail.\n");
1890cfae07fdSOuyang Changchun }
1891cfae07fdSOuyang Changchun 
1892cfae07fdSOuyang Changchun void
1893cfae07fdSOuyang Changchun dev_set_link_down(portid_t pid)
1894cfae07fdSOuyang Changchun {
1895492ab604SZhiyong Yang 	if (rte_eth_dev_set_link_down(pid) < 0)
1896cfae07fdSOuyang Changchun 		printf("\nSet link down fail.\n");
1897cfae07fdSOuyang Changchun }
1898cfae07fdSOuyang Changchun 
1899ce8d5614SIntel static int
1900ce8d5614SIntel all_ports_started(void)
1901ce8d5614SIntel {
1902ce8d5614SIntel 	portid_t pi;
1903ce8d5614SIntel 	struct rte_port *port;
1904ce8d5614SIntel 
19057d89b261SGaetan Rivet 	RTE_ETH_FOREACH_DEV(pi) {
1906ce8d5614SIntel 		port = &ports[pi];
1907ce8d5614SIntel 		/* Check if there is a port which is not started */
190841b05095SBernard Iremonger 		if ((port->port_status != RTE_PORT_STARTED) &&
190941b05095SBernard Iremonger 			(port->slave_flag == 0))
1910ce8d5614SIntel 			return 0;
1911ce8d5614SIntel 	}
1912ce8d5614SIntel 
1913ce8d5614SIntel 	/* No port is not started */
1914ce8d5614SIntel 	return 1;
1915ce8d5614SIntel }
1916ce8d5614SIntel 
1917148f963fSBruce Richardson int
19186018eb8cSShahaf Shuler port_is_stopped(portid_t port_id)
19196018eb8cSShahaf Shuler {
19206018eb8cSShahaf Shuler 	struct rte_port *port = &ports[port_id];
19216018eb8cSShahaf Shuler 
19226018eb8cSShahaf Shuler 	if ((port->port_status != RTE_PORT_STOPPED) &&
19236018eb8cSShahaf Shuler 	    (port->slave_flag == 0))
19246018eb8cSShahaf Shuler 		return 0;
19256018eb8cSShahaf Shuler 	return 1;
19266018eb8cSShahaf Shuler }
19276018eb8cSShahaf Shuler 
19286018eb8cSShahaf Shuler int
1929edab33b1STetsuya Mukawa all_ports_stopped(void)
1930edab33b1STetsuya Mukawa {
1931edab33b1STetsuya Mukawa 	portid_t pi;
1932edab33b1STetsuya Mukawa 
19337d89b261SGaetan Rivet 	RTE_ETH_FOREACH_DEV(pi) {
19346018eb8cSShahaf Shuler 		if (!port_is_stopped(pi))
1935edab33b1STetsuya Mukawa 			return 0;
1936edab33b1STetsuya Mukawa 	}
1937edab33b1STetsuya Mukawa 
1938edab33b1STetsuya Mukawa 	return 1;
1939edab33b1STetsuya Mukawa }
1940edab33b1STetsuya Mukawa 
1941edab33b1STetsuya Mukawa int
1942edab33b1STetsuya Mukawa port_is_started(portid_t port_id)
1943edab33b1STetsuya Mukawa {
1944edab33b1STetsuya Mukawa 	if (port_id_is_invalid(port_id, ENABLED_WARN))
1945edab33b1STetsuya Mukawa 		return 0;
1946edab33b1STetsuya Mukawa 
1947edab33b1STetsuya Mukawa 	if (ports[port_id].port_status != RTE_PORT_STARTED)
1948edab33b1STetsuya Mukawa 		return 0;
1949edab33b1STetsuya Mukawa 
1950edab33b1STetsuya Mukawa 	return 1;
1951edab33b1STetsuya Mukawa }
1952edab33b1STetsuya Mukawa 
1953edab33b1STetsuya Mukawa int
1954ce8d5614SIntel start_port(portid_t pid)
1955ce8d5614SIntel {
195692d2703eSMichael Qiu 	int diag, need_check_link_status = -1;
1957ce8d5614SIntel 	portid_t pi;
1958ce8d5614SIntel 	queueid_t qi;
1959ce8d5614SIntel 	struct rte_port *port;
19602950a769SDeclan Doherty 	struct ether_addr mac_addr;
196176ad4a2dSGaetan Rivet 	enum rte_eth_event_type event_type;
1962ce8d5614SIntel 
19634468635fSMichael Qiu 	if (port_id_is_invalid(pid, ENABLED_WARN))
19644468635fSMichael Qiu 		return 0;
19654468635fSMichael Qiu 
1966ce8d5614SIntel 	if(dcb_config)
1967ce8d5614SIntel 		dcb_test = 1;
19687d89b261SGaetan Rivet 	RTE_ETH_FOREACH_DEV(pi) {
1969edab33b1STetsuya Mukawa 		if (pid != pi && pid != (portid_t)RTE_PORT_ALL)
1970ce8d5614SIntel 			continue;
1971ce8d5614SIntel 
197292d2703eSMichael Qiu 		need_check_link_status = 0;
1973ce8d5614SIntel 		port = &ports[pi];
1974ce8d5614SIntel 		if (rte_atomic16_cmpset(&(port->port_status), RTE_PORT_STOPPED,
1975ce8d5614SIntel 						 RTE_PORT_HANDLING) == 0) {
1976ce8d5614SIntel 			printf("Port %d is now not stopped\n", pi);
1977ce8d5614SIntel 			continue;
1978ce8d5614SIntel 		}
1979ce8d5614SIntel 
1980ce8d5614SIntel 		if (port->need_reconfig > 0) {
1981ce8d5614SIntel 			port->need_reconfig = 0;
1982ce8d5614SIntel 
19837ee3e944SVasily Philipov 			if (flow_isolate_all) {
19847ee3e944SVasily Philipov 				int ret = port_flow_isolate(pi, 1);
19857ee3e944SVasily Philipov 				if (ret) {
19867ee3e944SVasily Philipov 					printf("Failed to apply isolated"
19877ee3e944SVasily Philipov 					       " mode on port %d\n", pi);
19887ee3e944SVasily Philipov 					return -1;
19897ee3e944SVasily Philipov 				}
19907ee3e944SVasily Philipov 			}
1991b5b38ed8SRaslan Darawsheh 			configure_rxtx_dump_callbacks(0);
19925706de65SJulien Cretin 			printf("Configuring Port %d (socket %u)\n", pi,
199320a0286fSLiu Xiaofeng 					port->socket_id);
1994ce8d5614SIntel 			/* configure port */
1995ce8d5614SIntel 			diag = rte_eth_dev_configure(pi, nb_rxq, nb_txq,
1996ce8d5614SIntel 						&(port->dev_conf));
1997ce8d5614SIntel 			if (diag != 0) {
1998ce8d5614SIntel 				if (rte_atomic16_cmpset(&(port->port_status),
1999ce8d5614SIntel 				RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0)
2000ce8d5614SIntel 					printf("Port %d can not be set back "
2001ce8d5614SIntel 							"to stopped\n", pi);
2002ce8d5614SIntel 				printf("Fail to configure port %d\n", pi);
2003ce8d5614SIntel 				/* try to reconfigure port next time */
2004ce8d5614SIntel 				port->need_reconfig = 1;
2005148f963fSBruce Richardson 				return -1;
2006ce8d5614SIntel 			}
2007ce8d5614SIntel 		}
2008ce8d5614SIntel 		if (port->need_reconfig_queues > 0) {
2009ce8d5614SIntel 			port->need_reconfig_queues = 0;
2010ce8d5614SIntel 			/* setup tx queues */
2011ce8d5614SIntel 			for (qi = 0; qi < nb_txq; qi++) {
2012b6ea6408SIntel 				if ((numa_support) &&
2013b6ea6408SIntel 					(txring_numa[pi] != NUMA_NO_CONFIG))
2014b6ea6408SIntel 					diag = rte_eth_tx_queue_setup(pi, qi,
2015d44f8a48SQi Zhang 						port->nb_tx_desc[qi],
2016d44f8a48SQi Zhang 						txring_numa[pi],
2017d44f8a48SQi Zhang 						&(port->tx_conf[qi]));
2018b6ea6408SIntel 				else
2019b6ea6408SIntel 					diag = rte_eth_tx_queue_setup(pi, qi,
2020d44f8a48SQi Zhang 						port->nb_tx_desc[qi],
2021d44f8a48SQi Zhang 						port->socket_id,
2022d44f8a48SQi Zhang 						&(port->tx_conf[qi]));
2023b6ea6408SIntel 
2024ce8d5614SIntel 				if (diag == 0)
2025ce8d5614SIntel 					continue;
2026ce8d5614SIntel 
2027ce8d5614SIntel 				/* Fail to setup tx queue, return */
2028ce8d5614SIntel 				if (rte_atomic16_cmpset(&(port->port_status),
2029ce8d5614SIntel 							RTE_PORT_HANDLING,
2030ce8d5614SIntel 							RTE_PORT_STOPPED) == 0)
2031ce8d5614SIntel 					printf("Port %d can not be set back "
2032ce8d5614SIntel 							"to stopped\n", pi);
2033d44f8a48SQi Zhang 				printf("Fail to configure port %d tx queues\n",
2034d44f8a48SQi Zhang 				       pi);
2035ce8d5614SIntel 				/* try to reconfigure queues next time */
2036ce8d5614SIntel 				port->need_reconfig_queues = 1;
2037148f963fSBruce Richardson 				return -1;
2038ce8d5614SIntel 			}
2039ce8d5614SIntel 			for (qi = 0; qi < nb_rxq; qi++) {
2040d44f8a48SQi Zhang 				/* setup rx queues */
2041b6ea6408SIntel 				if ((numa_support) &&
2042b6ea6408SIntel 					(rxring_numa[pi] != NUMA_NO_CONFIG)) {
2043b6ea6408SIntel 					struct rte_mempool * mp =
2044b6ea6408SIntel 						mbuf_pool_find(rxring_numa[pi]);
2045b6ea6408SIntel 					if (mp == NULL) {
2046b6ea6408SIntel 						printf("Failed to setup RX queue:"
2047b6ea6408SIntel 							"No mempool allocation"
2048b6ea6408SIntel 							" on the socket %d\n",
2049b6ea6408SIntel 							rxring_numa[pi]);
2050148f963fSBruce Richardson 						return -1;
2051b6ea6408SIntel 					}
2052b6ea6408SIntel 
2053b6ea6408SIntel 					diag = rte_eth_rx_queue_setup(pi, qi,
2054d4930794SFerruh Yigit 					     port->nb_rx_desc[qi],
2055d44f8a48SQi Zhang 					     rxring_numa[pi],
2056d44f8a48SQi Zhang 					     &(port->rx_conf[qi]),
2057d44f8a48SQi Zhang 					     mp);
20581e1d6bddSBernard Iremonger 				} else {
20591e1d6bddSBernard Iremonger 					struct rte_mempool *mp =
20601e1d6bddSBernard Iremonger 						mbuf_pool_find(port->socket_id);
20611e1d6bddSBernard Iremonger 					if (mp == NULL) {
20621e1d6bddSBernard Iremonger 						printf("Failed to setup RX queue:"
20631e1d6bddSBernard Iremonger 							"No mempool allocation"
20641e1d6bddSBernard Iremonger 							" on the socket %d\n",
20651e1d6bddSBernard Iremonger 							port->socket_id);
20661e1d6bddSBernard Iremonger 						return -1;
2067b6ea6408SIntel 					}
2068b6ea6408SIntel 					diag = rte_eth_rx_queue_setup(pi, qi,
2069d4930794SFerruh Yigit 					     port->nb_rx_desc[qi],
2070d44f8a48SQi Zhang 					     port->socket_id,
2071d44f8a48SQi Zhang 					     &(port->rx_conf[qi]),
2072d44f8a48SQi Zhang 					     mp);
20731e1d6bddSBernard Iremonger 				}
2074ce8d5614SIntel 				if (diag == 0)
2075ce8d5614SIntel 					continue;
2076ce8d5614SIntel 
2077ce8d5614SIntel 				/* Fail to setup rx queue, return */
2078ce8d5614SIntel 				if (rte_atomic16_cmpset(&(port->port_status),
2079ce8d5614SIntel 							RTE_PORT_HANDLING,
2080ce8d5614SIntel 							RTE_PORT_STOPPED) == 0)
2081ce8d5614SIntel 					printf("Port %d can not be set back "
2082ce8d5614SIntel 							"to stopped\n", pi);
2083d44f8a48SQi Zhang 				printf("Fail to configure port %d rx queues\n",
2084d44f8a48SQi Zhang 				       pi);
2085ce8d5614SIntel 				/* try to reconfigure queues next time */
2086ce8d5614SIntel 				port->need_reconfig_queues = 1;
2087148f963fSBruce Richardson 				return -1;
2088ce8d5614SIntel 			}
2089ce8d5614SIntel 		}
2090b5b38ed8SRaslan Darawsheh 		configure_rxtx_dump_callbacks(verbose_level);
2091ce8d5614SIntel 		/* start port */
2092ce8d5614SIntel 		if (rte_eth_dev_start(pi) < 0) {
2093ce8d5614SIntel 			printf("Fail to start port %d\n", pi);
2094ce8d5614SIntel 
2095ce8d5614SIntel 			/* Fail to setup rx queue, return */
2096ce8d5614SIntel 			if (rte_atomic16_cmpset(&(port->port_status),
2097ce8d5614SIntel 				RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0)
2098ce8d5614SIntel 				printf("Port %d can not be set back to "
2099ce8d5614SIntel 							"stopped\n", pi);
2100ce8d5614SIntel 			continue;
2101ce8d5614SIntel 		}
2102ce8d5614SIntel 
2103ce8d5614SIntel 		if (rte_atomic16_cmpset(&(port->port_status),
2104ce8d5614SIntel 			RTE_PORT_HANDLING, RTE_PORT_STARTED) == 0)
2105ce8d5614SIntel 			printf("Port %d can not be set into started\n", pi);
2106ce8d5614SIntel 
21072950a769SDeclan Doherty 		rte_eth_macaddr_get(pi, &mac_addr);
2108d8c89163SZijie Pan 		printf("Port %d: %02X:%02X:%02X:%02X:%02X:%02X\n", pi,
21092950a769SDeclan Doherty 				mac_addr.addr_bytes[0], mac_addr.addr_bytes[1],
21102950a769SDeclan Doherty 				mac_addr.addr_bytes[2], mac_addr.addr_bytes[3],
21112950a769SDeclan Doherty 				mac_addr.addr_bytes[4], mac_addr.addr_bytes[5]);
2112d8c89163SZijie Pan 
2113ce8d5614SIntel 		/* at least one port started, need checking link status */
2114ce8d5614SIntel 		need_check_link_status = 1;
2115ce8d5614SIntel 	}
2116ce8d5614SIntel 
21174fb82244SMatan Azrad 	for (event_type = RTE_ETH_EVENT_UNKNOWN;
21184fb82244SMatan Azrad 	     event_type < RTE_ETH_EVENT_MAX;
21194fb82244SMatan Azrad 	     event_type++) {
21204fb82244SMatan Azrad 		diag = rte_eth_dev_callback_register(RTE_ETH_ALL,
21214fb82244SMatan Azrad 						event_type,
21224fb82244SMatan Azrad 						eth_event_callback,
21234fb82244SMatan Azrad 						NULL);
21244fb82244SMatan Azrad 		if (diag) {
21254fb82244SMatan Azrad 			printf("Failed to setup even callback for event %d\n",
21264fb82244SMatan Azrad 				event_type);
21274fb82244SMatan Azrad 			return -1;
21284fb82244SMatan Azrad 		}
21294fb82244SMatan Azrad 	}
21304fb82244SMatan Azrad 
213192d2703eSMichael Qiu 	if (need_check_link_status == 1 && !no_link_check)
2132edab33b1STetsuya Mukawa 		check_all_ports_link_status(RTE_PORT_ALL);
213392d2703eSMichael Qiu 	else if (need_check_link_status == 0)
2134ce8d5614SIntel 		printf("Please stop the ports first\n");
2135ce8d5614SIntel 
2136ce8d5614SIntel 	printf("Done\n");
2137148f963fSBruce Richardson 	return 0;
2138ce8d5614SIntel }
2139ce8d5614SIntel 
2140ce8d5614SIntel void
2141ce8d5614SIntel stop_port(portid_t pid)
2142ce8d5614SIntel {
2143ce8d5614SIntel 	portid_t pi;
2144ce8d5614SIntel 	struct rte_port *port;
2145ce8d5614SIntel 	int need_check_link_status = 0;
2146ce8d5614SIntel 
2147ce8d5614SIntel 	if (dcb_test) {
2148ce8d5614SIntel 		dcb_test = 0;
2149ce8d5614SIntel 		dcb_config = 0;
2150ce8d5614SIntel 	}
21514468635fSMichael Qiu 
21524468635fSMichael Qiu 	if (port_id_is_invalid(pid, ENABLED_WARN))
21534468635fSMichael Qiu 		return;
21544468635fSMichael Qiu 
2155ce8d5614SIntel 	printf("Stopping ports...\n");
2156ce8d5614SIntel 
21577d89b261SGaetan Rivet 	RTE_ETH_FOREACH_DEV(pi) {
21584468635fSMichael Qiu 		if (pid != pi && pid != (portid_t)RTE_PORT_ALL)
2159ce8d5614SIntel 			continue;
2160ce8d5614SIntel 
2161a8ef3e3aSBernard Iremonger 		if (port_is_forwarding(pi) != 0 && test_done == 0) {
2162a8ef3e3aSBernard Iremonger 			printf("Please remove port %d from forwarding configuration.\n", pi);
2163a8ef3e3aSBernard Iremonger 			continue;
2164a8ef3e3aSBernard Iremonger 		}
2165a8ef3e3aSBernard Iremonger 
21660e545d30SBernard Iremonger 		if (port_is_bonding_slave(pi)) {
21670e545d30SBernard Iremonger 			printf("Please remove port %d from bonded device.\n", pi);
21680e545d30SBernard Iremonger 			continue;
21690e545d30SBernard Iremonger 		}
21700e545d30SBernard Iremonger 
2171ce8d5614SIntel 		port = &ports[pi];
2172ce8d5614SIntel 		if (rte_atomic16_cmpset(&(port->port_status), RTE_PORT_STARTED,
2173ce8d5614SIntel 						RTE_PORT_HANDLING) == 0)
2174ce8d5614SIntel 			continue;
2175ce8d5614SIntel 
2176ce8d5614SIntel 		rte_eth_dev_stop(pi);
2177ce8d5614SIntel 
2178ce8d5614SIntel 		if (rte_atomic16_cmpset(&(port->port_status),
2179ce8d5614SIntel 			RTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0)
2180ce8d5614SIntel 			printf("Port %d can not be set into stopped\n", pi);
2181ce8d5614SIntel 		need_check_link_status = 1;
2182ce8d5614SIntel 	}
2183bc202406SDavid Marchand 	if (need_check_link_status && !no_link_check)
2184edab33b1STetsuya Mukawa 		check_all_ports_link_status(RTE_PORT_ALL);
2185ce8d5614SIntel 
2186ce8d5614SIntel 	printf("Done\n");
2187ce8d5614SIntel }
2188ce8d5614SIntel 
2189ce6959bfSWisam Jaddo static void
2190ce6959bfSWisam Jaddo remove_unused_fwd_ports(void)
2191ce6959bfSWisam Jaddo {
2192ce6959bfSWisam Jaddo 	int i;
2193ce6959bfSWisam Jaddo 	int last_port_idx = nb_ports - 1;
2194ce6959bfSWisam Jaddo 
2195ce6959bfSWisam Jaddo 	for (i = 0; i <= last_port_idx; i++) { /* iterate in ports_ids */
2196ce6959bfSWisam Jaddo 		if (rte_eth_devices[ports_ids[i]].state != RTE_ETH_DEV_UNUSED)
2197ce6959bfSWisam Jaddo 			continue;
2198ce6959bfSWisam Jaddo 		/* skip unused ports at the end */
2199ce6959bfSWisam Jaddo 		while (i <= last_port_idx &&
2200ce6959bfSWisam Jaddo 				rte_eth_devices[ports_ids[last_port_idx]].state
2201ce6959bfSWisam Jaddo 				== RTE_ETH_DEV_UNUSED)
2202ce6959bfSWisam Jaddo 			last_port_idx--;
2203ce6959bfSWisam Jaddo 		if (last_port_idx < i)
2204ce6959bfSWisam Jaddo 			break;
2205ce6959bfSWisam Jaddo 		/* overwrite unused port with last valid port */
2206ce6959bfSWisam Jaddo 		ports_ids[i] = ports_ids[last_port_idx];
2207ce6959bfSWisam Jaddo 		/* decrease ports count */
2208ce6959bfSWisam Jaddo 		last_port_idx--;
2209ce6959bfSWisam Jaddo 	}
2210ce6959bfSWisam Jaddo 	nb_ports = rte_eth_dev_count_avail();
2211ce6959bfSWisam Jaddo 	update_fwd_ports(RTE_MAX_ETHPORTS);
2212ce6959bfSWisam Jaddo }
2213ce6959bfSWisam Jaddo 
2214ce8d5614SIntel void
2215ce8d5614SIntel close_port(portid_t pid)
2216ce8d5614SIntel {
2217ce8d5614SIntel 	portid_t pi;
2218ce8d5614SIntel 	struct rte_port *port;
2219ce8d5614SIntel 
22204468635fSMichael Qiu 	if (port_id_is_invalid(pid, ENABLED_WARN))
22214468635fSMichael Qiu 		return;
22224468635fSMichael Qiu 
2223ce8d5614SIntel 	printf("Closing ports...\n");
2224ce8d5614SIntel 
22257d89b261SGaetan Rivet 	RTE_ETH_FOREACH_DEV(pi) {
22264468635fSMichael Qiu 		if (pid != pi && pid != (portid_t)RTE_PORT_ALL)
2227ce8d5614SIntel 			continue;
2228ce8d5614SIntel 
2229a8ef3e3aSBernard Iremonger 		if (port_is_forwarding(pi) != 0 && test_done == 0) {
2230a8ef3e3aSBernard Iremonger 			printf("Please remove port %d from forwarding configuration.\n", pi);
2231a8ef3e3aSBernard Iremonger 			continue;
2232a8ef3e3aSBernard Iremonger 		}
2233a8ef3e3aSBernard Iremonger 
22340e545d30SBernard Iremonger 		if (port_is_bonding_slave(pi)) {
22350e545d30SBernard Iremonger 			printf("Please remove port %d from bonded device.\n", pi);
22360e545d30SBernard Iremonger 			continue;
22370e545d30SBernard Iremonger 		}
22380e545d30SBernard Iremonger 
2239ce8d5614SIntel 		port = &ports[pi];
2240ce8d5614SIntel 		if (rte_atomic16_cmpset(&(port->port_status),
2241d4e8ad64SMichael Qiu 			RTE_PORT_CLOSED, RTE_PORT_CLOSED) == 1) {
2242d4e8ad64SMichael Qiu 			printf("Port %d is already closed\n", pi);
2243d4e8ad64SMichael Qiu 			continue;
2244d4e8ad64SMichael Qiu 		}
2245d4e8ad64SMichael Qiu 
2246d4e8ad64SMichael Qiu 		if (rte_atomic16_cmpset(&(port->port_status),
2247ce8d5614SIntel 			RTE_PORT_STOPPED, RTE_PORT_HANDLING) == 0) {
2248ce8d5614SIntel 			printf("Port %d is now not stopped\n", pi);
2249ce8d5614SIntel 			continue;
2250ce8d5614SIntel 		}
2251ce8d5614SIntel 
2252938a184aSAdrien Mazarguil 		if (port->flow_list)
2253938a184aSAdrien Mazarguil 			port_flow_flush(pi);
2254ce8d5614SIntel 		rte_eth_dev_close(pi);
2255ce8d5614SIntel 
2256*23ea57a2SThomas Monjalon 		remove_unused_fwd_ports();
2257*23ea57a2SThomas Monjalon 
2258ce8d5614SIntel 		if (rte_atomic16_cmpset(&(port->port_status),
2259ce8d5614SIntel 			RTE_PORT_HANDLING, RTE_PORT_CLOSED) == 0)
2260b38bb262SPablo de Lara 			printf("Port %d cannot be set to closed\n", pi);
2261ce8d5614SIntel 	}
2262ce8d5614SIntel 
2263ce8d5614SIntel 	printf("Done\n");
2264ce8d5614SIntel }
2265ce8d5614SIntel 
2266edab33b1STetsuya Mukawa void
226797f1e196SWei Dai reset_port(portid_t pid)
226897f1e196SWei Dai {
226997f1e196SWei Dai 	int diag;
227097f1e196SWei Dai 	portid_t pi;
227197f1e196SWei Dai 	struct rte_port *port;
227297f1e196SWei Dai 
227397f1e196SWei Dai 	if (port_id_is_invalid(pid, ENABLED_WARN))
227497f1e196SWei Dai 		return;
227597f1e196SWei Dai 
227697f1e196SWei Dai 	printf("Resetting ports...\n");
227797f1e196SWei Dai 
227897f1e196SWei Dai 	RTE_ETH_FOREACH_DEV(pi) {
227997f1e196SWei Dai 		if (pid != pi && pid != (portid_t)RTE_PORT_ALL)
228097f1e196SWei Dai 			continue;
228197f1e196SWei Dai 
228297f1e196SWei Dai 		if (port_is_forwarding(pi) != 0 && test_done == 0) {
228397f1e196SWei Dai 			printf("Please remove port %d from forwarding "
228497f1e196SWei Dai 			       "configuration.\n", pi);
228597f1e196SWei Dai 			continue;
228697f1e196SWei Dai 		}
228797f1e196SWei Dai 
228897f1e196SWei Dai 		if (port_is_bonding_slave(pi)) {
228997f1e196SWei Dai 			printf("Please remove port %d from bonded device.\n",
229097f1e196SWei Dai 			       pi);
229197f1e196SWei Dai 			continue;
229297f1e196SWei Dai 		}
229397f1e196SWei Dai 
229497f1e196SWei Dai 		diag = rte_eth_dev_reset(pi);
229597f1e196SWei Dai 		if (diag == 0) {
229697f1e196SWei Dai 			port = &ports[pi];
229797f1e196SWei Dai 			port->need_reconfig = 1;
229897f1e196SWei Dai 			port->need_reconfig_queues = 1;
229997f1e196SWei Dai 		} else {
230097f1e196SWei Dai 			printf("Failed to reset port %d. diag=%d\n", pi, diag);
230197f1e196SWei Dai 		}
230297f1e196SWei Dai 	}
230397f1e196SWei Dai 
230497f1e196SWei Dai 	printf("Done\n");
230597f1e196SWei Dai }
230697f1e196SWei Dai 
230797f1e196SWei Dai void
2308edab33b1STetsuya Mukawa attach_port(char *identifier)
2309ce8d5614SIntel {
2310ebf5e9b7SBernard Iremonger 	portid_t pi = 0;
2311931126baSBernard Iremonger 	unsigned int socket_id;
2312ce8d5614SIntel 
2313edab33b1STetsuya Mukawa 	printf("Attaching a new port...\n");
2314edab33b1STetsuya Mukawa 
2315edab33b1STetsuya Mukawa 	if (identifier == NULL) {
2316edab33b1STetsuya Mukawa 		printf("Invalid parameters are specified\n");
2317edab33b1STetsuya Mukawa 		return;
2318ce8d5614SIntel 	}
2319ce8d5614SIntel 
2320edab33b1STetsuya Mukawa 	if (rte_eth_dev_attach(identifier, &pi))
2321edab33b1STetsuya Mukawa 		return;
2322edab33b1STetsuya Mukawa 
2323931126baSBernard Iremonger 	socket_id = (unsigned)rte_eth_dev_socket_id(pi);
232429841336SPhil Yang 	/* if socket_id is invalid, set to the first available socket. */
2325931126baSBernard Iremonger 	if (check_socket_id(socket_id) < 0)
232629841336SPhil Yang 		socket_id = socket_ids[0];
2327931126baSBernard Iremonger 	reconfig(pi, socket_id);
2328edab33b1STetsuya Mukawa 	rte_eth_promiscuous_enable(pi);
2329edab33b1STetsuya Mukawa 
23304918a357SXiaoyun Li 	ports_ids[nb_ports] = pi;
2331d9a42a69SThomas Monjalon 	nb_ports = rte_eth_dev_count_avail();
2332edab33b1STetsuya Mukawa 
2333edab33b1STetsuya Mukawa 	ports[pi].port_status = RTE_PORT_STOPPED;
2334edab33b1STetsuya Mukawa 
233503ce2c53SMatan Azrad 	update_fwd_ports(pi);
233603ce2c53SMatan Azrad 
2337edab33b1STetsuya Mukawa 	printf("Port %d is attached. Now total ports is %d\n", pi, nb_ports);
2338edab33b1STetsuya Mukawa 	printf("Done\n");
2339edab33b1STetsuya Mukawa }
2340edab33b1STetsuya Mukawa 
2341edab33b1STetsuya Mukawa void
234228caa76aSZhiyong Yang detach_port(portid_t port_id)
23435f4ec54fSChen Jing D(Mark) {
2344edab33b1STetsuya Mukawa 	char name[RTE_ETH_NAME_MAX_LEN];
23455f4ec54fSChen Jing D(Mark) 
2346edab33b1STetsuya Mukawa 	printf("Detaching a port...\n");
23475f4ec54fSChen Jing D(Mark) 
2348*23ea57a2SThomas Monjalon 	if (ports[port_id].port_status != RTE_PORT_CLOSED) {
23493f4a8370SThomas Monjalon 		if (ports[port_id].port_status != RTE_PORT_STOPPED) {
23503f4a8370SThomas Monjalon 			printf("Port not stopped\n");
2351edab33b1STetsuya Mukawa 			return;
2352edab33b1STetsuya Mukawa 		}
23533f4a8370SThomas Monjalon 		printf("Port was not closed\n");
2354938a184aSAdrien Mazarguil 		if (ports[port_id].flow_list)
2355938a184aSAdrien Mazarguil 			port_flow_flush(port_id);
23563f4a8370SThomas Monjalon 	}
2357938a184aSAdrien Mazarguil 
23583070419eSGaetan Rivet 	if (rte_eth_dev_detach(port_id, name)) {
2359adea04c4SZhiyong Yang 		TESTPMD_LOG(ERR, "Failed to detach port %u\n", port_id);
2360edab33b1STetsuya Mukawa 		return;
23613070419eSGaetan Rivet 	}
2362edab33b1STetsuya Mukawa 
2363ce6959bfSWisam Jaddo 	remove_unused_fwd_ports();
236403ce2c53SMatan Azrad 
2365adea04c4SZhiyong Yang 	printf("Port %u is detached. Now total ports is %d\n",
2366adea04c4SZhiyong Yang 			port_id, nb_ports);
2367edab33b1STetsuya Mukawa 	printf("Done\n");
2368edab33b1STetsuya Mukawa 	return;
23695f4ec54fSChen Jing D(Mark) }
23705f4ec54fSChen Jing D(Mark) 
2371af75078fSIntel void
2372af75078fSIntel pmd_test_exit(void)
2373af75078fSIntel {
2374124909d7SZhiyong Yang 	struct rte_device *device;
2375af75078fSIntel 	portid_t pt_id;
2376fb73e096SJeff Guo 	int ret;
2377af75078fSIntel 
23788210ec25SPablo de Lara 	if (test_done == 0)
23798210ec25SPablo de Lara 		stop_packet_forwarding();
23808210ec25SPablo de Lara 
2381d3a274ceSZhihong Wang 	if (ports != NULL) {
2382d3a274ceSZhihong Wang 		no_link_check = 1;
23837d89b261SGaetan Rivet 		RTE_ETH_FOREACH_DEV(pt_id) {
2384d3a274ceSZhihong Wang 			printf("\nShutting down port %d...\n", pt_id);
2385af75078fSIntel 			fflush(stdout);
2386d3a274ceSZhihong Wang 			stop_port(pt_id);
2387d3a274ceSZhihong Wang 			close_port(pt_id);
2388124909d7SZhiyong Yang 
2389124909d7SZhiyong Yang 			/*
2390124909d7SZhiyong Yang 			 * This is a workaround to fix a virtio-user issue that
2391124909d7SZhiyong Yang 			 * requires to call clean-up routine to remove existing
2392124909d7SZhiyong Yang 			 * socket.
2393124909d7SZhiyong Yang 			 * This workaround valid only for testpmd, needs a fix
2394124909d7SZhiyong Yang 			 * valid for all applications.
2395124909d7SZhiyong Yang 			 * TODO: Implement proper resource cleanup
2396124909d7SZhiyong Yang 			 */
2397124909d7SZhiyong Yang 			device = rte_eth_devices[pt_id].device;
2398124909d7SZhiyong Yang 			if (device && !strcmp(device->driver->name, "net_virtio_user"))
2399124909d7SZhiyong Yang 				detach_port(pt_id);
2400af75078fSIntel 		}
2401d3a274ceSZhihong Wang 	}
2402fb73e096SJeff Guo 
2403fb73e096SJeff Guo 	if (hot_plug) {
2404fb73e096SJeff Guo 		ret = rte_dev_event_monitor_stop();
24052049c511SJeff Guo 		if (ret) {
2406fb73e096SJeff Guo 			RTE_LOG(ERR, EAL,
2407fb73e096SJeff Guo 				"fail to stop device event monitor.");
24082049c511SJeff Guo 			return;
24092049c511SJeff Guo 		}
2410fb73e096SJeff Guo 
24112049c511SJeff Guo 		ret = rte_dev_event_callback_unregister(NULL,
24122049c511SJeff Guo 			eth_dev_event_callback, NULL);
24132049c511SJeff Guo 		if (ret < 0) {
2414fb73e096SJeff Guo 			RTE_LOG(ERR, EAL,
24152049c511SJeff Guo 				"fail to unregister device event callback.\n");
24162049c511SJeff Guo 			return;
24172049c511SJeff Guo 		}
24182049c511SJeff Guo 
24192049c511SJeff Guo 		ret = rte_dev_hotplug_handle_disable();
24202049c511SJeff Guo 		if (ret) {
24212049c511SJeff Guo 			RTE_LOG(ERR, EAL,
24222049c511SJeff Guo 				"fail to disable hotplug handling.\n");
24232049c511SJeff Guo 			return;
24242049c511SJeff Guo 		}
2425fb73e096SJeff Guo 	}
2426fb73e096SJeff Guo 
2427d3a274ceSZhihong Wang 	printf("\nBye...\n");
2428af75078fSIntel }
2429af75078fSIntel 
2430af75078fSIntel typedef void (*cmd_func_t)(void);
2431af75078fSIntel struct pmd_test_command {
2432af75078fSIntel 	const char *cmd_name;
2433af75078fSIntel 	cmd_func_t cmd_func;
2434af75078fSIntel };
2435af75078fSIntel 
2436af75078fSIntel #define PMD_TEST_CMD_NB (sizeof(pmd_test_menu) / sizeof(pmd_test_menu[0]))
2437af75078fSIntel 
2438ce8d5614SIntel /* Check the link status of all ports in up to 9s, and print them finally */
2439af75078fSIntel static void
2440edab33b1STetsuya Mukawa check_all_ports_link_status(uint32_t port_mask)
2441af75078fSIntel {
2442ce8d5614SIntel #define CHECK_INTERVAL 100 /* 100ms */
2443ce8d5614SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
2444f8244c63SZhiyong Yang 	portid_t portid;
2445f8244c63SZhiyong Yang 	uint8_t count, all_ports_up, print_flag = 0;
2446ce8d5614SIntel 	struct rte_eth_link link;
2447ce8d5614SIntel 
2448ce8d5614SIntel 	printf("Checking link statuses...\n");
2449ce8d5614SIntel 	fflush(stdout);
2450ce8d5614SIntel 	for (count = 0; count <= MAX_CHECK_TIME; count++) {
2451ce8d5614SIntel 		all_ports_up = 1;
24527d89b261SGaetan Rivet 		RTE_ETH_FOREACH_DEV(portid) {
2453ce8d5614SIntel 			if ((port_mask & (1 << portid)) == 0)
2454ce8d5614SIntel 				continue;
2455ce8d5614SIntel 			memset(&link, 0, sizeof(link));
2456ce8d5614SIntel 			rte_eth_link_get_nowait(portid, &link);
2457ce8d5614SIntel 			/* print link status if flag set */
2458ce8d5614SIntel 			if (print_flag == 1) {
2459ce8d5614SIntel 				if (link.link_status)
2460f8244c63SZhiyong Yang 					printf(
2461f8244c63SZhiyong Yang 					"Port%d Link Up. speed %u Mbps- %s\n",
2462f8244c63SZhiyong Yang 					portid, link.link_speed,
2463ce8d5614SIntel 				(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
2464ce8d5614SIntel 					("full-duplex") : ("half-duplex\n"));
2465ce8d5614SIntel 				else
2466f8244c63SZhiyong Yang 					printf("Port %d Link Down\n", portid);
2467ce8d5614SIntel 				continue;
2468ce8d5614SIntel 			}
2469ce8d5614SIntel 			/* clear all_ports_up flag if any link down */
247009419f23SThomas Monjalon 			if (link.link_status == ETH_LINK_DOWN) {
2471ce8d5614SIntel 				all_ports_up = 0;
2472ce8d5614SIntel 				break;
2473ce8d5614SIntel 			}
2474ce8d5614SIntel 		}
2475ce8d5614SIntel 		/* after finally printing all link status, get out */
2476ce8d5614SIntel 		if (print_flag == 1)
2477ce8d5614SIntel 			break;
2478ce8d5614SIntel 
2479ce8d5614SIntel 		if (all_ports_up == 0) {
2480ce8d5614SIntel 			fflush(stdout);
2481ce8d5614SIntel 			rte_delay_ms(CHECK_INTERVAL);
2482ce8d5614SIntel 		}
2483ce8d5614SIntel 
2484ce8d5614SIntel 		/* set the print_flag if all ports up or timeout */
2485ce8d5614SIntel 		if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {
2486ce8d5614SIntel 			print_flag = 1;
2487ce8d5614SIntel 		}
24888ea656f8SGaetan Rivet 
24898ea656f8SGaetan Rivet 		if (lsc_interrupt)
24908ea656f8SGaetan Rivet 			break;
2491ce8d5614SIntel 	}
2492af75078fSIntel }
2493af75078fSIntel 
2494284c908cSGaetan Rivet static void
2495284c908cSGaetan Rivet rmv_event_callback(void *arg)
2496284c908cSGaetan Rivet {
24973b97888aSMatan Azrad 	int need_to_start = 0;
24980da2a62bSMatan Azrad 	int org_no_link_check = no_link_check;
249928caa76aSZhiyong Yang 	portid_t port_id = (intptr_t)arg;
2500284c908cSGaetan Rivet 
2501284c908cSGaetan Rivet 	RTE_ETH_VALID_PORTID_OR_RET(port_id);
2502284c908cSGaetan Rivet 
25033b97888aSMatan Azrad 	if (!test_done && port_is_forwarding(port_id)) {
25043b97888aSMatan Azrad 		need_to_start = 1;
25053b97888aSMatan Azrad 		stop_packet_forwarding();
25063b97888aSMatan Azrad 	}
25070da2a62bSMatan Azrad 	no_link_check = 1;
2508284c908cSGaetan Rivet 	stop_port(port_id);
25090da2a62bSMatan Azrad 	no_link_check = org_no_link_check;
2510284c908cSGaetan Rivet 	close_port(port_id);
25113b97888aSMatan Azrad 	detach_port(port_id);
25123b97888aSMatan Azrad 	if (need_to_start)
25133b97888aSMatan Azrad 		start_packet_forwarding(0);
2514284c908cSGaetan Rivet }
2515284c908cSGaetan Rivet 
251676ad4a2dSGaetan Rivet /* This function is used by the interrupt thread */
2517d6af1a13SBernard Iremonger static int
2518f8244c63SZhiyong Yang eth_event_callback(portid_t port_id, enum rte_eth_event_type type, void *param,
2519d6af1a13SBernard Iremonger 		  void *ret_param)
252076ad4a2dSGaetan Rivet {
252176ad4a2dSGaetan Rivet 	static const char * const event_desc[] = {
252276ad4a2dSGaetan Rivet 		[RTE_ETH_EVENT_UNKNOWN] = "Unknown",
252376ad4a2dSGaetan Rivet 		[RTE_ETH_EVENT_INTR_LSC] = "LSC",
252476ad4a2dSGaetan Rivet 		[RTE_ETH_EVENT_QUEUE_STATE] = "Queue state",
252576ad4a2dSGaetan Rivet 		[RTE_ETH_EVENT_INTR_RESET] = "Interrupt reset",
252676ad4a2dSGaetan Rivet 		[RTE_ETH_EVENT_VF_MBOX] = "VF Mbox",
2527badb87c1SAnoob Joseph 		[RTE_ETH_EVENT_IPSEC] = "IPsec",
252876ad4a2dSGaetan Rivet 		[RTE_ETH_EVENT_MACSEC] = "MACsec",
252976ad4a2dSGaetan Rivet 		[RTE_ETH_EVENT_INTR_RMV] = "device removal",
25304fb82244SMatan Azrad 		[RTE_ETH_EVENT_NEW] = "device probed",
25314fb82244SMatan Azrad 		[RTE_ETH_EVENT_DESTROY] = "device released",
253276ad4a2dSGaetan Rivet 		[RTE_ETH_EVENT_MAX] = NULL,
253376ad4a2dSGaetan Rivet 	};
253476ad4a2dSGaetan Rivet 
253576ad4a2dSGaetan Rivet 	RTE_SET_USED(param);
2536d6af1a13SBernard Iremonger 	RTE_SET_USED(ret_param);
253776ad4a2dSGaetan Rivet 
253876ad4a2dSGaetan Rivet 	if (type >= RTE_ETH_EVENT_MAX) {
2539f431e010SHerakliusz Lipiec 		fprintf(stderr, "\nPort %" PRIu16 ": %s called upon invalid event %d\n",
254076ad4a2dSGaetan Rivet 			port_id, __func__, type);
254176ad4a2dSGaetan Rivet 		fflush(stderr);
25423af72783SGaetan Rivet 	} else if (event_print_mask & (UINT32_C(1) << type)) {
2543f431e010SHerakliusz Lipiec 		printf("\nPort %" PRIu16 ": %s event\n", port_id,
254476ad4a2dSGaetan Rivet 			event_desc[type]);
254576ad4a2dSGaetan Rivet 		fflush(stdout);
254676ad4a2dSGaetan Rivet 	}
2547284c908cSGaetan Rivet 
25480e45c64dSMatan Azrad 	if (port_id_is_invalid(port_id, DISABLED_WARN))
25490e45c64dSMatan Azrad 		return 0;
25500e45c64dSMatan Azrad 
2551284c908cSGaetan Rivet 	switch (type) {
2552284c908cSGaetan Rivet 	case RTE_ETH_EVENT_INTR_RMV:
2553284c908cSGaetan Rivet 		if (rte_eal_alarm_set(100000,
2554284c908cSGaetan Rivet 				rmv_event_callback, (void *)(intptr_t)port_id))
2555284c908cSGaetan Rivet 			fprintf(stderr, "Could not set up deferred device removal\n");
2556284c908cSGaetan Rivet 		break;
2557284c908cSGaetan Rivet 	default:
2558284c908cSGaetan Rivet 		break;
2559284c908cSGaetan Rivet 	}
2560d6af1a13SBernard Iremonger 	return 0;
256176ad4a2dSGaetan Rivet }
256276ad4a2dSGaetan Rivet 
2563fb73e096SJeff Guo /* This function is used by the interrupt thread */
2564fb73e096SJeff Guo static void
256589ecd110SJeff Guo eth_dev_event_callback(const char *device_name, enum rte_dev_event_type type,
2566fb73e096SJeff Guo 			     __rte_unused void *arg)
2567fb73e096SJeff Guo {
25682049c511SJeff Guo 	uint16_t port_id;
25692049c511SJeff Guo 	int ret;
25702049c511SJeff Guo 
2571fb73e096SJeff Guo 	if (type >= RTE_DEV_EVENT_MAX) {
2572fb73e096SJeff Guo 		fprintf(stderr, "%s called upon invalid event %d\n",
2573fb73e096SJeff Guo 			__func__, type);
2574fb73e096SJeff Guo 		fflush(stderr);
2575fb73e096SJeff Guo 	}
2576fb73e096SJeff Guo 
2577fb73e096SJeff Guo 	switch (type) {
2578fb73e096SJeff Guo 	case RTE_DEV_EVENT_REMOVE:
2579fb73e096SJeff Guo 		RTE_LOG(ERR, EAL, "The device: %s has been removed!\n",
2580fb73e096SJeff Guo 			device_name);
25812049c511SJeff Guo 		ret = rte_eth_dev_get_port_by_name(device_name, &port_id);
25822049c511SJeff Guo 		if (ret) {
25832049c511SJeff Guo 			RTE_LOG(ERR, EAL, "can not get port by device %s!\n",
25842049c511SJeff Guo 				device_name);
25852049c511SJeff Guo 			return;
25862049c511SJeff Guo 		}
25872049c511SJeff Guo 		rmv_event_callback((void *)(intptr_t)port_id);
2588fb73e096SJeff Guo 		break;
2589fb73e096SJeff Guo 	case RTE_DEV_EVENT_ADD:
2590fb73e096SJeff Guo 		RTE_LOG(ERR, EAL, "The device: %s has been added!\n",
2591fb73e096SJeff Guo 			device_name);
2592fb73e096SJeff Guo 		/* TODO: After finish kernel driver binding,
2593fb73e096SJeff Guo 		 * begin to attach port.
2594fb73e096SJeff Guo 		 */
2595fb73e096SJeff Guo 		break;
2596fb73e096SJeff Guo 	default:
2597fb73e096SJeff Guo 		break;
2598fb73e096SJeff Guo 	}
2599fb73e096SJeff Guo }
2600fb73e096SJeff Guo 
2601013af9b6SIntel static int
260228caa76aSZhiyong Yang set_tx_queue_stats_mapping_registers(portid_t port_id, struct rte_port *port)
2603af75078fSIntel {
2604013af9b6SIntel 	uint16_t i;
2605af75078fSIntel 	int diag;
2606013af9b6SIntel 	uint8_t mapping_found = 0;
2607af75078fSIntel 
2608013af9b6SIntel 	for (i = 0; i < nb_tx_queue_stats_mappings; i++) {
2609013af9b6SIntel 		if ((tx_queue_stats_mappings[i].port_id == port_id) &&
2610013af9b6SIntel 				(tx_queue_stats_mappings[i].queue_id < nb_txq )) {
2611013af9b6SIntel 			diag = rte_eth_dev_set_tx_queue_stats_mapping(port_id,
2612013af9b6SIntel 					tx_queue_stats_mappings[i].queue_id,
2613013af9b6SIntel 					tx_queue_stats_mappings[i].stats_counter_id);
2614013af9b6SIntel 			if (diag != 0)
2615013af9b6SIntel 				return diag;
2616013af9b6SIntel 			mapping_found = 1;
2617af75078fSIntel 		}
2618013af9b6SIntel 	}
2619013af9b6SIntel 	if (mapping_found)
2620013af9b6SIntel 		port->tx_queue_stats_mapping_enabled = 1;
2621013af9b6SIntel 	return 0;
2622013af9b6SIntel }
2623013af9b6SIntel 
2624013af9b6SIntel static int
262528caa76aSZhiyong Yang set_rx_queue_stats_mapping_registers(portid_t port_id, struct rte_port *port)
2626013af9b6SIntel {
2627013af9b6SIntel 	uint16_t i;
2628013af9b6SIntel 	int diag;
2629013af9b6SIntel 	uint8_t mapping_found = 0;
2630013af9b6SIntel 
2631013af9b6SIntel 	for (i = 0; i < nb_rx_queue_stats_mappings; i++) {
2632013af9b6SIntel 		if ((rx_queue_stats_mappings[i].port_id == port_id) &&
2633013af9b6SIntel 				(rx_queue_stats_mappings[i].queue_id < nb_rxq )) {
2634013af9b6SIntel 			diag = rte_eth_dev_set_rx_queue_stats_mapping(port_id,
2635013af9b6SIntel 					rx_queue_stats_mappings[i].queue_id,
2636013af9b6SIntel 					rx_queue_stats_mappings[i].stats_counter_id);
2637013af9b6SIntel 			if (diag != 0)
2638013af9b6SIntel 				return diag;
2639013af9b6SIntel 			mapping_found = 1;
2640013af9b6SIntel 		}
2641013af9b6SIntel 	}
2642013af9b6SIntel 	if (mapping_found)
2643013af9b6SIntel 		port->rx_queue_stats_mapping_enabled = 1;
2644013af9b6SIntel 	return 0;
2645013af9b6SIntel }
2646013af9b6SIntel 
2647013af9b6SIntel static void
264828caa76aSZhiyong Yang map_port_queue_stats_mapping_registers(portid_t pi, struct rte_port *port)
2649013af9b6SIntel {
2650013af9b6SIntel 	int diag = 0;
2651013af9b6SIntel 
2652013af9b6SIntel 	diag = set_tx_queue_stats_mapping_registers(pi, port);
2653af75078fSIntel 	if (diag != 0) {
2654013af9b6SIntel 		if (diag == -ENOTSUP) {
2655013af9b6SIntel 			port->tx_queue_stats_mapping_enabled = 0;
2656013af9b6SIntel 			printf("TX queue stats mapping not supported port id=%d\n", pi);
2657013af9b6SIntel 		}
2658013af9b6SIntel 		else
2659013af9b6SIntel 			rte_exit(EXIT_FAILURE,
2660013af9b6SIntel 					"set_tx_queue_stats_mapping_registers "
2661013af9b6SIntel 					"failed for port id=%d diag=%d\n",
2662af75078fSIntel 					pi, diag);
2663af75078fSIntel 	}
2664013af9b6SIntel 
2665013af9b6SIntel 	diag = set_rx_queue_stats_mapping_registers(pi, port);
2666af75078fSIntel 	if (diag != 0) {
2667013af9b6SIntel 		if (diag == -ENOTSUP) {
2668013af9b6SIntel 			port->rx_queue_stats_mapping_enabled = 0;
2669013af9b6SIntel 			printf("RX queue stats mapping not supported port id=%d\n", pi);
2670013af9b6SIntel 		}
2671013af9b6SIntel 		else
2672013af9b6SIntel 			rte_exit(EXIT_FAILURE,
2673013af9b6SIntel 					"set_rx_queue_stats_mapping_registers "
2674013af9b6SIntel 					"failed for port id=%d diag=%d\n",
2675af75078fSIntel 					pi, diag);
2676af75078fSIntel 	}
2677af75078fSIntel }
2678af75078fSIntel 
2679f2c5125aSPablo de Lara static void
2680f2c5125aSPablo de Lara rxtx_port_config(struct rte_port *port)
2681f2c5125aSPablo de Lara {
2682d44f8a48SQi Zhang 	uint16_t qid;
2683f2c5125aSPablo de Lara 
2684d44f8a48SQi Zhang 	for (qid = 0; qid < nb_rxq; qid++) {
2685d44f8a48SQi Zhang 		port->rx_conf[qid] = port->dev_info.default_rxconf;
2686d44f8a48SQi Zhang 
2687d44f8a48SQi Zhang 		/* Check if any Rx parameters have been passed */
2688f2c5125aSPablo de Lara 		if (rx_pthresh != RTE_PMD_PARAM_UNSET)
2689d44f8a48SQi Zhang 			port->rx_conf[qid].rx_thresh.pthresh = rx_pthresh;
2690f2c5125aSPablo de Lara 
2691f2c5125aSPablo de Lara 		if (rx_hthresh != RTE_PMD_PARAM_UNSET)
2692d44f8a48SQi Zhang 			port->rx_conf[qid].rx_thresh.hthresh = rx_hthresh;
2693f2c5125aSPablo de Lara 
2694f2c5125aSPablo de Lara 		if (rx_wthresh != RTE_PMD_PARAM_UNSET)
2695d44f8a48SQi Zhang 			port->rx_conf[qid].rx_thresh.wthresh = rx_wthresh;
2696f2c5125aSPablo de Lara 
2697f2c5125aSPablo de Lara 		if (rx_free_thresh != RTE_PMD_PARAM_UNSET)
2698d44f8a48SQi Zhang 			port->rx_conf[qid].rx_free_thresh = rx_free_thresh;
2699f2c5125aSPablo de Lara 
2700f2c5125aSPablo de Lara 		if (rx_drop_en != RTE_PMD_PARAM_UNSET)
2701d44f8a48SQi Zhang 			port->rx_conf[qid].rx_drop_en = rx_drop_en;
2702f2c5125aSPablo de Lara 
2703d44f8a48SQi Zhang 		port->nb_rx_desc[qid] = nb_rxd;
2704d44f8a48SQi Zhang 	}
2705d44f8a48SQi Zhang 
2706d44f8a48SQi Zhang 	for (qid = 0; qid < nb_txq; qid++) {
2707d44f8a48SQi Zhang 		port->tx_conf[qid] = port->dev_info.default_txconf;
2708d44f8a48SQi Zhang 
2709d44f8a48SQi Zhang 		/* Check if any Tx parameters have been passed */
2710f2c5125aSPablo de Lara 		if (tx_pthresh != RTE_PMD_PARAM_UNSET)
2711d44f8a48SQi Zhang 			port->tx_conf[qid].tx_thresh.pthresh = tx_pthresh;
2712f2c5125aSPablo de Lara 
2713f2c5125aSPablo de Lara 		if (tx_hthresh != RTE_PMD_PARAM_UNSET)
2714d44f8a48SQi Zhang 			port->tx_conf[qid].tx_thresh.hthresh = tx_hthresh;
2715f2c5125aSPablo de Lara 
2716f2c5125aSPablo de Lara 		if (tx_wthresh != RTE_PMD_PARAM_UNSET)
2717d44f8a48SQi Zhang 			port->tx_conf[qid].tx_thresh.wthresh = tx_wthresh;
2718f2c5125aSPablo de Lara 
2719f2c5125aSPablo de Lara 		if (tx_rs_thresh != RTE_PMD_PARAM_UNSET)
2720d44f8a48SQi Zhang 			port->tx_conf[qid].tx_rs_thresh = tx_rs_thresh;
2721f2c5125aSPablo de Lara 
2722f2c5125aSPablo de Lara 		if (tx_free_thresh != RTE_PMD_PARAM_UNSET)
2723d44f8a48SQi Zhang 			port->tx_conf[qid].tx_free_thresh = tx_free_thresh;
2724d44f8a48SQi Zhang 
2725d44f8a48SQi Zhang 		port->nb_tx_desc[qid] = nb_txd;
2726d44f8a48SQi Zhang 	}
2727f2c5125aSPablo de Lara }
2728f2c5125aSPablo de Lara 
2729013af9b6SIntel void
2730013af9b6SIntel init_port_config(void)
2731013af9b6SIntel {
2732013af9b6SIntel 	portid_t pid;
2733013af9b6SIntel 	struct rte_port *port;
2734013af9b6SIntel 
27357d89b261SGaetan Rivet 	RTE_ETH_FOREACH_DEV(pid) {
2736013af9b6SIntel 		port = &ports[pid];
2737013af9b6SIntel 		port->dev_conf.fdir_conf = fdir_conf;
2738422515b9SAdrien Mazarguil 		rte_eth_dev_info_get(pid, &port->dev_info);
27393ce690d3SBruce Richardson 		if (nb_rxq > 1) {
2740013af9b6SIntel 			port->dev_conf.rx_adv_conf.rss_conf.rss_key = NULL;
274190892962SQi Zhang 			port->dev_conf.rx_adv_conf.rss_conf.rss_hf =
2742422515b9SAdrien Mazarguil 				rss_hf & port->dev_info.flow_type_rss_offloads;
2743af75078fSIntel 		} else {
2744013af9b6SIntel 			port->dev_conf.rx_adv_conf.rss_conf.rss_key = NULL;
2745013af9b6SIntel 			port->dev_conf.rx_adv_conf.rss_conf.rss_hf = 0;
2746af75078fSIntel 		}
27473ce690d3SBruce Richardson 
27485f592039SJingjing Wu 		if (port->dcb_flag == 0) {
27493ce690d3SBruce Richardson 			if( port->dev_conf.rx_adv_conf.rss_conf.rss_hf != 0)
27503ce690d3SBruce Richardson 				port->dev_conf.rxmode.mq_mode = ETH_MQ_RX_RSS;
27513ce690d3SBruce Richardson 			else
27523ce690d3SBruce Richardson 				port->dev_conf.rxmode.mq_mode = ETH_MQ_RX_NONE;
27533ce690d3SBruce Richardson 		}
27543ce690d3SBruce Richardson 
2755f2c5125aSPablo de Lara 		rxtx_port_config(port);
2756013af9b6SIntel 
2757013af9b6SIntel 		rte_eth_macaddr_get(pid, &port->eth_addr);
2758013af9b6SIntel 
2759013af9b6SIntel 		map_port_queue_stats_mapping_registers(pid, port);
276050c4440eSThomas Monjalon #if defined RTE_LIBRTE_IXGBE_PMD && defined RTE_LIBRTE_IXGBE_BYPASS
2761e261265eSRadu Nicolau 		rte_pmd_ixgbe_bypass_init(pid);
27627b7e5ba7SIntel #endif
27638ea656f8SGaetan Rivet 
27648ea656f8SGaetan Rivet 		if (lsc_interrupt &&
27658ea656f8SGaetan Rivet 		    (rte_eth_devices[pid].data->dev_flags &
27668ea656f8SGaetan Rivet 		     RTE_ETH_DEV_INTR_LSC))
27678ea656f8SGaetan Rivet 			port->dev_conf.intr_conf.lsc = 1;
2768284c908cSGaetan Rivet 		if (rmv_interrupt &&
2769284c908cSGaetan Rivet 		    (rte_eth_devices[pid].data->dev_flags &
2770284c908cSGaetan Rivet 		     RTE_ETH_DEV_INTR_RMV))
2771284c908cSGaetan Rivet 			port->dev_conf.intr_conf.rmv = 1;
2772013af9b6SIntel 	}
2773013af9b6SIntel }
2774013af9b6SIntel 
277541b05095SBernard Iremonger void set_port_slave_flag(portid_t slave_pid)
277641b05095SBernard Iremonger {
277741b05095SBernard Iremonger 	struct rte_port *port;
277841b05095SBernard Iremonger 
277941b05095SBernard Iremonger 	port = &ports[slave_pid];
278041b05095SBernard Iremonger 	port->slave_flag = 1;
278141b05095SBernard Iremonger }
278241b05095SBernard Iremonger 
278341b05095SBernard Iremonger void clear_port_slave_flag(portid_t slave_pid)
278441b05095SBernard Iremonger {
278541b05095SBernard Iremonger 	struct rte_port *port;
278641b05095SBernard Iremonger 
278741b05095SBernard Iremonger 	port = &ports[slave_pid];
278841b05095SBernard Iremonger 	port->slave_flag = 0;
278941b05095SBernard Iremonger }
279041b05095SBernard Iremonger 
27910e545d30SBernard Iremonger uint8_t port_is_bonding_slave(portid_t slave_pid)
27920e545d30SBernard Iremonger {
27930e545d30SBernard Iremonger 	struct rte_port *port;
27940e545d30SBernard Iremonger 
27950e545d30SBernard Iremonger 	port = &ports[slave_pid];
2796b8b8b344SMatan Azrad 	if ((rte_eth_devices[slave_pid].data->dev_flags &
2797b8b8b344SMatan Azrad 	    RTE_ETH_DEV_BONDED_SLAVE) || (port->slave_flag == 1))
2798b8b8b344SMatan Azrad 		return 1;
2799b8b8b344SMatan Azrad 	return 0;
28000e545d30SBernard Iremonger }
28010e545d30SBernard Iremonger 
2802013af9b6SIntel const uint16_t vlan_tags[] = {
2803013af9b6SIntel 		0,  1,  2,  3,  4,  5,  6,  7,
2804013af9b6SIntel 		8,  9, 10, 11,  12, 13, 14, 15,
2805013af9b6SIntel 		16, 17, 18, 19, 20, 21, 22, 23,
2806013af9b6SIntel 		24, 25, 26, 27, 28, 29, 30, 31
2807013af9b6SIntel };
2808013af9b6SIntel 
2809013af9b6SIntel static  int
2810ac7c491cSKonstantin Ananyev get_eth_dcb_conf(portid_t pid, struct rte_eth_conf *eth_conf,
28111a572499SJingjing Wu 		 enum dcb_mode_enable dcb_mode,
28121a572499SJingjing Wu 		 enum rte_eth_nb_tcs num_tcs,
28131a572499SJingjing Wu 		 uint8_t pfc_en)
2814013af9b6SIntel {
2815013af9b6SIntel 	uint8_t i;
2816ac7c491cSKonstantin Ananyev 	int32_t rc;
2817ac7c491cSKonstantin Ananyev 	struct rte_eth_rss_conf rss_conf;
2818af75078fSIntel 
2819af75078fSIntel 	/*
2820013af9b6SIntel 	 * Builds up the correct configuration for dcb+vt based on the vlan tags array
2821013af9b6SIntel 	 * given above, and the number of traffic classes available for use.
2822af75078fSIntel 	 */
28231a572499SJingjing Wu 	if (dcb_mode == DCB_VT_ENABLED) {
28241a572499SJingjing Wu 		struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
28251a572499SJingjing Wu 				&eth_conf->rx_adv_conf.vmdq_dcb_conf;
28261a572499SJingjing Wu 		struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
28271a572499SJingjing Wu 				&eth_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2828013af9b6SIntel 
2829547d946cSNirmoy Das 		/* VMDQ+DCB RX and TX configurations */
28301a572499SJingjing Wu 		vmdq_rx_conf->enable_default_pool = 0;
28311a572499SJingjing Wu 		vmdq_rx_conf->default_pool = 0;
28321a572499SJingjing Wu 		vmdq_rx_conf->nb_queue_pools =
28331a572499SJingjing Wu 			(num_tcs ==  ETH_4_TCS ? ETH_32_POOLS : ETH_16_POOLS);
28341a572499SJingjing Wu 		vmdq_tx_conf->nb_queue_pools =
28351a572499SJingjing Wu 			(num_tcs ==  ETH_4_TCS ? ETH_32_POOLS : ETH_16_POOLS);
2836013af9b6SIntel 
28371a572499SJingjing Wu 		vmdq_rx_conf->nb_pool_maps = vmdq_rx_conf->nb_queue_pools;
28381a572499SJingjing Wu 		for (i = 0; i < vmdq_rx_conf->nb_pool_maps; i++) {
28391a572499SJingjing Wu 			vmdq_rx_conf->pool_map[i].vlan_id = vlan_tags[i];
28401a572499SJingjing Wu 			vmdq_rx_conf->pool_map[i].pools =
28411a572499SJingjing Wu 				1 << (i % vmdq_rx_conf->nb_queue_pools);
2842af75078fSIntel 		}
2843013af9b6SIntel 		for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2844f59908feSWei Dai 			vmdq_rx_conf->dcb_tc[i] = i % num_tcs;
2845f59908feSWei Dai 			vmdq_tx_conf->dcb_tc[i] = i % num_tcs;
2846013af9b6SIntel 		}
2847013af9b6SIntel 
2848013af9b6SIntel 		/* set DCB mode of RX and TX of multiple queues */
284932e7aa0bSIntel 		eth_conf->rxmode.mq_mode = ETH_MQ_RX_VMDQ_DCB;
285032e7aa0bSIntel 		eth_conf->txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
28511a572499SJingjing Wu 	} else {
28521a572499SJingjing Wu 		struct rte_eth_dcb_rx_conf *rx_conf =
28531a572499SJingjing Wu 				&eth_conf->rx_adv_conf.dcb_rx_conf;
28541a572499SJingjing Wu 		struct rte_eth_dcb_tx_conf *tx_conf =
28551a572499SJingjing Wu 				&eth_conf->tx_adv_conf.dcb_tx_conf;
2856013af9b6SIntel 
2857ac7c491cSKonstantin Ananyev 		rc = rte_eth_dev_rss_hash_conf_get(pid, &rss_conf);
2858ac7c491cSKonstantin Ananyev 		if (rc != 0)
2859ac7c491cSKonstantin Ananyev 			return rc;
2860ac7c491cSKonstantin Ananyev 
28611a572499SJingjing Wu 		rx_conf->nb_tcs = num_tcs;
28621a572499SJingjing Wu 		tx_conf->nb_tcs = num_tcs;
28631a572499SJingjing Wu 
2864bcd0e432SJingjing Wu 		for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2865bcd0e432SJingjing Wu 			rx_conf->dcb_tc[i] = i % num_tcs;
2866bcd0e432SJingjing Wu 			tx_conf->dcb_tc[i] = i % num_tcs;
2867013af9b6SIntel 		}
2868ac7c491cSKonstantin Ananyev 
28691a572499SJingjing Wu 		eth_conf->rxmode.mq_mode = ETH_MQ_RX_DCB_RSS;
2870ac7c491cSKonstantin Ananyev 		eth_conf->rx_adv_conf.rss_conf = rss_conf;
287132e7aa0bSIntel 		eth_conf->txmode.mq_mode = ETH_MQ_TX_DCB;
28721a572499SJingjing Wu 	}
28731a572499SJingjing Wu 
28741a572499SJingjing Wu 	if (pfc_en)
28751a572499SJingjing Wu 		eth_conf->dcb_capability_en =
28761a572499SJingjing Wu 				ETH_DCB_PG_SUPPORT | ETH_DCB_PFC_SUPPORT;
2877013af9b6SIntel 	else
2878013af9b6SIntel 		eth_conf->dcb_capability_en = ETH_DCB_PG_SUPPORT;
2879013af9b6SIntel 
2880013af9b6SIntel 	return 0;
2881013af9b6SIntel }
2882013af9b6SIntel 
2883013af9b6SIntel int
28841a572499SJingjing Wu init_port_dcb_config(portid_t pid,
28851a572499SJingjing Wu 		     enum dcb_mode_enable dcb_mode,
28861a572499SJingjing Wu 		     enum rte_eth_nb_tcs num_tcs,
28871a572499SJingjing Wu 		     uint8_t pfc_en)
2888013af9b6SIntel {
2889013af9b6SIntel 	struct rte_eth_conf port_conf;
2890013af9b6SIntel 	struct rte_port *rte_port;
2891013af9b6SIntel 	int retval;
2892013af9b6SIntel 	uint16_t i;
2893013af9b6SIntel 
28942a977b89SWenzhuo Lu 	rte_port = &ports[pid];
2895013af9b6SIntel 
2896013af9b6SIntel 	memset(&port_conf, 0, sizeof(struct rte_eth_conf));
2897013af9b6SIntel 	/* Enter DCB configuration status */
2898013af9b6SIntel 	dcb_config = 1;
2899013af9b6SIntel 
2900d5354e89SYanglong Wu 	port_conf.rxmode = rte_port->dev_conf.rxmode;
2901d5354e89SYanglong Wu 	port_conf.txmode = rte_port->dev_conf.txmode;
2902d5354e89SYanglong Wu 
2903013af9b6SIntel 	/*set configuration of DCB in vt mode and DCB in non-vt mode*/
2904ac7c491cSKonstantin Ananyev 	retval = get_eth_dcb_conf(pid, &port_conf, dcb_mode, num_tcs, pfc_en);
2905013af9b6SIntel 	if (retval < 0)
2906013af9b6SIntel 		return retval;
29070074d02fSShahaf Shuler 	port_conf.rxmode.offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
2908013af9b6SIntel 
29092f203d44SQi Zhang 	/* re-configure the device . */
29102f203d44SQi Zhang 	rte_eth_dev_configure(pid, nb_rxq, nb_rxq, &port_conf);
29112a977b89SWenzhuo Lu 
29122a977b89SWenzhuo Lu 	rte_eth_dev_info_get(pid, &rte_port->dev_info);
29132a977b89SWenzhuo Lu 
29142a977b89SWenzhuo Lu 	/* If dev_info.vmdq_pool_base is greater than 0,
29152a977b89SWenzhuo Lu 	 * the queue id of vmdq pools is started after pf queues.
29162a977b89SWenzhuo Lu 	 */
29172a977b89SWenzhuo Lu 	if (dcb_mode == DCB_VT_ENABLED &&
29182a977b89SWenzhuo Lu 	    rte_port->dev_info.vmdq_pool_base > 0) {
29192a977b89SWenzhuo Lu 		printf("VMDQ_DCB multi-queue mode is nonsensical"
29202a977b89SWenzhuo Lu 			" for port %d.", pid);
29212a977b89SWenzhuo Lu 		return -1;
29222a977b89SWenzhuo Lu 	}
29232a977b89SWenzhuo Lu 
29242a977b89SWenzhuo Lu 	/* Assume the ports in testpmd have the same dcb capability
29252a977b89SWenzhuo Lu 	 * and has the same number of rxq and txq in dcb mode
29262a977b89SWenzhuo Lu 	 */
29272a977b89SWenzhuo Lu 	if (dcb_mode == DCB_VT_ENABLED) {
292886ef65eeSBernard Iremonger 		if (rte_port->dev_info.max_vfs > 0) {
292986ef65eeSBernard Iremonger 			nb_rxq = rte_port->dev_info.nb_rx_queues;
293086ef65eeSBernard Iremonger 			nb_txq = rte_port->dev_info.nb_tx_queues;
293186ef65eeSBernard Iremonger 		} else {
29322a977b89SWenzhuo Lu 			nb_rxq = rte_port->dev_info.max_rx_queues;
29332a977b89SWenzhuo Lu 			nb_txq = rte_port->dev_info.max_tx_queues;
293486ef65eeSBernard Iremonger 		}
29352a977b89SWenzhuo Lu 	} else {
29362a977b89SWenzhuo Lu 		/*if vt is disabled, use all pf queues */
29372a977b89SWenzhuo Lu 		if (rte_port->dev_info.vmdq_pool_base == 0) {
29382a977b89SWenzhuo Lu 			nb_rxq = rte_port->dev_info.max_rx_queues;
29392a977b89SWenzhuo Lu 			nb_txq = rte_port->dev_info.max_tx_queues;
29402a977b89SWenzhuo Lu 		} else {
29412a977b89SWenzhuo Lu 			nb_rxq = (queueid_t)num_tcs;
29422a977b89SWenzhuo Lu 			nb_txq = (queueid_t)num_tcs;
29432a977b89SWenzhuo Lu 
29442a977b89SWenzhuo Lu 		}
29452a977b89SWenzhuo Lu 	}
29462a977b89SWenzhuo Lu 	rx_free_thresh = 64;
29472a977b89SWenzhuo Lu 
2948013af9b6SIntel 	memcpy(&rte_port->dev_conf, &port_conf, sizeof(struct rte_eth_conf));
2949013af9b6SIntel 
2950f2c5125aSPablo de Lara 	rxtx_port_config(rte_port);
2951013af9b6SIntel 	/* VLAN filter */
29520074d02fSShahaf Shuler 	rte_port->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
29531a572499SJingjing Wu 	for (i = 0; i < RTE_DIM(vlan_tags); i++)
2954013af9b6SIntel 		rx_vft_set(pid, vlan_tags[i], 1);
2955013af9b6SIntel 
2956013af9b6SIntel 	rte_eth_macaddr_get(pid, &rte_port->eth_addr);
2957013af9b6SIntel 	map_port_queue_stats_mapping_registers(pid, rte_port);
2958013af9b6SIntel 
29597741e4cfSIntel 	rte_port->dcb_flag = 1;
29607741e4cfSIntel 
2961013af9b6SIntel 	return 0;
2962af75078fSIntel }
2963af75078fSIntel 
2964ffc468ffSTetsuya Mukawa static void
2965ffc468ffSTetsuya Mukawa init_port(void)
2966ffc468ffSTetsuya Mukawa {
2967ffc468ffSTetsuya Mukawa 	/* Configuration of Ethernet ports. */
2968ffc468ffSTetsuya Mukawa 	ports = rte_zmalloc("testpmd: ports",
2969ffc468ffSTetsuya Mukawa 			    sizeof(struct rte_port) * RTE_MAX_ETHPORTS,
2970ffc468ffSTetsuya Mukawa 			    RTE_CACHE_LINE_SIZE);
2971ffc468ffSTetsuya Mukawa 	if (ports == NULL) {
2972ffc468ffSTetsuya Mukawa 		rte_exit(EXIT_FAILURE,
2973ffc468ffSTetsuya Mukawa 				"rte_zmalloc(%d struct rte_port) failed\n",
2974ffc468ffSTetsuya Mukawa 				RTE_MAX_ETHPORTS);
2975ffc468ffSTetsuya Mukawa 	}
297629841336SPhil Yang 
297729841336SPhil Yang 	/* Initialize ports NUMA structures */
297829841336SPhil Yang 	memset(port_numa, NUMA_NO_CONFIG, RTE_MAX_ETHPORTS);
297929841336SPhil Yang 	memset(rxring_numa, NUMA_NO_CONFIG, RTE_MAX_ETHPORTS);
298029841336SPhil Yang 	memset(txring_numa, NUMA_NO_CONFIG, RTE_MAX_ETHPORTS);
2981ffc468ffSTetsuya Mukawa }
2982ffc468ffSTetsuya Mukawa 
2983d3a274ceSZhihong Wang static void
2984d3a274ceSZhihong Wang force_quit(void)
2985d3a274ceSZhihong Wang {
2986d3a274ceSZhihong Wang 	pmd_test_exit();
2987d3a274ceSZhihong Wang 	prompt_exit();
2988d3a274ceSZhihong Wang }
2989d3a274ceSZhihong Wang 
2990d3a274ceSZhihong Wang static void
2991cfea1f30SPablo de Lara print_stats(void)
2992cfea1f30SPablo de Lara {
2993cfea1f30SPablo de Lara 	uint8_t i;
2994cfea1f30SPablo de Lara 	const char clr[] = { 27, '[', '2', 'J', '\0' };
2995cfea1f30SPablo de Lara 	const char top_left[] = { 27, '[', '1', ';', '1', 'H', '\0' };
2996cfea1f30SPablo de Lara 
2997cfea1f30SPablo de Lara 	/* Clear screen and move to top left */
2998cfea1f30SPablo de Lara 	printf("%s%s", clr, top_left);
2999cfea1f30SPablo de Lara 
3000cfea1f30SPablo de Lara 	printf("\nPort statistics ====================================");
3001cfea1f30SPablo de Lara 	for (i = 0; i < cur_fwd_config.nb_fwd_ports; i++)
3002cfea1f30SPablo de Lara 		nic_stats_display(fwd_ports_ids[i]);
3003cfea1f30SPablo de Lara }
3004cfea1f30SPablo de Lara 
3005cfea1f30SPablo de Lara static void
3006d3a274ceSZhihong Wang signal_handler(int signum)
3007d3a274ceSZhihong Wang {
3008d3a274ceSZhihong Wang 	if (signum == SIGINT || signum == SIGTERM) {
3009d3a274ceSZhihong Wang 		printf("\nSignal %d received, preparing to exit...\n",
3010d3a274ceSZhihong Wang 				signum);
3011102b7329SReshma Pattan #ifdef RTE_LIBRTE_PDUMP
3012102b7329SReshma Pattan 		/* uninitialize packet capture framework */
3013102b7329SReshma Pattan 		rte_pdump_uninit();
3014102b7329SReshma Pattan #endif
301562d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS
301662d3216dSReshma Pattan 		rte_latencystats_uninit();
301762d3216dSReshma Pattan #endif
3018d3a274ceSZhihong Wang 		force_quit();
3019d9a191a0SPhil Yang 		/* Set flag to indicate the force termination. */
3020d9a191a0SPhil Yang 		f_quit = 1;
3021d3a274ceSZhihong Wang 		/* exit with the expected status */
3022d3a274ceSZhihong Wang 		signal(signum, SIG_DFL);
3023d3a274ceSZhihong Wang 		kill(getpid(), signum);
3024d3a274ceSZhihong Wang 	}
3025d3a274ceSZhihong Wang }
3026d3a274ceSZhihong Wang 
3027af75078fSIntel int
3028af75078fSIntel main(int argc, char** argv)
3029af75078fSIntel {
3030af75078fSIntel 	int diag;
3031f8244c63SZhiyong Yang 	portid_t port_id;
30324918a357SXiaoyun Li 	uint16_t count;
3033fb73e096SJeff Guo 	int ret;
3034af75078fSIntel 
3035d3a274ceSZhihong Wang 	signal(SIGINT, signal_handler);
3036d3a274ceSZhihong Wang 	signal(SIGTERM, signal_handler);
3037d3a274ceSZhihong Wang 
3038af75078fSIntel 	diag = rte_eal_init(argc, argv);
3039af75078fSIntel 	if (diag < 0)
3040af75078fSIntel 		rte_panic("Cannot init EAL\n");
3041af75078fSIntel 
3042285fd101SOlivier Matz 	testpmd_logtype = rte_log_register("testpmd");
3043285fd101SOlivier Matz 	if (testpmd_logtype < 0)
3044285fd101SOlivier Matz 		rte_panic("Cannot register log type");
3045285fd101SOlivier Matz 	rte_log_set_level(testpmd_logtype, RTE_LOG_DEBUG);
3046285fd101SOlivier Matz 
30474aa0d012SAnatoly Burakov #ifdef RTE_LIBRTE_PDUMP
30484aa0d012SAnatoly Burakov 	/* initialize packet capture framework */
30494aa0d012SAnatoly Burakov 	rte_pdump_init(NULL);
30504aa0d012SAnatoly Burakov #endif
30514aa0d012SAnatoly Burakov 
30524918a357SXiaoyun Li 	count = 0;
30534918a357SXiaoyun Li 	RTE_ETH_FOREACH_DEV(port_id) {
30544918a357SXiaoyun Li 		ports_ids[count] = port_id;
30554918a357SXiaoyun Li 		count++;
30564918a357SXiaoyun Li 	}
30574918a357SXiaoyun Li 	nb_ports = (portid_t) count;
30584aa0d012SAnatoly Burakov 	if (nb_ports == 0)
30594aa0d012SAnatoly Burakov 		TESTPMD_LOG(WARNING, "No probed ethernet devices\n");
30604aa0d012SAnatoly Burakov 
30614aa0d012SAnatoly Burakov 	/* allocate port structures, and init them */
30624aa0d012SAnatoly Burakov 	init_port();
30634aa0d012SAnatoly Burakov 
30644aa0d012SAnatoly Burakov 	set_def_fwd_config();
30654aa0d012SAnatoly Burakov 	if (nb_lcores == 0)
30664aa0d012SAnatoly Burakov 		rte_panic("Empty set of forwarding logical cores - check the "
30674aa0d012SAnatoly Burakov 			  "core mask supplied in the command parameters\n");
30684aa0d012SAnatoly Burakov 
3069e505d84cSAnatoly Burakov 	/* Bitrate/latency stats disabled by default */
3070e505d84cSAnatoly Burakov #ifdef RTE_LIBRTE_BITRATE
3071e505d84cSAnatoly Burakov 	bitrate_enabled = 0;
3072e505d84cSAnatoly Burakov #endif
3073e505d84cSAnatoly Burakov #ifdef RTE_LIBRTE_LATENCY_STATS
3074e505d84cSAnatoly Burakov 	latencystats_enabled = 0;
3075e505d84cSAnatoly Burakov #endif
3076e505d84cSAnatoly Burakov 
3077fb7b8b32SAnatoly Burakov 	/* on FreeBSD, mlockall() is disabled by default */
3078fb7b8b32SAnatoly Burakov #ifdef RTE_EXEC_ENV_BSDAPP
3079fb7b8b32SAnatoly Burakov 	do_mlockall = 0;
3080fb7b8b32SAnatoly Burakov #else
3081fb7b8b32SAnatoly Burakov 	do_mlockall = 1;
3082fb7b8b32SAnatoly Burakov #endif
3083fb7b8b32SAnatoly Burakov 
3084e505d84cSAnatoly Burakov 	argc -= diag;
3085e505d84cSAnatoly Burakov 	argv += diag;
3086e505d84cSAnatoly Burakov 	if (argc > 1)
3087e505d84cSAnatoly Burakov 		launch_args_parse(argc, argv);
3088e505d84cSAnatoly Burakov 
3089e505d84cSAnatoly Burakov 	if (do_mlockall && mlockall(MCL_CURRENT | MCL_FUTURE)) {
3090285fd101SOlivier Matz 		TESTPMD_LOG(NOTICE, "mlockall() failed with error \"%s\"\n",
30911c036b16SEelco Chaudron 			strerror(errno));
30921c036b16SEelco Chaudron 	}
30931c036b16SEelco Chaudron 
309499cabef0SPablo de Lara 	if (tx_first && interactive)
309599cabef0SPablo de Lara 		rte_exit(EXIT_FAILURE, "--tx-first cannot be used on "
309699cabef0SPablo de Lara 				"interactive mode.\n");
30978820cba4SDavid Hunt 
30988820cba4SDavid Hunt 	if (tx_first && lsc_interrupt) {
30998820cba4SDavid Hunt 		printf("Warning: lsc_interrupt needs to be off when "
31008820cba4SDavid Hunt 				" using tx_first. Disabling.\n");
31018820cba4SDavid Hunt 		lsc_interrupt = 0;
31028820cba4SDavid Hunt 	}
31038820cba4SDavid Hunt 
31045a8fb55cSReshma Pattan 	if (!nb_rxq && !nb_txq)
31055a8fb55cSReshma Pattan 		printf("Warning: Either rx or tx queues should be non-zero\n");
31065a8fb55cSReshma Pattan 
31075a8fb55cSReshma Pattan 	if (nb_rxq > 1 && nb_rxq > nb_txq)
3108af75078fSIntel 		printf("Warning: nb_rxq=%d enables RSS configuration, "
3109af75078fSIntel 		       "but nb_txq=%d will prevent to fully test it.\n",
3110af75078fSIntel 		       nb_rxq, nb_txq);
3111af75078fSIntel 
3112af75078fSIntel 	init_config();
3113fb73e096SJeff Guo 
3114fb73e096SJeff Guo 	if (hot_plug) {
31152049c511SJeff Guo 		ret = rte_dev_hotplug_handle_enable();
3116fb73e096SJeff Guo 		if (ret) {
31172049c511SJeff Guo 			RTE_LOG(ERR, EAL,
31182049c511SJeff Guo 				"fail to enable hotplug handling.");
3119fb73e096SJeff Guo 			return -1;
3120fb73e096SJeff Guo 		}
3121fb73e096SJeff Guo 
31222049c511SJeff Guo 		ret = rte_dev_event_monitor_start();
31232049c511SJeff Guo 		if (ret) {
31242049c511SJeff Guo 			RTE_LOG(ERR, EAL,
31252049c511SJeff Guo 				"fail to start device event monitoring.");
31262049c511SJeff Guo 			return -1;
31272049c511SJeff Guo 		}
31282049c511SJeff Guo 
31292049c511SJeff Guo 		ret = rte_dev_event_callback_register(NULL,
31302049c511SJeff Guo 			eth_dev_event_callback, NULL);
31312049c511SJeff Guo 		if (ret) {
31322049c511SJeff Guo 			RTE_LOG(ERR, EAL,
31332049c511SJeff Guo 				"fail  to register device event callback\n");
31342049c511SJeff Guo 			return -1;
31352049c511SJeff Guo 		}
3136fb73e096SJeff Guo 	}
3137fb73e096SJeff Guo 
3138148f963fSBruce Richardson 	if (start_port(RTE_PORT_ALL) != 0)
3139148f963fSBruce Richardson 		rte_exit(EXIT_FAILURE, "Start ports failed\n");
3140af75078fSIntel 
3141ce8d5614SIntel 	/* set all ports to promiscuous mode by default */
31427d89b261SGaetan Rivet 	RTE_ETH_FOREACH_DEV(port_id)
3143ce8d5614SIntel 		rte_eth_promiscuous_enable(port_id);
3144af75078fSIntel 
31457e4441c8SRemy Horton 	/* Init metrics library */
31467e4441c8SRemy Horton 	rte_metrics_init(rte_socket_id());
31477e4441c8SRemy Horton 
314862d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS
314962d3216dSReshma Pattan 	if (latencystats_enabled != 0) {
315062d3216dSReshma Pattan 		int ret = rte_latencystats_init(1, NULL);
315162d3216dSReshma Pattan 		if (ret)
315262d3216dSReshma Pattan 			printf("Warning: latencystats init()"
315362d3216dSReshma Pattan 				" returned error %d\n",	ret);
315462d3216dSReshma Pattan 		printf("Latencystats running on lcore %d\n",
315562d3216dSReshma Pattan 			latencystats_lcore_id);
315662d3216dSReshma Pattan 	}
315762d3216dSReshma Pattan #endif
315862d3216dSReshma Pattan 
31597e4441c8SRemy Horton 	/* Setup bitrate stats */
31607e4441c8SRemy Horton #ifdef RTE_LIBRTE_BITRATE
3161e25e6c70SRemy Horton 	if (bitrate_enabled != 0) {
31627e4441c8SRemy Horton 		bitrate_data = rte_stats_bitrate_create();
31637e4441c8SRemy Horton 		if (bitrate_data == NULL)
3164e25e6c70SRemy Horton 			rte_exit(EXIT_FAILURE,
3165e25e6c70SRemy Horton 				"Could not allocate bitrate data.\n");
31667e4441c8SRemy Horton 		rte_stats_bitrate_reg(bitrate_data);
3167e25e6c70SRemy Horton 	}
31687e4441c8SRemy Horton #endif
31697e4441c8SRemy Horton 
31700d56cb81SThomas Monjalon #ifdef RTE_LIBRTE_CMDLINE
317181ef862bSAllain Legacy 	if (strlen(cmdline_filename) != 0)
317281ef862bSAllain Legacy 		cmdline_read_from_file(cmdline_filename);
317381ef862bSAllain Legacy 
3174ca7feb22SCyril Chemparathy 	if (interactive == 1) {
3175ca7feb22SCyril Chemparathy 		if (auto_start) {
3176ca7feb22SCyril Chemparathy 			printf("Start automatic packet forwarding\n");
3177ca7feb22SCyril Chemparathy 			start_packet_forwarding(0);
3178ca7feb22SCyril Chemparathy 		}
3179af75078fSIntel 		prompt();
31800de738cfSJiayu Hu 		pmd_test_exit();
3181ca7feb22SCyril Chemparathy 	} else
31820d56cb81SThomas Monjalon #endif
31830d56cb81SThomas Monjalon 	{
3184af75078fSIntel 		char c;
3185af75078fSIntel 		int rc;
3186af75078fSIntel 
3187d9a191a0SPhil Yang 		f_quit = 0;
3188d9a191a0SPhil Yang 
3189af75078fSIntel 		printf("No commandline core given, start packet forwarding\n");
319099cabef0SPablo de Lara 		start_packet_forwarding(tx_first);
3191cfea1f30SPablo de Lara 		if (stats_period != 0) {
3192cfea1f30SPablo de Lara 			uint64_t prev_time = 0, cur_time, diff_time = 0;
3193cfea1f30SPablo de Lara 			uint64_t timer_period;
3194cfea1f30SPablo de Lara 
3195cfea1f30SPablo de Lara 			/* Convert to number of cycles */
3196cfea1f30SPablo de Lara 			timer_period = stats_period * rte_get_timer_hz();
3197cfea1f30SPablo de Lara 
3198d9a191a0SPhil Yang 			while (f_quit == 0) {
3199cfea1f30SPablo de Lara 				cur_time = rte_get_timer_cycles();
3200cfea1f30SPablo de Lara 				diff_time += cur_time - prev_time;
3201cfea1f30SPablo de Lara 
3202cfea1f30SPablo de Lara 				if (diff_time >= timer_period) {
3203cfea1f30SPablo de Lara 					print_stats();
3204cfea1f30SPablo de Lara 					/* Reset the timer */
3205cfea1f30SPablo de Lara 					diff_time = 0;
3206cfea1f30SPablo de Lara 				}
3207cfea1f30SPablo de Lara 				/* Sleep to avoid unnecessary checks */
3208cfea1f30SPablo de Lara 				prev_time = cur_time;
3209cfea1f30SPablo de Lara 				sleep(1);
3210cfea1f30SPablo de Lara 			}
3211cfea1f30SPablo de Lara 		}
3212cfea1f30SPablo de Lara 
3213af75078fSIntel 		printf("Press enter to exit\n");
3214af75078fSIntel 		rc = read(0, &c, 1);
3215d3a274ceSZhihong Wang 		pmd_test_exit();
3216af75078fSIntel 		if (rc < 0)
3217af75078fSIntel 			return 1;
3218af75078fSIntel 	}
3219af75078fSIntel 
3220af75078fSIntel 	return 0;
3221af75078fSIntel }
3222