1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stdio.h> 35 #include <stdlib.h> 36 #include <stdint.h> 37 38 #include <rte_log.h> 39 #include <rte_port_ring.h> 40 #include <rte_table_stub.h> 41 #include <rte_pipeline.h> 42 43 #include "main.h" 44 45 void 46 app_main_loop_worker_pipeline_stub(void) { 47 struct rte_pipeline_params pipeline_params = { 48 .name = "pipeline", 49 .socket_id = rte_socket_id(), 50 }; 51 52 struct rte_pipeline *p; 53 uint32_t port_in_id[APP_MAX_PORTS]; 54 uint32_t port_out_id[APP_MAX_PORTS]; 55 uint32_t table_id[APP_MAX_PORTS]; 56 uint32_t i; 57 58 RTE_LOG(INFO, USER1, "Core %u is doing work (pipeline with stub " 59 "tables)\n", rte_lcore_id()); 60 61 /* Pipeline configuration */ 62 p = rte_pipeline_create(&pipeline_params); 63 if (p == NULL) 64 rte_panic("Unable to configure the pipeline\n"); 65 66 /* Input port configuration */ 67 for (i = 0; i < app.n_ports; i++) { 68 struct rte_port_ring_reader_params port_ring_params = { 69 .ring = app.rings_rx[i], 70 }; 71 72 struct rte_pipeline_port_in_params port_params = { 73 .ops = &rte_port_ring_reader_ops, 74 .arg_create = (void *) &port_ring_params, 75 .f_action = NULL, 76 .arg_ah = NULL, 77 .burst_size = app.burst_size_worker_read, 78 }; 79 80 if (rte_pipeline_port_in_create(p, &port_params, 81 &port_in_id[i])) 82 rte_panic("Unable to configure input port for " 83 "ring %d\n", i); 84 } 85 86 /* Output port configuration */ 87 for (i = 0; i < app.n_ports; i++) { 88 struct rte_port_ring_writer_params port_ring_params = { 89 .ring = app.rings_tx[i], 90 .tx_burst_sz = app.burst_size_worker_write, 91 }; 92 93 struct rte_pipeline_port_out_params port_params = { 94 .ops = &rte_port_ring_writer_ops, 95 .arg_create = (void *) &port_ring_params, 96 .f_action = NULL, 97 .arg_ah = NULL, 98 }; 99 100 if (rte_pipeline_port_out_create(p, &port_params, 101 &port_out_id[i])) 102 rte_panic("Unable to configure output port for " 103 "ring %d\n", i); 104 } 105 106 /* Table configuration */ 107 for (i = 0; i < app.n_ports; i++) { 108 struct rte_pipeline_table_params table_params = { 109 .ops = &rte_table_stub_ops, 110 .arg_create = NULL, 111 .f_action_hit = NULL, 112 .f_action_miss = NULL, 113 .arg_ah = NULL, 114 .action_data_size = 0, 115 }; 116 117 if (rte_pipeline_table_create(p, &table_params, &table_id[i])) 118 rte_panic("Unable to configure table %u\n", i); 119 } 120 121 /* Interconnecting ports and tables */ 122 for (i = 0; i < app.n_ports; i++) 123 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i], 124 table_id[i])) 125 rte_panic("Unable to connect input port %u to " 126 "table %u\n", port_in_id[i], table_id[i]); 127 128 /* Add entries to tables */ 129 for (i = 0; i < app.n_ports; i++) { 130 struct rte_pipeline_table_entry entry = { 131 .action = RTE_PIPELINE_ACTION_PORT, 132 {.port_id = port_out_id[i ^ 1]}, 133 }; 134 struct rte_pipeline_table_entry *default_entry_ptr; 135 136 if (rte_pipeline_table_default_entry_add(p, table_id[i], &entry, 137 &default_entry_ptr)) 138 rte_panic("Unable to add default entry to table %u\n", 139 table_id[i]); 140 } 141 142 /* Enable input ports */ 143 for (i = 0; i < app.n_ports; i++) 144 if (rte_pipeline_port_in_enable(p, port_in_id[i])) 145 rte_panic("Unable to enable input port %u\n", 146 port_in_id[i]); 147 148 /* Check pipeline consistency */ 149 if (rte_pipeline_check(p) < 0) 150 rte_panic("Pipeline consistency check failed\n"); 151 152 /* Run-time */ 153 #if APP_FLUSH == 0 154 for ( ; ; ) 155 rte_pipeline_run(p); 156 #else 157 for (i = 0; ; i++) { 158 rte_pipeline_run(p); 159 160 if ((i & APP_FLUSH) == 0) 161 rte_pipeline_flush(p); 162 } 163 #endif 164 } 165