1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stdio.h> 35 #include <stdlib.h> 36 #include <stdint.h> 37 38 #include <rte_log.h> 39 #include <rte_ethdev.h> 40 #include <rte_ether.h> 41 #include <rte_ip.h> 42 #include <rte_byteorder.h> 43 44 #include <rte_port_ring.h> 45 #include <rte_table_lpm.h> 46 #include <rte_pipeline.h> 47 48 #include "main.h" 49 50 void 51 app_main_loop_worker_pipeline_lpm(void) { 52 struct rte_pipeline_params pipeline_params = { 53 .name = "pipeline", 54 .socket_id = rte_socket_id(), 55 }; 56 57 struct rte_pipeline *p; 58 uint32_t port_in_id[APP_MAX_PORTS]; 59 uint32_t port_out_id[APP_MAX_PORTS]; 60 uint32_t table_id; 61 uint32_t i; 62 63 RTE_LOG(INFO, USER1, "Core %u is doing work (pipeline with " 64 "LPM table)\n", rte_lcore_id()); 65 66 /* Pipeline configuration */ 67 p = rte_pipeline_create(&pipeline_params); 68 if (p == NULL) 69 rte_panic("Unable to configure the pipeline\n"); 70 71 /* Input port configuration */ 72 for (i = 0; i < app.n_ports; i++) { 73 struct rte_port_ring_reader_params port_ring_params = { 74 .ring = app.rings_rx[i], 75 }; 76 77 struct rte_pipeline_port_in_params port_params = { 78 .ops = &rte_port_ring_reader_ops, 79 .arg_create = (void *) &port_ring_params, 80 .f_action = NULL, 81 .arg_ah = NULL, 82 .burst_size = app.burst_size_worker_read, 83 }; 84 85 if (rte_pipeline_port_in_create(p, &port_params, 86 &port_in_id[i])) 87 rte_panic("Unable to configure input port for " 88 "ring %d\n", i); 89 } 90 91 /* Output port configuration */ 92 for (i = 0; i < app.n_ports; i++) { 93 struct rte_port_ring_writer_params port_ring_params = { 94 .ring = app.rings_tx[i], 95 .tx_burst_sz = app.burst_size_worker_write, 96 }; 97 98 struct rte_pipeline_port_out_params port_params = { 99 .ops = &rte_port_ring_writer_ops, 100 .arg_create = (void *) &port_ring_params, 101 .f_action = NULL, 102 .f_action_bulk = NULL, 103 .arg_ah = NULL, 104 }; 105 106 if (rte_pipeline_port_out_create(p, &port_params, 107 &port_out_id[i])) 108 rte_panic("Unable to configure output port for " 109 "ring %d\n", i); 110 } 111 112 /* Table configuration */ 113 { 114 struct rte_table_lpm_params table_lpm_params = { 115 .n_rules = 1 << 24, 116 .entry_unique_size = 117 sizeof(struct rte_pipeline_table_entry), 118 .offset = 32, 119 }; 120 121 struct rte_pipeline_table_params table_params = { 122 .ops = &rte_table_lpm_ops, 123 .arg_create = &table_lpm_params, 124 .f_action_hit = NULL, 125 .f_action_miss = NULL, 126 .arg_ah = NULL, 127 .action_data_size = 0, 128 }; 129 130 if (rte_pipeline_table_create(p, &table_params, &table_id)) 131 rte_panic("Unable to configure the LPM table\n"); 132 } 133 134 /* Interconnecting ports and tables */ 135 for (i = 0; i < app.n_ports; i++) 136 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i], 137 table_id)) 138 rte_panic("Unable to connect input port %u to " 139 "table %u\n", port_in_id[i], table_id); 140 141 /* Add entries to tables */ 142 for (i = 0; i < app.n_ports; i++) { 143 struct rte_pipeline_table_entry entry = { 144 .action = RTE_PIPELINE_ACTION_PORT, 145 {.port_id = port_out_id[i & (app.n_ports - 1)]}, 146 }; 147 148 struct rte_table_lpm_key key = { 149 .ip = i << (24 - __builtin_popcount(app.n_ports - 1)), 150 .depth = 8 + __builtin_popcount(app.n_ports - 1), 151 }; 152 153 struct rte_pipeline_table_entry *entry_ptr; 154 155 int key_found, status; 156 157 printf("Adding rule to LPM table (IPv4 destination = %" 158 PRIu32 ".%" PRIu32 ".%" PRIu32 ".%" PRIu32 "/%" PRIu8 159 " => port out = %" PRIu32 ")\n", 160 (key.ip & 0xFF000000) >> 24, 161 (key.ip & 0x00FF0000) >> 16, 162 (key.ip & 0x0000FF00) >> 8, 163 key.ip & 0x000000FF, 164 key.depth, 165 i); 166 167 status = rte_pipeline_table_entry_add(p, table_id, &key, &entry, 168 &key_found, &entry_ptr); 169 if (status < 0) 170 rte_panic("Unable to add entry to table %u (%d)\n", 171 table_id, status); 172 } 173 174 /* Enable input ports */ 175 for (i = 0; i < app.n_ports; i++) 176 if (rte_pipeline_port_in_enable(p, port_in_id[i])) 177 rte_panic("Unable to enable input port %u\n", 178 port_in_id[i]); 179 180 /* Check pipeline consistency */ 181 if (rte_pipeline_check(p) < 0) 182 rte_panic("Pipeline consistency check failed\n"); 183 184 /* Run-time */ 185 #if APP_FLUSH == 0 186 for ( ; ; ) 187 rte_pipeline_run(p); 188 #else 189 for (i = 0; ; i++) { 190 rte_pipeline_run(p); 191 192 if ((i & APP_FLUSH) == 0) 193 rte_pipeline_flush(p); 194 } 195 #endif 196 } 197