1d60b4185SPavan Nikhilesh /* 2d60b4185SPavan Nikhilesh * SPDX-License-Identifier: BSD-3-Clause 3d60b4185SPavan Nikhilesh * Copyright 2017 Cavium, Inc. 4d60b4185SPavan Nikhilesh */ 5d60b4185SPavan Nikhilesh 6d60b4185SPavan Nikhilesh #include "test_pipeline_common.h" 7d60b4185SPavan Nikhilesh 8d60b4185SPavan Nikhilesh /* See http://dpdk.org/doc/guides/tools/testeventdev.html for test details */ 9d60b4185SPavan Nikhilesh 10d60b4185SPavan Nikhilesh static __rte_always_inline int 11d60b4185SPavan Nikhilesh pipeline_queue_nb_event_queues(struct evt_options *opt) 12d60b4185SPavan Nikhilesh { 13*d9a42a69SThomas Monjalon uint16_t eth_count = rte_eth_dev_count_avail(); 14d60b4185SPavan Nikhilesh 15d60b4185SPavan Nikhilesh return (eth_count * opt->nb_stages) + eth_count; 16d60b4185SPavan Nikhilesh } 17d60b4185SPavan Nikhilesh 18d60b4185SPavan Nikhilesh static int 19314bcf58SPavan Nikhilesh pipeline_queue_worker_single_stage_tx(void *arg) 20314bcf58SPavan Nikhilesh { 21314bcf58SPavan Nikhilesh PIPELINE_WROKER_SINGLE_STAGE_INIT; 22314bcf58SPavan Nikhilesh 23314bcf58SPavan Nikhilesh while (t->done == false) { 24314bcf58SPavan Nikhilesh uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0); 25314bcf58SPavan Nikhilesh 26314bcf58SPavan Nikhilesh if (!event) { 27314bcf58SPavan Nikhilesh rte_pause(); 28314bcf58SPavan Nikhilesh continue; 29314bcf58SPavan Nikhilesh } 30314bcf58SPavan Nikhilesh 31314bcf58SPavan Nikhilesh if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 32314bcf58SPavan Nikhilesh pipeline_tx_pkt(ev.mbuf); 33314bcf58SPavan Nikhilesh w->processed_pkts++; 34314bcf58SPavan Nikhilesh } else { 35314bcf58SPavan Nikhilesh ev.queue_id++; 36314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC); 37314bcf58SPavan Nikhilesh pipeline_event_enqueue(dev, port, &ev); 38314bcf58SPavan Nikhilesh } 39314bcf58SPavan Nikhilesh } 40314bcf58SPavan Nikhilesh 41314bcf58SPavan Nikhilesh return 0; 42314bcf58SPavan Nikhilesh } 43314bcf58SPavan Nikhilesh 44314bcf58SPavan Nikhilesh static int 45314bcf58SPavan Nikhilesh pipeline_queue_worker_single_stage_fwd(void *arg) 46314bcf58SPavan Nikhilesh { 47314bcf58SPavan Nikhilesh PIPELINE_WROKER_SINGLE_STAGE_INIT; 48314bcf58SPavan Nikhilesh const uint8_t tx_queue = t->tx_service.queue_id; 49314bcf58SPavan Nikhilesh 50314bcf58SPavan Nikhilesh while (t->done == false) { 51314bcf58SPavan Nikhilesh uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0); 52314bcf58SPavan Nikhilesh 53314bcf58SPavan Nikhilesh if (!event) { 54314bcf58SPavan Nikhilesh rte_pause(); 55314bcf58SPavan Nikhilesh continue; 56314bcf58SPavan Nikhilesh } 57314bcf58SPavan Nikhilesh 58314bcf58SPavan Nikhilesh ev.queue_id = tx_queue; 59314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC); 60314bcf58SPavan Nikhilesh pipeline_event_enqueue(dev, port, &ev); 61314bcf58SPavan Nikhilesh w->processed_pkts++; 62314bcf58SPavan Nikhilesh } 63314bcf58SPavan Nikhilesh 64314bcf58SPavan Nikhilesh return 0; 65314bcf58SPavan Nikhilesh } 66314bcf58SPavan Nikhilesh 67314bcf58SPavan Nikhilesh static int 68314bcf58SPavan Nikhilesh pipeline_queue_worker_single_stage_burst_tx(void *arg) 69314bcf58SPavan Nikhilesh { 70314bcf58SPavan Nikhilesh PIPELINE_WROKER_SINGLE_STAGE_BURST_INIT; 71314bcf58SPavan Nikhilesh 72314bcf58SPavan Nikhilesh while (t->done == false) { 73314bcf58SPavan Nikhilesh uint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev, 74314bcf58SPavan Nikhilesh BURST_SIZE, 0); 75314bcf58SPavan Nikhilesh 76314bcf58SPavan Nikhilesh if (!nb_rx) { 77314bcf58SPavan Nikhilesh rte_pause(); 78314bcf58SPavan Nikhilesh continue; 79314bcf58SPavan Nikhilesh } 80314bcf58SPavan Nikhilesh 81314bcf58SPavan Nikhilesh for (i = 0; i < nb_rx; i++) { 82314bcf58SPavan Nikhilesh rte_prefetch0(ev[i + 1].mbuf); 83314bcf58SPavan Nikhilesh if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) { 84314bcf58SPavan Nikhilesh 85314bcf58SPavan Nikhilesh pipeline_tx_pkt(ev[i].mbuf); 86314bcf58SPavan Nikhilesh ev[i].op = RTE_EVENT_OP_RELEASE; 87314bcf58SPavan Nikhilesh w->processed_pkts++; 88314bcf58SPavan Nikhilesh } else { 89314bcf58SPavan Nikhilesh ev[i].queue_id++; 90314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev[i], 91314bcf58SPavan Nikhilesh RTE_SCHED_TYPE_ATOMIC); 92314bcf58SPavan Nikhilesh } 93314bcf58SPavan Nikhilesh } 94314bcf58SPavan Nikhilesh 95314bcf58SPavan Nikhilesh pipeline_event_enqueue_burst(dev, port, ev, nb_rx); 96314bcf58SPavan Nikhilesh } 97314bcf58SPavan Nikhilesh 98314bcf58SPavan Nikhilesh return 0; 99314bcf58SPavan Nikhilesh } 100314bcf58SPavan Nikhilesh 101314bcf58SPavan Nikhilesh static int 102314bcf58SPavan Nikhilesh pipeline_queue_worker_single_stage_burst_fwd(void *arg) 103314bcf58SPavan Nikhilesh { 104314bcf58SPavan Nikhilesh PIPELINE_WROKER_SINGLE_STAGE_BURST_INIT; 105314bcf58SPavan Nikhilesh const uint8_t tx_queue = t->tx_service.queue_id; 106314bcf58SPavan Nikhilesh 107314bcf58SPavan Nikhilesh while (t->done == false) { 108314bcf58SPavan Nikhilesh uint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev, 109314bcf58SPavan Nikhilesh BURST_SIZE, 0); 110314bcf58SPavan Nikhilesh 111314bcf58SPavan Nikhilesh if (!nb_rx) { 112314bcf58SPavan Nikhilesh rte_pause(); 113314bcf58SPavan Nikhilesh continue; 114314bcf58SPavan Nikhilesh } 115314bcf58SPavan Nikhilesh 116314bcf58SPavan Nikhilesh for (i = 0; i < nb_rx; i++) { 117314bcf58SPavan Nikhilesh rte_prefetch0(ev[i + 1].mbuf); 118314bcf58SPavan Nikhilesh ev[i].queue_id = tx_queue; 119314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC); 120314bcf58SPavan Nikhilesh w->processed_pkts++; 121314bcf58SPavan Nikhilesh } 122314bcf58SPavan Nikhilesh 123314bcf58SPavan Nikhilesh pipeline_event_enqueue_burst(dev, port, ev, nb_rx); 124314bcf58SPavan Nikhilesh } 125314bcf58SPavan Nikhilesh 126314bcf58SPavan Nikhilesh return 0; 127314bcf58SPavan Nikhilesh } 128314bcf58SPavan Nikhilesh 129314bcf58SPavan Nikhilesh 130314bcf58SPavan Nikhilesh static int 131314bcf58SPavan Nikhilesh pipeline_queue_worker_multi_stage_tx(void *arg) 132314bcf58SPavan Nikhilesh { 133314bcf58SPavan Nikhilesh PIPELINE_WROKER_MULTI_STAGE_INIT; 134314bcf58SPavan Nikhilesh const uint8_t nb_stages = t->opt->nb_stages + 1; 135314bcf58SPavan Nikhilesh 136314bcf58SPavan Nikhilesh while (t->done == false) { 137314bcf58SPavan Nikhilesh uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0); 138314bcf58SPavan Nikhilesh 139314bcf58SPavan Nikhilesh if (!event) { 140314bcf58SPavan Nikhilesh rte_pause(); 141314bcf58SPavan Nikhilesh continue; 142314bcf58SPavan Nikhilesh } 143314bcf58SPavan Nikhilesh 144314bcf58SPavan Nikhilesh cq_id = ev.queue_id % nb_stages; 145314bcf58SPavan Nikhilesh 146314bcf58SPavan Nikhilesh if (cq_id >= last_queue) { 147314bcf58SPavan Nikhilesh if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 148314bcf58SPavan Nikhilesh 149314bcf58SPavan Nikhilesh pipeline_tx_pkt(ev.mbuf); 150314bcf58SPavan Nikhilesh w->processed_pkts++; 151314bcf58SPavan Nikhilesh continue; 152314bcf58SPavan Nikhilesh } 153314bcf58SPavan Nikhilesh ev.queue_id += (cq_id == last_queue) ? 1 : 0; 154314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC); 155314bcf58SPavan Nikhilesh } else { 156314bcf58SPavan Nikhilesh ev.queue_id++; 157314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev, sched_type_list[cq_id]); 158314bcf58SPavan Nikhilesh } 159314bcf58SPavan Nikhilesh 160314bcf58SPavan Nikhilesh pipeline_event_enqueue(dev, port, &ev); 161314bcf58SPavan Nikhilesh } 162314bcf58SPavan Nikhilesh return 0; 163314bcf58SPavan Nikhilesh } 164314bcf58SPavan Nikhilesh 165314bcf58SPavan Nikhilesh static int 166314bcf58SPavan Nikhilesh pipeline_queue_worker_multi_stage_fwd(void *arg) 167314bcf58SPavan Nikhilesh { 168314bcf58SPavan Nikhilesh PIPELINE_WROKER_MULTI_STAGE_INIT; 169314bcf58SPavan Nikhilesh const uint8_t nb_stages = t->opt->nb_stages + 1; 170314bcf58SPavan Nikhilesh const uint8_t tx_queue = t->tx_service.queue_id; 171314bcf58SPavan Nikhilesh 172314bcf58SPavan Nikhilesh while (t->done == false) { 173314bcf58SPavan Nikhilesh uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0); 174314bcf58SPavan Nikhilesh 175314bcf58SPavan Nikhilesh if (!event) { 176314bcf58SPavan Nikhilesh rte_pause(); 177314bcf58SPavan Nikhilesh continue; 178314bcf58SPavan Nikhilesh } 179314bcf58SPavan Nikhilesh 180314bcf58SPavan Nikhilesh cq_id = ev.queue_id % nb_stages; 181314bcf58SPavan Nikhilesh 182314bcf58SPavan Nikhilesh if (cq_id == last_queue) { 183314bcf58SPavan Nikhilesh ev.queue_id = tx_queue; 184314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC); 185314bcf58SPavan Nikhilesh w->processed_pkts++; 186314bcf58SPavan Nikhilesh } else { 187314bcf58SPavan Nikhilesh ev.queue_id++; 188314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev, sched_type_list[cq_id]); 189314bcf58SPavan Nikhilesh } 190314bcf58SPavan Nikhilesh 191314bcf58SPavan Nikhilesh pipeline_event_enqueue(dev, port, &ev); 192314bcf58SPavan Nikhilesh } 193314bcf58SPavan Nikhilesh return 0; 194314bcf58SPavan Nikhilesh } 195314bcf58SPavan Nikhilesh 196314bcf58SPavan Nikhilesh static int 197314bcf58SPavan Nikhilesh pipeline_queue_worker_multi_stage_burst_tx(void *arg) 198314bcf58SPavan Nikhilesh { 199314bcf58SPavan Nikhilesh PIPELINE_WROKER_MULTI_STAGE_BURST_INIT; 200314bcf58SPavan Nikhilesh const uint8_t nb_stages = t->opt->nb_stages + 1; 201314bcf58SPavan Nikhilesh 202314bcf58SPavan Nikhilesh while (t->done == false) { 203314bcf58SPavan Nikhilesh uint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev, 204314bcf58SPavan Nikhilesh BURST_SIZE, 0); 205314bcf58SPavan Nikhilesh 206314bcf58SPavan Nikhilesh if (!nb_rx) { 207314bcf58SPavan Nikhilesh rte_pause(); 208314bcf58SPavan Nikhilesh continue; 209314bcf58SPavan Nikhilesh } 210314bcf58SPavan Nikhilesh 211314bcf58SPavan Nikhilesh for (i = 0; i < nb_rx; i++) { 212314bcf58SPavan Nikhilesh rte_prefetch0(ev[i + 1].mbuf); 213314bcf58SPavan Nikhilesh cq_id = ev[i].queue_id % nb_stages; 214314bcf58SPavan Nikhilesh 215314bcf58SPavan Nikhilesh if (cq_id >= last_queue) { 216314bcf58SPavan Nikhilesh if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) { 217314bcf58SPavan Nikhilesh 218314bcf58SPavan Nikhilesh pipeline_tx_pkt(ev[i].mbuf); 219314bcf58SPavan Nikhilesh ev[i].op = RTE_EVENT_OP_RELEASE; 220314bcf58SPavan Nikhilesh w->processed_pkts++; 221314bcf58SPavan Nikhilesh continue; 222314bcf58SPavan Nikhilesh } 223314bcf58SPavan Nikhilesh 224314bcf58SPavan Nikhilesh ev[i].queue_id += (cq_id == last_queue) ? 1 : 0; 225314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev[i], 226314bcf58SPavan Nikhilesh RTE_SCHED_TYPE_ATOMIC); 227314bcf58SPavan Nikhilesh } else { 228314bcf58SPavan Nikhilesh ev[i].queue_id++; 229314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev[i], 230314bcf58SPavan Nikhilesh sched_type_list[cq_id]); 231314bcf58SPavan Nikhilesh } 232314bcf58SPavan Nikhilesh 233314bcf58SPavan Nikhilesh } 234314bcf58SPavan Nikhilesh 235314bcf58SPavan Nikhilesh pipeline_event_enqueue_burst(dev, port, ev, nb_rx); 236314bcf58SPavan Nikhilesh } 237314bcf58SPavan Nikhilesh return 0; 238314bcf58SPavan Nikhilesh } 239314bcf58SPavan Nikhilesh 240314bcf58SPavan Nikhilesh static int 241314bcf58SPavan Nikhilesh pipeline_queue_worker_multi_stage_burst_fwd(void *arg) 242314bcf58SPavan Nikhilesh { 243314bcf58SPavan Nikhilesh PIPELINE_WROKER_MULTI_STAGE_BURST_INIT; 244314bcf58SPavan Nikhilesh const uint8_t nb_stages = t->opt->nb_stages + 1; 245314bcf58SPavan Nikhilesh const uint8_t tx_queue = t->tx_service.queue_id; 246314bcf58SPavan Nikhilesh 247314bcf58SPavan Nikhilesh while (t->done == false) { 248314bcf58SPavan Nikhilesh uint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev, 249314bcf58SPavan Nikhilesh BURST_SIZE, 0); 250314bcf58SPavan Nikhilesh 251314bcf58SPavan Nikhilesh if (!nb_rx) { 252314bcf58SPavan Nikhilesh rte_pause(); 253314bcf58SPavan Nikhilesh continue; 254314bcf58SPavan Nikhilesh } 255314bcf58SPavan Nikhilesh 256314bcf58SPavan Nikhilesh for (i = 0; i < nb_rx; i++) { 257314bcf58SPavan Nikhilesh rte_prefetch0(ev[i + 1].mbuf); 258314bcf58SPavan Nikhilesh cq_id = ev[i].queue_id % nb_stages; 259314bcf58SPavan Nikhilesh 260314bcf58SPavan Nikhilesh if (cq_id == last_queue) { 261314bcf58SPavan Nikhilesh ev[i].queue_id = tx_queue; 262314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev[i], 263314bcf58SPavan Nikhilesh RTE_SCHED_TYPE_ATOMIC); 264314bcf58SPavan Nikhilesh w->processed_pkts++; 265314bcf58SPavan Nikhilesh } else { 266314bcf58SPavan Nikhilesh ev[i].queue_id++; 267314bcf58SPavan Nikhilesh pipeline_fwd_event(&ev[i], 268314bcf58SPavan Nikhilesh sched_type_list[cq_id]); 269314bcf58SPavan Nikhilesh } 270314bcf58SPavan Nikhilesh } 271314bcf58SPavan Nikhilesh 272314bcf58SPavan Nikhilesh pipeline_event_enqueue_burst(dev, port, ev, nb_rx); 273314bcf58SPavan Nikhilesh } 274314bcf58SPavan Nikhilesh return 0; 275314bcf58SPavan Nikhilesh } 276314bcf58SPavan Nikhilesh 277314bcf58SPavan Nikhilesh static int 278d60b4185SPavan Nikhilesh worker_wrapper(void *arg) 279d60b4185SPavan Nikhilesh { 280314bcf58SPavan Nikhilesh struct worker_data *w = arg; 281314bcf58SPavan Nikhilesh struct evt_options *opt = w->t->opt; 282314bcf58SPavan Nikhilesh const bool burst = evt_has_burst_mode(w->dev_id); 283314bcf58SPavan Nikhilesh const bool mt_safe = !w->t->mt_unsafe; 284314bcf58SPavan Nikhilesh const uint8_t nb_stages = opt->nb_stages; 285314bcf58SPavan Nikhilesh RTE_SET_USED(opt); 286314bcf58SPavan Nikhilesh 287314bcf58SPavan Nikhilesh if (nb_stages == 1) { 288314bcf58SPavan Nikhilesh if (!burst && mt_safe) 289314bcf58SPavan Nikhilesh return pipeline_queue_worker_single_stage_tx(arg); 290314bcf58SPavan Nikhilesh else if (!burst && !mt_safe) 291314bcf58SPavan Nikhilesh return pipeline_queue_worker_single_stage_fwd(arg); 292314bcf58SPavan Nikhilesh else if (burst && mt_safe) 293314bcf58SPavan Nikhilesh return pipeline_queue_worker_single_stage_burst_tx(arg); 294314bcf58SPavan Nikhilesh else if (burst && !mt_safe) 295314bcf58SPavan Nikhilesh return pipeline_queue_worker_single_stage_burst_fwd( 296314bcf58SPavan Nikhilesh arg); 297314bcf58SPavan Nikhilesh } else { 298314bcf58SPavan Nikhilesh if (!burst && mt_safe) 299314bcf58SPavan Nikhilesh return pipeline_queue_worker_multi_stage_tx(arg); 300314bcf58SPavan Nikhilesh else if (!burst && !mt_safe) 301314bcf58SPavan Nikhilesh return pipeline_queue_worker_multi_stage_fwd(arg); 302314bcf58SPavan Nikhilesh else if (burst && mt_safe) 303314bcf58SPavan Nikhilesh return pipeline_queue_worker_multi_stage_burst_tx(arg); 304314bcf58SPavan Nikhilesh else if (burst && !mt_safe) 305314bcf58SPavan Nikhilesh return pipeline_queue_worker_multi_stage_burst_fwd(arg); 306314bcf58SPavan Nikhilesh 307314bcf58SPavan Nikhilesh } 308d60b4185SPavan Nikhilesh rte_panic("invalid worker\n"); 309d60b4185SPavan Nikhilesh } 310d60b4185SPavan Nikhilesh 311d60b4185SPavan Nikhilesh static int 312d60b4185SPavan Nikhilesh pipeline_queue_launch_lcores(struct evt_test *test, struct evt_options *opt) 313d60b4185SPavan Nikhilesh { 314d60b4185SPavan Nikhilesh struct test_pipeline *t = evt_test_priv(test); 315d60b4185SPavan Nikhilesh 316d60b4185SPavan Nikhilesh if (t->mt_unsafe) 317d60b4185SPavan Nikhilesh rte_service_component_runstate_set(t->tx_service.service_id, 1); 318d60b4185SPavan Nikhilesh return pipeline_launch_lcores(test, opt, worker_wrapper); 319d60b4185SPavan Nikhilesh } 320d60b4185SPavan Nikhilesh 321d60b4185SPavan Nikhilesh static int 322d60b4185SPavan Nikhilesh pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt) 323d60b4185SPavan Nikhilesh { 324d60b4185SPavan Nikhilesh int ret; 325d60b4185SPavan Nikhilesh int nb_ports; 326d60b4185SPavan Nikhilesh int nb_queues; 327d60b4185SPavan Nikhilesh int nb_stages = opt->nb_stages; 328d60b4185SPavan Nikhilesh uint8_t queue; 329d60b4185SPavan Nikhilesh struct rte_event_dev_info info; 330d60b4185SPavan Nikhilesh struct test_pipeline *t = evt_test_priv(test); 331d60b4185SPavan Nikhilesh uint8_t tx_evqueue_id = 0; 332d60b4185SPavan Nikhilesh uint8_t queue_arr[RTE_EVENT_MAX_QUEUES_PER_DEV]; 333d60b4185SPavan Nikhilesh uint8_t nb_worker_queues = 0; 334d60b4185SPavan Nikhilesh 335d60b4185SPavan Nikhilesh nb_ports = evt_nr_active_lcores(opt->wlcores); 336*d9a42a69SThomas Monjalon nb_queues = rte_eth_dev_count_avail() * (nb_stages); 337d60b4185SPavan Nikhilesh 338d60b4185SPavan Nikhilesh /* Extra port for Tx service. */ 339d60b4185SPavan Nikhilesh if (t->mt_unsafe) { 340d60b4185SPavan Nikhilesh tx_evqueue_id = nb_queues; 341d60b4185SPavan Nikhilesh nb_ports++; 342d60b4185SPavan Nikhilesh nb_queues++; 343d60b4185SPavan Nikhilesh } else 344*d9a42a69SThomas Monjalon nb_queues += rte_eth_dev_count_avail(); 345d60b4185SPavan Nikhilesh 346d60b4185SPavan Nikhilesh rte_event_dev_info_get(opt->dev_id, &info); 347d60b4185SPavan Nikhilesh 348d60b4185SPavan Nikhilesh const struct rte_event_dev_config config = { 349d60b4185SPavan Nikhilesh .nb_event_queues = nb_queues, 350d60b4185SPavan Nikhilesh .nb_event_ports = nb_ports, 351d60b4185SPavan Nikhilesh .nb_events_limit = info.max_num_events, 352d60b4185SPavan Nikhilesh .nb_event_queue_flows = opt->nb_flows, 353d60b4185SPavan Nikhilesh .nb_event_port_dequeue_depth = 354d60b4185SPavan Nikhilesh info.max_event_port_dequeue_depth, 355d60b4185SPavan Nikhilesh .nb_event_port_enqueue_depth = 356d60b4185SPavan Nikhilesh info.max_event_port_enqueue_depth, 357d60b4185SPavan Nikhilesh }; 358d60b4185SPavan Nikhilesh ret = rte_event_dev_configure(opt->dev_id, &config); 359d60b4185SPavan Nikhilesh if (ret) { 360d60b4185SPavan Nikhilesh evt_err("failed to configure eventdev %d", opt->dev_id); 361d60b4185SPavan Nikhilesh return ret; 362d60b4185SPavan Nikhilesh } 363d60b4185SPavan Nikhilesh 364d60b4185SPavan Nikhilesh struct rte_event_queue_conf q_conf = { 365d60b4185SPavan Nikhilesh .priority = RTE_EVENT_DEV_PRIORITY_NORMAL, 366d60b4185SPavan Nikhilesh .nb_atomic_flows = opt->nb_flows, 367d60b4185SPavan Nikhilesh .nb_atomic_order_sequences = opt->nb_flows, 368d60b4185SPavan Nikhilesh }; 369d60b4185SPavan Nikhilesh /* queue configurations */ 370d60b4185SPavan Nikhilesh for (queue = 0; queue < nb_queues; queue++) { 371d60b4185SPavan Nikhilesh uint8_t slot; 372d60b4185SPavan Nikhilesh 373d60b4185SPavan Nikhilesh if (!t->mt_unsafe) { 374d60b4185SPavan Nikhilesh slot = queue % (nb_stages + 1); 375d60b4185SPavan Nikhilesh q_conf.schedule_type = slot == nb_stages ? 376d60b4185SPavan Nikhilesh RTE_SCHED_TYPE_ATOMIC : 377d60b4185SPavan Nikhilesh opt->sched_type_list[slot]; 378d60b4185SPavan Nikhilesh } else { 379d60b4185SPavan Nikhilesh slot = queue % nb_stages; 380d60b4185SPavan Nikhilesh 381d60b4185SPavan Nikhilesh if (queue == tx_evqueue_id) { 382d60b4185SPavan Nikhilesh q_conf.schedule_type = RTE_SCHED_TYPE_ATOMIC; 383d60b4185SPavan Nikhilesh q_conf.event_queue_cfg = 384d60b4185SPavan Nikhilesh RTE_EVENT_QUEUE_CFG_SINGLE_LINK; 385d60b4185SPavan Nikhilesh } else { 386d60b4185SPavan Nikhilesh q_conf.schedule_type = 387d60b4185SPavan Nikhilesh opt->sched_type_list[slot]; 388d60b4185SPavan Nikhilesh queue_arr[nb_worker_queues] = queue; 389d60b4185SPavan Nikhilesh nb_worker_queues++; 390d60b4185SPavan Nikhilesh } 391d60b4185SPavan Nikhilesh } 392d60b4185SPavan Nikhilesh 393d60b4185SPavan Nikhilesh ret = rte_event_queue_setup(opt->dev_id, queue, &q_conf); 394d60b4185SPavan Nikhilesh if (ret) { 395d60b4185SPavan Nikhilesh evt_err("failed to setup queue=%d", queue); 396d60b4185SPavan Nikhilesh return ret; 397d60b4185SPavan Nikhilesh } 398d60b4185SPavan Nikhilesh } 399d60b4185SPavan Nikhilesh 400535c630cSPavan Nikhilesh if (opt->wkr_deq_dep > info.max_event_port_dequeue_depth) 401535c630cSPavan Nikhilesh opt->wkr_deq_dep = info.max_event_port_dequeue_depth; 402535c630cSPavan Nikhilesh 403d60b4185SPavan Nikhilesh /* port configuration */ 404d60b4185SPavan Nikhilesh const struct rte_event_port_conf p_conf = { 405d60b4185SPavan Nikhilesh .dequeue_depth = opt->wkr_deq_dep, 406d60b4185SPavan Nikhilesh .enqueue_depth = info.max_event_port_dequeue_depth, 407d60b4185SPavan Nikhilesh .new_event_threshold = info.max_num_events, 408d60b4185SPavan Nikhilesh }; 409d60b4185SPavan Nikhilesh 410d60b4185SPavan Nikhilesh /* 411d60b4185SPavan Nikhilesh * If tx is multi thread safe then allow workers to do Tx else use Tx 412d60b4185SPavan Nikhilesh * service to Tx packets. 413d60b4185SPavan Nikhilesh */ 414d60b4185SPavan Nikhilesh if (t->mt_unsafe) { 415d60b4185SPavan Nikhilesh ret = pipeline_event_port_setup(test, opt, queue_arr, 416d60b4185SPavan Nikhilesh nb_worker_queues, p_conf); 417d60b4185SPavan Nikhilesh if (ret) 418d60b4185SPavan Nikhilesh return ret; 419d60b4185SPavan Nikhilesh 420d60b4185SPavan Nikhilesh ret = pipeline_event_tx_service_setup(test, opt, tx_evqueue_id, 421d60b4185SPavan Nikhilesh nb_ports - 1, p_conf); 422d60b4185SPavan Nikhilesh 423d60b4185SPavan Nikhilesh } else 424d60b4185SPavan Nikhilesh ret = pipeline_event_port_setup(test, opt, NULL, nb_queues, 425d60b4185SPavan Nikhilesh p_conf); 426d60b4185SPavan Nikhilesh 427d60b4185SPavan Nikhilesh if (ret) 428d60b4185SPavan Nikhilesh return ret; 429d60b4185SPavan Nikhilesh /* 430d60b4185SPavan Nikhilesh * The pipelines are setup in the following manner: 431d60b4185SPavan Nikhilesh * 432d60b4185SPavan Nikhilesh * eth_dev_count = 2, nb_stages = 2. 433d60b4185SPavan Nikhilesh * 434d60b4185SPavan Nikhilesh * Multi thread safe : 435d60b4185SPavan Nikhilesh * queues = 6 436d60b4185SPavan Nikhilesh * stride = 3 437d60b4185SPavan Nikhilesh * 438d60b4185SPavan Nikhilesh * event queue pipelines: 439d60b4185SPavan Nikhilesh * eth0 -> q0 -> q1 -> (q2->tx) 440d60b4185SPavan Nikhilesh * eth1 -> q3 -> q4 -> (q5->tx) 441d60b4185SPavan Nikhilesh * 442d60b4185SPavan Nikhilesh * q2, q5 configured as ATOMIC 443d60b4185SPavan Nikhilesh * 444d60b4185SPavan Nikhilesh * Multi thread unsafe : 445d60b4185SPavan Nikhilesh * queues = 5 446d60b4185SPavan Nikhilesh * stride = 2 447d60b4185SPavan Nikhilesh * 448d60b4185SPavan Nikhilesh * event queue pipelines: 449d60b4185SPavan Nikhilesh * eth0 -> q0 -> q1 450d60b4185SPavan Nikhilesh * } (q4->tx) Tx service 451d60b4185SPavan Nikhilesh * eth1 -> q2 -> q3 452d60b4185SPavan Nikhilesh * 453d60b4185SPavan Nikhilesh * q4 configured as SINGLE_LINK|ATOMIC 454d60b4185SPavan Nikhilesh */ 455d60b4185SPavan Nikhilesh ret = pipeline_event_rx_adapter_setup(opt, 456d60b4185SPavan Nikhilesh t->mt_unsafe ? nb_stages : nb_stages + 1, p_conf); 457d60b4185SPavan Nikhilesh if (ret) 458d60b4185SPavan Nikhilesh return ret; 459d60b4185SPavan Nikhilesh 460d60b4185SPavan Nikhilesh if (!evt_has_distributed_sched(opt->dev_id)) { 461d60b4185SPavan Nikhilesh uint32_t service_id; 462d60b4185SPavan Nikhilesh rte_event_dev_service_id_get(opt->dev_id, &service_id); 463d60b4185SPavan Nikhilesh ret = evt_service_setup(service_id); 464d60b4185SPavan Nikhilesh if (ret) { 465d60b4185SPavan Nikhilesh evt_err("No service lcore found to run event dev."); 466d60b4185SPavan Nikhilesh return ret; 467d60b4185SPavan Nikhilesh } 468d60b4185SPavan Nikhilesh } 469d60b4185SPavan Nikhilesh 470d60b4185SPavan Nikhilesh ret = rte_event_dev_start(opt->dev_id); 471d60b4185SPavan Nikhilesh if (ret) { 472d60b4185SPavan Nikhilesh evt_err("failed to start eventdev %d", opt->dev_id); 473d60b4185SPavan Nikhilesh return ret; 474d60b4185SPavan Nikhilesh } 475d60b4185SPavan Nikhilesh 476d60b4185SPavan Nikhilesh return 0; 477d60b4185SPavan Nikhilesh } 478d60b4185SPavan Nikhilesh 479d60b4185SPavan Nikhilesh static void 480d60b4185SPavan Nikhilesh pipeline_queue_opt_dump(struct evt_options *opt) 481d60b4185SPavan Nikhilesh { 482d60b4185SPavan Nikhilesh pipeline_opt_dump(opt, pipeline_queue_nb_event_queues(opt)); 483d60b4185SPavan Nikhilesh } 484d60b4185SPavan Nikhilesh 485d60b4185SPavan Nikhilesh static int 486d60b4185SPavan Nikhilesh pipeline_queue_opt_check(struct evt_options *opt) 487d60b4185SPavan Nikhilesh { 488d60b4185SPavan Nikhilesh return pipeline_opt_check(opt, pipeline_queue_nb_event_queues(opt)); 489d60b4185SPavan Nikhilesh } 490d60b4185SPavan Nikhilesh 491d60b4185SPavan Nikhilesh static bool 492d60b4185SPavan Nikhilesh pipeline_queue_capability_check(struct evt_options *opt) 493d60b4185SPavan Nikhilesh { 494d60b4185SPavan Nikhilesh struct rte_event_dev_info dev_info; 495d60b4185SPavan Nikhilesh 496d60b4185SPavan Nikhilesh rte_event_dev_info_get(opt->dev_id, &dev_info); 497d60b4185SPavan Nikhilesh if (dev_info.max_event_queues < pipeline_queue_nb_event_queues(opt) || 498d60b4185SPavan Nikhilesh dev_info.max_event_ports < 499d60b4185SPavan Nikhilesh evt_nr_active_lcores(opt->wlcores)) { 500d60b4185SPavan Nikhilesh evt_err("not enough eventdev queues=%d/%d or ports=%d/%d", 501d60b4185SPavan Nikhilesh pipeline_queue_nb_event_queues(opt), 502d60b4185SPavan Nikhilesh dev_info.max_event_queues, 503d60b4185SPavan Nikhilesh evt_nr_active_lcores(opt->wlcores), 504d60b4185SPavan Nikhilesh dev_info.max_event_ports); 505d60b4185SPavan Nikhilesh } 506d60b4185SPavan Nikhilesh 507d60b4185SPavan Nikhilesh return true; 508d60b4185SPavan Nikhilesh } 509d60b4185SPavan Nikhilesh 510d60b4185SPavan Nikhilesh static const struct evt_test_ops pipeline_queue = { 511d60b4185SPavan Nikhilesh .cap_check = pipeline_queue_capability_check, 512d60b4185SPavan Nikhilesh .opt_check = pipeline_queue_opt_check, 513d60b4185SPavan Nikhilesh .opt_dump = pipeline_queue_opt_dump, 514d60b4185SPavan Nikhilesh .test_setup = pipeline_test_setup, 515d60b4185SPavan Nikhilesh .mempool_setup = pipeline_mempool_setup, 516d60b4185SPavan Nikhilesh .ethdev_setup = pipeline_ethdev_setup, 517d60b4185SPavan Nikhilesh .eventdev_setup = pipeline_queue_eventdev_setup, 518d60b4185SPavan Nikhilesh .launch_lcores = pipeline_queue_launch_lcores, 519d60b4185SPavan Nikhilesh .eventdev_destroy = pipeline_eventdev_destroy, 520d60b4185SPavan Nikhilesh .mempool_destroy = pipeline_mempool_destroy, 521d60b4185SPavan Nikhilesh .ethdev_destroy = pipeline_ethdev_destroy, 522d60b4185SPavan Nikhilesh .test_result = pipeline_test_result, 523d60b4185SPavan Nikhilesh .test_destroy = pipeline_test_destroy, 524d60b4185SPavan Nikhilesh }; 525d60b4185SPavan Nikhilesh 526d60b4185SPavan Nikhilesh EVT_TEST_REGISTER(pipeline_queue); 527