1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #ifndef _EVT_COMMON_ 6 #define _EVT_COMMON_ 7 8 #include <rte_common.h> 9 #include <rte_crypto.h> 10 #include <rte_debug.h> 11 #include <rte_event_crypto_adapter.h> 12 #include <rte_event_dma_adapter.h> 13 #include <rte_eventdev.h> 14 #include <rte_service.h> 15 16 #define CLNRM "\x1b[0m" 17 #define CLRED "\x1b[31m" 18 #define CLGRN "\x1b[32m" 19 #define CLYEL "\x1b[33m" 20 21 #define evt_err(fmt, args...) \ 22 fprintf(stderr, CLRED"error: %s() "fmt CLNRM "\n", __func__, ## args) 23 24 #define evt_info(fmt, args...) \ 25 fprintf(stdout, CLYEL""fmt CLNRM "\n", ## args) 26 27 #define EVT_STR_FMT 20 28 29 #define evt_dump(str, fmt, val...) \ 30 printf("\t%-*s : "fmt"\n", EVT_STR_FMT, str, ## val) 31 32 #define evt_dump_begin(str) printf("\t%-*s : {", EVT_STR_FMT, str) 33 34 #define evt_dump_end printf("\b}\n") 35 36 #define EVT_MAX_STAGES 64 37 #define EVT_MAX_PORTS 256 38 #define EVT_MAX_QUEUES 256 39 40 enum evt_prod_type { 41 EVT_PROD_TYPE_NONE, 42 EVT_PROD_TYPE_SYNT, /* Producer type Synthetic i.e. CPU. */ 43 EVT_PROD_TYPE_ETH_RX_ADPTR, /* Producer type Eth Rx Adapter. */ 44 EVT_PROD_TYPE_EVENT_TIMER_ADPTR, /* Producer type Timer Adapter. */ 45 EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR, /* Producer type Crypto Adapter. */ 46 EVT_PROD_TYPE_EVENT_DMA_ADPTR, /* Producer type DMA Adapter. */ 47 EVT_PROD_TYPE_MAX, 48 }; 49 50 struct evt_options { 51 #define EVT_TEST_NAME_MAX_LEN 32 52 #define EVT_CRYPTO_MAX_KEY_SIZE 256 53 #define EVT_CRYPTO_MAX_IV_SIZE 16 54 char test_name[EVT_TEST_NAME_MAX_LEN]; 55 bool plcores[RTE_MAX_LCORE]; 56 bool wlcores[RTE_MAX_LCORE]; 57 bool crypto_cipher_bit_mode; 58 int pool_sz; 59 int socket_id; 60 int nb_stages; 61 int verbose_level; 62 uint8_t dev_id; 63 uint8_t timdev_cnt; 64 uint8_t nb_timer_adptrs; 65 uint8_t timdev_use_burst; 66 uint8_t per_port_pool; 67 uint8_t sched_type_list[EVT_MAX_STAGES]; 68 uint16_t mbuf_sz; 69 uint16_t wkr_deq_dep; 70 uint16_t vector_size; 71 uint16_t eth_queues; 72 uint16_t crypto_cipher_iv_sz; 73 uint32_t nb_flows; 74 uint32_t tx_first; 75 uint16_t tx_pkt_sz; 76 uint32_t max_pkt_sz; 77 uint32_t prod_enq_burst_sz; 78 uint32_t deq_tmo_nsec; 79 uint32_t crypto_cipher_key_sz; 80 uint32_t q_priority:1; 81 uint32_t fwd_latency:1; 82 uint32_t ena_vector : 1; 83 uint64_t nb_pkts; 84 uint64_t nb_timers; 85 uint64_t expiry_nsec; 86 uint64_t max_tmo_nsec; 87 uint64_t vector_tmo_nsec; 88 uint64_t timer_tick_nsec; 89 uint64_t optm_timer_tick_nsec; 90 enum evt_prod_type prod_type; 91 enum rte_event_dma_adapter_mode dma_adptr_mode; 92 enum rte_event_crypto_adapter_mode crypto_adptr_mode; 93 enum rte_crypto_op_type crypto_op_type; 94 enum rte_crypto_cipher_algorithm crypto_cipher_alg; 95 uint8_t crypto_cipher_key[EVT_CRYPTO_MAX_KEY_SIZE]; 96 }; 97 98 static inline bool 99 evt_has_distributed_sched(uint8_t dev_id) 100 { 101 struct rte_event_dev_info dev_info; 102 103 rte_event_dev_info_get(dev_id, &dev_info); 104 return (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED) ? 105 true : false; 106 } 107 108 static inline bool 109 evt_has_burst_mode(uint8_t dev_id) 110 { 111 struct rte_event_dev_info dev_info; 112 113 rte_event_dev_info_get(dev_id, &dev_info); 114 return (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_BURST_MODE) ? 115 true : false; 116 } 117 118 119 static inline bool 120 evt_has_all_types_queue(uint8_t dev_id) 121 { 122 struct rte_event_dev_info dev_info; 123 124 rte_event_dev_info_get(dev_id, &dev_info); 125 return (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES) ? 126 true : false; 127 } 128 129 static inline bool 130 evt_has_flow_id(uint8_t dev_id) 131 { 132 struct rte_event_dev_info dev_info; 133 134 rte_event_dev_info_get(dev_id, &dev_info); 135 return (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_CARRY_FLOW_ID) ? 136 true : false; 137 } 138 139 static inline int 140 evt_service_setup(uint32_t service_id) 141 { 142 int32_t core_cnt; 143 unsigned int lcore = 0; 144 uint32_t core_array[RTE_MAX_LCORE]; 145 uint8_t cnt; 146 uint8_t min_cnt = UINT8_MAX; 147 148 if (!rte_service_lcore_count()) 149 return -ENOENT; 150 151 core_cnt = rte_service_lcore_list(core_array, 152 RTE_MAX_LCORE); 153 if (core_cnt < 0) 154 return -ENOENT; 155 /* Get the core which has least number of services running. */ 156 while (core_cnt--) { 157 /* Reset default mapping */ 158 rte_service_map_lcore_set(service_id, 159 core_array[core_cnt], 0); 160 cnt = rte_service_lcore_count_services( 161 core_array[core_cnt]); 162 if (cnt < min_cnt) { 163 lcore = core_array[core_cnt]; 164 min_cnt = cnt; 165 } 166 } 167 if (rte_service_map_lcore_set(service_id, lcore, 1)) 168 return -ENOENT; 169 170 return 0; 171 } 172 173 static inline int 174 evt_configure_eventdev(struct evt_options *opt, uint8_t nb_queues, 175 uint8_t nb_ports) 176 { 177 struct rte_event_dev_info info; 178 int ret; 179 180 memset(&info, 0, sizeof(struct rte_event_dev_info)); 181 ret = rte_event_dev_info_get(opt->dev_id, &info); 182 if (ret) { 183 evt_err("failed to get eventdev info %d", opt->dev_id); 184 return ret; 185 } 186 187 if (opt->deq_tmo_nsec) { 188 if (opt->deq_tmo_nsec < info.min_dequeue_timeout_ns) { 189 opt->deq_tmo_nsec = info.min_dequeue_timeout_ns; 190 evt_info("dequeue_timeout_ns too low, using %d", 191 opt->deq_tmo_nsec); 192 } 193 if (opt->deq_tmo_nsec > info.max_dequeue_timeout_ns) { 194 opt->deq_tmo_nsec = info.max_dequeue_timeout_ns; 195 evt_info("dequeue_timeout_ns too high, using %d", 196 opt->deq_tmo_nsec); 197 } 198 } 199 200 const struct rte_event_dev_config config = { 201 .dequeue_timeout_ns = opt->deq_tmo_nsec, 202 .nb_event_queues = nb_queues, 203 .nb_event_ports = nb_ports, 204 .nb_single_link_event_port_queues = 0, 205 .nb_events_limit = info.max_num_events, 206 .nb_event_queue_flows = opt->nb_flows, 207 .nb_event_port_dequeue_depth = 208 info.max_event_port_dequeue_depth, 209 .nb_event_port_enqueue_depth = 210 info.max_event_port_enqueue_depth, 211 }; 212 213 return rte_event_dev_configure(opt->dev_id, &config); 214 } 215 216 #endif /* _EVT_COMMON_*/ 217