1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Intel Corporation 3 */ 4 5 #include <stdbool.h> 6 #include <stdlib.h> 7 8 #include <rte_crypto.h> 9 #include <rte_cryptodev.h> 10 #include <rte_cycles.h> 11 #include <rte_malloc.h> 12 13 #include "cperf_ops.h" 14 #include "cperf_test_pmd_cyclecount.h" 15 #include "cperf_test_common.h" 16 17 #define PRETTY_HDR_FMT "%12s%12s%12s%12s%12s%12s%12s%12s%12s%12s\n\n" 18 #define PRETTY_LINE_FMT "%12u%12u%12u%12u%12u%12u%12u%12.0f%12.0f%12.0f\n" 19 #define CSV_HDR_FMT "%s,%s,%s,%s,%s,%s,%s,%s,%s,%s\n" 20 #define CSV_LINE_FMT "%10u,%10u,%u,%u,%u,%u,%u,%.3f,%.3f,%.3f\n" 21 22 struct cperf_pmd_cyclecount_ctx { 23 uint8_t dev_id; 24 uint16_t qp_id; 25 uint8_t lcore_id; 26 27 struct rte_mempool *pool; 28 struct rte_crypto_op **ops; 29 struct rte_crypto_op **ops_processed; 30 31 void *sess; 32 33 cperf_populate_ops_t populate_ops; 34 35 uint32_t src_buf_offset; 36 uint32_t dst_buf_offset; 37 38 const struct cperf_options *options; 39 const struct cperf_test_vector *test_vector; 40 }; 41 42 struct pmd_cyclecount_state { 43 struct cperf_pmd_cyclecount_ctx *ctx; 44 const struct cperf_options *opts; 45 uint32_t lcore; 46 uint64_t delay; 47 int linearize; 48 uint32_t ops_enqd; 49 uint32_t ops_deqd; 50 uint32_t ops_enq_retries; 51 uint32_t ops_deq_retries; 52 double cycles_per_build; 53 double cycles_per_enq; 54 double cycles_per_deq; 55 }; 56 57 static const uint16_t iv_offset = 58 sizeof(struct rte_crypto_op) + sizeof(struct rte_crypto_sym_op); 59 60 static void 61 cperf_pmd_cyclecount_test_free(struct cperf_pmd_cyclecount_ctx *ctx) 62 { 63 if (!ctx) 64 return; 65 66 if (ctx->sess) { 67 #ifdef RTE_LIB_SECURITY 68 if (ctx->options->op_type == CPERF_PDCP || 69 ctx->options->op_type == CPERF_DOCSIS) { 70 struct rte_security_ctx *sec_ctx = 71 (struct rte_security_ctx *) 72 rte_cryptodev_get_sec_ctx(ctx->dev_id); 73 rte_security_session_destroy(sec_ctx, 74 (void *)ctx->sess); 75 } else 76 #endif 77 rte_cryptodev_sym_session_free(ctx->dev_id, ctx->sess); 78 } 79 80 rte_mempool_free(ctx->pool); 81 82 rte_free(ctx->ops); 83 84 rte_free(ctx->ops_processed); 85 86 rte_free(ctx); 87 } 88 89 void * 90 cperf_pmd_cyclecount_test_constructor(struct rte_mempool *sess_mp, 91 uint8_t dev_id, uint16_t qp_id, 92 const struct cperf_options *options, 93 const struct cperf_test_vector *test_vector, 94 const struct cperf_op_fns *op_fns) 95 { 96 struct cperf_pmd_cyclecount_ctx *ctx = NULL; 97 98 /* preallocate buffers for crypto ops as they can get quite big */ 99 size_t alloc_sz = sizeof(struct rte_crypto_op *) * 100 options->nb_descriptors; 101 102 ctx = rte_malloc(NULL, sizeof(struct cperf_pmd_cyclecount_ctx), 0); 103 if (ctx == NULL) 104 goto err; 105 106 ctx->dev_id = dev_id; 107 ctx->qp_id = qp_id; 108 109 ctx->populate_ops = op_fns->populate_ops; 110 ctx->options = options; 111 ctx->test_vector = test_vector; 112 113 /* IV goes at the end of the crypto operation */ 114 uint16_t iv_offset = sizeof(struct rte_crypto_op) + 115 sizeof(struct rte_crypto_sym_op); 116 117 ctx->sess = op_fns->sess_create(sess_mp, dev_id, options, 118 test_vector, iv_offset); 119 if (ctx->sess == NULL) 120 goto err; 121 122 if (cperf_alloc_common_memory(options, test_vector, dev_id, qp_id, 0, 123 &ctx->src_buf_offset, &ctx->dst_buf_offset, 124 &ctx->pool) < 0) 125 goto err; 126 127 ctx->ops = rte_malloc("ops", alloc_sz, 0); 128 if (!ctx->ops) 129 goto err; 130 131 ctx->ops_processed = rte_malloc("ops_processed", alloc_sz, 0); 132 if (!ctx->ops_processed) 133 goto err; 134 135 return ctx; 136 137 err: 138 cperf_pmd_cyclecount_test_free(ctx); 139 140 return NULL; 141 } 142 143 /* benchmark alloc-build-free of ops */ 144 static inline int 145 pmd_cyclecount_bench_ops(struct pmd_cyclecount_state *state, uint32_t cur_op, 146 uint16_t test_burst_size) 147 { 148 uint32_t iter_ops_left = state->opts->total_ops - cur_op; 149 uint32_t iter_ops_needed = 150 RTE_MIN(state->opts->nb_descriptors, iter_ops_left); 151 uint32_t cur_iter_op; 152 uint32_t imix_idx = 0; 153 154 for (cur_iter_op = 0; cur_iter_op < iter_ops_needed; 155 cur_iter_op += test_burst_size) { 156 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op, 157 test_burst_size); 158 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op]; 159 160 /* Allocate objects containing crypto operations and mbufs */ 161 if (rte_mempool_get_bulk(state->ctx->pool, (void **)ops, 162 burst_size) != 0) { 163 RTE_LOG(ERR, USER1, 164 "Failed to allocate more crypto operations " 165 "from the crypto operation pool.\n" 166 "Consider increasing the pool size " 167 "with --pool-sz\n"); 168 return -1; 169 } 170 171 /* Setup crypto op, attach mbuf etc */ 172 (state->ctx->populate_ops)(ops, 173 state->ctx->src_buf_offset, 174 state->ctx->dst_buf_offset, 175 burst_size, 176 state->ctx->sess, state->opts, 177 state->ctx->test_vector, iv_offset, 178 &imix_idx, NULL); 179 180 #ifdef CPERF_LINEARIZATION_ENABLE 181 /* Check if source mbufs require coalescing */ 182 if (state->linearize) { 183 uint8_t i; 184 for (i = 0; i < burst_size; i++) { 185 struct rte_mbuf *src = ops[i]->sym->m_src; 186 rte_pktmbuf_linearize(src); 187 } 188 } 189 #endif /* CPERF_LINEARIZATION_ENABLE */ 190 rte_mempool_put_bulk(state->ctx->pool, (void **)ops, 191 burst_size); 192 } 193 194 return 0; 195 } 196 197 /* allocate and build ops (no free) */ 198 static int 199 pmd_cyclecount_build_ops(struct pmd_cyclecount_state *state, 200 uint32_t iter_ops_needed, uint16_t test_burst_size) 201 { 202 uint32_t cur_iter_op; 203 uint32_t imix_idx = 0; 204 205 for (cur_iter_op = 0; cur_iter_op < iter_ops_needed; 206 cur_iter_op += test_burst_size) { 207 uint32_t burst_size = RTE_MIN( 208 iter_ops_needed - cur_iter_op, test_burst_size); 209 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op]; 210 211 /* Allocate objects containing crypto operations and mbufs */ 212 if (rte_mempool_get_bulk(state->ctx->pool, (void **)ops, 213 burst_size) != 0) { 214 RTE_LOG(ERR, USER1, 215 "Failed to allocate more crypto operations " 216 "from the crypto operation pool.\n" 217 "Consider increasing the pool size " 218 "with --pool-sz\n"); 219 return -1; 220 } 221 222 /* Setup crypto op, attach mbuf etc */ 223 (state->ctx->populate_ops)(ops, 224 state->ctx->src_buf_offset, 225 state->ctx->dst_buf_offset, 226 burst_size, 227 state->ctx->sess, state->opts, 228 state->ctx->test_vector, iv_offset, 229 &imix_idx, NULL); 230 } 231 return 0; 232 } 233 234 /* benchmark enqueue, returns number of ops enqueued */ 235 static uint32_t 236 pmd_cyclecount_bench_enq(struct pmd_cyclecount_state *state, 237 uint32_t iter_ops_needed, uint16_t test_burst_size) 238 { 239 /* Enqueue full descriptor ring of ops on crypto device */ 240 uint32_t cur_iter_op = 0; 241 while (cur_iter_op < iter_ops_needed) { 242 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op, 243 test_burst_size); 244 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op]; 245 uint32_t burst_enqd; 246 247 burst_enqd = rte_cryptodev_enqueue_burst(state->ctx->dev_id, 248 state->ctx->qp_id, ops, burst_size); 249 250 /* if we couldn't enqueue anything, the queue is full */ 251 if (!burst_enqd) { 252 /* don't try to dequeue anything we didn't enqueue */ 253 return cur_iter_op; 254 } 255 256 if (burst_enqd < burst_size) 257 state->ops_enq_retries++; 258 state->ops_enqd += burst_enqd; 259 cur_iter_op += burst_enqd; 260 } 261 return iter_ops_needed; 262 } 263 264 /* benchmark dequeue */ 265 static void 266 pmd_cyclecount_bench_deq(struct pmd_cyclecount_state *state, 267 uint32_t iter_ops_needed, uint16_t test_burst_size) 268 { 269 /* Dequeue full descriptor ring of ops on crypto device */ 270 uint32_t cur_iter_op = 0; 271 while (cur_iter_op < iter_ops_needed) { 272 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op, 273 test_burst_size); 274 struct rte_crypto_op **ops_processed = 275 &state->ctx->ops[cur_iter_op]; 276 uint32_t burst_deqd; 277 278 burst_deqd = rte_cryptodev_dequeue_burst(state->ctx->dev_id, 279 state->ctx->qp_id, ops_processed, burst_size); 280 281 if (burst_deqd < burst_size) 282 state->ops_deq_retries++; 283 state->ops_deqd += burst_deqd; 284 cur_iter_op += burst_deqd; 285 } 286 } 287 288 /* run benchmark per burst size */ 289 static inline int 290 pmd_cyclecount_bench_burst_sz( 291 struct pmd_cyclecount_state *state, uint16_t test_burst_size) 292 { 293 uint64_t tsc_start; 294 uint64_t tsc_end; 295 uint64_t tsc_op; 296 uint64_t tsc_enq; 297 uint64_t tsc_deq; 298 uint32_t cur_op; 299 300 /* reset all counters */ 301 tsc_enq = 0; 302 tsc_deq = 0; 303 state->ops_enqd = 0; 304 state->ops_enq_retries = 0; 305 state->ops_deqd = 0; 306 state->ops_deq_retries = 0; 307 308 /* 309 * Benchmark crypto op alloc-build-free separately. 310 */ 311 tsc_start = rte_rdtsc_precise(); 312 313 for (cur_op = 0; cur_op < state->opts->total_ops; 314 cur_op += state->opts->nb_descriptors) { 315 if (unlikely(pmd_cyclecount_bench_ops( 316 state, cur_op, test_burst_size))) 317 return -1; 318 } 319 320 tsc_end = rte_rdtsc_precise(); 321 tsc_op = tsc_end - tsc_start; 322 323 324 /* 325 * Hardware acceleration cyclecount benchmarking loop. 326 * 327 * We're benchmarking raw enq/deq performance by filling up the device 328 * queue, so we never get any failed enqs unless the driver won't accept 329 * the exact number of descriptors we requested, or the driver won't 330 * wrap around the end of the TX ring. However, since we're only 331 * dequeuing once we've filled up the queue, we have to benchmark it 332 * piecemeal and then average out the results. 333 */ 334 cur_op = 0; 335 while (cur_op < state->opts->total_ops) { 336 uint32_t iter_ops_left = state->opts->total_ops - cur_op; 337 uint32_t iter_ops_needed = RTE_MIN( 338 state->opts->nb_descriptors, iter_ops_left); 339 uint32_t iter_ops_allocd = iter_ops_needed; 340 341 /* allocate and build ops */ 342 if (unlikely(pmd_cyclecount_build_ops(state, iter_ops_needed, 343 test_burst_size))) 344 return -1; 345 346 tsc_start = rte_rdtsc_precise(); 347 348 /* fill up TX ring */ 349 iter_ops_needed = pmd_cyclecount_bench_enq(state, 350 iter_ops_needed, test_burst_size); 351 352 tsc_end = rte_rdtsc_precise(); 353 354 tsc_enq += tsc_end - tsc_start; 355 356 /* allow for HW to catch up */ 357 if (state->delay) 358 rte_delay_us_block(state->delay); 359 360 tsc_start = rte_rdtsc_precise(); 361 362 /* drain RX ring */ 363 pmd_cyclecount_bench_deq(state, iter_ops_needed, 364 test_burst_size); 365 366 tsc_end = rte_rdtsc_precise(); 367 368 tsc_deq += tsc_end - tsc_start; 369 370 cur_op += iter_ops_needed; 371 372 /* 373 * we may not have processed all ops that we allocated, so 374 * free everything we've allocated. 375 */ 376 rte_mempool_put_bulk(state->ctx->pool, 377 (void **)state->ctx->ops, iter_ops_allocd); 378 } 379 380 state->cycles_per_build = (double)tsc_op / state->opts->total_ops; 381 state->cycles_per_enq = (double)tsc_enq / state->ops_enqd; 382 state->cycles_per_deq = (double)tsc_deq / state->ops_deqd; 383 384 return 0; 385 } 386 387 int 388 cperf_pmd_cyclecount_test_runner(void *test_ctx) 389 { 390 struct pmd_cyclecount_state state = {0}; 391 const struct cperf_options *opts; 392 uint16_t test_burst_size; 393 uint8_t burst_size_idx = 0; 394 395 state.ctx = test_ctx; 396 opts = state.ctx->options; 397 state.opts = opts; 398 state.lcore = rte_lcore_id(); 399 state.linearize = 0; 400 401 static uint16_t display_once; 402 static bool warmup = true; 403 404 /* 405 * We need a small delay to allow for hardware to process all the crypto 406 * operations. We can't automatically figure out what the delay should 407 * be, so we leave it up to the user (by default it's 0). 408 */ 409 state.delay = 1000 * opts->pmdcc_delay; 410 411 #ifdef CPERF_LINEARIZATION_ENABLE 412 struct rte_cryptodev_info dev_info; 413 414 /* Check if source mbufs require coalescing */ 415 if (opts->segments_sz < ctx->options->max_buffer_size) { 416 rte_cryptodev_info_get(state.ctx->dev_id, &dev_info); 417 if ((dev_info.feature_flags & 418 RTE_CRYPTODEV_FF_MBUF_SCATTER_GATHER) == 419 0) { 420 state.linearize = 1; 421 } 422 } 423 #endif /* CPERF_LINEARIZATION_ENABLE */ 424 425 state.ctx->lcore_id = state.lcore; 426 427 /* Get first size from range or list */ 428 if (opts->inc_burst_size != 0) 429 test_burst_size = opts->min_burst_size; 430 else 431 test_burst_size = opts->burst_size_list[0]; 432 433 while (test_burst_size <= opts->max_burst_size) { 434 /* do a benchmark run */ 435 if (pmd_cyclecount_bench_burst_sz(&state, test_burst_size)) 436 return -1; 437 438 /* 439 * First run is always a warm up run. 440 */ 441 if (warmup) { 442 warmup = false; 443 continue; 444 } 445 446 uint16_t exp = 0; 447 if (!opts->csv) { 448 if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, 449 __ATOMIC_RELAXED, __ATOMIC_RELAXED)) 450 printf(PRETTY_HDR_FMT, "lcore id", "Buf Size", 451 "Burst Size", "Enqueued", 452 "Dequeued", "Enq Retries", 453 "Deq Retries", "Cycles/Op", 454 "Cycles/Enq", "Cycles/Deq"); 455 456 printf(PRETTY_LINE_FMT, state.ctx->lcore_id, 457 opts->test_buffer_size, test_burst_size, 458 state.ops_enqd, state.ops_deqd, 459 state.ops_enq_retries, 460 state.ops_deq_retries, 461 state.cycles_per_build, 462 state.cycles_per_enq, 463 state.cycles_per_deq); 464 } else { 465 if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, 466 __ATOMIC_RELAXED, __ATOMIC_RELAXED)) 467 printf(CSV_HDR_FMT, "# lcore id", "Buf Size", 468 "Burst Size", "Enqueued", 469 "Dequeued", "Enq Retries", 470 "Deq Retries", "Cycles/Op", 471 "Cycles/Enq", "Cycles/Deq"); 472 473 printf(CSV_LINE_FMT, state.ctx->lcore_id, 474 opts->test_buffer_size, test_burst_size, 475 state.ops_enqd, state.ops_deqd, 476 state.ops_enq_retries, 477 state.ops_deq_retries, 478 state.cycles_per_build, 479 state.cycles_per_enq, 480 state.cycles_per_deq); 481 } 482 483 /* Get next size from range or list */ 484 if (opts->inc_burst_size != 0) 485 test_burst_size += opts->inc_burst_size; 486 else { 487 if (++burst_size_idx == opts->burst_size_count) 488 break; 489 test_burst_size = opts->burst_size_list[burst_size_idx]; 490 } 491 } 492 493 return 0; 494 } 495 496 void 497 cperf_pmd_cyclecount_test_destructor(void *arg) 498 { 499 struct cperf_pmd_cyclecount_ctx *ctx = arg; 500 501 if (ctx == NULL) 502 return; 503 504 cperf_pmd_cyclecount_test_free(ctx); 505 } 506