1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Intel Corporation 3 */ 4 5 #include <stdbool.h> 6 #include <stdlib.h> 7 8 #include <rte_crypto.h> 9 #include <rte_cryptodev.h> 10 #include <rte_cycles.h> 11 #include <rte_malloc.h> 12 13 #include "cperf_ops.h" 14 #include "cperf_test_pmd_cyclecount.h" 15 #include "cperf_test_common.h" 16 17 #define PRETTY_HDR_FMT "%12s%12s%12s%12s%12s%12s%12s%12s%12s%12s\n\n" 18 #define PRETTY_LINE_FMT "%12u%12u%12u%12u%12u%12u%12u%12.0f%12.0f%12.0f\n" 19 #define CSV_HDR_FMT "%s,%s,%s,%s,%s,%s,%s,%s,%s,%s\n" 20 #define CSV_LINE_FMT "%10u,%10u,%u,%u,%u,%u,%u,%.3f,%.3f,%.3f\n" 21 22 struct cperf_pmd_cyclecount_ctx { 23 uint8_t dev_id; 24 uint16_t qp_id; 25 uint8_t lcore_id; 26 27 struct rte_mempool *pool; 28 struct rte_crypto_op **ops; 29 struct rte_crypto_op **ops_processed; 30 31 void *sess; 32 33 cperf_populate_ops_t populate_ops; 34 35 uint32_t src_buf_offset; 36 uint32_t dst_buf_offset; 37 38 const struct cperf_options *options; 39 const struct cperf_test_vector *test_vector; 40 }; 41 42 struct pmd_cyclecount_state { 43 struct cperf_pmd_cyclecount_ctx *ctx; 44 const struct cperf_options *opts; 45 uint32_t lcore; 46 uint64_t delay; 47 int linearize; 48 uint32_t ops_enqd; 49 uint32_t ops_deqd; 50 uint32_t ops_enq_retries; 51 uint32_t ops_deq_retries; 52 double cycles_per_build; 53 double cycles_per_enq; 54 double cycles_per_deq; 55 }; 56 57 static const uint16_t iv_offset = 58 sizeof(struct rte_crypto_op) + sizeof(struct rte_crypto_sym_op); 59 60 static void 61 cperf_pmd_cyclecount_test_free(struct cperf_pmd_cyclecount_ctx *ctx) 62 { 63 if (!ctx) 64 return; 65 66 if (ctx->sess) { 67 #ifdef RTE_LIB_SECURITY 68 if (ctx->options->op_type == CPERF_PDCP || 69 ctx->options->op_type == CPERF_DOCSIS) { 70 void *sec_ctx = rte_cryptodev_get_sec_ctx(ctx->dev_id); 71 72 rte_security_session_destroy(sec_ctx, (void *)ctx->sess); 73 } else 74 #endif 75 rte_cryptodev_sym_session_free(ctx->dev_id, ctx->sess); 76 } 77 78 rte_mempool_free(ctx->pool); 79 80 rte_free(ctx->ops); 81 82 rte_free(ctx->ops_processed); 83 84 rte_free(ctx); 85 } 86 87 void * 88 cperf_pmd_cyclecount_test_constructor(struct rte_mempool *sess_mp, 89 uint8_t dev_id, uint16_t qp_id, 90 const struct cperf_options *options, 91 const struct cperf_test_vector *test_vector, 92 const struct cperf_op_fns *op_fns) 93 { 94 struct cperf_pmd_cyclecount_ctx *ctx = NULL; 95 96 /* preallocate buffers for crypto ops as they can get quite big */ 97 size_t alloc_sz = sizeof(struct rte_crypto_op *) * 98 options->nb_descriptors; 99 100 ctx = rte_malloc(NULL, sizeof(struct cperf_pmd_cyclecount_ctx), 0); 101 if (ctx == NULL) 102 goto err; 103 104 ctx->dev_id = dev_id; 105 ctx->qp_id = qp_id; 106 107 ctx->populate_ops = op_fns->populate_ops; 108 ctx->options = options; 109 ctx->test_vector = test_vector; 110 111 /* IV goes at the end of the crypto operation */ 112 uint16_t iv_offset = sizeof(struct rte_crypto_op) + 113 sizeof(struct rte_crypto_sym_op); 114 115 ctx->sess = op_fns->sess_create(sess_mp, dev_id, options, 116 test_vector, iv_offset); 117 if (ctx->sess == NULL) 118 goto err; 119 120 if (cperf_alloc_common_memory(options, test_vector, dev_id, qp_id, 0, 121 &ctx->src_buf_offset, &ctx->dst_buf_offset, 122 &ctx->pool) < 0) 123 goto err; 124 125 ctx->ops = rte_malloc("ops", alloc_sz, 0); 126 if (!ctx->ops) 127 goto err; 128 129 ctx->ops_processed = rte_malloc("ops_processed", alloc_sz, 0); 130 if (!ctx->ops_processed) 131 goto err; 132 133 return ctx; 134 135 err: 136 cperf_pmd_cyclecount_test_free(ctx); 137 138 return NULL; 139 } 140 141 /* benchmark alloc-build-free of ops */ 142 static inline int 143 pmd_cyclecount_bench_ops(struct pmd_cyclecount_state *state, uint32_t cur_op, 144 uint16_t test_burst_size) 145 { 146 uint32_t iter_ops_left = state->opts->total_ops - cur_op; 147 uint32_t iter_ops_needed = 148 RTE_MIN(state->opts->nb_descriptors, iter_ops_left); 149 uint32_t cur_iter_op; 150 uint32_t imix_idx = 0; 151 152 for (cur_iter_op = 0; cur_iter_op < iter_ops_needed; 153 cur_iter_op += test_burst_size) { 154 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op, 155 test_burst_size); 156 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op]; 157 158 /* Allocate objects containing crypto operations and mbufs */ 159 if (rte_mempool_get_bulk(state->ctx->pool, (void **)ops, 160 burst_size) != 0) { 161 RTE_LOG(ERR, USER1, 162 "Failed to allocate more crypto operations " 163 "from the crypto operation pool.\n" 164 "Consider increasing the pool size " 165 "with --pool-sz\n"); 166 return -1; 167 } 168 169 /* Setup crypto op, attach mbuf etc */ 170 (state->ctx->populate_ops)(ops, 171 state->ctx->src_buf_offset, 172 state->ctx->dst_buf_offset, 173 burst_size, 174 state->ctx->sess, state->opts, 175 state->ctx->test_vector, iv_offset, 176 &imix_idx, NULL); 177 178 #ifdef CPERF_LINEARIZATION_ENABLE 179 /* Check if source mbufs require coalescing */ 180 if (state->linearize) { 181 uint8_t i; 182 for (i = 0; i < burst_size; i++) { 183 struct rte_mbuf *src = ops[i]->sym->m_src; 184 rte_pktmbuf_linearize(src); 185 } 186 } 187 #endif /* CPERF_LINEARIZATION_ENABLE */ 188 rte_mempool_put_bulk(state->ctx->pool, (void **)ops, 189 burst_size); 190 } 191 192 return 0; 193 } 194 195 /* allocate and build ops (no free) */ 196 static int 197 pmd_cyclecount_build_ops(struct pmd_cyclecount_state *state, 198 uint32_t iter_ops_needed, uint16_t test_burst_size) 199 { 200 uint32_t cur_iter_op; 201 uint32_t imix_idx = 0; 202 203 for (cur_iter_op = 0; cur_iter_op < iter_ops_needed; 204 cur_iter_op += test_burst_size) { 205 uint32_t burst_size = RTE_MIN( 206 iter_ops_needed - cur_iter_op, test_burst_size); 207 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op]; 208 209 /* Allocate objects containing crypto operations and mbufs */ 210 if (rte_mempool_get_bulk(state->ctx->pool, (void **)ops, 211 burst_size) != 0) { 212 RTE_LOG(ERR, USER1, 213 "Failed to allocate more crypto operations " 214 "from the crypto operation pool.\n" 215 "Consider increasing the pool size " 216 "with --pool-sz\n"); 217 return -1; 218 } 219 220 /* Setup crypto op, attach mbuf etc */ 221 (state->ctx->populate_ops)(ops, 222 state->ctx->src_buf_offset, 223 state->ctx->dst_buf_offset, 224 burst_size, 225 state->ctx->sess, state->opts, 226 state->ctx->test_vector, iv_offset, 227 &imix_idx, NULL); 228 } 229 return 0; 230 } 231 232 /* benchmark enqueue, returns number of ops enqueued */ 233 static uint32_t 234 pmd_cyclecount_bench_enq(struct pmd_cyclecount_state *state, 235 uint32_t iter_ops_needed, uint16_t test_burst_size) 236 { 237 /* Enqueue full descriptor ring of ops on crypto device */ 238 uint32_t cur_iter_op = 0; 239 while (cur_iter_op < iter_ops_needed) { 240 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op, 241 test_burst_size); 242 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op]; 243 uint32_t burst_enqd; 244 245 burst_enqd = rte_cryptodev_enqueue_burst(state->ctx->dev_id, 246 state->ctx->qp_id, ops, burst_size); 247 248 /* if we couldn't enqueue anything, the queue is full */ 249 if (!burst_enqd) { 250 /* don't try to dequeue anything we didn't enqueue */ 251 return cur_iter_op; 252 } 253 254 if (burst_enqd < burst_size) 255 state->ops_enq_retries++; 256 state->ops_enqd += burst_enqd; 257 cur_iter_op += burst_enqd; 258 } 259 return iter_ops_needed; 260 } 261 262 /* benchmark dequeue */ 263 static void 264 pmd_cyclecount_bench_deq(struct pmd_cyclecount_state *state, 265 uint32_t iter_ops_needed, uint16_t test_burst_size) 266 { 267 /* Dequeue full descriptor ring of ops on crypto device */ 268 uint32_t cur_iter_op = 0; 269 while (cur_iter_op < iter_ops_needed) { 270 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op, 271 test_burst_size); 272 struct rte_crypto_op **ops_processed = 273 &state->ctx->ops[cur_iter_op]; 274 uint32_t burst_deqd; 275 276 burst_deqd = rte_cryptodev_dequeue_burst(state->ctx->dev_id, 277 state->ctx->qp_id, ops_processed, burst_size); 278 279 if (burst_deqd < burst_size) 280 state->ops_deq_retries++; 281 state->ops_deqd += burst_deqd; 282 cur_iter_op += burst_deqd; 283 } 284 } 285 286 /* run benchmark per burst size */ 287 static inline int 288 pmd_cyclecount_bench_burst_sz( 289 struct pmd_cyclecount_state *state, uint16_t test_burst_size) 290 { 291 uint64_t tsc_start; 292 uint64_t tsc_end; 293 uint64_t tsc_op; 294 uint64_t tsc_enq; 295 uint64_t tsc_deq; 296 uint32_t cur_op; 297 298 /* reset all counters */ 299 tsc_enq = 0; 300 tsc_deq = 0; 301 state->ops_enqd = 0; 302 state->ops_enq_retries = 0; 303 state->ops_deqd = 0; 304 state->ops_deq_retries = 0; 305 306 /* 307 * Benchmark crypto op alloc-build-free separately. 308 */ 309 tsc_start = rte_rdtsc_precise(); 310 311 for (cur_op = 0; cur_op < state->opts->total_ops; 312 cur_op += state->opts->nb_descriptors) { 313 if (unlikely(pmd_cyclecount_bench_ops( 314 state, cur_op, test_burst_size))) 315 return -1; 316 } 317 318 tsc_end = rte_rdtsc_precise(); 319 tsc_op = tsc_end - tsc_start; 320 321 322 /* 323 * Hardware acceleration cyclecount benchmarking loop. 324 * 325 * We're benchmarking raw enq/deq performance by filling up the device 326 * queue, so we never get any failed enqs unless the driver won't accept 327 * the exact number of descriptors we requested, or the driver won't 328 * wrap around the end of the TX ring. However, since we're only 329 * dequeuing once we've filled up the queue, we have to benchmark it 330 * piecemeal and then average out the results. 331 */ 332 cur_op = 0; 333 while (cur_op < state->opts->total_ops) { 334 uint32_t iter_ops_left = state->opts->total_ops - cur_op; 335 uint32_t iter_ops_needed = RTE_MIN( 336 state->opts->nb_descriptors, iter_ops_left); 337 uint32_t iter_ops_allocd = iter_ops_needed; 338 339 /* allocate and build ops */ 340 if (unlikely(pmd_cyclecount_build_ops(state, iter_ops_needed, 341 test_burst_size))) 342 return -1; 343 344 tsc_start = rte_rdtsc_precise(); 345 346 /* fill up TX ring */ 347 iter_ops_needed = pmd_cyclecount_bench_enq(state, 348 iter_ops_needed, test_burst_size); 349 350 tsc_end = rte_rdtsc_precise(); 351 352 tsc_enq += tsc_end - tsc_start; 353 354 /* allow for HW to catch up */ 355 if (state->delay) 356 rte_delay_us_block(state->delay); 357 358 tsc_start = rte_rdtsc_precise(); 359 360 /* drain RX ring */ 361 pmd_cyclecount_bench_deq(state, iter_ops_needed, 362 test_burst_size); 363 364 tsc_end = rte_rdtsc_precise(); 365 366 tsc_deq += tsc_end - tsc_start; 367 368 cur_op += iter_ops_needed; 369 370 /* 371 * we may not have processed all ops that we allocated, so 372 * free everything we've allocated. 373 */ 374 rte_mempool_put_bulk(state->ctx->pool, 375 (void **)state->ctx->ops, iter_ops_allocd); 376 } 377 378 state->cycles_per_build = (double)tsc_op / state->opts->total_ops; 379 state->cycles_per_enq = (double)tsc_enq / state->ops_enqd; 380 state->cycles_per_deq = (double)tsc_deq / state->ops_deqd; 381 382 return 0; 383 } 384 385 int 386 cperf_pmd_cyclecount_test_runner(void *test_ctx) 387 { 388 struct pmd_cyclecount_state state = {0}; 389 const struct cperf_options *opts; 390 uint16_t test_burst_size; 391 uint8_t burst_size_idx = 0; 392 393 state.ctx = test_ctx; 394 opts = state.ctx->options; 395 state.opts = opts; 396 state.lcore = rte_lcore_id(); 397 state.linearize = 0; 398 399 static uint16_t display_once; 400 static bool warmup = true; 401 402 /* 403 * We need a small delay to allow for hardware to process all the crypto 404 * operations. We can't automatically figure out what the delay should 405 * be, so we leave it up to the user (by default it's 0). 406 */ 407 state.delay = 1000 * opts->pmdcc_delay; 408 409 #ifdef CPERF_LINEARIZATION_ENABLE 410 struct rte_cryptodev_info dev_info; 411 412 /* Check if source mbufs require coalescing */ 413 if (opts->segments_sz < ctx->options->max_buffer_size) { 414 rte_cryptodev_info_get(state.ctx->dev_id, &dev_info); 415 if ((dev_info.feature_flags & 416 RTE_CRYPTODEV_FF_MBUF_SCATTER_GATHER) == 417 0) { 418 state.linearize = 1; 419 } 420 } 421 #endif /* CPERF_LINEARIZATION_ENABLE */ 422 423 state.ctx->lcore_id = state.lcore; 424 425 /* Get first size from range or list */ 426 if (opts->inc_burst_size != 0) 427 test_burst_size = opts->min_burst_size; 428 else 429 test_burst_size = opts->burst_size_list[0]; 430 431 while (test_burst_size <= opts->max_burst_size) { 432 /* do a benchmark run */ 433 if (pmd_cyclecount_bench_burst_sz(&state, test_burst_size)) 434 return -1; 435 436 /* 437 * First run is always a warm up run. 438 */ 439 if (warmup) { 440 warmup = false; 441 continue; 442 } 443 444 uint16_t exp = 0; 445 if (!opts->csv) { 446 if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, 447 __ATOMIC_RELAXED, __ATOMIC_RELAXED)) 448 printf(PRETTY_HDR_FMT, "lcore id", "Buf Size", 449 "Burst Size", "Enqueued", 450 "Dequeued", "Enq Retries", 451 "Deq Retries", "Cycles/Op", 452 "Cycles/Enq", "Cycles/Deq"); 453 454 printf(PRETTY_LINE_FMT, state.ctx->lcore_id, 455 opts->test_buffer_size, test_burst_size, 456 state.ops_enqd, state.ops_deqd, 457 state.ops_enq_retries, 458 state.ops_deq_retries, 459 state.cycles_per_build, 460 state.cycles_per_enq, 461 state.cycles_per_deq); 462 } else { 463 if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, 464 __ATOMIC_RELAXED, __ATOMIC_RELAXED)) 465 printf(CSV_HDR_FMT, "# lcore id", "Buf Size", 466 "Burst Size", "Enqueued", 467 "Dequeued", "Enq Retries", 468 "Deq Retries", "Cycles/Op", 469 "Cycles/Enq", "Cycles/Deq"); 470 471 printf(CSV_LINE_FMT, state.ctx->lcore_id, 472 opts->test_buffer_size, test_burst_size, 473 state.ops_enqd, state.ops_deqd, 474 state.ops_enq_retries, 475 state.ops_deq_retries, 476 state.cycles_per_build, 477 state.cycles_per_enq, 478 state.cycles_per_deq); 479 } 480 481 /* Get next size from range or list */ 482 if (opts->inc_burst_size != 0) 483 test_burst_size += opts->inc_burst_size; 484 else { 485 if (++burst_size_idx == opts->burst_size_count) 486 break; 487 test_burst_size = opts->burst_size_list[burst_size_idx]; 488 } 489 } 490 491 return 0; 492 } 493 494 void 495 cperf_pmd_cyclecount_test_destructor(void *arg) 496 { 497 struct cperf_pmd_cyclecount_ctx *ctx = arg; 498 499 if (ctx == NULL) 500 return; 501 502 cperf_pmd_cyclecount_test_free(ctx); 503 } 504