1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2017 Intel Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Intel Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <stdbool.h> 34 35 #include <rte_crypto.h> 36 #include <rte_cryptodev.h> 37 #include <rte_cycles.h> 38 #include <rte_malloc.h> 39 40 #include "cperf_ops.h" 41 #include "cperf_test_pmd_cyclecount.h" 42 #include "cperf_test_common.h" 43 44 #define PRETTY_HDR_FMT "%12s%12s%12s%12s%12s%12s%12s%12s%12s%12s\n\n" 45 #define PRETTY_LINE_FMT "%12u%12u%12u%12u%12u%12u%12u%12.0f%12.0f%12.0f\n" 46 #define CSV_HDR_FMT "%s,%s,%s,%s,%s,%s,%s,%s,%s,%s\n" 47 #define CSV_LINE_FMT "%10u;%10u;%u;%u;%u;%u;%u;%.f3;%.f3;%.f3\n" 48 49 struct cperf_pmd_cyclecount_ctx { 50 uint8_t dev_id; 51 uint16_t qp_id; 52 uint8_t lcore_id; 53 54 struct rte_mempool *pool; 55 struct rte_crypto_op **ops; 56 struct rte_crypto_op **ops_processed; 57 58 struct rte_cryptodev_sym_session *sess; 59 60 cperf_populate_ops_t populate_ops; 61 62 uint32_t src_buf_offset; 63 uint32_t dst_buf_offset; 64 65 const struct cperf_options *options; 66 const struct cperf_test_vector *test_vector; 67 }; 68 69 struct pmd_cyclecount_state { 70 struct cperf_pmd_cyclecount_ctx *ctx; 71 const struct cperf_options *opts; 72 uint32_t lcore; 73 uint64_t delay; 74 int linearize; 75 uint32_t ops_enqd; 76 uint32_t ops_deqd; 77 uint32_t ops_enq_retries; 78 uint32_t ops_deq_retries; 79 double cycles_per_build; 80 double cycles_per_enq; 81 double cycles_per_deq; 82 }; 83 84 static const uint16_t iv_offset = 85 sizeof(struct rte_crypto_op) + sizeof(struct rte_crypto_sym_op); 86 87 static void 88 cperf_pmd_cyclecount_test_free(struct cperf_pmd_cyclecount_ctx *ctx) 89 { 90 if (ctx) { 91 if (ctx->sess) { 92 rte_cryptodev_sym_session_clear(ctx->dev_id, ctx->sess); 93 rte_cryptodev_sym_session_free(ctx->sess); 94 } 95 96 if (ctx->pool) 97 rte_mempool_free(ctx->pool); 98 99 if (ctx->ops) 100 rte_free(ctx->ops); 101 102 if (ctx->ops_processed) 103 rte_free(ctx->ops_processed); 104 105 rte_free(ctx); 106 } 107 } 108 109 void * 110 cperf_pmd_cyclecount_test_constructor(struct rte_mempool *sess_mp, 111 uint8_t dev_id, uint16_t qp_id, 112 const struct cperf_options *options, 113 const struct cperf_test_vector *test_vector, 114 const struct cperf_op_fns *op_fns) 115 { 116 struct cperf_pmd_cyclecount_ctx *ctx = NULL; 117 118 /* preallocate buffers for crypto ops as they can get quite big */ 119 size_t alloc_sz = sizeof(struct rte_crypto_op *) * 120 options->nb_descriptors; 121 122 ctx = rte_malloc(NULL, sizeof(struct cperf_pmd_cyclecount_ctx), 0); 123 if (ctx == NULL) 124 goto err; 125 126 ctx->dev_id = dev_id; 127 ctx->qp_id = qp_id; 128 129 ctx->populate_ops = op_fns->populate_ops; 130 ctx->options = options; 131 ctx->test_vector = test_vector; 132 133 /* IV goes at the end of the crypto operation */ 134 uint16_t iv_offset = sizeof(struct rte_crypto_op) + 135 sizeof(struct rte_crypto_sym_op); 136 137 ctx->sess = op_fns->sess_create( 138 sess_mp, dev_id, options, test_vector, iv_offset); 139 if (ctx->sess == NULL) 140 goto err; 141 142 if (cperf_alloc_common_memory(options, test_vector, dev_id, qp_id, 0, 143 &ctx->src_buf_offset, &ctx->dst_buf_offset, 144 &ctx->pool) < 0) 145 goto err; 146 147 ctx->ops = rte_malloc("ops", alloc_sz, 0); 148 if (!ctx->ops) 149 goto err; 150 151 ctx->ops_processed = rte_malloc("ops_processed", alloc_sz, 0); 152 if (!ctx->ops_processed) 153 goto err; 154 155 return ctx; 156 157 err: 158 cperf_pmd_cyclecount_test_free(ctx); 159 160 return NULL; 161 } 162 163 /* benchmark alloc-build-free of ops */ 164 static inline int 165 pmd_cyclecount_bench_ops(struct pmd_cyclecount_state *state, uint32_t cur_op, 166 uint16_t test_burst_size) 167 { 168 uint32_t iter_ops_left = state->opts->total_ops - cur_op; 169 uint32_t iter_ops_needed = 170 RTE_MIN(state->opts->nb_descriptors, iter_ops_left); 171 uint32_t cur_iter_op; 172 173 for (cur_iter_op = 0; cur_iter_op < iter_ops_needed; 174 cur_iter_op += test_burst_size) { 175 uint32_t burst_size = RTE_MIN(state->opts->total_ops - cur_op, 176 test_burst_size); 177 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op]; 178 179 /* Allocate objects containing crypto operations and mbufs */ 180 if (rte_mempool_get_bulk(state->ctx->pool, (void **)ops, 181 burst_size) != 0) { 182 RTE_LOG(ERR, USER1, 183 "Failed to allocate more crypto operations " 184 "from the the crypto operation pool.\n" 185 "Consider increasing the pool size " 186 "with --pool-sz\n"); 187 return -1; 188 } 189 190 /* Setup crypto op, attach mbuf etc */ 191 (state->ctx->populate_ops)(ops, 192 state->ctx->src_buf_offset, 193 state->ctx->dst_buf_offset, 194 burst_size, 195 state->ctx->sess, state->opts, 196 state->ctx->test_vector, iv_offset); 197 198 #ifdef CPERF_LINEARIZATION_ENABLE 199 /* Check if source mbufs require coalescing */ 200 if (state->linearize) { 201 uint8_t i; 202 for (i = 0; i < burst_size; i++) { 203 struct rte_mbuf *src = ops[i]->sym->m_src; 204 rte_pktmbuf_linearize(src); 205 } 206 } 207 #endif /* CPERF_LINEARIZATION_ENABLE */ 208 rte_mempool_put_bulk(state->ctx->pool, (void **)ops, 209 burst_size); 210 } 211 212 return 0; 213 } 214 215 /* allocate and build ops (no free) */ 216 static int 217 pmd_cyclecount_build_ops(struct pmd_cyclecount_state *state, 218 uint32_t iter_ops_needed, uint16_t test_burst_size) 219 { 220 uint32_t cur_iter_op; 221 222 for (cur_iter_op = 0; cur_iter_op < iter_ops_needed; 223 cur_iter_op += test_burst_size) { 224 uint32_t burst_size = RTE_MIN( 225 iter_ops_needed - cur_iter_op, test_burst_size); 226 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op]; 227 228 /* Allocate objects containing crypto operations and mbufs */ 229 if (rte_mempool_get_bulk(state->ctx->pool, (void **)ops, 230 burst_size) != 0) { 231 RTE_LOG(ERR, USER1, 232 "Failed to allocate more crypto operations " 233 "from the the crypto operation pool.\n" 234 "Consider increasing the pool size " 235 "with --pool-sz\n"); 236 return -1; 237 } 238 239 /* Setup crypto op, attach mbuf etc */ 240 (state->ctx->populate_ops)(ops, 241 state->ctx->src_buf_offset, 242 state->ctx->dst_buf_offset, 243 burst_size, 244 state->ctx->sess, state->opts, 245 state->ctx->test_vector, iv_offset); 246 } 247 return 0; 248 } 249 250 /* benchmark enqueue, returns number of ops enqueued */ 251 static uint32_t 252 pmd_cyclecount_bench_enq(struct pmd_cyclecount_state *state, 253 uint32_t iter_ops_needed, uint16_t test_burst_size) 254 { 255 /* Enqueue full descriptor ring of ops on crypto device */ 256 uint32_t cur_iter_op = 0; 257 while (cur_iter_op < iter_ops_needed) { 258 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op, 259 test_burst_size); 260 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op]; 261 uint32_t burst_enqd; 262 263 burst_enqd = rte_cryptodev_enqueue_burst(state->ctx->dev_id, 264 state->ctx->qp_id, ops, burst_size); 265 266 /* if we couldn't enqueue anything, the queue is full */ 267 if (!burst_enqd) { 268 /* don't try to dequeue anything we didn't enqueue */ 269 return cur_iter_op; 270 } 271 272 if (burst_enqd < burst_size) 273 state->ops_enq_retries++; 274 state->ops_enqd += burst_enqd; 275 cur_iter_op += burst_enqd; 276 } 277 return iter_ops_needed; 278 } 279 280 /* benchmark dequeue */ 281 static void 282 pmd_cyclecount_bench_deq(struct pmd_cyclecount_state *state, 283 uint32_t iter_ops_needed, uint16_t test_burst_size) 284 { 285 /* Dequeue full descriptor ring of ops on crypto device */ 286 uint32_t cur_iter_op = 0; 287 while (cur_iter_op < iter_ops_needed) { 288 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op, 289 test_burst_size); 290 struct rte_crypto_op **ops_processed = 291 &state->ctx->ops[cur_iter_op]; 292 uint32_t burst_deqd; 293 294 burst_deqd = rte_cryptodev_dequeue_burst(state->ctx->dev_id, 295 state->ctx->qp_id, ops_processed, burst_size); 296 297 if (burst_deqd < burst_size) 298 state->ops_deq_retries++; 299 state->ops_deqd += burst_deqd; 300 cur_iter_op += burst_deqd; 301 } 302 } 303 304 /* run benchmark per burst size */ 305 static inline int 306 pmd_cyclecount_bench_burst_sz( 307 struct pmd_cyclecount_state *state, uint16_t test_burst_size) 308 { 309 uint64_t tsc_start; 310 uint64_t tsc_end; 311 uint64_t tsc_op; 312 uint64_t tsc_enq; 313 uint64_t tsc_deq; 314 uint32_t cur_op; 315 316 /* reset all counters */ 317 tsc_enq = 0; 318 tsc_deq = 0; 319 state->ops_enqd = 0; 320 state->ops_enq_retries = 0; 321 state->ops_deqd = 0; 322 state->ops_deq_retries = 0; 323 324 /* 325 * Benchmark crypto op alloc-build-free separately. 326 */ 327 tsc_start = rte_rdtsc_precise(); 328 329 for (cur_op = 0; cur_op < state->opts->total_ops; 330 cur_op += state->opts->nb_descriptors) { 331 if (unlikely(pmd_cyclecount_bench_ops( 332 state, cur_op, test_burst_size))) 333 return -1; 334 } 335 336 tsc_end = rte_rdtsc_precise(); 337 tsc_op = tsc_end - tsc_start; 338 339 340 /* 341 * Hardware acceleration cyclecount benchmarking loop. 342 * 343 * We're benchmarking raw enq/deq performance by filling up the device 344 * queue, so we never get any failed enqs unless the driver won't accept 345 * the exact number of descriptors we requested, or the driver won't 346 * wrap around the end of the TX ring. However, since we're only 347 * dequeueing once we've filled up the queue, we have to benchmark it 348 * piecemeal and then average out the results. 349 */ 350 cur_op = 0; 351 while (cur_op < state->opts->total_ops) { 352 uint32_t iter_ops_left = state->opts->total_ops - cur_op; 353 uint32_t iter_ops_needed = RTE_MIN( 354 state->opts->nb_descriptors, iter_ops_left); 355 uint32_t iter_ops_allocd = iter_ops_needed; 356 357 /* allocate and build ops */ 358 if (unlikely(pmd_cyclecount_build_ops(state, iter_ops_needed, 359 test_burst_size))) 360 return -1; 361 362 tsc_start = rte_rdtsc_precise(); 363 364 /* fill up TX ring */ 365 iter_ops_needed = pmd_cyclecount_bench_enq(state, 366 iter_ops_needed, test_burst_size); 367 368 tsc_end = rte_rdtsc_precise(); 369 370 tsc_enq += tsc_end - tsc_start; 371 372 /* allow for HW to catch up */ 373 if (state->delay) 374 rte_delay_us_block(state->delay); 375 376 tsc_start = rte_rdtsc_precise(); 377 378 /* drain RX ring */ 379 pmd_cyclecount_bench_deq(state, iter_ops_needed, 380 test_burst_size); 381 382 tsc_end = rte_rdtsc_precise(); 383 384 tsc_deq += tsc_end - tsc_start; 385 386 cur_op += iter_ops_needed; 387 388 /* 389 * we may not have processed all ops that we allocated, so 390 * free everything we've allocated. 391 */ 392 rte_mempool_put_bulk(state->ctx->pool, 393 (void **)state->ctx->ops, iter_ops_allocd); 394 } 395 396 state->cycles_per_build = (double)tsc_op / state->opts->total_ops; 397 state->cycles_per_enq = (double)tsc_enq / state->ops_enqd; 398 state->cycles_per_deq = (double)tsc_deq / state->ops_deqd; 399 400 return 0; 401 } 402 403 int 404 cperf_pmd_cyclecount_test_runner(void *test_ctx) 405 { 406 struct pmd_cyclecount_state state = {0}; 407 const struct cperf_options *opts; 408 uint16_t test_burst_size; 409 uint8_t burst_size_idx = 0; 410 411 state.ctx = test_ctx; 412 opts = state.ctx->options; 413 state.opts = opts; 414 state.lcore = rte_lcore_id(); 415 state.linearize = 0; 416 417 static int only_once; 418 static bool warmup = true; 419 420 /* 421 * We need a small delay to allow for hardware to process all the crypto 422 * operations. We can't automatically figure out what the delay should 423 * be, so we leave it up to the user (by default it's 0). 424 */ 425 state.delay = 1000 * opts->pmdcc_delay; 426 427 #ifdef CPERF_LINEARIZATION_ENABLE 428 struct rte_cryptodev_info dev_info; 429 430 /* Check if source mbufs require coalescing */ 431 if (opts->segments_sz < ctx->options->max_buffer_size) { 432 rte_cryptodev_info_get(state.ctx->dev_id, &dev_info); 433 if ((dev_info.feature_flags & 434 RTE_CRYPTODEV_FF_MBUF_SCATTER_GATHER) == 435 0) { 436 state.linearize = 1; 437 } 438 } 439 #endif /* CPERF_LINEARIZATION_ENABLE */ 440 441 state.ctx->lcore_id = state.lcore; 442 443 /* Get first size from range or list */ 444 if (opts->inc_burst_size != 0) 445 test_burst_size = opts->min_burst_size; 446 else 447 test_burst_size = opts->burst_size_list[0]; 448 449 while (test_burst_size <= opts->max_burst_size) { 450 /* do a benchmark run */ 451 if (pmd_cyclecount_bench_burst_sz(&state, test_burst_size)) 452 return -1; 453 454 /* 455 * First run is always a warm up run. 456 */ 457 if (warmup) { 458 warmup = false; 459 continue; 460 } 461 462 if (!opts->csv) { 463 if (!only_once) 464 printf(PRETTY_HDR_FMT, "lcore id", "Buf Size", 465 "Burst Size", "Enqueued", 466 "Dequeued", "Enq Retries", 467 "Deq Retries", "Cycles/Op", 468 "Cycles/Enq", "Cycles/Deq"); 469 only_once = 1; 470 471 printf(PRETTY_LINE_FMT, state.ctx->lcore_id, 472 opts->test_buffer_size, test_burst_size, 473 state.ops_enqd, state.ops_deqd, 474 state.ops_enq_retries, 475 state.ops_deq_retries, 476 state.cycles_per_build, 477 state.cycles_per_enq, 478 state.cycles_per_deq); 479 } else { 480 if (!only_once) 481 printf(CSV_HDR_FMT, "# lcore id", "Buf Size", 482 "Burst Size", "Enqueued", 483 "Dequeued", "Enq Retries", 484 "Deq Retries", "Cycles/Op", 485 "Cycles/Enq", "Cycles/Deq"); 486 only_once = 1; 487 488 printf(CSV_LINE_FMT, state.ctx->lcore_id, 489 opts->test_buffer_size, test_burst_size, 490 state.ops_enqd, state.ops_deqd, 491 state.ops_enq_retries, 492 state.ops_deq_retries, 493 state.cycles_per_build, 494 state.cycles_per_enq, 495 state.cycles_per_deq); 496 } 497 498 /* Get next size from range or list */ 499 if (opts->inc_burst_size != 0) 500 test_burst_size += opts->inc_burst_size; 501 else { 502 if (++burst_size_idx == opts->burst_size_count) 503 break; 504 test_burst_size = opts->burst_size_list[burst_size_idx]; 505 } 506 } 507 508 return 0; 509 } 510 511 void 512 cperf_pmd_cyclecount_test_destructor(void *arg) 513 { 514 struct cperf_pmd_cyclecount_ctx *ctx = arg; 515 516 if (ctx == NULL) 517 return; 518 519 cperf_pmd_cyclecount_test_free(ctx); 520 } 521