1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz and Don Ahn. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $ 39 */ 40 41 /* 42 * Routines to handle clock hardware. 43 */ 44 45 /* 46 * inittodr, settodr and support routines written 47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 48 * 49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 50 */ 51 52 #if 0 53 #include "opt_clock.h" 54 #endif 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/eventhandler.h> 59 #include <sys/time.h> 60 #include <sys/kernel.h> 61 #include <sys/bus.h> 62 #include <sys/sysctl.h> 63 #include <sys/cons.h> 64 #include <sys/systimer.h> 65 #include <sys/globaldata.h> 66 #include <sys/thread2.h> 67 #include <sys/systimer.h> 68 #include <sys/machintr.h> 69 #include <sys/interrupt.h> 70 71 #include <machine/clock.h> 72 #include <machine/cputypes.h> 73 #include <machine/frame.h> 74 #include <machine/ipl.h> 75 #include <machine/limits.h> 76 #include <machine/md_var.h> 77 #include <machine/psl.h> 78 #include <machine/segments.h> 79 #include <machine/smp.h> 80 #include <machine/specialreg.h> 81 #include <machine/intr_machdep.h> 82 83 #include <machine_base/apic/ioapic.h> 84 #include <machine_base/apic/ioapic_abi.h> 85 #include <machine_base/icu/icu.h> 86 #include <bus/isa/isa.h> 87 #include <bus/isa/rtc.h> 88 #include <machine_base/isa/timerreg.h> 89 90 static void i8254_restore(void); 91 static void resettodr_on_shutdown(void *arg __unused); 92 93 /* 94 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 95 * can use a simple formula for leap years. 96 */ 97 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 98 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 99 100 #ifndef TIMER_FREQ 101 #define TIMER_FREQ 1193182 102 #endif 103 104 static uint8_t i8254_walltimer_sel; 105 static uint16_t i8254_walltimer_cntr; 106 107 int adjkerntz; /* local offset from GMT in seconds */ 108 int disable_rtc_set; /* disable resettodr() if != 0 */ 109 int tsc_present; 110 int64_t tsc_frequency; 111 int tsc_is_broken; 112 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 113 int timer0_running; 114 enum tstate { RELEASED, ACQUIRED }; 115 enum tstate timer0_state; 116 enum tstate timer1_state; 117 enum tstate timer2_state; 118 119 static int beeping = 0; 120 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 121 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 122 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 123 static int rtc_loaded; 124 125 static int i8254_cputimer_div; 126 127 static int i8254_nointr; 128 static int i8254_intr_disable = 1; 129 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable); 130 131 static struct callout sysbeepstop_ch; 132 133 static sysclock_t i8254_cputimer_count(void); 134 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last); 135 static void i8254_cputimer_destruct(struct cputimer *cputimer); 136 137 static struct cputimer i8254_cputimer = { 138 SLIST_ENTRY_INITIALIZER, 139 "i8254", 140 CPUTIMER_PRI_8254, 141 0, 142 i8254_cputimer_count, 143 cputimer_default_fromhz, 144 cputimer_default_fromus, 145 i8254_cputimer_construct, 146 i8254_cputimer_destruct, 147 TIMER_FREQ, 148 0, 0, 0 149 }; 150 151 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t); 152 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *); 153 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t); 154 155 static struct cputimer_intr i8254_cputimer_intr = { 156 .freq = TIMER_FREQ, 157 .reload = i8254_intr_reload, 158 .enable = cputimer_intr_default_enable, 159 .config = i8254_intr_config, 160 .restart = cputimer_intr_default_restart, 161 .pmfixup = cputimer_intr_default_pmfixup, 162 .initclock = i8254_intr_initclock, 163 .next = SLIST_ENTRY_INITIALIZER, 164 .name = "i8254", 165 .type = CPUTIMER_INTR_8254, 166 .prio = CPUTIMER_INTR_PRIO_8254, 167 .caps = CPUTIMER_INTR_CAP_PS 168 }; 169 170 /* 171 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped 172 * counting as of this interrupt. We use timer1 in free-running mode (not 173 * generating any interrupts) as our main counter. Each cpu has timeouts 174 * pending. 175 * 176 * This code is INTR_MPSAFE and may be called without the BGL held. 177 */ 178 static void 179 clkintr(void *dummy, void *frame_arg) 180 { 181 static sysclock_t sysclock_count; /* NOTE! Must be static */ 182 struct globaldata *gd = mycpu; 183 struct globaldata *gscan; 184 int n; 185 186 /* 187 * SWSTROBE mode is a one-shot, the timer is no longer running 188 */ 189 timer0_running = 0; 190 191 /* 192 * XXX the dispatcher needs work. right now we call systimer_intr() 193 * directly or via IPI for any cpu with systimers queued, which is 194 * usually *ALL* of them. We need to use the LAPIC timer for this. 195 */ 196 sysclock_count = sys_cputimer->count(); 197 for (n = 0; n < ncpus; ++n) { 198 gscan = globaldata_find(n); 199 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL) 200 continue; 201 if (gscan != gd) { 202 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 203 &sysclock_count, 1); 204 } else { 205 systimer_intr(&sysclock_count, 0, frame_arg); 206 } 207 } 208 } 209 210 211 /* 212 * NOTE! not MP safe. 213 */ 214 int 215 acquire_timer2(int mode) 216 { 217 if (timer2_state != RELEASED) 218 return (-1); 219 timer2_state = ACQUIRED; 220 221 /* 222 * This access to the timer registers is as atomic as possible 223 * because it is a single instruction. We could do better if we 224 * knew the rate. 225 */ 226 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 227 return (0); 228 } 229 230 int 231 release_timer2(void) 232 { 233 if (timer2_state != ACQUIRED) 234 return (-1); 235 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 236 timer2_state = RELEASED; 237 return (0); 238 } 239 240 #include "opt_ddb.h" 241 #ifdef DDB 242 #include <ddb/ddb.h> 243 244 DB_SHOW_COMMAND(rtc, rtc) 245 { 246 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 247 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 248 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 249 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 250 } 251 #endif /* DDB */ 252 253 /* 254 * Return the current cpu timer count as a 32 bit integer. 255 */ 256 static 257 sysclock_t 258 i8254_cputimer_count(void) 259 { 260 static __uint16_t cputimer_last; 261 __uint16_t count; 262 sysclock_t ret; 263 264 clock_lock(); 265 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH); 266 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */ 267 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8); 268 count = -count; /* -> countup */ 269 if (count < cputimer_last) /* rollover */ 270 i8254_cputimer.base += 0x00010000; 271 ret = i8254_cputimer.base | count; 272 cputimer_last = count; 273 clock_unlock(); 274 return(ret); 275 } 276 277 /* 278 * This function is called whenever the system timebase changes, allowing 279 * us to calculate what is needed to convert a system timebase tick 280 * into an 8254 tick for the interrupt timer. If we can convert to a 281 * simple shift, multiplication, or division, we do so. Otherwise 64 282 * bit arithmatic is required every time the interrupt timer is reloaded. 283 */ 284 static void 285 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer) 286 { 287 int freq; 288 int div; 289 290 /* 291 * Will a simple divide do the trick? 292 */ 293 div = (timer->freq + (cti->freq / 2)) / cti->freq; 294 freq = cti->freq * div; 295 296 if (freq >= timer->freq - 1 && freq <= timer->freq + 1) 297 i8254_cputimer_div = div; 298 else 299 i8254_cputimer_div = 0; 300 } 301 302 /* 303 * Reload for the next timeout. It is possible for the reload value 304 * to be 0 or negative, indicating that an immediate timer interrupt 305 * is desired. For now make the minimum 2 ticks. 306 * 307 * We may have to convert from the system timebase to the 8254 timebase. 308 */ 309 static void 310 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 311 { 312 __uint16_t count; 313 314 if (i8254_cputimer_div) 315 reload /= i8254_cputimer_div; 316 else 317 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 318 319 if ((int)reload < 2) 320 reload = 2; 321 322 clock_lock(); 323 if (timer0_running) { 324 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */ 325 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */ 326 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */ 327 if (reload < count) { 328 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 329 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 330 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 331 } 332 } else { 333 timer0_running = 1; 334 if (reload > 0xFFFF) 335 reload = 0; /* full count */ 336 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 337 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 338 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 339 } 340 clock_unlock(); 341 } 342 343 /* 344 * DELAY(usec) - Spin for the specified number of microseconds. 345 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds, 346 * but do a thread switch in the loop 347 * 348 * Relies on timer 1 counting down from (cputimer_freq / hz) 349 * Note: timer had better have been programmed before this is first used! 350 */ 351 static void 352 DODELAY(int n, int doswitch) 353 { 354 int delta, prev_tick, tick, ticks_left; 355 356 #ifdef DELAYDEBUG 357 int getit_calls = 1; 358 int n1; 359 static int state = 0; 360 361 if (state == 0) { 362 state = 1; 363 for (n1 = 1; n1 <= 10000000; n1 *= 10) 364 DELAY(n1); 365 state = 2; 366 } 367 if (state == 1) 368 kprintf("DELAY(%d)...", n); 369 #endif 370 /* 371 * Guard against the timer being uninitialized if we are called 372 * early for console i/o. 373 */ 374 if (timer0_state == RELEASED) 375 i8254_restore(); 376 377 /* 378 * Read the counter first, so that the rest of the setup overhead is 379 * counted. Then calculate the number of hardware timer ticks 380 * required, rounding up to be sure we delay at least the requested 381 * number of microseconds. 382 */ 383 prev_tick = sys_cputimer->count(); 384 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) / 385 1000000; 386 387 /* 388 * Loop until done. 389 */ 390 while (ticks_left > 0) { 391 tick = sys_cputimer->count(); 392 #ifdef DELAYDEBUG 393 ++getit_calls; 394 #endif 395 delta = tick - prev_tick; 396 prev_tick = tick; 397 if (delta < 0) 398 delta = 0; 399 ticks_left -= delta; 400 if (doswitch && ticks_left > 0) 401 lwkt_switch(); 402 cpu_pause(); 403 } 404 #ifdef DELAYDEBUG 405 if (state == 1) 406 kprintf(" %d calls to getit() at %d usec each\n", 407 getit_calls, (n + 5) / getit_calls); 408 #endif 409 } 410 411 /* 412 * DELAY() never switches. 413 */ 414 void 415 DELAY(int n) 416 { 417 DODELAY(n, 0); 418 } 419 420 /* 421 * Returns non-zero if the specified time period has elapsed. Call 422 * first with last_clock set to 0. 423 */ 424 int 425 CHECKTIMEOUT(TOTALDELAY *tdd) 426 { 427 sysclock_t delta; 428 int us; 429 430 if (tdd->started == 0) { 431 if (timer0_state == RELEASED) 432 i8254_restore(); 433 tdd->last_clock = sys_cputimer->count(); 434 tdd->started = 1; 435 return(0); 436 } 437 delta = sys_cputimer->count() - tdd->last_clock; 438 us = (u_int64_t)delta * (u_int64_t)1000000 / 439 (u_int64_t)sys_cputimer->freq; 440 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq / 441 1000000; 442 tdd->us -= us; 443 return (tdd->us < 0); 444 } 445 446 447 /* 448 * DRIVERSLEEP() does not switch if called with a spinlock held or 449 * from a hard interrupt. 450 */ 451 void 452 DRIVERSLEEP(int usec) 453 { 454 globaldata_t gd = mycpu; 455 456 if (gd->gd_intr_nesting_level || gd->gd_spinlocks) { 457 DODELAY(usec, 0); 458 } else { 459 DODELAY(usec, 1); 460 } 461 } 462 463 static void 464 sysbeepstop(void *chan) 465 { 466 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 467 beeping = 0; 468 release_timer2(); 469 } 470 471 int 472 sysbeep(int pitch, int period) 473 { 474 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 475 return(-1); 476 if (sysbeep_enable == 0) 477 return(-1); 478 /* 479 * Nobody else is using timer2, we do not need the clock lock 480 */ 481 outb(TIMER_CNTR2, pitch); 482 outb(TIMER_CNTR2, (pitch>>8)); 483 if (!beeping) { 484 /* enable counter2 output to speaker */ 485 outb(IO_PPI, inb(IO_PPI) | 3); 486 beeping = period; 487 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL); 488 } 489 return (0); 490 } 491 492 /* 493 * RTC support routines 494 */ 495 496 int 497 rtcin(int reg) 498 { 499 u_char val; 500 501 crit_enter(); 502 outb(IO_RTC, reg); 503 inb(0x84); 504 val = inb(IO_RTC + 1); 505 inb(0x84); 506 crit_exit(); 507 return (val); 508 } 509 510 static __inline void 511 writertc(u_char reg, u_char val) 512 { 513 crit_enter(); 514 inb(0x84); 515 outb(IO_RTC, reg); 516 inb(0x84); 517 outb(IO_RTC + 1, val); 518 inb(0x84); /* XXX work around wrong order in rtcin() */ 519 crit_exit(); 520 } 521 522 static __inline int 523 readrtc(int port) 524 { 525 return(bcd2bin(rtcin(port))); 526 } 527 528 static u_int 529 calibrate_clocks(void) 530 { 531 u_int64_t old_tsc; 532 u_int count, prev_count, tot_count; 533 int sec, start_sec, timeout; 534 535 if (bootverbose) 536 kprintf("Calibrating clock(s) ... "); 537 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 538 goto fail; 539 timeout = 100000000; 540 541 /* Read the mc146818A seconds counter. */ 542 for (;;) { 543 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 544 sec = rtcin(RTC_SEC); 545 break; 546 } 547 if (--timeout == 0) 548 goto fail; 549 } 550 551 /* Wait for the mC146818A seconds counter to change. */ 552 start_sec = sec; 553 for (;;) { 554 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 555 sec = rtcin(RTC_SEC); 556 if (sec != start_sec) 557 break; 558 } 559 if (--timeout == 0) 560 goto fail; 561 } 562 563 /* Start keeping track of the i8254 counter. */ 564 prev_count = sys_cputimer->count(); 565 tot_count = 0; 566 567 if (tsc_present) 568 old_tsc = rdtsc(); 569 else 570 old_tsc = 0; /* shut up gcc */ 571 572 /* 573 * Wait for the mc146818A seconds counter to change. Read the i8254 574 * counter for each iteration since this is convenient and only 575 * costs a few usec of inaccuracy. The timing of the final reads 576 * of the counters almost matches the timing of the initial reads, 577 * so the main cause of inaccuracy is the varying latency from 578 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 579 * rtcin(RTC_SEC) that returns a changed seconds count. The 580 * maximum inaccuracy from this cause is < 10 usec on 486's. 581 */ 582 start_sec = sec; 583 for (;;) { 584 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 585 sec = rtcin(RTC_SEC); 586 count = sys_cputimer->count(); 587 tot_count += (int)(count - prev_count); 588 prev_count = count; 589 if (sec != start_sec) 590 break; 591 if (--timeout == 0) 592 goto fail; 593 } 594 595 /* 596 * Read the cpu cycle counter. The timing considerations are 597 * similar to those for the i8254 clock. 598 */ 599 if (tsc_present) { 600 tsc_frequency = rdtsc() - old_tsc; 601 } 602 603 if (tsc_present) 604 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency); 605 kprintf("i8254 clock: %u Hz\n", tot_count); 606 return (tot_count); 607 608 fail: 609 kprintf("failed, using default i8254 clock of %u Hz\n", 610 i8254_cputimer.freq); 611 return (i8254_cputimer.freq); 612 } 613 614 static void 615 i8254_restore(void) 616 { 617 timer0_state = ACQUIRED; 618 619 clock_lock(); 620 621 /* 622 * Timer0 is our fine-grained variable clock interrupt 623 */ 624 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 625 outb(TIMER_CNTR0, 2); /* lsb */ 626 outb(TIMER_CNTR0, 0); /* msb */ 627 clock_unlock(); 628 629 if (!i8254_nointr) { 630 cputimer_intr_register(&i8254_cputimer_intr); 631 cputimer_intr_select(&i8254_cputimer_intr, 0); 632 } 633 634 /* 635 * Timer1 or timer2 is our free-running clock, but only if another 636 * has not been selected. 637 */ 638 cputimer_register(&i8254_cputimer); 639 cputimer_select(&i8254_cputimer, 0); 640 } 641 642 static void 643 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 644 { 645 int which; 646 647 /* 648 * Should we use timer 1 or timer 2 ? 649 */ 650 which = 0; 651 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which); 652 if (which != 1 && which != 2) 653 which = 2; 654 655 switch(which) { 656 case 1: 657 timer->name = "i8254_timer1"; 658 timer->type = CPUTIMER_8254_SEL1; 659 i8254_walltimer_sel = TIMER_SEL1; 660 i8254_walltimer_cntr = TIMER_CNTR1; 661 timer1_state = ACQUIRED; 662 break; 663 case 2: 664 timer->name = "i8254_timer2"; 665 timer->type = CPUTIMER_8254_SEL2; 666 i8254_walltimer_sel = TIMER_SEL2; 667 i8254_walltimer_cntr = TIMER_CNTR2; 668 timer2_state = ACQUIRED; 669 break; 670 } 671 672 timer->base = (oldclock + 0xFFFF) & ~0xFFFF; 673 674 clock_lock(); 675 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT); 676 outb(i8254_walltimer_cntr, 0); /* lsb */ 677 outb(i8254_walltimer_cntr, 0); /* msb */ 678 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */ 679 clock_unlock(); 680 } 681 682 static void 683 i8254_cputimer_destruct(struct cputimer *timer) 684 { 685 switch(timer->type) { 686 case CPUTIMER_8254_SEL1: 687 timer1_state = RELEASED; 688 break; 689 case CPUTIMER_8254_SEL2: 690 timer2_state = RELEASED; 691 break; 692 default: 693 break; 694 } 695 timer->type = 0; 696 } 697 698 static void 699 rtc_restore(void) 700 { 701 /* Restore all of the RTC's "status" (actually, control) registers. */ 702 writertc(RTC_STATUSB, RTCSB_24HR); 703 writertc(RTC_STATUSA, rtc_statusa); 704 writertc(RTC_STATUSB, rtc_statusb); 705 } 706 707 /* 708 * Restore all the timers. 709 * 710 * This function is called to resynchronize our core timekeeping after a 711 * long halt, e.g. from apm_default_resume() and friends. It is also 712 * called if after a BIOS call we have detected munging of the 8254. 713 * It is necessary because cputimer_count() counter's delta may have grown 714 * too large for nanouptime() and friends to handle, or (in the case of 8254 715 * munging) might cause the SYSTIMER code to prematurely trigger. 716 */ 717 void 718 timer_restore(void) 719 { 720 crit_enter(); 721 i8254_restore(); /* restore timer_freq and hz */ 722 rtc_restore(); /* reenable RTC interrupts */ 723 crit_exit(); 724 } 725 726 /* 727 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 728 */ 729 void 730 startrtclock(void) 731 { 732 u_int delta, freq; 733 734 /* 735 * Can we use the TSC? 736 */ 737 if (cpu_feature & CPUID_TSC) 738 tsc_present = 1; 739 else 740 tsc_present = 0; 741 742 /* 743 * Initial RTC state, don't do anything unexpected 744 */ 745 writertc(RTC_STATUSA, rtc_statusa); 746 writertc(RTC_STATUSB, RTCSB_24HR); 747 748 /* 749 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 750 * generate an interrupt, which we will ignore for now. 751 * 752 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000 753 * (so it counts a full 2^16 and repeats). We will use this timer 754 * for our counting. 755 */ 756 i8254_restore(); 757 freq = calibrate_clocks(); 758 #ifdef CLK_CALIBRATION_LOOP 759 if (bootverbose) { 760 kprintf( 761 "Press a key on the console to abort clock calibration\n"); 762 while (cncheckc() == -1) 763 calibrate_clocks(); 764 } 765 #endif 766 767 /* 768 * Use the calibrated i8254 frequency if it seems reasonable. 769 * Otherwise use the default, and don't use the calibrated i586 770 * frequency. 771 */ 772 delta = freq > i8254_cputimer.freq ? 773 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq; 774 if (delta < i8254_cputimer.freq / 100) { 775 #ifndef CLK_USE_I8254_CALIBRATION 776 if (bootverbose) 777 kprintf( 778 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 779 freq = i8254_cputimer.freq; 780 #endif 781 /* 782 * NOTE: 783 * Interrupt timer's freq must be adjusted 784 * before we change the cuptimer's frequency. 785 */ 786 i8254_cputimer_intr.freq = freq; 787 cputimer_set_frequency(&i8254_cputimer, freq); 788 } else { 789 if (bootverbose) 790 kprintf( 791 "%d Hz differs from default of %d Hz by more than 1%%\n", 792 freq, i8254_cputimer.freq); 793 tsc_frequency = 0; 794 } 795 796 #ifndef CLK_USE_TSC_CALIBRATION 797 if (tsc_frequency != 0) { 798 if (bootverbose) 799 kprintf( 800 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 801 tsc_frequency = 0; 802 } 803 #endif 804 if (tsc_present && tsc_frequency == 0) { 805 /* 806 * Calibration of the i586 clock relative to the mc146818A 807 * clock failed. Do a less accurate calibration relative 808 * to the i8254 clock. 809 */ 810 u_int64_t old_tsc = rdtsc(); 811 812 DELAY(1000000); 813 tsc_frequency = rdtsc() - old_tsc; 814 #ifdef CLK_USE_TSC_CALIBRATION 815 if (bootverbose) { 816 kprintf("TSC clock: %llu Hz (Method B)\n", 817 tsc_frequency); 818 } 819 #endif 820 } 821 822 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST); 823 } 824 825 /* 826 * Sync the time of day back to the RTC on shutdown, but only if 827 * we have already loaded it and have not crashed. 828 */ 829 static void 830 resettodr_on_shutdown(void *arg __unused) 831 { 832 if (rtc_loaded && panicstr == NULL) { 833 resettodr(); 834 } 835 } 836 837 /* 838 * Initialize the time of day register, based on the time base which is, e.g. 839 * from a filesystem. 840 */ 841 void 842 inittodr(time_t base) 843 { 844 unsigned long sec, days; 845 int year, month; 846 int y, m; 847 struct timespec ts; 848 849 if (base) { 850 ts.tv_sec = base; 851 ts.tv_nsec = 0; 852 set_timeofday(&ts); 853 } 854 855 /* Look if we have a RTC present and the time is valid */ 856 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 857 goto wrong_time; 858 859 /* wait for time update to complete */ 860 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 861 crit_enter(); 862 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 863 crit_exit(); 864 crit_enter(); 865 } 866 867 days = 0; 868 #ifdef USE_RTC_CENTURY 869 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 870 #else 871 year = readrtc(RTC_YEAR) + 1900; 872 if (year < 1970) 873 year += 100; 874 #endif 875 if (year < 1970) { 876 crit_exit(); 877 goto wrong_time; 878 } 879 month = readrtc(RTC_MONTH); 880 for (m = 1; m < month; m++) 881 days += daysinmonth[m-1]; 882 if ((month > 2) && LEAPYEAR(year)) 883 days ++; 884 days += readrtc(RTC_DAY) - 1; 885 for (y = 1970; y < year; y++) 886 days += DAYSPERYEAR + LEAPYEAR(y); 887 sec = ((( days * 24 + 888 readrtc(RTC_HRS)) * 60 + 889 readrtc(RTC_MIN)) * 60 + 890 readrtc(RTC_SEC)); 891 /* sec now contains the number of seconds, since Jan 1 1970, 892 in the local time zone */ 893 894 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 895 896 y = time_second - sec; 897 if (y <= -2 || y >= 2) { 898 /* badly off, adjust it */ 899 ts.tv_sec = sec; 900 ts.tv_nsec = 0; 901 set_timeofday(&ts); 902 } 903 rtc_loaded = 1; 904 crit_exit(); 905 return; 906 907 wrong_time: 908 kprintf("Invalid time in real time clock.\n"); 909 kprintf("Check and reset the date immediately!\n"); 910 } 911 912 /* 913 * Write system time back to RTC 914 */ 915 void 916 resettodr(void) 917 { 918 struct timeval tv; 919 unsigned long tm; 920 int m; 921 int y; 922 923 if (disable_rtc_set) 924 return; 925 926 microtime(&tv); 927 tm = tv.tv_sec; 928 929 crit_enter(); 930 /* Disable RTC updates and interrupts. */ 931 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 932 933 /* Calculate local time to put in RTC */ 934 935 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 936 937 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 938 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 939 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 940 941 /* We have now the days since 01-01-1970 in tm */ 942 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 943 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 944 tm >= m; 945 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 946 tm -= m; 947 948 /* Now we have the years in y and the day-of-the-year in tm */ 949 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 950 #ifdef USE_RTC_CENTURY 951 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 952 #endif 953 for (m = 0; ; m++) { 954 int ml; 955 956 ml = daysinmonth[m]; 957 if (m == 1 && LEAPYEAR(y)) 958 ml++; 959 if (tm < ml) 960 break; 961 tm -= ml; 962 } 963 964 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 965 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 966 967 /* Reenable RTC updates and interrupts. */ 968 writertc(RTC_STATUSB, rtc_statusb); 969 crit_exit(); 970 } 971 972 static int 973 i8254_ioapic_trial(int irq, struct cputimer_intr *cti) 974 { 975 sysclock_t base; 976 long lastcnt; 977 978 /* 979 * Following code assumes the 8254 is the cpu timer, 980 * so make sure it is. 981 */ 982 KKASSERT(sys_cputimer == &i8254_cputimer); 983 KKASSERT(cti == &i8254_cputimer_intr); 984 985 lastcnt = get_interrupt_counter(irq, mycpuid); 986 987 /* 988 * Force an 8254 Timer0 interrupt and wait 1/100s for 989 * it to happen, then see if we got it. 990 */ 991 kprintf("IOAPIC: testing 8254 interrupt delivery\n"); 992 993 i8254_intr_reload(cti, 2); 994 base = sys_cputimer->count(); 995 while (sys_cputimer->count() - base < sys_cputimer->freq / 100) 996 ; /* nothing */ 997 998 if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0) 999 return ENOENT; 1000 return 0; 1001 } 1002 1003 /* 1004 * Start both clocks running. DragonFly note: the stat clock is no longer 1005 * used. Instead, 8254 based systimers are used for all major clock 1006 * interrupts. 1007 */ 1008 static void 1009 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected) 1010 { 1011 void *clkdesc = NULL; 1012 int irq = 0, mixed_mode = 0, error; 1013 1014 KKASSERT(mycpuid == 0); 1015 callout_init_mp(&sysbeepstop_ch); 1016 1017 if (!selected && i8254_intr_disable) 1018 goto nointr; 1019 1020 /* 1021 * The stat interrupt mask is different without the 1022 * statistics clock. Also, don't set the interrupt 1023 * flag which would normally cause the RTC to generate 1024 * interrupts. 1025 */ 1026 rtc_statusb = RTCSB_24HR; 1027 1028 /* Finish initializing 8254 timer 0. */ 1029 if (ioapic_enable) { 1030 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE, 1031 INTR_POLARITY_HIGH); 1032 if (irq < 0) { 1033 mixed_mode_setup: 1034 error = ioapic_conf_legacy_extint(0); 1035 if (!error) { 1036 irq = machintr_legacy_intr_find(0, 1037 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH); 1038 if (irq < 0) 1039 error = ENOENT; 1040 } 1041 1042 if (error) { 1043 if (!selected) { 1044 kprintf("IOAPIC: setup mixed mode for " 1045 "irq 0 failed: %d\n", error); 1046 goto nointr; 1047 } else { 1048 panic("IOAPIC: setup mixed mode for " 1049 "irq 0 failed: %d\n", error); 1050 } 1051 } 1052 mixed_mode = 1; 1053 } 1054 clkdesc = register_int(irq, clkintr, NULL, "clk", 1055 NULL, 1056 INTR_EXCL | INTR_CLOCK | 1057 INTR_NOPOLL | INTR_MPSAFE | 1058 INTR_NOENTROPY, 0); 1059 } else { 1060 register_int(0, clkintr, NULL, "clk", NULL, 1061 INTR_EXCL | INTR_CLOCK | 1062 INTR_NOPOLL | INTR_MPSAFE | 1063 INTR_NOENTROPY, 0); 1064 } 1065 1066 /* Initialize RTC. */ 1067 writertc(RTC_STATUSA, rtc_statusa); 1068 writertc(RTC_STATUSB, RTCSB_24HR); 1069 1070 if (ioapic_enable) { 1071 error = i8254_ioapic_trial(irq, cti); 1072 if (error) { 1073 if (mixed_mode) { 1074 if (!selected) { 1075 kprintf("IOAPIC: mixed mode for irq %d " 1076 "trial failed: %d\n", 1077 irq, error); 1078 goto nointr; 1079 } else { 1080 panic("IOAPIC: mixed mode for irq %d " 1081 "trial failed: %d\n", irq, error); 1082 } 1083 } else { 1084 kprintf("IOAPIC: warning 8254 is not connected " 1085 "to the correct pin, try mixed mode\n"); 1086 unregister_int(clkdesc, 0); 1087 goto mixed_mode_setup; 1088 } 1089 } 1090 } 1091 return; 1092 1093 nointr: 1094 i8254_nointr = 1; /* don't try to register again */ 1095 cputimer_intr_deregister(cti); 1096 } 1097 1098 void 1099 setstatclockrate(int newhz) 1100 { 1101 if (newhz == RTC_PROFRATE) 1102 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1103 else 1104 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1105 writertc(RTC_STATUSA, rtc_statusa); 1106 } 1107 1108 #if 0 1109 static unsigned 1110 tsc_get_timecount(struct timecounter *tc) 1111 { 1112 return (rdtsc()); 1113 } 1114 #endif 1115 1116 #ifdef KERN_TIMESTAMP 1117 #define KERN_TIMESTAMP_SIZE 16384 1118 static u_long tsc[KERN_TIMESTAMP_SIZE] ; 1119 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc, 1120 sizeof(tsc), "LU", "Kernel timestamps"); 1121 void 1122 _TSTMP(u_int32_t x) 1123 { 1124 static int i; 1125 1126 tsc[i] = (u_int32_t)rdtsc(); 1127 tsc[i+1] = x; 1128 i = i + 2; 1129 if (i >= KERN_TIMESTAMP_SIZE) 1130 i = 0; 1131 tsc[i] = 0; /* mark last entry */ 1132 } 1133 #endif /* KERN_TIMESTAMP */ 1134 1135 /* 1136 * 1137 */ 1138 1139 static int 1140 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS) 1141 { 1142 sysclock_t count; 1143 __uint64_t tscval; 1144 char buf[32]; 1145 1146 crit_enter(); 1147 if (sys_cputimer == &i8254_cputimer) 1148 count = sys_cputimer->count(); 1149 else 1150 count = 0; 1151 if (tsc_present) 1152 tscval = rdtsc(); 1153 else 1154 tscval = 0; 1155 crit_exit(); 1156 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval); 1157 return(SYSCTL_OUT(req, buf, strlen(buf) + 1)); 1158 } 1159 1160 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254"); 1161 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0, 1162 "frequency"); 1163 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD, 1164 0, 0, hw_i8254_timestamp, "A", ""); 1165 1166 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD, 1167 &tsc_present, 0, "TSC Available"); 1168 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD, 1169 &tsc_frequency, 0, "TSC Frequency"); 1170 1171