1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz and Don Ahn. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $ 39 */ 40 41 /* 42 * Routines to handle clock hardware. 43 */ 44 45 /* 46 * inittodr, settodr and support routines written 47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 48 * 49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 50 */ 51 52 #if 0 53 #include "use_apm.h" 54 #include "opt_clock.h" 55 #endif 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/eventhandler.h> 60 #include <sys/time.h> 61 #include <sys/kernel.h> 62 #include <sys/bus.h> 63 #ifndef SMP 64 #include <sys/lock.h> 65 #endif 66 #include <sys/sysctl.h> 67 #include <sys/cons.h> 68 #include <sys/systimer.h> 69 #include <sys/globaldata.h> 70 #include <sys/thread2.h> 71 #include <sys/systimer.h> 72 #include <sys/machintr.h> 73 74 #include <machine/clock.h> 75 #ifdef CLK_CALIBRATION_LOOP 76 #endif 77 #include <machine/cputypes.h> 78 #include <machine/frame.h> 79 #include <machine/ipl.h> 80 #include <machine/limits.h> 81 #include <machine/md_var.h> 82 #include <machine/psl.h> 83 #include <machine/segments.h> 84 #include <machine/smp.h> 85 #include <machine/specialreg.h> 86 87 #include <machine_base/icu/icu.h> 88 #include <bus/isa/isa.h> 89 #include <bus/isa/rtc.h> 90 #include <machine_base/isa/timerreg.h> 91 92 #include <machine_base/isa/intr_machdep.h> 93 94 #ifdef SMP /* APIC-IO */ 95 /* The interrupt triggered by the 8254 (timer) chip */ 96 int apic_8254_intr; 97 static void setup_8254_mixed_mode (void); 98 #endif 99 static void i8254_restore(void); 100 static void resettodr_on_shutdown(void *arg __unused); 101 102 /* 103 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 104 * can use a simple formula for leap years. 105 */ 106 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 107 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 108 109 #ifndef TIMER_FREQ 110 #define TIMER_FREQ 1193182 111 #endif 112 113 static uint8_t i8254_walltimer_sel; 114 static uint16_t i8254_walltimer_cntr; 115 116 int adjkerntz; /* local offset from GMT in seconds */ 117 int disable_rtc_set; /* disable resettodr() if != 0 */ 118 int tsc_present; 119 int64_t tsc_frequency; 120 int tsc_is_broken; 121 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 122 int timer0_running; 123 enum tstate { RELEASED, ACQUIRED }; 124 enum tstate timer0_state; 125 enum tstate timer1_state; 126 enum tstate timer2_state; 127 128 static int beeping = 0; 129 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 130 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 131 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 132 static int rtc_loaded; 133 134 static int i8254_cputimer_div; 135 136 static int i8254_nointr; 137 static int i8254_intr_disable = 0; 138 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable); 139 140 static struct callout sysbeepstop_ch; 141 142 static sysclock_t i8254_cputimer_count(void); 143 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last); 144 static void i8254_cputimer_destruct(struct cputimer *cputimer); 145 146 static struct cputimer i8254_cputimer = { 147 SLIST_ENTRY_INITIALIZER, 148 "i8254", 149 CPUTIMER_PRI_8254, 150 0, 151 i8254_cputimer_count, 152 cputimer_default_fromhz, 153 cputimer_default_fromus, 154 i8254_cputimer_construct, 155 i8254_cputimer_destruct, 156 TIMER_FREQ, 157 0, 0, 0 158 }; 159 160 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t); 161 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *); 162 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t); 163 164 static struct cputimer_intr i8254_cputimer_intr = { 165 .freq = TIMER_FREQ, 166 .reload = i8254_intr_reload, 167 .enable = cputimer_intr_default_enable, 168 .config = i8254_intr_config, 169 .restart = cputimer_intr_default_restart, 170 .pmfixup = cputimer_intr_default_pmfixup, 171 .initclock = i8254_intr_initclock, 172 .next = SLIST_ENTRY_INITIALIZER, 173 .name = "i8254", 174 .type = CPUTIMER_INTR_8254, 175 .prio = CPUTIMER_INTR_PRIO_8254, 176 .caps = CPUTIMER_INTR_CAP_PS 177 }; 178 179 /* 180 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped 181 * counting as of this interrupt. We use timer1 in free-running mode (not 182 * generating any interrupts) as our main counter. Each cpu has timeouts 183 * pending. 184 * 185 * This code is INTR_MPSAFE and may be called without the BGL held. 186 */ 187 static void 188 clkintr(void *dummy, void *frame_arg) 189 { 190 static sysclock_t sysclock_count; /* NOTE! Must be static */ 191 struct globaldata *gd = mycpu; 192 #ifdef SMP 193 struct globaldata *gscan; 194 int n; 195 #endif 196 197 /* 198 * SWSTROBE mode is a one-shot, the timer is no longer running 199 */ 200 timer0_running = 0; 201 202 /* 203 * XXX the dispatcher needs work. right now we call systimer_intr() 204 * directly or via IPI for any cpu with systimers queued, which is 205 * usually *ALL* of them. We need to use the LAPIC timer for this. 206 */ 207 sysclock_count = sys_cputimer->count(); 208 #ifdef SMP 209 for (n = 0; n < ncpus; ++n) { 210 gscan = globaldata_find(n); 211 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL) 212 continue; 213 if (gscan != gd) { 214 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 215 &sysclock_count, 0); 216 } else { 217 systimer_intr(&sysclock_count, 0, frame_arg); 218 } 219 } 220 #else 221 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL) 222 systimer_intr(&sysclock_count, 0, frame_arg); 223 #endif 224 } 225 226 227 /* 228 * NOTE! not MP safe. 229 */ 230 int 231 acquire_timer2(int mode) 232 { 233 if (timer2_state != RELEASED) 234 return (-1); 235 timer2_state = ACQUIRED; 236 237 /* 238 * This access to the timer registers is as atomic as possible 239 * because it is a single instruction. We could do better if we 240 * knew the rate. 241 */ 242 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 243 return (0); 244 } 245 246 int 247 release_timer2(void) 248 { 249 if (timer2_state != ACQUIRED) 250 return (-1); 251 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 252 timer2_state = RELEASED; 253 return (0); 254 } 255 256 /* 257 * This routine receives statistical clock interrupts from the RTC. 258 * As explained above, these occur at 128 interrupts per second. 259 * When profiling, we receive interrupts at a rate of 1024 Hz. 260 * 261 * This does not actually add as much overhead as it sounds, because 262 * when the statistical clock is active, the hardclock driver no longer 263 * needs to keep (inaccurate) statistics on its own. This decouples 264 * statistics gathering from scheduling interrupts. 265 * 266 * The RTC chip requires that we read status register C (RTC_INTR) 267 * to acknowledge an interrupt, before it will generate the next one. 268 * Under high interrupt load, rtcintr() can be indefinitely delayed and 269 * the clock can tick immediately after the read from RTC_INTR. In this 270 * case, the mc146818A interrupt signal will not drop for long enough 271 * to register with the 8259 PIC. If an interrupt is missed, the stat 272 * clock will halt, considerably degrading system performance. This is 273 * why we use 'while' rather than a more straightforward 'if' below. 274 * Stat clock ticks can still be lost, causing minor loss of accuracy 275 * in the statistics, but the stat clock will no longer stop. 276 */ 277 static void 278 rtcintr(void *dummy, void *frame) 279 { 280 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 281 ; 282 /* statclock(frame); no longer used */ 283 } 284 285 #include "opt_ddb.h" 286 #ifdef DDB 287 #include <ddb/ddb.h> 288 289 DB_SHOW_COMMAND(rtc, rtc) 290 { 291 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 292 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 293 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 294 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 295 } 296 #endif /* DDB */ 297 298 /* 299 * Return the current cpu timer count as a 32 bit integer. 300 */ 301 static 302 sysclock_t 303 i8254_cputimer_count(void) 304 { 305 static __uint16_t cputimer_last; 306 __uint16_t count; 307 sysclock_t ret; 308 309 clock_lock(); 310 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH); 311 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */ 312 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8); 313 count = -count; /* -> countup */ 314 if (count < cputimer_last) /* rollover */ 315 i8254_cputimer.base += 0x00010000; 316 ret = i8254_cputimer.base | count; 317 cputimer_last = count; 318 clock_unlock(); 319 return(ret); 320 } 321 322 /* 323 * This function is called whenever the system timebase changes, allowing 324 * us to calculate what is needed to convert a system timebase tick 325 * into an 8254 tick for the interrupt timer. If we can convert to a 326 * simple shift, multiplication, or division, we do so. Otherwise 64 327 * bit arithmatic is required every time the interrupt timer is reloaded. 328 */ 329 static void 330 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer) 331 { 332 int freq; 333 int div; 334 335 /* 336 * Will a simple divide do the trick? 337 */ 338 div = (timer->freq + (cti->freq / 2)) / cti->freq; 339 freq = cti->freq * div; 340 341 if (freq >= timer->freq - 1 && freq <= timer->freq + 1) 342 i8254_cputimer_div = div; 343 else 344 i8254_cputimer_div = 0; 345 } 346 347 /* 348 * Reload for the next timeout. It is possible for the reload value 349 * to be 0 or negative, indicating that an immediate timer interrupt 350 * is desired. For now make the minimum 2 ticks. 351 * 352 * We may have to convert from the system timebase to the 8254 timebase. 353 */ 354 static void 355 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload) 356 { 357 __uint16_t count; 358 359 if (i8254_cputimer_div) 360 reload /= i8254_cputimer_div; 361 else 362 reload = (int64_t)reload * cti->freq / sys_cputimer->freq; 363 364 if ((int)reload < 2) 365 reload = 2; 366 367 clock_lock(); 368 if (timer0_running) { 369 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */ 370 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */ 371 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */ 372 if (reload < count) { 373 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 374 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 375 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 376 } 377 } else { 378 timer0_running = 1; 379 if (reload > 0xFFFF) 380 reload = 0; /* full count */ 381 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 382 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */ 383 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */ 384 } 385 clock_unlock(); 386 } 387 388 /* 389 * DELAY(usec) - Spin for the specified number of microseconds. 390 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds, 391 * but do a thread switch in the loop 392 * 393 * Relies on timer 1 counting down from (cputimer_freq / hz) 394 * Note: timer had better have been programmed before this is first used! 395 */ 396 static void 397 DODELAY(int n, int doswitch) 398 { 399 int delta, prev_tick, tick, ticks_left; 400 401 #ifdef DELAYDEBUG 402 int getit_calls = 1; 403 int n1; 404 static int state = 0; 405 406 if (state == 0) { 407 state = 1; 408 for (n1 = 1; n1 <= 10000000; n1 *= 10) 409 DELAY(n1); 410 state = 2; 411 } 412 if (state == 1) 413 kprintf("DELAY(%d)...", n); 414 #endif 415 /* 416 * Guard against the timer being uninitialized if we are called 417 * early for console i/o. 418 */ 419 if (timer0_state == RELEASED) 420 i8254_restore(); 421 422 /* 423 * Read the counter first, so that the rest of the setup overhead is 424 * counted. Then calculate the number of hardware timer ticks 425 * required, rounding up to be sure we delay at least the requested 426 * number of microseconds. 427 */ 428 prev_tick = sys_cputimer->count(); 429 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) / 430 1000000; 431 432 /* 433 * Loop until done. 434 */ 435 while (ticks_left > 0) { 436 tick = sys_cputimer->count(); 437 #ifdef DELAYDEBUG 438 ++getit_calls; 439 #endif 440 delta = tick - prev_tick; 441 prev_tick = tick; 442 if (delta < 0) 443 delta = 0; 444 ticks_left -= delta; 445 if (doswitch && ticks_left > 0) 446 lwkt_switch(); 447 cpu_pause(); 448 } 449 #ifdef DELAYDEBUG 450 if (state == 1) 451 kprintf(" %d calls to getit() at %d usec each\n", 452 getit_calls, (n + 5) / getit_calls); 453 #endif 454 } 455 456 /* 457 * DELAY() never switches. 458 */ 459 void 460 DELAY(int n) 461 { 462 DODELAY(n, 0); 463 } 464 465 /* 466 * Returns non-zero if the specified time period has elapsed. Call 467 * first with last_clock set to 0. 468 */ 469 int 470 CHECKTIMEOUT(TOTALDELAY *tdd) 471 { 472 sysclock_t delta; 473 int us; 474 475 if (tdd->started == 0) { 476 if (timer0_state == RELEASED) 477 i8254_restore(); 478 tdd->last_clock = sys_cputimer->count(); 479 tdd->started = 1; 480 return(0); 481 } 482 delta = sys_cputimer->count() - tdd->last_clock; 483 us = (u_int64_t)delta * (u_int64_t)1000000 / 484 (u_int64_t)sys_cputimer->freq; 485 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq / 486 1000000; 487 tdd->us -= us; 488 return (tdd->us < 0); 489 } 490 491 492 /* 493 * DRIVERSLEEP() does not switch if called with a spinlock held or 494 * from a hard interrupt. 495 */ 496 void 497 DRIVERSLEEP(int usec) 498 { 499 globaldata_t gd = mycpu; 500 501 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) { 502 DODELAY(usec, 0); 503 } else { 504 DODELAY(usec, 1); 505 } 506 } 507 508 static void 509 sysbeepstop(void *chan) 510 { 511 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 512 beeping = 0; 513 release_timer2(); 514 } 515 516 int 517 sysbeep(int pitch, int period) 518 { 519 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 520 return(-1); 521 if (sysbeep_enable == 0) 522 return(-1); 523 /* 524 * Nobody else is using timer2, we do not need the clock lock 525 */ 526 outb(TIMER_CNTR2, pitch); 527 outb(TIMER_CNTR2, (pitch>>8)); 528 if (!beeping) { 529 /* enable counter2 output to speaker */ 530 outb(IO_PPI, inb(IO_PPI) | 3); 531 beeping = period; 532 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL); 533 } 534 return (0); 535 } 536 537 /* 538 * RTC support routines 539 */ 540 541 int 542 rtcin(int reg) 543 { 544 u_char val; 545 546 crit_enter(); 547 outb(IO_RTC, reg); 548 inb(0x84); 549 val = inb(IO_RTC + 1); 550 inb(0x84); 551 crit_exit(); 552 return (val); 553 } 554 555 static __inline void 556 writertc(u_char reg, u_char val) 557 { 558 crit_enter(); 559 inb(0x84); 560 outb(IO_RTC, reg); 561 inb(0x84); 562 outb(IO_RTC + 1, val); 563 inb(0x84); /* XXX work around wrong order in rtcin() */ 564 crit_exit(); 565 } 566 567 static __inline int 568 readrtc(int port) 569 { 570 return(bcd2bin(rtcin(port))); 571 } 572 573 static u_int 574 calibrate_clocks(void) 575 { 576 u_int64_t old_tsc; 577 u_int count, prev_count, tot_count; 578 int sec, start_sec, timeout; 579 580 if (bootverbose) 581 kprintf("Calibrating clock(s) ... "); 582 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 583 goto fail; 584 timeout = 100000000; 585 586 /* Read the mc146818A seconds counter. */ 587 for (;;) { 588 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 589 sec = rtcin(RTC_SEC); 590 break; 591 } 592 if (--timeout == 0) 593 goto fail; 594 } 595 596 /* Wait for the mC146818A seconds counter to change. */ 597 start_sec = sec; 598 for (;;) { 599 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 600 sec = rtcin(RTC_SEC); 601 if (sec != start_sec) 602 break; 603 } 604 if (--timeout == 0) 605 goto fail; 606 } 607 608 /* Start keeping track of the i8254 counter. */ 609 prev_count = sys_cputimer->count(); 610 tot_count = 0; 611 612 if (tsc_present) 613 old_tsc = rdtsc(); 614 else 615 old_tsc = 0; /* shut up gcc */ 616 617 /* 618 * Wait for the mc146818A seconds counter to change. Read the i8254 619 * counter for each iteration since this is convenient and only 620 * costs a few usec of inaccuracy. The timing of the final reads 621 * of the counters almost matches the timing of the initial reads, 622 * so the main cause of inaccuracy is the varying latency from 623 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 624 * rtcin(RTC_SEC) that returns a changed seconds count. The 625 * maximum inaccuracy from this cause is < 10 usec on 486's. 626 */ 627 start_sec = sec; 628 for (;;) { 629 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 630 sec = rtcin(RTC_SEC); 631 count = sys_cputimer->count(); 632 tot_count += (int)(count - prev_count); 633 prev_count = count; 634 if (sec != start_sec) 635 break; 636 if (--timeout == 0) 637 goto fail; 638 } 639 640 /* 641 * Read the cpu cycle counter. The timing considerations are 642 * similar to those for the i8254 clock. 643 */ 644 if (tsc_present) { 645 tsc_frequency = rdtsc() - old_tsc; 646 } 647 648 if (tsc_present) 649 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency); 650 kprintf("i8254 clock: %u Hz\n", tot_count); 651 return (tot_count); 652 653 fail: 654 kprintf("failed, using default i8254 clock of %u Hz\n", 655 i8254_cputimer.freq); 656 return (i8254_cputimer.freq); 657 } 658 659 static void 660 i8254_restore(void) 661 { 662 timer0_state = ACQUIRED; 663 664 clock_lock(); 665 666 /* 667 * Timer0 is our fine-grained variable clock interrupt 668 */ 669 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT); 670 outb(TIMER_CNTR0, 2); /* lsb */ 671 outb(TIMER_CNTR0, 0); /* msb */ 672 clock_unlock(); 673 674 if (!i8254_nointr) { 675 cputimer_intr_register(&i8254_cputimer_intr); 676 cputimer_intr_select(&i8254_cputimer_intr, 0); 677 } 678 679 /* 680 * Timer1 or timer2 is our free-running clock, but only if another 681 * has not been selected. 682 */ 683 cputimer_register(&i8254_cputimer); 684 cputimer_select(&i8254_cputimer, 0); 685 } 686 687 static void 688 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock) 689 { 690 int which; 691 692 /* 693 * Should we use timer 1 or timer 2 ? 694 */ 695 which = 0; 696 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which); 697 if (which != 1 && which != 2) 698 which = 2; 699 700 switch(which) { 701 case 1: 702 timer->name = "i8254_timer1"; 703 timer->type = CPUTIMER_8254_SEL1; 704 i8254_walltimer_sel = TIMER_SEL1; 705 i8254_walltimer_cntr = TIMER_CNTR1; 706 timer1_state = ACQUIRED; 707 break; 708 case 2: 709 timer->name = "i8254_timer2"; 710 timer->type = CPUTIMER_8254_SEL2; 711 i8254_walltimer_sel = TIMER_SEL2; 712 i8254_walltimer_cntr = TIMER_CNTR2; 713 timer2_state = ACQUIRED; 714 break; 715 } 716 717 timer->base = (oldclock + 0xFFFF) & ~0xFFFF; 718 719 clock_lock(); 720 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT); 721 outb(i8254_walltimer_cntr, 0); /* lsb */ 722 outb(i8254_walltimer_cntr, 0); /* msb */ 723 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */ 724 clock_unlock(); 725 } 726 727 static void 728 i8254_cputimer_destruct(struct cputimer *timer) 729 { 730 switch(timer->type) { 731 case CPUTIMER_8254_SEL1: 732 timer1_state = RELEASED; 733 break; 734 case CPUTIMER_8254_SEL2: 735 timer2_state = RELEASED; 736 break; 737 default: 738 break; 739 } 740 timer->type = 0; 741 } 742 743 static void 744 rtc_restore(void) 745 { 746 /* Restore all of the RTC's "status" (actually, control) registers. */ 747 writertc(RTC_STATUSB, RTCSB_24HR); 748 writertc(RTC_STATUSA, rtc_statusa); 749 writertc(RTC_STATUSB, rtc_statusb); 750 } 751 752 /* 753 * Restore all the timers. 754 * 755 * This function is called to resynchronize our core timekeeping after a 756 * long halt, e.g. from apm_default_resume() and friends. It is also 757 * called if after a BIOS call we have detected munging of the 8254. 758 * It is necessary because cputimer_count() counter's delta may have grown 759 * too large for nanouptime() and friends to handle, or (in the case of 8254 760 * munging) might cause the SYSTIMER code to prematurely trigger. 761 */ 762 void 763 timer_restore(void) 764 { 765 crit_enter(); 766 i8254_restore(); /* restore timer_freq and hz */ 767 rtc_restore(); /* reenable RTC interrupts */ 768 crit_exit(); 769 } 770 771 /* 772 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 773 */ 774 void 775 startrtclock(void) 776 { 777 u_int delta, freq; 778 779 /* 780 * Can we use the TSC? 781 */ 782 if (cpu_feature & CPUID_TSC) 783 tsc_present = 1; 784 else 785 tsc_present = 0; 786 787 /* 788 * Initial RTC state, don't do anything unexpected 789 */ 790 writertc(RTC_STATUSA, rtc_statusa); 791 writertc(RTC_STATUSB, RTCSB_24HR); 792 793 /* 794 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 795 * generate an interrupt, which we will ignore for now. 796 * 797 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000 798 * (so it counts a full 2^16 and repeats). We will use this timer 799 * for our counting. 800 */ 801 i8254_restore(); 802 freq = calibrate_clocks(); 803 #ifdef CLK_CALIBRATION_LOOP 804 if (bootverbose) { 805 kprintf( 806 "Press a key on the console to abort clock calibration\n"); 807 while (cncheckc() == -1) 808 calibrate_clocks(); 809 } 810 #endif 811 812 /* 813 * Use the calibrated i8254 frequency if it seems reasonable. 814 * Otherwise use the default, and don't use the calibrated i586 815 * frequency. 816 */ 817 delta = freq > i8254_cputimer.freq ? 818 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq; 819 if (delta < i8254_cputimer.freq / 100) { 820 #ifndef CLK_USE_I8254_CALIBRATION 821 if (bootverbose) 822 kprintf( 823 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 824 freq = i8254_cputimer.freq; 825 #endif 826 /* 827 * NOTE: 828 * Interrupt timer's freq must be adjusted 829 * before we change the cuptimer's frequency. 830 */ 831 i8254_cputimer_intr.freq = freq; 832 cputimer_set_frequency(&i8254_cputimer, freq); 833 } else { 834 if (bootverbose) 835 kprintf( 836 "%d Hz differs from default of %d Hz by more than 1%%\n", 837 freq, i8254_cputimer.freq); 838 tsc_frequency = 0; 839 } 840 841 #ifndef CLK_USE_TSC_CALIBRATION 842 if (tsc_frequency != 0) { 843 if (bootverbose) 844 kprintf( 845 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 846 tsc_frequency = 0; 847 } 848 #endif 849 if (tsc_present && tsc_frequency == 0) { 850 /* 851 * Calibration of the i586 clock relative to the mc146818A 852 * clock failed. Do a less accurate calibration relative 853 * to the i8254 clock. 854 */ 855 u_int64_t old_tsc = rdtsc(); 856 857 DELAY(1000000); 858 tsc_frequency = rdtsc() - old_tsc; 859 #ifdef CLK_USE_TSC_CALIBRATION 860 if (bootverbose) { 861 kprintf("TSC clock: %llu Hz (Method B)\n", 862 tsc_frequency); 863 } 864 #endif 865 } 866 867 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST); 868 869 #if !defined(SMP) 870 /* 871 * We can not use the TSC in SMP mode, until we figure out a 872 * cheap (impossible), reliable and precise (yeah right!) way 873 * to synchronize the TSCs of all the CPUs. 874 * Curse Intel for leaving the counter out of the I/O APIC. 875 */ 876 877 #if NAPM > 0 878 /* 879 * We can not use the TSC if we support APM. Precise timekeeping 880 * on an APM'ed machine is at best a fools pursuit, since 881 * any and all of the time spent in various SMM code can't 882 * be reliably accounted for. Reading the RTC is your only 883 * source of reliable time info. The i8254 looses too of course 884 * but we need to have some kind of time... 885 * We don't know at this point whether APM is going to be used 886 * or not, nor when it might be activated. Play it safe. 887 */ 888 return; 889 #endif /* NAPM > 0 */ 890 891 #endif /* !defined(SMP) */ 892 } 893 894 /* 895 * Sync the time of day back to the RTC on shutdown, but only if 896 * we have already loaded it and have not crashed. 897 */ 898 static void 899 resettodr_on_shutdown(void *arg __unused) 900 { 901 if (rtc_loaded && panicstr == NULL) { 902 resettodr(); 903 } 904 } 905 906 /* 907 * Initialize the time of day register, based on the time base which is, e.g. 908 * from a filesystem. 909 */ 910 void 911 inittodr(time_t base) 912 { 913 unsigned long sec, days; 914 int year, month; 915 int y, m; 916 struct timespec ts; 917 918 if (base) { 919 ts.tv_sec = base; 920 ts.tv_nsec = 0; 921 set_timeofday(&ts); 922 } 923 924 /* Look if we have a RTC present and the time is valid */ 925 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 926 goto wrong_time; 927 928 /* wait for time update to complete */ 929 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 930 crit_enter(); 931 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 932 crit_exit(); 933 crit_enter(); 934 } 935 936 days = 0; 937 #ifdef USE_RTC_CENTURY 938 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 939 #else 940 year = readrtc(RTC_YEAR) + 1900; 941 if (year < 1970) 942 year += 100; 943 #endif 944 if (year < 1970) { 945 crit_exit(); 946 goto wrong_time; 947 } 948 month = readrtc(RTC_MONTH); 949 for (m = 1; m < month; m++) 950 days += daysinmonth[m-1]; 951 if ((month > 2) && LEAPYEAR(year)) 952 days ++; 953 days += readrtc(RTC_DAY) - 1; 954 for (y = 1970; y < year; y++) 955 days += DAYSPERYEAR + LEAPYEAR(y); 956 sec = ((( days * 24 + 957 readrtc(RTC_HRS)) * 60 + 958 readrtc(RTC_MIN)) * 60 + 959 readrtc(RTC_SEC)); 960 /* sec now contains the number of seconds, since Jan 1 1970, 961 in the local time zone */ 962 963 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 964 965 y = time_second - sec; 966 if (y <= -2 || y >= 2) { 967 /* badly off, adjust it */ 968 ts.tv_sec = sec; 969 ts.tv_nsec = 0; 970 set_timeofday(&ts); 971 } 972 rtc_loaded = 1; 973 crit_exit(); 974 return; 975 976 wrong_time: 977 kprintf("Invalid time in real time clock.\n"); 978 kprintf("Check and reset the date immediately!\n"); 979 } 980 981 /* 982 * Write system time back to RTC 983 */ 984 void 985 resettodr(void) 986 { 987 struct timeval tv; 988 unsigned long tm; 989 int m; 990 int y; 991 992 if (disable_rtc_set) 993 return; 994 995 microtime(&tv); 996 tm = tv.tv_sec; 997 998 crit_enter(); 999 /* Disable RTC updates and interrupts. */ 1000 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1001 1002 /* Calculate local time to put in RTC */ 1003 1004 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1005 1006 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1007 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1008 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1009 1010 /* We have now the days since 01-01-1970 in tm */ 1011 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1012 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1013 tm >= m; 1014 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1015 tm -= m; 1016 1017 /* Now we have the years in y and the day-of-the-year in tm */ 1018 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1019 #ifdef USE_RTC_CENTURY 1020 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1021 #endif 1022 for (m = 0; ; m++) { 1023 int ml; 1024 1025 ml = daysinmonth[m]; 1026 if (m == 1 && LEAPYEAR(y)) 1027 ml++; 1028 if (tm < ml) 1029 break; 1030 tm -= ml; 1031 } 1032 1033 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1034 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1035 1036 /* Reenable RTC updates and interrupts. */ 1037 writertc(RTC_STATUSB, rtc_statusb); 1038 crit_exit(); 1039 } 1040 1041 1042 /* 1043 * Start both clocks running. DragonFly note: the stat clock is no longer 1044 * used. Instead, 8254 based systimers are used for all major clock 1045 * interrupts. 1046 */ 1047 static void 1048 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected) 1049 { 1050 int diag; 1051 #ifdef SMP /* APIC-IO */ 1052 int apic_8254_trial = 0; 1053 void *clkdesc = NULL; 1054 #endif 1055 1056 callout_init(&sysbeepstop_ch); 1057 1058 if (!selected && i8254_intr_disable) { 1059 i8254_nointr = 1; /* don't try to register again */ 1060 cputimer_intr_deregister(cti); 1061 return; 1062 } 1063 1064 /* 1065 * The stat interrupt mask is different without the 1066 * statistics clock. Also, don't set the interrupt 1067 * flag which would normally cause the RTC to generate 1068 * interrupts. 1069 */ 1070 rtc_statusb = RTCSB_24HR; 1071 1072 /* Finish initializing 8254 timer 0. */ 1073 #ifdef SMP /* APIC-IO */ 1074 if (apic_io_enable) { 1075 apic_8254_intr = isa_apic_irq(0); 1076 if (apic_8254_intr >= 0 ) { 1077 if (apic_int_type(0, 0) == 3) 1078 apic_8254_trial = 1; 1079 } else { 1080 /* look for ExtInt on pin 0 */ 1081 if (apic_int_type(0, 0) == 3) { 1082 apic_8254_intr = apic_irq(0, 0); 1083 setup_8254_mixed_mode(); 1084 } else 1085 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1086 } 1087 1088 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk", 1089 NULL, 1090 INTR_EXCL | INTR_CLOCK | 1091 INTR_NOPOLL | INTR_MPSAFE | 1092 INTR_NOENTROPY); 1093 machintr_intren(apic_8254_intr); 1094 } else { 1095 #endif 1096 register_int(0, clkintr, NULL, "clk", NULL, 1097 INTR_EXCL | INTR_CLOCK | 1098 INTR_NOPOLL | INTR_MPSAFE | 1099 INTR_NOENTROPY); 1100 machintr_intren(ICU_IRQ0); 1101 #ifdef SMP /* APIC-IO */ 1102 } 1103 #endif 1104 1105 /* Initialize RTC. */ 1106 writertc(RTC_STATUSA, rtc_statusa); 1107 writertc(RTC_STATUSB, RTCSB_24HR); 1108 1109 #ifdef SMP /* APIC-IO */ 1110 if (apic_io_enable) { 1111 if (apic_8254_trial) { 1112 sysclock_t base; 1113 long lastcnt; 1114 1115 /* 1116 * Following code assumes the 8254 is the cpu timer, 1117 * so make sure it is. 1118 */ 1119 KKASSERT(sys_cputimer == &i8254_cputimer); 1120 KKASSERT(cti == &i8254_cputimer_intr); 1121 1122 lastcnt = get_interrupt_counter(apic_8254_intr); 1123 1124 /* 1125 * Force an 8254 Timer0 interrupt and wait 1/100s for 1126 * it to happen, then see if we got it. 1127 */ 1128 kprintf("APIC_IO: Testing 8254 interrupt delivery\n"); 1129 i8254_intr_reload(cti, 2); 1130 base = sys_cputimer->count(); 1131 while (sys_cputimer->count() - base < sys_cputimer->freq / 100) 1132 ; /* nothing */ 1133 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) { 1134 /* 1135 * The MP table is broken. 1136 * The 8254 was not connected to the specified pin 1137 * on the IO APIC. 1138 * Workaround: Limited variant of mixed mode. 1139 */ 1140 machintr_intrdis(apic_8254_intr); 1141 unregister_int(clkdesc); 1142 kprintf("APIC_IO: Broken MP table detected: " 1143 "8254 is not connected to " 1144 "IOAPIC #%d intpin %d\n", 1145 int_to_apicintpin[apic_8254_intr].ioapic, 1146 int_to_apicintpin[apic_8254_intr].int_pin); 1147 /* 1148 * Revoke current ISA IRQ 0 assignment and 1149 * configure a fallback interrupt routing from 1150 * the 8254 Timer via the 8259 PIC to the 1151 * an ExtInt interrupt line on IOAPIC #0 intpin 0. 1152 * We reuse the low level interrupt handler number. 1153 */ 1154 if (apic_irq(0, 0) < 0) { 1155 revoke_apic_irq(apic_8254_intr); 1156 assign_apic_irq(0, 0, apic_8254_intr); 1157 } 1158 apic_8254_intr = apic_irq(0, 0); 1159 setup_8254_mixed_mode(); 1160 register_int(apic_8254_intr, clkintr, NULL, "clk", 1161 NULL, 1162 INTR_EXCL | INTR_CLOCK | 1163 INTR_NOPOLL | INTR_MPSAFE | 1164 INTR_NOENTROPY); 1165 machintr_intren(apic_8254_intr); 1166 } 1167 } 1168 if (apic_int_type(0, 0) != 3 || 1169 int_to_apicintpin[apic_8254_intr].ioapic != 0 || 1170 int_to_apicintpin[apic_8254_intr].int_pin != 0) { 1171 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n", 1172 int_to_apicintpin[apic_8254_intr].ioapic, 1173 int_to_apicintpin[apic_8254_intr].int_pin); 1174 } else { 1175 kprintf("APIC_IO: " 1176 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n"); 1177 } 1178 } 1179 #endif 1180 } 1181 1182 #ifdef SMP /* APIC-IO */ 1183 1184 static void 1185 setup_8254_mixed_mode(void) 1186 { 1187 /* 1188 * Allow 8254 timer to INTerrupt 8259: 1189 * re-initialize master 8259: 1190 * reset; prog 4 bytes, single ICU, edge triggered 1191 */ 1192 outb(IO_ICU1, 0x13); 1193 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */ 1194 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1195 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1196 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1197 1198 /* program IO APIC for type 3 INT on INT0 */ 1199 if (ext_int_setup(0, 0) < 0) 1200 panic("8254 redirect via APIC pin0 impossible!"); 1201 } 1202 #endif 1203 1204 void 1205 setstatclockrate(int newhz) 1206 { 1207 if (newhz == RTC_PROFRATE) 1208 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1209 else 1210 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1211 writertc(RTC_STATUSA, rtc_statusa); 1212 } 1213 1214 #if 0 1215 static unsigned 1216 tsc_get_timecount(struct timecounter *tc) 1217 { 1218 return (rdtsc()); 1219 } 1220 #endif 1221 1222 #ifdef KERN_TIMESTAMP 1223 #define KERN_TIMESTAMP_SIZE 16384 1224 static u_long tsc[KERN_TIMESTAMP_SIZE] ; 1225 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc, 1226 sizeof(tsc), "LU", "Kernel timestamps"); 1227 void 1228 _TSTMP(u_int32_t x) 1229 { 1230 static int i; 1231 1232 tsc[i] = (u_int32_t)rdtsc(); 1233 tsc[i+1] = x; 1234 i = i + 2; 1235 if (i >= KERN_TIMESTAMP_SIZE) 1236 i = 0; 1237 tsc[i] = 0; /* mark last entry */ 1238 } 1239 #endif /* KERN_TIMESTAMP */ 1240 1241 /* 1242 * 1243 */ 1244 1245 static int 1246 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS) 1247 { 1248 sysclock_t count; 1249 __uint64_t tscval; 1250 char buf[32]; 1251 1252 crit_enter(); 1253 if (sys_cputimer == &i8254_cputimer) 1254 count = sys_cputimer->count(); 1255 else 1256 count = 0; 1257 if (tsc_present) 1258 tscval = rdtsc(); 1259 else 1260 tscval = 0; 1261 crit_exit(); 1262 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval); 1263 return(SYSCTL_OUT(req, buf, strlen(buf) + 1)); 1264 } 1265 1266 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254"); 1267 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0, 1268 "frequency"); 1269 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD, 1270 0, 0, hw_i8254_timestamp, "A", ""); 1271 1272 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD, 1273 &tsc_present, 0, "TSC Available"); 1274 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD, 1275 &tsc_frequency, 0, "TSC Frequency"); 1276 1277