1 /* 2 *********************************************************************************************** 3 ** O.S : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA SATA/SAS RAID HOST Adapter 8 ** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] 9 *********************************************************************************************** 10 ************************************************************************ 11 ** Copyright (C) 2002 - 2010, Areca Technology Corporation All rights reserved. 12 ** 13 ** Web site: www.areca.com.tw 14 ** E-mail: erich@areca.com.tw; ching2048@areca.com.tw 15 ** 16 ** Redistribution and use in source and binary forms,with or without 17 ** modification,are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice,this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice,this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 31 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 32 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ************************************************************************** 38 * $FreeBSD: src/sys/dev/arcmsr/arcmsr.h,v 1.7 2010/07/21 18:50:24 delphij Exp $ 39 */ 40 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.17 2010-07-15" 41 #define ARCMSR_SCSI_INITIATOR_ID 255 42 #define ARCMSR_DEV_SECTOR_SIZE 512 43 #define ARCMSR_MAX_XFER_SECTORS 4096 44 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 45 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 46 #define ARCMSR_MAX_CHIPTYPE_NUM 4 47 #define ARCMSR_MAX_OUTSTANDING_CMD 256 48 #define ARCMSR_MAX_START_JOB 257 49 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 50 #define ARCMSR_MAX_FREESRB_NUM 320 51 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 52 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 53 #define ARCMSR_MAX_ADAPTER 4 54 #define ARCMSR_RELEASE_SIMQ_LEVEL 230 55 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 56 /* 57 ********************************************************************* 58 */ 59 #ifndef TRUE 60 #define TRUE 1 61 #endif 62 #ifndef FALSE 63 #define FALSE 0 64 #endif 65 #ifndef INTR_ENTROPY 66 # define INTR_ENTROPY 0 67 #endif 68 69 #ifndef offsetof 70 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 71 #endif 72 /* 73 ********************************************************************************** 74 ** 75 ********************************************************************************** 76 */ 77 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 78 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 79 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 80 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 81 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 82 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 83 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 84 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 85 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 86 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 87 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 88 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 89 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 90 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 91 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 92 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 93 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 94 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 95 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 96 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 97 98 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 99 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 100 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 101 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 102 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 103 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 104 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 105 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 106 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 107 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 108 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 109 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 110 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 111 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 112 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 113 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 114 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 115 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 116 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 117 118 #ifndef PCIR_BARS 119 #define PCIR_BARS 0x10 120 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 121 #endif 122 123 #define PCI_BASE_ADDR0 0x10 124 #define PCI_BASE_ADDR1 0x14 125 #define PCI_BASE_ADDR2 0x18 126 #define PCI_BASE_ADDR3 0x1C 127 #define PCI_BASE_ADDR4 0x20 128 #define PCI_BASE_ADDR5 0x24 129 /* 130 ********************************************************************************** 131 ** 132 ********************************************************************************** 133 */ 134 #define ARCMSR_SCSICMD_IOCTL 0x77 135 #define ARCMSR_CDEVSW_IOCTL 0x88 136 #define ARCMSR_MESSAGE_FAIL 0x0001 137 #define ARCMSR_MESSAGE_SUCCESS 0x0000 138 /* 139 ********************************************************************************** 140 ** 141 ********************************************************************************** 142 */ 143 #define arcmsr_ccbsrb_ptr spriv_ptr0 144 #define arcmsr_ccbacb_ptr spriv_ptr1 145 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 146 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 147 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 148 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 149 /* 150 ********************************************************************************** 151 ** 152 ********************************************************************************** 153 */ 154 struct CMD_MESSAGE { 155 u_int32_t HeaderLength; 156 u_int8_t Signature[8]; 157 u_int32_t Timeout; 158 u_int32_t ControlCode; 159 u_int32_t ReturnCode; 160 u_int32_t Length; 161 }; 162 163 struct CMD_MESSAGE_FIELD { 164 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 165 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 166 }; 167 168 /************************************************************************/ 169 /************************************************************************/ 170 171 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 172 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 173 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 174 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 175 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 176 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 177 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 178 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 179 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 180 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 181 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 182 183 /*DeviceType*/ 184 #define ARECA_SATA_RAID 0x90000000 185 186 /*FunctionCode*/ 187 #define FUNCTION_READ_RQBUFFER 0x0801 188 #define FUNCTION_WRITE_WQBUFFER 0x0802 189 #define FUNCTION_CLEAR_RQBUFFER 0x0803 190 #define FUNCTION_CLEAR_WQBUFFER 0x0804 191 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 192 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 193 #define FUNCTION_SAY_HELLO 0x0807 194 #define FUNCTION_SAY_GOODBYE 0x0808 195 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 196 /* 197 ************************************************************************ 198 ** IOCTL CONTROL CODE 199 ************************************************************************ 200 */ 201 /* ARECA IO CONTROL CODE*/ 202 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 203 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 204 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 205 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 206 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 207 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 208 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 209 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 210 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 211 212 /* ARECA IOCTL ReturnCode */ 213 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 214 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 215 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 216 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 217 /* 218 ************************************************************************ 219 ** SPEC. for Areca HBB adapter 220 ************************************************************************ 221 */ 222 /* ARECA HBB COMMAND for its FIRMWARE */ 223 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 224 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 225 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 226 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 227 228 /* ARECA FLAG LANGUAGE */ 229 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 230 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 231 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 232 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 233 234 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 235 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 236 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 237 238 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 239 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 240 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 241 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 242 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 243 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 244 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 245 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 246 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 247 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 248 249 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 250 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 251 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 252 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 253 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 254 255 /* data tunnel buffer between user space program and its firmware */ 256 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 257 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 258 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 259 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 260 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 261 #define ARCMSR_HBB_BASE0_LEN 0x00021000 262 #define ARCMSR_HBB_BASE1_LEN 0x00010000 263 /* 264 ************************************************************************ 265 ** SPEC. for Areca HBC adapter 266 ************************************************************************ 267 */ 268 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 269 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 270 /* Host Interrupt Mask */ 271 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 272 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 273 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 274 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 275 /* Host Interrupt Status */ 276 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 277 /* 278 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 279 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 280 */ 281 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 282 /* 283 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 284 ** value. This bit clears only when Outbound Doorbell bits 285 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 286 ** Clear register clears bits in the Outbound Doorbell register. 287 */ 288 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 289 /* 290 ** Set whenever the Outbound Post List Producer/Consumer 291 ** Register (FIFO) is not empty. It clears when the Outbound 292 ** Post List FIFO is empty. 293 */ 294 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 295 /* 296 ** This bit indicates a SAS interrupt from a source external to 297 ** the PCIe core. This bit is not maskable. 298 */ 299 /* DoorBell*/ 300 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 301 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 302 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 303 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 304 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 305 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 306 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 307 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 308 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 309 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 310 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 311 312 /* 313 ************************************************************* 314 ** structure for holding DMA address data 315 ************************************************************* 316 */ 317 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 318 /* 319 ************************************************************************************************ 320 ** ARECA FIRMWARE SPEC 321 ************************************************************************************************ 322 ** Usage of IOP331 adapter 323 ** (All In/Out is in IOP331's view) 324 ** 1. Message 0 --> InitThread message and retrun code 325 ** 2. Doorbell is used for RS-232 emulation 326 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 327 ** bit1 -- data out has been read (DRIVER DATA READ OK) 328 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 329 ** bit1 -- data in has been read (IOP331 DATA READ OK) 330 ** 3. Index Memory Usage 331 ** offset 0xf00 : for RS232 out (request buffer) 332 ** offset 0xe00 : for RS232 in (scratch buffer) 333 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 334 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 335 ** 4. RS-232 emulation 336 ** Currently 128 byte buffer is used 337 ** 1st u_int32_t : Data length (1--124) 338 ** Byte 4--127 : Max 124 bytes of data 339 ** 5. PostQ 340 ** All SCSI Command must be sent through postQ: 341 ** (inbound queue port) Request frame must be 32 bytes aligned 342 ** # bit27--bit31 => flag for post ccb 343 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 344 ** bit31 : 0 : 256 bytes frame 345 ** 1 : 512 bytes frame 346 ** bit30 : 0 : normal request 347 ** 1 : BIOS request 348 ** bit29 : reserved 349 ** bit28 : reserved 350 ** bit27 : reserved 351 ** ------------------------------------------------------------------------------- 352 ** (outbount queue port) Request reply 353 ** # bit27--bit31 => flag for reply 354 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 355 ** bit31 : must be 0 (for this type of reply) 356 ** bit30 : reserved for BIOS handshake 357 ** bit29 : reserved 358 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 359 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 360 ** bit27 : reserved 361 ** 6. BIOS request 362 ** All BIOS request is the same with request from PostQ 363 ** Except : 364 ** Request frame is sent from configuration space 365 ** offset: 0x78 : Request Frame (bit30 == 1) 366 ** offset: 0x18 : writeonly to generate IRQ to IOP331 367 ** Completion of request: 368 ** (bit30 == 0, bit28==err flag) 369 ** 7. Definition of SGL entry (structure) 370 ** 8. Message1 Out - Diag Status Code (????) 371 ** 9. Message0 message code : 372 ** 0x00 : NOP 373 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 374 ** Signature 0x87974060(4) 375 ** Request len 0x00000200(4) 376 ** numbers of queue 0x00000100(4) 377 ** SDRAM Size 0x00000100(4)-->256 MB 378 ** IDE Channels 0x00000008(4) 379 ** vendor 40 bytes char 380 ** model 8 bytes char 381 ** FirmVer 16 bytes char 382 ** Device Map 16 bytes char 383 ** 384 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 385 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 386 ** Signature 0x87974063(4) 387 ** UPPER32 of Request Frame (4)-->Driver Only 388 ** 0x03 : Reset (Abort all queued Command) 389 ** 0x04 : Stop Background Activity 390 ** 0x05 : Flush Cache 391 ** 0x06 : Start Background Activity (re-start if background is halted) 392 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 393 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 394 ** byte 0 : 0xaa <-- signature 395 ** byte 1 : 0x55 <-- signature 396 ** byte 2 : year (04) 397 ** byte 3 : month (1..12) 398 ** byte 4 : date (1..31) 399 ** byte 5 : hour (0..23) 400 ** byte 6 : minute (0..59) 401 ** byte 7 : second (0..59) 402 ** ********************************************************************************* 403 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 404 ** ==> Difference from IOP348 405 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 406 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 407 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 408 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 409 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 410 ** <A> use doorbell to generate interrupt 411 ** 412 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 413 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 414 ** 415 ** a. Message1: Out - Diag Status Code (????) 416 ** 417 ** b. Message0: message code 418 ** 0x00 : NOP 419 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 420 ** Signature 0x87974060(4) 421 ** Request len 0x00000200(4) 422 ** numbers of queue 0x00000100(4) 423 ** SDRAM Size 0x00000100(4)-->256 MB 424 ** IDE Channels 0x00000008(4) 425 ** vendor 40 bytes char 426 ** model 8 bytes char 427 ** FirmVer 16 bytes char 428 ** Device Map 16 bytes char 429 ** cfgVersion ULONG <== Added for checking of new firmware capability 430 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 431 ** Signature 0x87974063(4) 432 ** UPPER32 of Request Frame (4)-->Driver Only 433 ** 0x03 : Reset (Abort all queued Command) 434 ** 0x04 : Stop Background Activity 435 ** 0x05 : Flush Cache 436 ** 0x06 : Start Background Activity (re-start if background is halted) 437 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 438 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 439 ** byte 0 : 0xaa <-- signature 440 ** byte 1 : 0x55 <-- signature 441 ** byte 2 : year (04) 442 ** byte 3 : month (1..12) 443 ** byte 4 : date (1..31) 444 ** byte 5 : hour (0..23) 445 ** byte 6 : minute (0..59) 446 ** byte 7 : second (0..59) 447 ** 448 ** <2> Doorbell Register is used for RS-232 emulation 449 ** <A> different clear register 450 ** <B> different bit0 definition (bit0 is reserved) 451 ** 452 ** inbound doorbell : at offset 0x20 453 ** inbound doorbell clear : at offset 0x70 454 ** 455 ** inbound doorbell : bit0 -- reserved 456 ** bit1 -- data in ready (DRIVER DATA WRITE OK) 457 ** bit2 -- data out has been read (DRIVER DATA READ OK) 458 ** bit3 -- inbound message 0 ready 459 ** bit4 -- more than 12 request completed in a time 460 ** 461 ** outbound doorbell : at offset 0x9C 462 ** outbound doorbell clear : at offset 0xA0 463 ** 464 ** outbound doorbell : bit0 -- reserved 465 ** bit1 -- data out ready (IOP DATA WRITE OK) 466 ** bit2 -- data in has been read (IOP DATA READ OK) 467 ** bit3 -- outbound message 0 ready 468 ** 469 ** <3> Index Memory Usage (Buffer Area) 470 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 471 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 472 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 473 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 474 ** 475 ** <4> PostQ (Command Post Address) 476 ** All SCSI Command must be sent through postQ: 477 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 478 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 479 ** outbound queue port32 at offset 0x44 480 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 481 ** <A> For 32bit queue, access low part is enough to send/receive request 482 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 483 ** same for outbound queue port 484 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 485 ** to post inbound request in a single instruction, and use 64bit instruction 486 ** to retrieve outbound request in a single instruction. 487 ** If in 32bit environment, when sending inbound queue, write high part first 488 ** then write low part. For receiving outbound request, read high part first 489 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 490 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 491 ** consistency of the FIFO. Another way to check empty is to check status flag 492 ** at 0x30 bit3. 493 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 494 ** For BIOS, 16bytes aligned is OK 495 ** For Driver, 32bytes alignment is recommended. 496 ** POST Command bit0 to bit3 is defined differently 497 ** ---------------------------- 498 ** bit0:1 for PULL mode (must be 1) 499 ** ---------------------------- 500 ** bit3/2/1: for arcmsr cdb size (arccdbsize) 501 ** 000: <= 0x0080 (128) 502 ** 001: <= 0x0100 (256) 503 ** 010: <= 0x0180 (384) 504 ** 011: <= 0x0200 (512) 505 ** 100: <= 0x0280 (640) 506 ** 101: <= 0x0300 (768) 507 ** 110: <= 0x0300 (reserved) 508 ** 111: <= 0x0300 (reserved) 509 ** ----------------------------- 510 ** if len > 0x300 the len always set as 0x300 511 ** ----------------------------- 512 ** post addr = addr | ((len-1) >> 6) | 1 513 ** ----------------------------- 514 ** page length in command buffer still required, 515 ** 516 ** if page length > 3, 517 ** firmware will assume more request data need to be retrieved 518 ** 519 ** <D> Outbound Posting 520 ** bit0:0 , no error, 1 with error, refer to status buffer 521 ** bit1:0 , reserved (will be 0) 522 ** bit2:0 , reserved (will be 0) 523 ** bit3:0 , reserved (will be 0) 524 ** bit63-4: Completed command address 525 ** 526 ** <E> BIOS support, no special support is required. 527 ** LSI2108 support I/O register 528 ** All driver functionality is supported through I/O address 529 ** 530 ** For further spec, refer to 531 ** \spec\lsi\2108 for Areca\2108\LSISAS2108_PG_NoEncryption.pdf : Chapter 8 (8-11/8-28) 532 ** \spec\lsi\2108 for Areca\2108\SAS2108_RM_20.pdf : for configuration space 533 ************************************************************************************************ 534 */ 535 /* signature of set and get firmware config */ 536 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 537 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 538 /* message code of inbound message register */ 539 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 540 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 541 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 542 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 543 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 544 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 545 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 546 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 547 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 548 /* doorbell interrupt generator */ 549 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 550 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 551 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 552 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 553 /* srb areca cdb flag */ 554 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 555 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 556 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 557 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 558 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 559 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 560 /* outbound firmware ok */ 561 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 562 /* 563 ********************************** 564 ** 565 ********************************** 566 */ 567 /* size 8 bytes */ 568 /* 32bit Scatter-Gather list */ 569 struct SG32ENTRY { /* length bit 24 == 0 */ 570 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 571 u_int32_t address; 572 }; 573 /* size 12 bytes */ 574 /* 64bit Scatter-Gather list */ 575 struct SG64ENTRY { /* length bit 24 == 1 */ 576 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 577 u_int32_t address; 578 u_int32_t addresshigh; 579 }; 580 struct SGENTRY_UNION { 581 union { 582 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 583 struct SG64ENTRY sg64entry; /* 30h */ 584 }u; 585 }; 586 /* 587 ********************************** 588 ** 589 ********************************** 590 */ 591 struct QBUFFER { 592 u_int32_t data_len; 593 u_int8_t data[124]; 594 }; 595 /* 596 ************************************************************************************************ 597 ** FIRMWARE INFO 598 ************************************************************************************************ 599 */ 600 #define ARCMSR_FW_MODEL_OFFSET 15 601 #define ARCMSR_FW_VERS_OFFSET 17 602 #define ARCMSR_FW_DEVMAP_OFFSET 21 603 #define ARCMSR_FW_CFGVER_OFFSET 25 604 605 struct FIRMWARE_INFO { 606 u_int32_t signature; /*0,00-03*/ 607 u_int32_t request_len; /*1,04-07*/ 608 u_int32_t numbers_queue; /*2,08-11*/ 609 u_int32_t sdram_size; /*3,12-15*/ 610 u_int32_t ide_channels; /*4,16-19*/ 611 char vendor[40]; /*5,20-59*/ 612 char model[8]; /*15,60-67*/ 613 char firmware_ver[16]; /*17,68-83*/ 614 char device_map[16]; /*21,84-99*/ 615 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 616 char cfgSerial[16]; /*26,104-119*/ 617 u_int32_t cfgPicStatus; /*30,120-123*/ 618 }; 619 /* (A) For cfgVersion in FIRMWARE_INFO 620 ** if low BYTE (byte#0) >= 3 (version 3) 621 ** then byte#1 report the capability of the firmware can xfer in a single request 622 ** 623 ** byte#1 624 ** 0 256K 625 ** 1 512K 626 ** 2 1M 627 ** 3 2M 628 ** 4 4M 629 ** 5 8M 630 ** 6 16M 631 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 632 ** Driver support new xfer method need to set this field to indicate 633 ** large CDB block in 0x100 unit (we use 0x100 byte as one page) 634 ** e.g. If the length of CDB including MSG header and SGL is 0x1508 635 ** driver need to set the msgPages to 0x16 636 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 637 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag 638 ** <= 0x100 1 0 639 ** <= 0x200 2 1 640 ** <= 0x300 3 1 641 ** <= 0x400 4 1 642 ** . 643 ** . 644 */ 645 646 /* 647 ************************************************************************************************ 648 ** size 0x1F8 (504) 649 ************************************************************************************************ 650 */ 651 struct ARCMSR_CDB { 652 u_int8_t Bus; /* 00h should be 0 */ 653 u_int8_t TargetID; /* 01h should be 0--15 */ 654 u_int8_t LUN; /* 02h should be 0--7 */ 655 u_int8_t Function; /* 03h should be 1 */ 656 657 u_int8_t CdbLength; /* 04h not used now */ 658 u_int8_t sgcount; /* 05h */ 659 u_int8_t Flags; /* 06h */ 660 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 661 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 662 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 663 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 664 #define ARCMSR_CDB_FLAG_HEADQ 0x08 665 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 666 u_int8_t msgPages; /* 07h */ 667 668 u_int32_t Context; /* 08h Address of this request */ 669 u_int32_t DataLength; /* 0ch not used now */ 670 671 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 672 /* 673 ******************************************************** 674 **Device Status : the same from SCSI bus if error occur 675 ** SCSI bus status codes. 676 ******************************************************** 677 */ 678 u_int8_t DeviceStatus; /* 20h if error */ 679 #define SCSISTAT_GOOD 0x00 680 #define SCSISTAT_CHECK_CONDITION 0x02 681 #define SCSISTAT_CONDITION_MET 0x04 682 #define SCSISTAT_BUSY 0x08 683 #define SCSISTAT_INTERMEDIATE 0x10 684 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 685 #define SCSISTAT_RESERVATION_CONFLICT 0x18 686 #define SCSISTAT_COMMAND_TERMINATED 0x22 687 #define SCSISTAT_QUEUE_FULL 0x28 688 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 689 #define ARCMSR_DEV_ABORTED 0xF1 690 #define ARCMSR_DEV_INIT_FAIL 0xF2 691 692 u_int8_t SenseData[15]; /* 21h output */ 693 694 union { 695 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 696 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 697 } u; 698 }; 699 /* 700 ********************************************************************* 701 ** Command Control Block (SrbExtension) 702 ** SRB must be not cross page boundary,and the order from offset 0 703 ** structure describing an ATA disk request 704 ** this SRB length must be 32 bytes boundary 705 ********************************************************************* 706 */ 707 struct CommandControlBlock { 708 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 709 u_int32_t cdb_shifted_phyaddr; /* 504-507 */ 710 u_int32_t arc_cdb_size; /* 508-511 */ 711 /* ======================512+32 bytes============================ */ 712 #if defined(__x86_64__) || defined(__amd64__) || defined(__ia64__) || defined(__sparc64__) || defined(__powerpc__) 713 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 714 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 715 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 716 u_int16_t srb_flags; /* 536-537 */ 717 u_int16_t startdone; /* 538-539 */ 718 u_int32_t reserved2; /* 540-543 */ 719 #else 720 union ccb *pccb; /* 512-515 pointer of freebsd scsi command */ 721 struct AdapterControlBlock *acb; /* 516-519 */ 722 bus_dmamap_t dm_segs_dmamap; /* 520-523 */ 723 u_int16_t srb_flags; /* 524-525 */ 724 u_int16_t startdone; /* 526-527 */ 725 u_int32_t reserved2[4]; /* 528-531 532-535 536-539 540-543 */ 726 #endif 727 /* ========================================================== */ 728 /* struct callout ccb_callout; */ 729 }; 730 /* srb_flags */ 731 #define SRB_FLAG_READ 0x0000 732 #define SRB_FLAG_WRITE 0x0001 733 #define SRB_FLAG_ERROR 0x0002 734 #define SRB_FLAG_FLUSHCACHE 0x0004 735 #define SRB_FLAG_MASTER_ABORTED 0x0008 736 #define SRB_FLAG_DMAVALID 0x0010 737 #define SRB_FLAG_DMACONSISTENT 0x0020 738 #define SRB_FLAG_DMAWRITE 0x0040 739 #define SRB_FLAG_PKTBIND 0x0080 740 /* startdone */ 741 #define ARCMSR_SRB_DONE 0x0000 742 #define ARCMSR_SRB_UNBUILD 0x0000 743 #define ARCMSR_SRB_TIMEOUT 0x1111 744 #define ARCMSR_SRB_RETRY 0x2222 745 #define ARCMSR_SRB_START 0x55AA 746 #define ARCMSR_SRB_PENDING 0xAA55 747 #define ARCMSR_SRB_RESET 0xA5A5 748 #define ARCMSR_SRB_ABORTED 0x5A5A 749 #define ARCMSR_SRB_ILLEGAL 0xFFFF 750 /* 751 ********************************************************************* 752 ** Adapter Control Block 753 ********************************************************************* 754 */ 755 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 756 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 757 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */ 758 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ 759 760 struct AdapterControlBlock { 761 u_int32_t adapter_type; /* adapter A,B..... */ 762 763 bus_space_tag_t btag[2]; 764 bus_space_handle_t bhandle[2]; 765 bus_dma_tag_t parent_dmat; 766 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 767 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 768 bus_dmamap_t srb_dmamap; 769 device_t pci_dev; 770 struct cdev * ioctl_dev; 771 int pci_unit; 772 773 struct resource * sys_res_arcmsr[2]; 774 struct resource * irqres; 775 void * ih; /* interrupt handle */ 776 777 /* Hooks into the CAM XPT */ 778 struct cam_sim *psim; 779 struct cam_path *ppath; 780 u_int8_t * uncacheptr; 781 unsigned long vir2phy_offset; 782 union { 783 unsigned long phyaddr; 784 struct { 785 u_int32_t phyadd_low; 786 u_int32_t phyadd_high; 787 }B; 788 } srb_phyaddr; 789 // unsigned long srb_phyaddr; 790 /* Offset is used in making arc cdb physical to virtual calculations */ 791 u_int32_t outbound_int_enable; 792 793 struct MessageUnit_UNION * pmu; /* message unit ATU inbound base address0 */ 794 795 u_int8_t adapter_index; /* */ 796 u_int8_t irq; 797 u_int16_t acb_flags; /* */ 798 799 struct CommandControlBlock * psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 800 struct CommandControlBlock * srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 801 int32_t workingsrb_doneindex; /* done srb array index */ 802 int32_t workingsrb_startindex; /* start srb array index */ 803 int32_t srboutstandingcount; 804 805 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 806 u_int32_t rqbuf_firstindex; /* first of read buffer */ 807 u_int32_t rqbuf_lastindex; /* last of read buffer */ 808 809 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 810 u_int32_t wqbuf_firstindex; /* first of write buffer */ 811 u_int32_t wqbuf_lastindex; /* last of write buffer */ 812 813 arcmsr_lock_t workingQ_done_lock; 814 arcmsr_lock_t workingQ_start_lock; 815 arcmsr_lock_t qbuffer_lock; 816 817 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 818 u_int32_t num_resets; 819 u_int32_t num_aborts; 820 u_int32_t firm_request_len; /*1,04-07*/ 821 u_int32_t firm_numbers_queue; /*2,08-11*/ 822 u_int32_t firm_sdram_size; /*3,12-15*/ 823 u_int32_t firm_ide_channels; /*4,16-19*/ 824 u_int32_t firm_cfg_version; 825 char firm_model[12]; /*15,60-67*/ 826 char firm_version[20]; /*17,68-83*/ 827 char device_map[20]; /*21,84-99 */ 828 struct callout devmap_callout; 829 };/* HW_DEVICE_EXTENSION */ 830 /* acb_flags */ 831 #define ACB_F_SCSISTOPADAPTER 0x0001 832 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 833 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 834 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 835 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 836 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 837 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 838 #define ACB_F_BUS_RESET 0x0080 839 #define ACB_F_IOP_INITED 0x0100 /* iop init */ 840 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 841 #define ACB_F_CAM_DEV_QFRZN 0x0400 842 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 843 #define ACB_F_SRB_FUNCTION_POWER 0x1000 844 /* devstate */ 845 #define ARECA_RAID_GONE 0x55 846 #define ARECA_RAID_GOOD 0xaa 847 /* 848 ********************************************************************* 849 ** Message Unit structure 850 ********************************************************************* 851 */ 852 struct HBA_MessageUnit 853 { 854 u_int32_t resrved0[4]; /*0000 000F*/ 855 u_int32_t inbound_msgaddr0; /*0010 0013*/ 856 u_int32_t inbound_msgaddr1; /*0014 0017*/ 857 u_int32_t outbound_msgaddr0; /*0018 001B*/ 858 u_int32_t outbound_msgaddr1; /*001C 001F*/ 859 u_int32_t inbound_doorbell; /*0020 0023*/ 860 u_int32_t inbound_intstatus; /*0024 0027*/ 861 u_int32_t inbound_intmask; /*0028 002B*/ 862 u_int32_t outbound_doorbell; /*002C 002F*/ 863 u_int32_t outbound_intstatus; /*0030 0033*/ 864 u_int32_t outbound_intmask; /*0034 0037*/ 865 u_int32_t reserved1[2]; /*0038 003F*/ 866 u_int32_t inbound_queueport; /*0040 0043*/ 867 u_int32_t outbound_queueport; /*0044 0047*/ 868 u_int32_t reserved2[2]; /*0048 004F*/ 869 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 870 u_int32_t reserved4[128]; /*0800 09FF 128*/ 871 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 872 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 873 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 874 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 875 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 876 }; 877 /* 878 ********************************************************************* 879 ** 880 ********************************************************************* 881 */ 882 struct HBB_DOORBELL 883 { 884 u_int8_t doorbell_reserved[132096]; /*reserved */ 885 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 886 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 887 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 888 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 889 }; 890 /* 891 ********************************************************************* 892 ** 893 ********************************************************************* 894 */ 895 struct HBB_RWBUFFER 896 { 897 u_int8_t message_reserved0[64000]; /*reserved */ 898 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 899 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 900 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 901 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 902 }; 903 /* 904 ********************************************************************* 905 ** 906 ********************************************************************* 907 */ 908 struct HBB_MessageUnit 909 { 910 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 911 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 912 int32_t postq_index; /* post queue index */ 913 int32_t doneq_index; /* done queue index */ 914 struct HBB_DOORBELL *hbb_doorbell; 915 struct HBB_RWBUFFER *hbb_rwbuffer; 916 }; 917 918 /* 919 ********************************************************************* 920 ** 921 ********************************************************************* 922 */ 923 struct HBC_MessageUnit { 924 u_int32_t message_unit_status; /*0000 0003*/ 925 u_int32_t slave_error_attribute; /*0004 0007*/ 926 u_int32_t slave_error_address; /*0008 000B*/ 927 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 928 u_int32_t master_error_attribute; /*0010 0013*/ 929 u_int32_t master_error_address_low; /*0014 0017*/ 930 u_int32_t master_error_address_high; /*0018 001B*/ 931 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 932 u_int32_t inbound_doorbell; /*0020 0023*/ 933 u_int32_t diagnostic_rw_data; /*0024 0027*/ 934 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 935 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 936 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 937 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 938 u_int32_t dcr_data; /*0038 003B*/ 939 u_int32_t dcr_address; /*003C 003F*/ 940 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 941 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 942 u_int32_t hcb_pci_address_low; /*0048 004B*/ 943 u_int32_t hcb_pci_address_high; /*004C 004F*/ 944 u_int32_t iop_int_status; /*0050 0053*/ 945 u_int32_t iop_int_mask; /*0054 0057*/ 946 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 947 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 948 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 949 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 950 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 951 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 952 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 953 u_int32_t i2o_message_unit_control; /*0074 0077*/ 954 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 955 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 956 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 957 u_int32_t message_dest_address_index; /*0090 0093*/ 958 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 959 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 960 u_int32_t outbound_doorbell; /*009C 009F*/ 961 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 962 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 963 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 964 u_int32_t reserved0; /*00AC 00AF*/ 965 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 966 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 967 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 968 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 969 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 970 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 971 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 972 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 973 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 974 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 975 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 976 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 977 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 978 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 979 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 980 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 981 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 982 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 983 u_int32_t host_diagnostic; /*00F8 00FB*/ 984 u_int32_t write_sequence; /*00FC 00FF*/ 985 u_int32_t reserved1[34]; /*0100 0187*/ 986 u_int32_t reserved2[1950]; /*0188 1FFF*/ 987 u_int32_t message_wbuffer[32]; /*2000 207F*/ 988 u_int32_t reserved3[32]; /*2080 20FF*/ 989 u_int32_t message_rbuffer[32]; /*2100 217F*/ 990 u_int32_t reserved4[32]; /*2180 21FF*/ 991 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 992 }; 993 994 /* 995 ********************************************************************* 996 ** 997 ********************************************************************* 998 */ 999 struct MessageUnit_UNION 1000 { 1001 union { 1002 struct HBA_MessageUnit hbamu; 1003 struct HBB_MessageUnit hbbmu; 1004 struct HBC_MessageUnit hbcmu; 1005 } muu; 1006 }; 1007 1008 /* 1009 ************************************************************* 1010 ************************************************************* 1011 */ 1012 struct SENSE_DATA { 1013 u_int8_t ErrorCode:7; 1014 u_int8_t Valid:1; 1015 u_int8_t SegmentNumber; 1016 u_int8_t SenseKey:4; 1017 u_int8_t Reserved:1; 1018 u_int8_t IncorrectLength:1; 1019 u_int8_t EndOfMedia:1; 1020 u_int8_t FileMark:1; 1021 u_int8_t Information[4]; 1022 u_int8_t AdditionalSenseLength; 1023 u_int8_t CommandSpecificInformation[4]; 1024 u_int8_t AdditionalSenseCode; 1025 u_int8_t AdditionalSenseCodeQualifier; 1026 u_int8_t FieldReplaceableUnitCode; 1027 u_int8_t SenseKeySpecific[3]; 1028 }; 1029 /* 1030 ********************************** 1031 ** Peripheral Device Type definitions 1032 ********************************** 1033 */ 1034 #define SCSI_DASD 0x00 /* Direct-access Device */ 1035 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1036 #define SCSI_PRINTER 0x02 /* Printer device */ 1037 #define SCSI_PROCESSOR 0x03 /* Processor device */ 1038 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 1039 #define SCSI_CDROM 0x05 /* CD-ROM device */ 1040 #define SCSI_SCANNER 0x06 /* Scanner device */ 1041 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 1042 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1043 #define SCSI_COMM 0x09 /* Communications device */ 1044 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 1045 /* 1046 ************************************************************************************************************ 1047 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1048 ** 80331 PCI-to-PCI Bridge 1049 ** PCI Configuration Space 1050 ** 1051 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1052 ** Programming Interface 1053 ** ======================== 1054 ** Configuration Register Address Space Groupings and Ranges 1055 ** ============================================================= 1056 ** Register Group Configuration Offset 1057 ** ------------------------------------------------------------- 1058 ** Standard PCI Configuration 00-3Fh 1059 ** ------------------------------------------------------------- 1060 ** Device Specific Registers 40-A7h 1061 ** ------------------------------------------------------------- 1062 ** Reserved A8-CBh 1063 ** ------------------------------------------------------------- 1064 ** Enhanced Capability List CC-FFh 1065 ** ========================================================================================================== 1066 ** Standard PCI [Type 1] Configuration Space Address Map 1067 ** ********************************************************************************************************** 1068 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1069 ** ---------------------------------------------------------------------------------------------------------- 1070 ** | Device ID | Vendor ID | 00h 1071 ** ---------------------------------------------------------------------------------------------------------- 1072 ** | Primary Status | Primary Command | 04h 1073 ** ---------------------------------------------------------------------------------------------------------- 1074 ** | Class Code | RevID | 08h 1075 ** ---------------------------------------------------------------------------------------------------------- 1076 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1077 ** ---------------------------------------------------------------------------------------------------------- 1078 ** | Reserved | 10h 1079 ** ---------------------------------------------------------------------------------------------------------- 1080 ** | Reserved | 14h 1081 ** ---------------------------------------------------------------------------------------------------------- 1082 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1083 ** ---------------------------------------------------------------------------------------------------------- 1084 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 1085 ** ---------------------------------------------------------------------------------------------------------- 1086 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1087 ** ---------------------------------------------------------------------------------------------------------- 1088 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1089 ** ---------------------------------------------------------------------------------------------------------- 1090 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1091 ** ---------------------------------------------------------------------------------------------------------- 1092 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1093 ** ---------------------------------------------------------------------------------------------------------- 1094 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1095 ** ---------------------------------------------------------------------------------------------------------- 1096 ** | Reserved | Capabilities Pointer | 34h 1097 ** ---------------------------------------------------------------------------------------------------------- 1098 ** | Reserved | 38h 1099 ** ---------------------------------------------------------------------------------------------------------- 1100 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1101 **============================================================================================================= 1102 */ 1103 /* 1104 **============================================================================================================= 1105 ** 0x03-0x00 : 1106 ** Bit Default Description 1107 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1108 ** ID is unique per product speed as indicated. 1109 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1110 **============================================================================================================= 1111 */ 1112 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1113 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1114 /* 1115 **============================================================================== 1116 ** 0x05-0x04 : command register 1117 ** Bit Default Description 1118 **15:11 00h Reserved 1119 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1120 ** The bridge does not support interrupts. 1121 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1122 ** transactions on the primary bus. 1123 ** The bridge does not generate fast back to back 1124 ** transactions on the primary bus. 1125 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1126 ** 0=The bridge does not assert P_SERR#. 1127 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1128 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1129 ** that bridge does not perform address or data stepping, 1130 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1131 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 1132 ** Also bridge does not assert P_SERR# in response to 1133 ** a detected address or attribute parity error. 1134 ** 1=When a data parity error is detected bridge asserts S_PERR#. 1135 ** The bridge also asserts P_SERR# 1136 ** (when enabled globally via bit(8) of this register) 1137 ** in response to a detected address or attribute parity error. 1138 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1139 ** VGA palette write transactions are I/O transactions 1140 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1141 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1142 ** or are fully decoding 1143 ** (i.e., must be all 0's depending upon the VGA 1144 ** aliasing bit in the Bridge Control Register, offset 3Eh. 1145 ** P_AD[31:16] equal to 0000h 1146 ** 0=The bridge ignores VGA palette write transactions, 1147 ** unless decoded by the standard I/O address range window. 1148 ** 1=The bridge responds to VGA palette write transactions 1149 ** with medium DEVSEL# timing and forwards them to the secondary bus. 1150 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1151 ** MWI transactions targeting resources on the opposite side of the bridge, 1152 ** however, are forwarded as MWI transactions. 1153 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1154 ** This bit is read only and always returns 0 when read 1155 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1156 ** Initiation of configuration transactions is not affected by the state of this bit. 1157 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1158 ** 1=The bridge is enabled to function as an initiator on the primary interface. 1159 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1160 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 1161 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 1162 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1163 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1164 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1165 **============================================================================== 1166 */ 1167 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1168 #define PCI_DISABLE_INTERRUPT 0x0400 1169 /* 1170 **============================================================================== 1171 ** 0x07-0x06 : status register 1172 ** Bit Default Description 1173 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1174 ** attribute or data parity error. 1175 ** This bit is set regardless of the state of the PER bit in the command register. 1176 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1177 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1178 ** acting as the initiator on the primary bus, 1179 ** its transaction (with the exception of special cycles) 1180 ** has been terminated with a Master Abort. 1181 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1182 ** acting as the initiator on the primary bus, 1183 ** its transaction has been terminated with a Target Abort. 1184 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1185 ** as the target of a transaction, terminates it with a Target Abort. 1186 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1187 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1188 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1189 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1190 ** The bridge is the current master on the primary bus 1191 ** S_PERR# is detected asserted or is asserted by bridge 1192 ** The Parity Error Response bit is set in the Command register 1193 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1194 ** is able to respond to fast back to back transactions on its primary interface. 1195 ** 06 0 Reserved 1196 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1197 ** 1 = 1198 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1199 ** Offset 34h (Capability Pointer register) 1200 ** provides the offset for the first entry 1201 ** in the linked list of enhanced capabilities. 1202 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1203 ** The bridge does not support interrupts. 1204 ** 02:00 000 Reserved 1205 **============================================================================== 1206 */ 1207 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1208 #define ARCMSR_ADAP_66MHZ 0x20 1209 /* 1210 **============================================================================== 1211 ** 0x08 : revision ID 1212 ** Bit Default Description 1213 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1214 **============================================================================== 1215 */ 1216 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1217 /* 1218 **============================================================================== 1219 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1220 ** Bit Default Description 1221 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1222 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1223 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1224 **============================================================================== 1225 */ 1226 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1227 /* 1228 **============================================================================== 1229 ** 0x0c : cache line size 1230 ** Bit Default Description 1231 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1232 ** The contents of this register are factored into 1233 ** internal policy decisions associated with memory read prefetching, 1234 ** and the promotion of Memory Write transactions to MWI transactions. 1235 ** Valid cache line sizes are 8 and 16 dwords. 1236 ** When the cache line size is set to an invalid value, 1237 ** bridge behaves as though the cache line size was set to 00h. 1238 **============================================================================== 1239 */ 1240 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1241 /* 1242 **============================================================================== 1243 ** 0x0d : latency timer (number of pci clock 00-ff ) 1244 ** Bit Default Description 1245 ** Primary Latency Timer (PTV): 1246 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1247 ** referenced from the assertion of FRAME# to the expiration of the timer, 1248 ** when bridge may continue as master of the current transaction. All bits are writable, 1249 ** resulting in a granularity of 1 PCI clock cycle. 1250 ** When the timer expires (i.e., equals 00h) 1251 ** bridge relinquishes the bus after the first data transfer 1252 ** when its PCI bus grant has been deasserted. 1253 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1254 ** Indicates the number of PCI clock cycles, 1255 ** referenced from the assertion of FRAME# to the expiration of the timer, 1256 ** when bridge may continue as master of the current transaction. 1257 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1258 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1259 ** (Except in the case where MLT expires within 3 data phases 1260 ** of an ADB.In this case bridge continues on 1261 ** until it reaches the next ADB before relinquishing the bus.) 1262 **============================================================================== 1263 */ 1264 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1265 /* 1266 **============================================================================== 1267 ** 0x0e : (header type,single function ) 1268 ** Bit Default Description 1269 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1270 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1271 ** Returns ��01h�� when read indicating 1272 ** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1273 **============================================================================== 1274 */ 1275 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1276 /* 1277 **============================================================================== 1278 ** 0x0f : 1279 **============================================================================== 1280 */ 1281 /* 1282 **============================================================================== 1283 ** 0x13-0x10 : 1284 ** PCI CFG Base Address #0 (0x10) 1285 **============================================================================== 1286 */ 1287 /* 1288 **============================================================================== 1289 ** 0x17-0x14 : 1290 ** PCI CFG Base Address #1 (0x14) 1291 **============================================================================== 1292 */ 1293 /* 1294 **============================================================================== 1295 ** 0x1b-0x18 : 1296 ** PCI CFG Base Address #2 (0x18) 1297 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1298 ** Bit Default Description 1299 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1300 ** Any Type 1 configuration cycle 1301 ** on the primary bus whose bus number is greater than the secondary bus number, 1302 ** and less than or equal to the subordinate bus number 1303 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1304 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1305 ** Any Type 1 configuration cycle matching this bus number 1306 ** is translated to a Type 0 configuration cycle (or a Special Cycle) 1307 ** before being executed on bridge's secondary PCI bus. 1308 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1309 ** Any Type 1 configuration cycle on the primary interface 1310 ** with a bus number that is less than the contents 1311 ** of this register field does not be claimed by bridge. 1312 **-----------------0x1B--Secondary Latency Timer Register - SLTR 1313 ** Bit Default Description 1314 ** Secondary Latency Timer (STV): 1315 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1316 ** Indicates the number of PCI clock cycles, 1317 ** referenced from the assertion of FRAME# to the expiration of the timer, 1318 ** when bridge may continue as master of the current transaction. All bits are writable, 1319 ** resulting in a granularity of 1 PCI clock cycle. 1320 ** When the timer expires (i.e., equals 00h) 1321 ** bridge relinquishes the bus after the first data transfer 1322 ** when its PCI bus grant has been deasserted. 1323 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1324 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1325 ** to the expiration of the timer, 1326 ** when bridge may continue as master of the current transaction. All bits are writable, 1327 ** resulting in a granularity of 1 PCI clock cycle. 1328 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1329 ** (Except in the case where MLT expires within 3 data phases of an ADB. 1330 ** In this case bridge continues on until it reaches the next ADB 1331 ** before relinquishing the bus) 1332 **============================================================================== 1333 */ 1334 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1335 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1336 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1337 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1338 /* 1339 **============================================================================== 1340 ** 0x1f-0x1c : 1341 ** PCI CFG Base Address #3 (0x1C) 1342 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1343 ** Bit Default Description 1344 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1345 ** determine when to forward I/O transactions from one interface to the other. 1346 ** These bits correspond to address lines 15:12 for 4KB alignment. 1347 ** Bits 11:0 are assumed to be FFFh. 1348 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1349 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1350 ** an address range to determine when to forward I/O transactions 1351 ** from one interface to the other. 1352 ** These bits correspond to address lines 15:12 for 4KB alignment. 1353 ** Bits 11:0 are assumed to be 000h. 1354 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1355 **-----------------0x1F,0x1E--Secondary Status Register - SSR 1356 ** Bit Default Description 1357 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1358 ** attribute or data parity error on its secondary interface. 1359 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1360 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1361 ** acting as the initiator on the secondary bus, 1362 ** it's transaction (with the exception of special cycles) 1363 ** has been terminated with a Master Abort. 1364 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1365 ** acting as the initiator on the secondary bus, 1366 ** it's transaction has been terminated with a Target Abort. 1367 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1368 ** as the target of a transaction, terminates it with a Target Abort. 1369 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1370 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1371 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1372 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1373 ** The bridge is the current master on the secondary bus 1374 ** S_PERR# is detected asserted or is asserted by bridge 1375 ** The Parity Error Response bit is set in the Command register 1376 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1377 ** 06 0b Reserved 1378 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1379 ** 1 = 1380 ** 04:00 00h Reserved 1381 **============================================================================== 1382 */ 1383 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1384 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1385 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1386 /* 1387 **============================================================================== 1388 ** 0x23-0x20 : 1389 ** PCI CFG Base Address #4 (0x20) 1390 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1391 ** Bit Default Description 1392 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1393 ** the upper 1MB aligned value (exclusive) of the range. 1394 ** The incoming address must be less than or equal to this value. 1395 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1396 ** are assumed to be F FFFFh. 1397 ** 19:16 0h Reserved. 1398 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1399 ** of the incoming address to determine the lower 1MB 1400 ** aligned value (inclusive) of the range. 1401 ** The incoming address must be greater than or equal to this value. 1402 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1403 ** are assumed to be 0 0000h. 1404 ** 03:00 0h Reserved. 1405 **============================================================================== 1406 */ 1407 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1408 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1409 /* 1410 **============================================================================== 1411 ** 0x27-0x24 : 1412 ** PCI CFG Base Address #5 (0x24) 1413 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1414 ** Bit Default Description 1415 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1416 ** the upper 1MB aligned value (exclusive) of the range. 1417 ** The incoming address must be less than or equal to this value. 1418 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1419 ** are assumed to be F FFFFh. 1420 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1421 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1422 ** of the incoming address to determine the lower 1MB aligned value (inclusive) 1423 ** of the range. 1424 ** The incoming address must be greater than or equal to this value. 1425 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1426 ** are assumed to be 0 0000h. 1427 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1428 **============================================================================== 1429 */ 1430 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1431 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1432 /* 1433 **============================================================================== 1434 ** 0x2b-0x28 : 1435 ** Bit Default Description 1436 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1437 ** bridge supports full 64-bit addressing. 1438 **============================================================================== 1439 */ 1440 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1441 /* 1442 **============================================================================== 1443 ** 0x2f-0x2c : 1444 ** Bit Default Description 1445 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1446 ** bridge supports full 64-bit addressing. 1447 **============================================================================== 1448 */ 1449 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1450 /* 1451 **============================================================================== 1452 ** 0x33-0x30 : 1453 ** Bit Default Description 1454 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1455 ** space. (Power Management Capability Registers) 1456 **============================================================================== 1457 */ 1458 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1459 /* 1460 **============================================================================== 1461 ** 0x3b-0x35 : reserved 1462 **============================================================================== 1463 */ 1464 /* 1465 **============================================================================== 1466 ** 0x3d-0x3c : 1467 ** 1468 ** Bit Default Description 1469 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1470 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1471 **============================================================================== 1472 */ 1473 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1474 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1475 /* 1476 **============================================================================== 1477 ** 0x3f-0x3e : 1478 ** Bit Default Description 1479 ** 15:12 0h Reserved 1480 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1481 ** to a timer discard on either the primary or secondary interface. 1482 ** 0b=SERR# is not asserted. 1483 ** 1b=SERR# is asserted. 1484 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1485 ** The delayed completion is then discarded. 1486 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1487 ** that bridge waits for an initiator on the secondary bus 1488 ** to repeat a delayed transaction request. 1489 ** The counter starts when the delayed transaction completion is ready 1490 ** to be returned to the initiator. 1491 ** When the initiator has not repeated the transaction 1492 ** at least once before the counter expires,bridge 1493 ** discards the delayed transaction from its queues. 1494 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1495 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1496 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1497 ** that bridge waits for an initiator on the primary bus 1498 ** to repeat a delayed transaction request. 1499 ** The counter starts when the delayed transaction completion 1500 ** is ready to be returned to the initiator. 1501 ** When the initiator has not repeated the transaction 1502 ** at least once before the counter expires, 1503 ** bridge discards the delayed transaction from its queues. 1504 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1505 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1506 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1507 ** 06 0b Secondary Bus Reset (SBR): 1508 ** When cleared to 0b: The bridge deasserts S_RST#, 1509 ** when it had been asserted by writing this bit to a 1b. 1510 ** When set to 1b: The bridge asserts S_RST#. 1511 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1512 ** when a master abort termination occurs in response to 1513 ** a delayed transaction initiated by bridge on the target bus. 1514 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1515 ** and returns FFFF FFFFh when a read. 1516 ** 1b=When the transaction had not yet been completed on the initiator bus 1517 ** (e.g.,delayed reads, or non-posted writes), 1518 ** then bridge returns a Target Abort in response to the original requester 1519 ** when it returns looking for its delayed completion on the initiator bus. 1520 ** When the transaction had completed on the initiator bus (e.g., a PMW), 1521 ** then bridge asserts P_SERR# (when enabled). 1522 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1523 ** while attempting to deliver a posted memory write on the destination bus. 1524 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1525 ** (also of this register), 1526 ** and the VGA Palette Snoop Enable bit (Command Register). 1527 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1528 ** the VGA Aliasing bit for the corresponding enabled functionality,: 1529 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1530 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1531 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1532 ** then this bit has no impact on bridge behavior. 1533 ** 03 0b VGA Enable: Setting this bit enables address decoding 1534 ** and transaction forwarding of the following VGA transactions from the primary bus 1535 ** to the secondary bus: 1536 ** frame buffer memory addresses 000A0000h:000BFFFFh, 1537 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 1538 ** or must be ��000000b�� 1539 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1540 ** I/O and Memory Enable bits must be set in the Command register 1541 ** to enable forwarding of VGA cycles. 1542 ** 02 0b ISA Enable: Setting this bit enables special handling 1543 ** for the forwarding of ISA I/O transactions that fall within the address range 1544 ** specified by the I/O Base and Limit registers, 1545 ** and are within the lowest 64Kbyte of the I/O address map 1546 ** (i.e., 0000 0000h - 0000 FFFFh). 1547 ** 0b=All I/O transactions that fall within the I/O Base 1548 ** and Limit registers' specified range are forwarded 1549 ** from primary to secondary unfiltered. 1550 ** 1b=Blocks the forwarding from primary to secondary 1551 ** of the top 768 bytes of each 1Kbyte alias. 1552 ** On the secondary the top 768 bytes of each 1K alias 1553 ** are inversely decoded and forwarded 1554 ** from secondary to primary. 1555 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1556 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1557 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1558 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1559 ** that is detected on its secondary interface. 1560 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1561 ** Also bridge does not assert P_SERR# in response to a detected address 1562 ** or attribute parity error. 1563 ** 1b=When a data parity error is detected bridge asserts S_PERR#. 1564 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1565 ** of the Command register) 1566 ** in response to a detected address or attribute parity error. 1567 **============================================================================== 1568 */ 1569 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1570 /* 1571 ************************************************************************** 1572 ** Device Specific Registers 40-A7h 1573 ************************************************************************** 1574 ** ---------------------------------------------------------------------------------------------------------- 1575 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1576 ** ---------------------------------------------------------------------------------------------------------- 1577 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 1578 ** ---------------------------------------------------------------------------------------------------------- 1579 ** | Bridge Control 2 | Bridge Control 1 | 44h 1580 ** ---------------------------------------------------------------------------------------------------------- 1581 ** | Reserved | Bridge Status | 48h 1582 ** ---------------------------------------------------------------------------------------------------------- 1583 ** | Reserved | 4Ch 1584 ** ---------------------------------------------------------------------------------------------------------- 1585 ** | Prefetch Policy | Multi-Transaction Timer | 50h 1586 ** ---------------------------------------------------------------------------------------------------------- 1587 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 1588 ** ---------------------------------------------------------------------------------------------------------- 1589 ** | Reserved | Reserved | Secondary Decode Enable | 58h 1590 ** ---------------------------------------------------------------------------------------------------------- 1591 ** | Reserved | Secondary IDSEL | 5Ch 1592 ** ---------------------------------------------------------------------------------------------------------- 1593 ** | Reserved | 5Ch 1594 ** ---------------------------------------------------------------------------------------------------------- 1595 ** | Reserved | 68h:CBh 1596 ** ---------------------------------------------------------------------------------------------------------- 1597 ************************************************************************** 1598 **============================================================================== 1599 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 1600 ** Bit Default Description 1601 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 1602 ** (PCI=16 clocks,PCI-X=6 clocks). 1603 ** Note that this field is only meaningful when: 1604 ** # Bit[11] of this register is set to 1b, 1605 ** indicating that a Grant Time-out violation had occurred. 1606 ** # bridge internal arbiter is enabled. 1607 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 1608 ** 0000b REQ#/GNT#[0] 1609 ** 0001b REQ#/GNT#[1] 1610 ** 0010b REQ#/GNT#[2] 1611 ** 0011b REQ#/GNT#[3] 1612 ** 1111b Default Value (no violation detected) 1613 ** When bit[11] is cleared by software, this field reverts back to its default value. 1614 ** All other values are Reserved 1615 ** 11 0b Grant Time-out Occurred: When set to 1b, 1616 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 1617 ** Software clears this bit by writing a 1b to it. 1618 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 1619 ** 1=During bus idle, bridge parks the bus on itself. 1620 ** The bus grant is removed from the last master and internally asserted to bridge. 1621 ** 09:08 00b Reserved 1622 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 1623 ** Each bit of this field assigns its corresponding secondary 1624 ** bus master to either the high priority arbiter ring (1b) 1625 ** or to the low priority arbiter ring (0b). 1626 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 1627 ** Bit [6] corresponds to the bridge internal secondary bus request 1628 ** while Bit [7] corresponds to the SATU secondary bus request. 1629 ** Bits [5:4] are unused. 1630 ** 0b=Indicates that the master belongs to the low priority group. 1631 ** 1b=Indicates that the master belongs to the high priority group 1632 **================================================================================= 1633 ** 0x43: Bridge Control Register 0 - BCR0 1634 ** Bit Default Description 1635 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 1636 ** and the Posted Write data is limited to 4KB. 1637 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 1638 ** 14 Posted Memory Write transactions and 8KB of posted write data. 1639 ** 06:03 0H Reserved. 1640 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 1641 ** to perform upstream prefetch operations for Memory 1642 ** Read requests received on its secondary interface. 1643 ** This bit also controls the bridge's ability to generate advanced read commands 1644 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 1645 ** to a Conventional PCI bus. 1646 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 1647 ** The use of Memory Read Line and Memory Read 1648 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request 1649 ** to an upstream bus operating in Conventional PCI mode. 1650 ** 1b=bridge treats upstream PCI Memory Read requests as though 1651 ** they target non-prefetchable memory and forwards upstream PCI-X Memory 1652 ** Read Block commands as Memory Read 1653 ** when the primary bus is operating 1654 ** in Conventional PCI mode. 1655 ** NOTE: This bit does not affect bridge ability to perform read prefetching 1656 ** when the received command is Memory Read Line or Memory Read Multiple. 1657 **================================================================================= 1658 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 1659 ** Bit Default Description 1660 ** 15:08 0000000b Reserved 1661 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 1662 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 1663 ** The three options for handling these alias commands are to either pass it as is, 1664 ** re-map to the actual block memory read/write command encoding, or ignore 1665 ** the transaction forcing a Master Abort to occur on the Origination Bus. 1666 ** Bit (7:6) Handling of command 1667 ** 0 0 Re-map to Memory Read/Write Block before forwarding 1668 ** 0 1 Enqueue and forward the alias command code unaltered 1669 ** 1 0 Ignore the transaction, forcing Master Abort 1670 ** 1 1 Reserved 1671 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 1672 ** The watchdog timers are used to detect prohibitively long latencies in the system. 1673 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 1674 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 1675 ** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 1676 ** and as the number of times being retried when operating in Conventional PCI mode) 1677 ** 0b=All 2 24 watchdog timers are enabled. 1678 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to 1679 ** the number of attempts bridge makes when initiating a PMW, 1680 ** transacting a Delayed Transaction, or how long it waits for 1681 ** a split completion corresponding to one of its requests. 1682 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 1683 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 1684 ** 0b=The Secondary bus arbiter times out an agent 1685 ** that does not assert FRAME# within 16/6 clocks of receiving its grant, 1686 ** once the bus has gone idle. 1687 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 1688 ** An infringing agent does not receive a subsequent GNT# 1689 ** until it de-asserts its REQ# for at least one clock cycle. 1690 ** 1b=GNT# time-out mechanism is disabled. 1691 ** 03 00b Reserved. 1692 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 1693 ** The time out mechanism is used to ensure that initiators 1694 ** of delayed transactions return for their delayed completion data/status 1695 ** within a reasonable amount of time after it is available from bridge. 1696 ** 0b=The secondary master time-out counter is enabled 1697 ** and uses the value specified by the Secondary Discard Timer bit 1698 ** (see Bridge Control Register). 1699 ** 1b=The secondary master time-out counter is disabled. 1700 ** The bridge waits indefinitely for a secondary bus master 1701 ** to repeat a delayed transaction. 1702 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 1703 ** The time out mechanism is used to ensure that initiators 1704 ** of delayed transactions return for their delayed completion data/status 1705 ** within a reasonable amount of time after it is available from bridge. 1706 ** 0b=The primary master time-out counter is enabled and uses the value specified 1707 ** by the Primary Discard Timer bit (see Bridge Control Register). 1708 ** 1b=The secondary master time-out counter is disabled. 1709 ** The bridge waits indefinitely for a secondary bus master 1710 ** to repeat a delayed transaction. 1711 ** 00 0b Reserved 1712 **================================================================================= 1713 ** 0x47-0x46: Bridge Control Register 2 - BCR2 1714 ** Bit Default Description 1715 ** 15:07 0000b Reserved. 1716 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 1717 ** This bit disables all of the secondary PCI clock outputs including 1718 ** the feedback clock S_CLKOUT. 1719 ** This means that the user is required to provide an S_CLKIN input source. 1720 ** 05:04 11 (66 MHz) Preserved. 1721 ** 01 (100 MHz) 1722 ** 00 (133 MHz) 1723 ** 03:00 Fh (100 MHz & 66 MHz) 1724 ** 7h (133 MHz) 1725 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 1726 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 1727 ** default to being enabled following the rising edge of P_RST#, depending on the 1728 ** frequency of the secondary bus clock: 1729 ** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 1730 ** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 1731 ** �E Designs with 133 MHz Secondary PCI clock power up 1732 ** with the lower order 3 S_CLKOs enabled by default. 1733 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 1734 ** to downstream device clock inputs. 1735 **================================================================================= 1736 ** 0x49-0x48: Bridge Status Register - BSR 1737 ** Bit Default Description 1738 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1739 ** is conditionally asserted when the secondary discard timer expires. 1740 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 1741 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1742 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 1743 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1744 ** when bridge discards an upstream split read request 1745 ** after waiting in excess of 2 24 clocks for the corresponding 1746 ** Split Completion to arrive. 1747 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 1748 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1749 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 1750 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1751 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 1752 ** Split Completion to arrive. 1753 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1754 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1755 ** by bridge, to retire a PMW upstream. 1756 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1757 ** is conditionally asserted when a Target Abort occurs as a result of an attempt, 1758 ** by bridge, to retire a PMW upstream. 1759 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1760 ** is conditionally asserted when bridge discards an upstream PMW transaction 1761 ** after receiving 2 24 target retries from the primary bus target 1762 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1763 ** is conditionally asserted when a data parity error is detected by bridge 1764 ** while attempting to retire a PMW upstream 1765 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 1766 ** is conditionally asserted when bridge detects an address parity error on 1767 ** the secondary bus. 1768 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1769 ** is conditionally asserted when the primary bus discard timer expires. 1770 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 1771 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1772 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 1773 ** from the secondary bus target. 1774 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1775 ** when bridge discards a downstream split read request 1776 ** after waiting in excess of 2 24 clocks for the corresponding 1777 ** Split Completion to arrive. 1778 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 1779 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1780 ** when bridge discards a downstream delayed write transaction request 1781 ** after receiving 2 24 target retries from the secondary bus target. 1782 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1783 ** is conditionally asserted when bridge discards a downstream 1784 ** split write request after waiting in excess of 2 24 clocks 1785 ** for the corresponding Split Completion to arrive. 1786 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 1787 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1788 ** by bridge, to retire a PMW downstream. 1789 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 1790 ** when a Target Abort occurs as a result of an attempt, by bridge, 1791 ** to retire a PMW downstream. 1792 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1793 ** is conditionally asserted when bridge discards a downstream PMW transaction 1794 ** after receiving 2 24 target retries from the secondary bus target 1795 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1796 ** is conditionally asserted when a data parity error is detected by bridge 1797 ** while attempting to retire a PMW downstream. 1798 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 1799 ** when bridge detects an address parity error on the primary bus. 1800 **================================================================================== 1801 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 1802 ** Bit Default Description 1803 ** 15:13 000b Reserved 1804 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 1805 ** that a secondary bus master has its grant maintained in order to enable 1806 ** multiple transactions to execute within the same arbitration cycle. 1807 ** Bit[02:00] GNT# Extended Duration 1808 ** 000 MTT Disabled (Default=no GNT# extension) 1809 ** 001 16 clocks 1810 ** 010 32 clocks 1811 ** 011 64 clocks 1812 ** 100 128 clocks 1813 ** 101 256 clocks 1814 ** 110 Invalid (treated as 000) 1815 ** 111 Invalid (treated as 000) 1816 ** 09:08 00b Reserved 1817 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 1818 ** pair supported by bridge secondary arbiter. 1819 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 1820 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 1821 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 1822 ** When a given bit is set to 1b, its corresponding REQ#/GNT# 1823 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 1824 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 1825 **================================================================================== 1826 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 1827 ** Bit Default Description 1828 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 1829 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 1830 ** using the FirstRead parameter. 1831 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 1832 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 1833 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 1834 ** the number of bytes to prefetch from the secondary bus interface 1835 ** on the initial PreFetch operation. 1836 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 1837 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1838 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 1839 ** in calculating the number of bytes to prefetch from the primary 1840 ** bus interface on subsequent PreFetch operations given 1841 ** that the read demands were not satisfied using 1842 ** the FirstRead parameter. 1843 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 1844 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 1845 ** Memory Read Multiple 6 cache lines 1846 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 1847 ** in calculating the number of bytes to prefetch from 1848 ** the primary bus interface on the initial PreFetch operation. 1849 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 1850 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1851 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 1852 ** algorithm for the secondary and the primary bus interfaces. 1853 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 1854 ** enable bits for REQ#/GNT#[2:0]. 1855 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 1856 ** 1b: enables the staged pre-fetch feature 1857 ** 0b: disables staged pre-fetch, 1858 ** and hardwires read pre-fetch policy to the following for 1859 ** Memory Read, 1860 ** Memory Read Line, 1861 ** and Memory Read Multiple commands: 1862 ** Command Type Hardwired Pre-Fetch Amount... 1863 ** Memory Read 4 DWORDs 1864 ** Memory Read Line 1 cache line 1865 ** Memory Read Multiple 2 cache lines 1866 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 1867 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 1868 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 1869 **================================================================================== 1870 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 1871 ** Bit Default Description 1872 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 1873 ** in response to its discarding of a delayed transaction that was initiated from the primary bus. 1874 ** 0b=bridge asserts P_SERR#. 1875 ** 1b=bridge does not assert P_SERR# 1876 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1877 ** 0b=bridge asserts P_SERR#. 1878 ** 1b=bridge does not assert P_SERR# 1879 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1880 ** 0b=bridge asserts P_SERR#. 1881 ** 1b=bridge does not assert P_SERR# 1882 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 1883 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 1884 ** 0b=bridge asserts P_SERR#. 1885 ** 1b=bridge does not assert P_SERR# 1886 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 1887 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 1888 ** 0b=bridge asserts P_SERR#. 1889 ** 1b=bridge does not assert P_SERR# 1890 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 1891 ** it discards an upstream posted write transaction. 1892 ** 0b=bridge asserts P_SERR#. 1893 ** 1b=bridge does not assert P_SERR# 1894 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 1895 ** when a data parity error is detected while attempting to retire on of its PMWs upstream. 1896 ** 0b=bridge asserts P_SERR#. 1897 ** 1b=bridge does not assert P_SERR# 1898 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 1899 ** when it detects an address parity error on the secondary bus. 1900 ** 0b=bridge asserts P_SERR#. 1901 ** 1b=bridge does not assert P_SERR# 1902 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 1903 ** its discarding of a delayed transaction that was initiated on the secondary bus. 1904 ** 0b=bridge asserts P_SERR#. 1905 ** 1b=bridge does not assert P_SERR# 1906 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1907 ** 0b=bridge asserts P_SERR#. 1908 ** 1b=bridge does not assert P_SERR# 1909 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1910 ** 0b=bridge asserts P_SERR#. 1911 ** 1b=bridge does not assert P_SERR# 1912 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 1913 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 1914 ** 0b=bridge asserts P_SERR#. 1915 ** 1b=bridge does not assert P_SERR# 1916 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 1917 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 1918 ** 0b=bridge asserts P_SERR#. 1919 ** 1b=bridge does not assert P_SERR# 1920 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 1921 ** that it discards a downstream posted write transaction. 1922 ** 0b=bridge asserts P_SERR#. 1923 ** 1b=bridge does not assert P_SERR# 1924 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 1925 ** when a data parity error is detected while attempting to retire on of its PMWs downstream. 1926 ** 0b=bridge asserts P_SERR#. 1927 ** 1b=bridge does not assert P_SERR# 1928 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 1929 ** when it detects an address parity error on the primary bus. 1930 ** 0b=bridge asserts P_SERR#. 1931 ** 1b=bridge does not assert P_SERR# 1932 **=============================================================================== 1933 ** 0x56: Pre-Boot Status Register - PBSR 1934 ** Bit Default Description 1935 ** 07 1 Reserved 1936 ** 06 - Reserved - value indeterminate 1937 ** 05:02 0 Reserved 1938 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 1939 ** This bit reflect captured S_133EN strap, 1940 ** indicating the maximum secondary bus clock frequency when in PCI-X mode. 1941 ** Max Allowable Secondary Bus Frequency 1942 ** ** S_133EN PCI-X Mode 1943 ** ** 0 100 MHz 1944 ** ** 1 133 MH 1945 ** 00 0b Reserved 1946 **=============================================================================== 1947 ** 0x59-0x58: Secondary Decode Enable Register - SDER 1948 ** Bit Default Description 1949 ** 15:03 FFF1h Preserved. 1950 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 1951 ** bridge overrides its secondary inverse decode logic and not 1952 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 1953 ** This creates a private memory space on the Secondary PCI bus 1954 ** that allows peer-to-peer transactions. 1955 ** 01:00 10 2 Preserved. 1956 **=============================================================================== 1957 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 1958 ** Bit Default Description 1959 ** 15:10 000000 2 Reserved. 1960 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 1961 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 1962 ** When this bit is clear, 1963 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 1964 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 1965 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 1966 ** When this bit is clear, 1967 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 1968 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 1969 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 1970 ** When this bit is clear, 1971 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 1972 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 1973 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 1974 ** When this bit is clear, 1975 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 1976 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 1977 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 1978 ** When this bit is clear, 1979 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 1980 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 1981 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 1982 ** When this bit is clear, 1983 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 1984 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 1985 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 1986 ** When this bit is clear, 1987 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 1988 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 1989 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 1990 ** When this bit is clear, 1991 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 1992 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 1993 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 1994 ** When this bit is clear, 1995 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 1996 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 1997 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 1998 ** When this bit is clear, 1999 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2000 ************************************************************************** 2001 */ 2002 /* 2003 ************************************************************************** 2004 ** Reserved A8-CBh 2005 ************************************************************************** 2006 */ 2007 /* 2008 ************************************************************************** 2009 ** PCI Extended Enhanced Capabilities List CC-FFh 2010 ************************************************************************** 2011 ** ---------------------------------------------------------------------------------------------------------- 2012 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2013 ** ---------------------------------------------------------------------------------------------------------- 2014 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2015 ** ---------------------------------------------------------------------------------------------------------- 2016 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2017 ** ---------------------------------------------------------------------------------------------------------- 2018 ** | Reserved | Reserved | Reserved | E4h 2019 ** ---------------------------------------------------------------------------------------------------------- 2020 ** | Reserved | E8h 2021 ** ---------------------------------------------------------------------------------------------------------- 2022 ** | Reserved | Reserved | Reserved | Reserved | ECh 2023 ** ---------------------------------------------------------------------------------------------------------- 2024 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2025 ** ---------------------------------------------------------------------------------------------------------- 2026 ** | PCI-X Bridge Status | F4h 2027 ** ---------------------------------------------------------------------------------------------------------- 2028 ** | PCI-X Upstream Split Transaction Control | F8h 2029 ** ---------------------------------------------------------------------------------------------------------- 2030 ** | PCI-X Downstream Split Transaction Control | FCh 2031 ** ---------------------------------------------------------------------------------------------------------- 2032 **=============================================================================== 2033 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2034 ** Bit Default Description 2035 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2036 **=============================================================================== 2037 ** 0xDD: Next Item Pointer - PM_NXTP 2038 ** Bit Default Description 2039 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2040 **=============================================================================== 2041 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2042 ** Bit Default Description 2043 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2044 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2045 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2046 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2047 ** This returns 000b as PME# wake-up for bridge is not implemented. 2048 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2049 ** 04:03 00 Reserved 2050 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2051 **=============================================================================== 2052 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2053 ** Bit Default Description 2054 ** 15:09 00h Reserved 2055 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2056 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2057 ** 07:02 00h Reserved 2058 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2059 ** a function and to set the Function into a new power state. 2060 ** 00 - D0 state 2061 ** 01 - D1 state 2062 ** 10 - D2 state 2063 ** 11 - D3 hot state 2064 **=============================================================================== 2065 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2066 ** Bit Default Description 2067 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2068 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2069 ** is to occur as a direct result of programming the function to D3 hot. 2070 ** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2071 ** 05:00 00h Reserved 2072 **=============================================================================== 2073 ** 0xE3: Power Management Data Register - PMDR 2074 ** Bit Default Description 2075 ** 07:00 00h Reserved 2076 **=============================================================================== 2077 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2078 ** Bit Default Description 2079 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2080 **=============================================================================== 2081 ** 0xF1: Next Item Pointer - PX_NXTP 2082 ** Bit Default Description 2083 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2084 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 2085 **=============================================================================== 2086 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2087 ** Bit Default Description 2088 ** 15:09 00h Reserved 2089 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2090 ** The values are: 2091 ** ** BitsMax FrequencyClock Period 2092 ** ** 000PCI ModeN/A 2093 ** ** 00166 15 2094 ** ** 01010010 2095 ** ** 0111337.5 2096 ** ** 1xxreservedreserved 2097 ** ** The default value for this register is the operating frequency of the secondary bus 2098 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2099 ** secondary bus to the primary bus because there is not enough room within the limit 2100 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 2101 ** Transaction Control register. The bridge does not set this bit. 2102 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2103 ** The bridge does not set this bit. 2104 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2105 ** equal to bridge secondary bus number, device number 00h, 2106 ** and function number 0 is received on the secondary interface. 2107 ** This bit is cleared by software writing a '1'. 2108 ** 02 0b Split Completion Discarded (SCD): This bit is set 2109 ** when bridge discards a split completion moving toward the secondary bus 2110 ** because the requester would not accept it. This bit cleared by software writing a '1'. 2111 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2112 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2113 **=============================================================================== 2114 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2115 ** Bit Default Description 2116 ** 31:22 0 Reserved 2117 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2118 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2119 ** because bridge throttles traffic on the completion side. 2120 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2121 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2122 ** this bit by writing a 1b to it. 2123 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2124 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2125 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2126 ** 0=The maximum operating frequency is 66 MHz. 2127 ** 1=The maximum operating frequency is 133 MHz. 2128 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2129 ** 0=Primary Interface is connected as a 32-bit PCI bus. 2130 ** 1=Primary Interface is connected as a 64-bit PCI bus. 2131 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2132 ** of the BNUM register at offset 18h. 2133 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2134 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2135 ** May be updated whenever a PCI-X 2136 ** configuration write cycle that targets bridge scores a hit. 2137 ** 02:00 0h Function Number (FNUM): The bridge Function # 2138 **=============================================================================== 2139 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2140 ** Bit Default Description 2141 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2142 ** Software is permitted to program this register to any value greater than or equal to 2143 ** the contents of the Split Transaction Capacity register. A value less than the contents 2144 ** of the Split Transaction Capacity register causes unspecified results. 2145 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2146 ** size regardless of the amount of buffer space available. 2147 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2148 ** split completions. This register controls behavior of the bridge buffers for forwarding 2149 ** Split Transactions from a primary bus requester to a secondary bus completer. 2150 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2151 **=============================================================================== 2152 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2153 ** Bit Default Description 2154 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2155 ** Software is permitted to program this register to any value greater than or equal to 2156 ** the contents of the Split Transaction Capacity register. A value less than the contents 2157 ** of the Split Transaction Capacity register causes unspecified results. 2158 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2159 ** size regardless of the amount of buffer space available. 2160 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2161 ** split completions. This register controls behavior of the bridge buffers for forwarding 2162 ** Split Transactions from a primary bus requester to a secondary bus completer. 2163 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2164 ** (7936 bytes). 2165 ************************************************************************** 2166 */ 2167 2168 2169 2170 2171 /* 2172 ************************************************************************************************************************************* 2173 ** 80331 Address Translation Unit Register Definitions 2174 ** ATU Interface Configuration Header Format 2175 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2176 ************************************************************************************************************************************* 2177 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2178 **=================================================================================================================================== 2179 ** | ATU Device ID | Vendor ID | 00h 2180 ** ---------------------------------------------------------------------------------------------------------- 2181 ** | Status | Command | 04H 2182 ** ---------------------------------------------------------------------------------------------------------- 2183 ** | ATU Class Code | Revision ID | 08H 2184 ** ---------------------------------------------------------------------------------------------------------- 2185 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2186 ** ---------------------------------------------------------------------------------------------------------- 2187 ** | Inbound ATU Base Address 0 | 10H 2188 ** ---------------------------------------------------------------------------------------------------------- 2189 ** | Inbound ATU Upper Base Address 0 | 14H 2190 ** ---------------------------------------------------------------------------------------------------------- 2191 ** | Inbound ATU Base Address 1 | 18H 2192 ** ---------------------------------------------------------------------------------------------------------- 2193 ** | Inbound ATU Upper Base Address 1 | 1CH 2194 ** ---------------------------------------------------------------------------------------------------------- 2195 ** | Inbound ATU Base Address 2 | 20H 2196 ** ---------------------------------------------------------------------------------------------------------- 2197 ** | Inbound ATU Upper Base Address 2 | 24H 2198 ** ---------------------------------------------------------------------------------------------------------- 2199 ** | Reserved | 28H 2200 ** ---------------------------------------------------------------------------------------------------------- 2201 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2202 ** ---------------------------------------------------------------------------------------------------------- 2203 ** | Expansion ROM Base Address | 30H 2204 ** ---------------------------------------------------------------------------------------------------------- 2205 ** | Reserved Capabilities Pointer | 34H 2206 ** ---------------------------------------------------------------------------------------------------------- 2207 ** | Reserved | 38H 2208 ** ---------------------------------------------------------------------------------------------------------- 2209 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2210 ** ---------------------------------------------------------------------------------------------------------- 2211 ********************************************************************************************************************* 2212 */ 2213 /* 2214 *********************************************************************************** 2215 ** ATU Vendor ID Register - ATUVID 2216 ** ----------------------------------------------------------------- 2217 ** Bit Default Description 2218 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2219 ** This register, combined with the DID, uniquely identify the PCI device. 2220 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2221 ** to simulate the interface of a standard mechanism currently used by existing application software. 2222 *********************************************************************************** 2223 */ 2224 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2225 /* 2226 *********************************************************************************** 2227 ** ATU Device ID Register - ATUDID 2228 ** ----------------------------------------------------------------- 2229 ** Bit Default Description 2230 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2231 ** This ID, combined with the VID, uniquely identify any PCI device. 2232 *********************************************************************************** 2233 */ 2234 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2235 /* 2236 *********************************************************************************** 2237 ** ATU Command Register - ATUCMD 2238 ** ----------------------------------------------------------------- 2239 ** Bit Default Description 2240 ** 15:11 000000 2 Reserved 2241 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2242 ** 0=enables the assertion of interrupt signal. 2243 ** 1=disables the assertion of its interrupt signal. 2244 ** 09 0 2 Fast Back to Back Enable - When cleared, 2245 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2246 ** Ignored when operating in the PCI-X mode. 2247 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2248 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2249 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2250 ** of address stepping for PCI-X mode. 2251 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2252 ** is detected. When cleared, parity checking is disabled. 2253 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2254 ** does not perform VGA palette snooping. 2255 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2256 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2257 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2258 ** Not implemented and a reserved bit field. 2259 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2260 ** When cleared, disables the device from generating PCI accesses. 2261 ** When set, allows the device to behave as a PCI bus master. 2262 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2263 ** of the state of this bit. 2264 ** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2265 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2266 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2267 ** Not implemented and a reserved bit field. 2268 *********************************************************************************** 2269 */ 2270 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2271 /* 2272 *********************************************************************************** 2273 ** ATU Status Register - ATUSR (Sheet 1 of 2) 2274 ** ----------------------------------------------------------------- 2275 ** Bit Default Description 2276 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2277 ** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2278 ** �E Write Data Parity Error when the ATU is a target (inbound write). 2279 ** �E Read Data Parity Error when the ATU is a requester (outbound read). 2280 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2281 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2282 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2283 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2284 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2285 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2286 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2287 ** terminates the transaction on the PCI bus with a target abort. 2288 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2289 ** timing for a target device in Conventional PCI Mode regardless of the operating mode 2290 ** (except configuration accesses). 2291 ** 00 2=Fast 2292 ** 01 2=Medium 2293 ** 10 2=Slow 2294 ** 11 2=Reserved 2295 ** The ATU interface uses Medium timing. 2296 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2297 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2298 ** �E And the ATU acted as the requester 2299 ** for the operation in which the error occurred. 2300 ** �E And the ATUCMD register��s Parity Error Response bit is set 2301 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2302 ** �E And the ATUCMD register��s Parity Error Response bit is set 2303 ** 07 1 2 (Conventional mode) 2304 ** 0 2 (PCI-X mode) 2305 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2306 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2307 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2308 ** 06 0 2 UDF Supported - User Definable Features are not supported 2309 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2310 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2311 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2312 ** when the Interrupt Disable bit in the command register is a 0. 2313 ** 0=ATU interrupt signal deasserted. 2314 ** 1=ATU interrupt signal asserted. 2315 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2316 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2317 ** interrupt signal. 2318 ** 02:00 00000 2 Reserved. 2319 *********************************************************************************** 2320 */ 2321 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2322 /* 2323 *********************************************************************************** 2324 ** ATU Revision ID Register - ATURID 2325 ** ----------------------------------------------------------------- 2326 ** Bit Default Description 2327 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 2328 *********************************************************************************** 2329 */ 2330 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2331 /* 2332 *********************************************************************************** 2333 ** ATU Class Code Register - ATUCCR 2334 ** ----------------------------------------------------------------- 2335 ** Bit Default Description 2336 ** 23:16 05H Base Class - Memory Controller 2337 ** 15:08 80H Sub Class - Other Memory Controller 2338 ** 07:00 00H Programming Interface - None defined 2339 *********************************************************************************** 2340 */ 2341 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2342 /* 2343 *********************************************************************************** 2344 ** ATU Cacheline Size Register - ATUCLSR 2345 ** ----------------------------------------------------------------- 2346 ** Bit Default Description 2347 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2348 *********************************************************************************** 2349 */ 2350 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2351 /* 2352 *********************************************************************************** 2353 ** ATU Latency Timer Register - ATULT 2354 ** ----------------------------------------------------------------- 2355 ** Bit Default Description 2356 ** 07:03 00000 2 (for Conventional mode) 2357 ** 01000 2 (for PCI-X mode) 2358 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2359 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2360 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2361 *********************************************************************************** 2362 */ 2363 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2364 /* 2365 *********************************************************************************** 2366 ** ATU Header Type Register - ATUHTR 2367 ** ----------------------------------------------------------------- 2368 ** Bit Default Description 2369 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2370 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2371 ** header conforms to PCI Local Bus Specification, Revision 2.3. 2372 *********************************************************************************** 2373 */ 2374 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2375 /* 2376 *********************************************************************************** 2377 ** ATU BIST Register - ATUBISTR 2378 ** 2379 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2380 ** initiated. This register is the interface between the host processor requesting BIST functions and 2381 ** the 80331 replying with the results from the software implementation of the BIST functionality. 2382 ** ----------------------------------------------------------------- 2383 ** Bit Default Description 2384 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2385 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2386 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2387 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2388 ** found in ATUBISTR register bits [3:0]. 2389 ** When the ATUCR BIST Interrupt Enable bit is clear: 2390 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2391 ** The Intel XScale core does not clear this bit. 2392 ** 05:04 00 2 Reserved 2393 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2394 ** The Intel XScale core places the results of the software BIST in these bits. 2395 ** A nonzero value indicates a device-specific error. 2396 *********************************************************************************** 2397 */ 2398 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2399 2400 /* 2401 *************************************************************************************** 2402 ** ATU Base Registers and Associated Limit Registers 2403 *************************************************************************************** 2404 ** Base Address Register Limit Register Description 2405 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2406 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2407 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2408 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2409 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2410 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2411 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2412 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2413 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2414 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2415 **-------------------------------------------------------------------------------------- 2416 ** ATU Inbound Window 1 is not a translate window. 2417 ** The ATU does not claim any PCI accesses that fall within this range. 2418 ** This window is used to allocate host memory for use by Private Devices. 2419 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2420 *********************************************************************************** 2421 */ 2422 2423 /* 2424 *********************************************************************************** 2425 ** Inbound ATU Base Address Register 0 - IABAR0 2426 ** 2427 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2428 ** defines the block of memory addresses where the inbound translation window 0 begins. 2429 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2430 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2431 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2432 ** depending on the value located within the IALR0. 2433 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2434 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2435 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2436 ** Warning: 2437 ** When IALR0 is cleared prior to host configuration: 2438 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 2439 ** Assuming IALR0 is not cleared: 2440 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2441 ** when the Prefetchable Indicator is cleared prior to host configuration, 2442 ** the user should also set the Type Indicator for 32 bit addressability. 2443 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2444 ** when the Prefetchable Indicator is set prior to host configuration, the user 2445 ** should also set the Type Indicator for 64 bit addressability. 2446 ** This is the default for IABAR0. 2447 ** ----------------------------------------------------------------- 2448 ** Bit Default Description 2449 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2450 ** the translation function is to respond to when addressed from the PCI bus. 2451 ** 11:04 00H Reserved. 2452 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2453 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2454 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2455 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2456 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2457 ** The ATU does not occupy I/O space, 2458 ** thus this bit must be zero. 2459 *********************************************************************************** 2460 */ 2461 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2462 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2463 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2464 /* 2465 *********************************************************************************** 2466 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2467 ** 2468 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2469 ** Together with the Translation Base Address this register defines the actual location the translation 2470 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2471 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2472 ** Note: 2473 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2474 ** the IAUBAR0 register attributes are read-only. 2475 ** ----------------------------------------------------------------- 2476 ** Bit Default Description 2477 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2478 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2479 *********************************************************************************** 2480 */ 2481 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2482 /* 2483 *********************************************************************************** 2484 ** Inbound ATU Base Address Register 1 - IABAR1 2485 ** 2486 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2487 ** defines the block of memory addresses where the inbound translation window 1 begins. 2488 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2489 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2490 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2491 ** Warning: 2492 ** When a non-zero value is not written to IALR1 prior to host configuration, 2493 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2494 ** This is the default for IABAR1. 2495 ** Assuming a non-zero value is written to IALR1, 2496 ** the user may set the Prefetchable Indicator 2497 ** or the Type Indicator: 2498 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2499 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2500 ** the user should also leave the Type Indicator set for 32 bit addressability. 2501 ** This is the default for IABAR1. 2502 ** b. when the Prefetchable Indicator is set prior to host configuration, 2503 ** the user should also set the Type Indicator for 64 bit addressability. 2504 ** ----------------------------------------------------------------- 2505 ** Bit Default Description 2506 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2507 ** 11:04 00H Reserved. 2508 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2509 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2510 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2511 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2512 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2513 ** The ATU does not occupy I/O space, 2514 ** thus this bit must be zero. 2515 *********************************************************************************** 2516 */ 2517 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2518 /* 2519 *********************************************************************************** 2520 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2521 ** 2522 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2523 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2524 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2525 ** The programmed value within the base address register must comply with the PCI programming 2526 ** requirements for address alignment. 2527 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2528 ** from the PCI bus. 2529 ** Note: 2530 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2531 ** the IAUBAR1 register attributes are read-only. 2532 ** This is the default for IABAR1. 2533 ** ----------------------------------------------------------------- 2534 ** Bit Default Description 2535 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2536 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2537 *********************************************************************************** 2538 */ 2539 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2540 /* 2541 *********************************************************************************** 2542 ** Inbound ATU Base Address Register 2 - IABAR2 2543 ** 2544 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2545 ** defines the block of memory addresses where the inbound translation window 2 begins. 2546 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2547 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2548 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2549 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2550 ** Warning: 2551 ** When a non-zero value is not written to IALR2 prior to host configuration, 2552 ** the user should not set either the Prefetchable Indicator 2553 ** or the Type Indicator for 64 bit addressability. 2554 ** This is the default for IABAR2. 2555 ** Assuming a non-zero value is written to IALR2, 2556 ** the user may set the Prefetchable Indicator 2557 ** or the Type Indicator: 2558 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2559 ** when the Prefetchable Indicator is not set prior to host configuration, 2560 ** the user should also leave the Type Indicator set for 32 bit addressability. 2561 ** This is the default for IABAR2. 2562 ** b. when the Prefetchable Indicator is set prior to host configuration, 2563 ** the user should also set the Type Indicator for 64 bit addressability. 2564 ** ----------------------------------------------------------------- 2565 ** Bit Default Description 2566 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2567 ** the translation function is to respond to when addressed from the PCI bus. 2568 ** 11:04 00H Reserved. 2569 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2570 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2571 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2572 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2573 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2574 ** The ATU does not occupy I/O space, 2575 ** thus this bit must be zero. 2576 *********************************************************************************** 2577 */ 2578 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 2579 /* 2580 *********************************************************************************** 2581 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 2582 ** 2583 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2584 ** Together with the Translation Base Address this register defines the actual location 2585 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2586 ** The programmed value within the base address register must comply with the PCI programming 2587 ** requirements for address alignment. 2588 ** Note: 2589 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 2590 ** the IAUBAR2 register attributes are read-only. 2591 ** This is the default for IABAR2. 2592 ** ----------------------------------------------------------------- 2593 ** Bit Default Description 2594 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 2595 ** these bits define the actual location the translation function is to respond to 2596 ** when addressed from the PCI bus for addresses > 4GBytes. 2597 *********************************************************************************** 2598 */ 2599 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 2600 /* 2601 *********************************************************************************** 2602 ** ATU Subsystem Vendor ID Register - ASVIR 2603 ** ----------------------------------------------------------------- 2604 ** Bit Default Description 2605 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 2606 *********************************************************************************** 2607 */ 2608 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 2609 /* 2610 *********************************************************************************** 2611 ** ATU Subsystem ID Register - ASIR 2612 ** ----------------------------------------------------------------- 2613 ** Bit Default Description 2614 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 2615 *********************************************************************************** 2616 */ 2617 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 2618 /* 2619 *********************************************************************************** 2620 ** Expansion ROM Base Address Register -ERBAR 2621 ** ----------------------------------------------------------------- 2622 ** Bit Default Description 2623 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 2624 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 2625 ** 11:01 000H Reserved 2626 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address 2627 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 2628 *********************************************************************************** 2629 */ 2630 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 2631 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 2632 /* 2633 *********************************************************************************** 2634 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 2635 ** ----------------------------------------------------------------- 2636 ** Bit Default Description 2637 ** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 2638 ** that points to the 80331 PCl Bus Power Management extended capability. 2639 *********************************************************************************** 2640 */ 2641 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 2642 /* 2643 *********************************************************************************** 2644 ** Determining Block Sizes for Base Address Registers 2645 ** The required address size and type can be determined by writing ones to a base address register and 2646 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 2647 ** address registers upwards, the programmer can determine the required address space size. The 2648 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 2649 ** Table 105 describes the relationship between the values read back and the byte sizes the base 2650 ** address register requires. 2651 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 2652 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 2653 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 2654 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 2655 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 2656 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 2657 ** associated limit registers to enable which bits within the base address register are read/write and 2658 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 2659 ** other PCI devices even though the limit is variable. 2660 ** Table 105. Memory Block Size Read Response 2661 ** Response After Writing all 1s 2662 ** to the Base Address Register 2663 ** Size 2664 ** (Bytes) 2665 ** Response After Writing all 1s 2666 ** to the Base Address Register 2667 ** Size 2668 ** (Bytes) 2669 ** FFFFFFF0H 16 FFF00000H 1 M 2670 ** FFFFFFE0H 32 FFE00000H 2 M 2671 ** FFFFFFC0H 64 FFC00000H 4 M 2672 ** FFFFFF80H 128 FF800000H 8 M 2673 ** FFFFFF00H 256 FF000000H 16 M 2674 ** FFFFFE00H 512 FE000000H 32 M 2675 ** FFFFFC00H 1K FC000000H 64 M 2676 ** FFFFF800H 2K F8000000H 128 M 2677 ** FFFFF000H 4K F0000000H 256 M 2678 ** FFFFE000H 8K E0000000H 512 M 2679 ** FFFFC000H 16K C0000000H 1 G 2680 ** FFFF8000H 32K 80000000H 2 G 2681 ** FFFF0000H 64K 2682 ** 00000000H 2683 ** Register not 2684 ** imple-mented, 2685 ** no 2686 ** address 2687 ** space 2688 ** required. 2689 ** FFFE0000H 128K 2690 ** FFFC0000H 256K 2691 ** FFF80000H 512K 2692 ** 2693 *************************************************************************************** 2694 */ 2695 2696 2697 2698 /* 2699 *********************************************************************************** 2700 ** ATU Interrupt Line Register - ATUILR 2701 ** ----------------------------------------------------------------- 2702 ** Bit Default Description 2703 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 2704 ** request line connects to the device's PCI interrupt request lines 2705 ** (as specified in the interrupt pin register). 2706 ** A value of FFH signifies ��no connection�� or ��unknown��. 2707 *********************************************************************************** 2708 */ 2709 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 2710 /* 2711 *********************************************************************************** 2712 ** ATU Interrupt Pin Register - ATUIPR 2713 ** ----------------------------------------------------------------- 2714 ** Bit Default Description 2715 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 2716 *********************************************************************************** 2717 */ 2718 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 2719 /* 2720 *********************************************************************************** 2721 ** ATU Minimum Grant Register - ATUMGNT 2722 ** ----------------------------------------------------------------- 2723 ** Bit Default Description 2724 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 2725 *********************************************************************************** 2726 */ 2727 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 2728 /* 2729 *********************************************************************************** 2730 ** ATU Maximum Latency Register - ATUMLAT 2731 ** ----------------------------------------------------------------- 2732 ** Bit Default Description 2733 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 2734 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 2735 *********************************************************************************** 2736 */ 2737 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 2738 /* 2739 *********************************************************************************** 2740 ** Inbound Address Translation 2741 ** 2742 ** The ATU allows external PCI bus initiators to directly access the internal bus. 2743 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 2744 ** The process of inbound address translation involves two steps: 2745 ** 1. Address Detection. 2746 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 2747 ** within the address windows defined for the inbound ATU. 2748 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 2749 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 2750 ** 2. Address Translation. 2751 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 2752 ** The ATU uses the following registers in inbound address window 0 translation: 2753 ** �E Inbound ATU Base Address Register 0 2754 ** �E Inbound ATU Limit Register 0 2755 ** �E Inbound ATU Translate Value Register 0 2756 ** The ATU uses the following registers in inbound address window 2 translation: 2757 ** �E Inbound ATU Base Address Register 2 2758 ** �E Inbound ATU Limit Register 2 2759 ** �E Inbound ATU Translate Value Register 2 2760 ** The ATU uses the following registers in inbound address window 3 translation: 2761 ** �E Inbound ATU Base Address Register 3 2762 ** �E Inbound ATU Limit Register 3 2763 ** �E Inbound ATU Translate Value Register 3 2764 ** Note: Inbound Address window 1 is not a translate window. 2765 ** Instead, window 1 may be used to allocate host memory for Private Devices. 2766 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 2767 ** thus the host BIOS does not configure window 3. 2768 ** Window 3 is intended to be used as a special window into local memory for private PCI 2769 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 2770 ** PCI-to-PCI Bridge in 80331 or 2771 ** Inbound address detection is determined from the 32-bit PCI address, 2772 ** (64-bit PCI address during DACs) the base address register and the limit register. 2773 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 2774 ** 2775 ** The algorithm for detection is: 2776 ** 2777 ** Equation 1. Inbound Address Detection 2778 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 2779 ** the PCI Address is claimed by the Inbound ATU. 2780 ** 2781 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 2782 ** with the associated inbound limit register. 2783 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 2784 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 2785 ** 2786 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 2787 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 2788 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 2789 ** lower 32-bits are used during address translation. 2790 ** The algorithm is: 2791 ** 2792 ** 2793 ** Equation 2. Inbound Translation 2794 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 2795 ** 2796 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 2797 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 2798 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 2799 ** read and write commands excluding inbound configuration read and writes. 2800 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 2801 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 2802 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 2803 ** example: 2804 ** Register Values 2805 ** Base_Register=3A00 0000H 2806 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 2807 ** Value_Register=B100 0000H 2808 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 2809 ** 2810 ** Address Detection (32-bit address) 2811 ** 2812 ** PCI_Address & Limit_Register == Base_Register 2813 ** 3A45 012CH & FF80 0000H == 3A00 0000H 2814 ** 2815 ** ANS: PCI_Address is in the Inbound Translation Window 2816 ** Address Translation (to get internal bus address) 2817 ** 2818 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 2819 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 2820 ** 2821 ** ANS:IB_Address=B145 012CH 2822 *********************************************************************************** 2823 */ 2824 2825 2826 2827 /* 2828 *********************************************************************************** 2829 ** Inbound ATU Limit Register 0 - IALR0 2830 ** 2831 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 2832 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2833 ** PCI addresses to internal bus addresses. 2834 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 2835 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2836 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2837 ** Specification, Revision 2.3 for additional information on programming base address registers. 2838 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 2839 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 2840 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 2841 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 2842 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 2843 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 2844 ** ----------------------------------------------------------------- 2845 ** Bit Default Description 2846 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 2847 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 2848 ** 11:00 000H Reserved 2849 *********************************************************************************** 2850 */ 2851 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 2852 /* 2853 *********************************************************************************** 2854 ** Inbound ATU Translate Value Register 0 - IATVR0 2855 ** 2856 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 2857 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2858 ** inbound ATU address translation. 2859 ** ----------------------------------------------------------------- 2860 ** Bit Default Description 2861 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 2862 ** This value must be 64-bit aligned on the internal bus. 2863 ** The default address allows the ATU to access the internal 80331 memory-mapped registers. 2864 ** 11:00 000H Reserved 2865 *********************************************************************************** 2866 */ 2867 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 2868 /* 2869 *********************************************************************************** 2870 ** Expansion ROM Limit Register - ERLR 2871 ** 2872 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 2873 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 2874 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 2875 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 2876 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 2877 ** the corresponding bit within the ERBAR read/write from PCI. 2878 ** ----------------------------------------------------------------- 2879 ** Bit Default Description 2880 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 2881 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 2882 ** 11:00 000H Reserved. 2883 *********************************************************************************** 2884 */ 2885 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 2886 /* 2887 *********************************************************************************** 2888 ** Expansion ROM Translate Value Register - ERTVR 2889 ** 2890 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 2891 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 2892 ** Expansion ROM address translation. 2893 ** ----------------------------------------------------------------- 2894 ** Bit Default Description 2895 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 2896 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 2897 ** 11:00 000H Reserved 2898 *********************************************************************************** 2899 */ 2900 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 2901 /* 2902 *********************************************************************************** 2903 ** Inbound ATU Limit Register 1 - IALR1 2904 ** 2905 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 2906 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 2907 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 2908 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 2909 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 2910 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 2911 ** register. 2912 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 2913 ** not process any PCI bus transactions to this memory range. 2914 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 2915 ** IAUBAR1, and IALR1. 2916 ** ----------------------------------------------------------------- 2917 ** Bit Default Description 2918 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 2919 ** required for the ATUs memory window 1. 2920 ** 11:00 000H Reserved 2921 *********************************************************************************** 2922 */ 2923 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 2924 /* 2925 *********************************************************************************** 2926 ** Inbound ATU Limit Register 2 - IALR2 2927 ** 2928 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 2929 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2930 ** PCI addresses to internal bus addresses. 2931 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 2932 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 2933 ** register provides the block size requirements for the base address register. The remaining registers 2934 ** used for performing address translation are discussed in Section 3.2.1.1. 2935 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 2936 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2937 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2938 ** Specification, Revision 2.3 for additional information on programming base address registers. 2939 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 2940 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 2941 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 2942 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 2943 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 2944 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 2945 ** register. 2946 ** ----------------------------------------------------------------- 2947 ** Bit Default Description 2948 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 2949 ** required for the ATUs memory window 2. 2950 ** 11:00 000H Reserved 2951 *********************************************************************************** 2952 */ 2953 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 2954 /* 2955 *********************************************************************************** 2956 ** Inbound ATU Translate Value Register 2 - IATVR2 2957 ** 2958 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 2959 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2960 ** inbound ATU address translation. 2961 ** ----------------------------------------------------------------- 2962 ** Bit Default Description 2963 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 2964 ** This value must be 64-bit aligned on the internal bus. 2965 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 2966 ** 11:00 000H Reserved 2967 *********************************************************************************** 2968 */ 2969 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 2970 /* 2971 *********************************************************************************** 2972 ** Outbound I/O Window Translate Value Register - OIOWTVR 2973 ** 2974 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 2975 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 2976 ** result of the outbound ATU address translation. 2977 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 2978 ** length of 64 Kbytes. 2979 ** ----------------------------------------------------------------- 2980 ** Bit Default Description 2981 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 2982 ** 15:00 0000H Reserved 2983 *********************************************************************************** 2984 */ 2985 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 2986 /* 2987 *********************************************************************************** 2988 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 2989 ** 2990 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 2991 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 2992 ** driven on the PCI bus as a result of the outbound ATU address translation. 2993 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 2994 ** of 64 Mbytes. 2995 ** ----------------------------------------------------------------- 2996 ** Bit Default Description 2997 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 2998 ** 25:02 00 0000H Reserved 2999 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3000 ** Only linear incrementing mode is supported. 3001 *********************************************************************************** 3002 */ 3003 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3004 /* 3005 *********************************************************************************** 3006 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3007 ** 3008 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3009 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3010 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3011 ** a SAC is generated on the PCI bus. 3012 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3013 ** length of 64 Mbytes. 3014 ** ----------------------------------------------------------------- 3015 ** Bit Default Description 3016 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3017 *********************************************************************************** 3018 */ 3019 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3020 /* 3021 *********************************************************************************** 3022 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3023 ** 3024 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3025 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3026 ** driven on the PCI bus as a result of the outbound ATU address translation. 3027 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3028 ** of 64 Mbytes. 3029 ** ----------------------------------------------------------------- 3030 ** Bit Default Description 3031 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3032 ** 25:02 00 0000H Reserved 3033 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3034 ** Only linear incrementing mode is supported. 3035 *********************************************************************************** 3036 */ 3037 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3038 /* 3039 *********************************************************************************** 3040 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3041 ** 3042 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3043 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3044 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3045 ** a SAC is generated on the PCI bus. 3046 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3047 ** of 64 Mbytes. 3048 ** ----------------------------------------------------------------- 3049 ** Bit Default Description 3050 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3051 *********************************************************************************** 3052 */ 3053 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3054 /* 3055 *********************************************************************************** 3056 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3057 ** 3058 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3059 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3060 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3061 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3062 ** ----------------------------------------------------------------- 3063 ** Bit Default Description 3064 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3065 *********************************************************************************** 3066 */ 3067 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3068 /* 3069 *********************************************************************************** 3070 ** ATU Configuration Register - ATUCR 3071 ** 3072 ** The ATU Configuration Register controls the outbound address translation for address translation 3073 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3074 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3075 ** interrupt enabling. 3076 ** ----------------------------------------------------------------- 3077 ** Bit Default Description 3078 ** 31:20 00H Reserved 3079 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3080 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3081 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3082 ** applicable in the PCI-X mode. 3083 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3084 ** with Direct Addressing enabled (bit 7 of the ATUCR set), 3085 ** the ATU forwards internal bus cycles with an address between 0000.0040H and 3086 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3087 ** When clear, no translation occurs. 3088 ** 17 0 2 Reserved 3089 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3090 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3091 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3092 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3093 ** 14:10 00000 2 Reserved 3094 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3095 ** when the ATU detects that SERR# was asserted. When clear, 3096 ** the Intel XScale core is not interrupted when SERR# is detected. 3097 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3098 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3099 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3100 ** the ATUCR. 3101 ** 07:04 0000 2 Reserved 3102 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3103 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3104 ** in the ATUBISTR register. 3105 ** 02 0 2 Reserved 3106 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3107 ** When cleared, disables the outbound ATU. 3108 ** 00 0 2 Reserved 3109 *********************************************************************************** 3110 */ 3111 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3112 /* 3113 *********************************************************************************** 3114 ** PCI Configuration and Status Register - PCSR 3115 ** 3116 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3117 ** various features of the PCI bus interface. 3118 ** ----------------------------------------------------------------- 3119 ** Bit Default Description 3120 ** 31:19 0000H Reserved 3121 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3122 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3123 ** Response bit is cleared. Set under the following conditions: 3124 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3125 ** 17:16 Varies with 3126 ** external state 3127 ** of DEVSEL#, 3128 ** STOP#, and 3129 ** TRDY#, 3130 ** during 3131 ** P_RST# 3132 ** PCI-X capability - These two bits define the mode of 3133 ** the PCI bus (conventional or PCI-X) as well as the 3134 ** operating frequency in the case of PCI-X mode. 3135 ** 00 - Conventional PCI mode 3136 ** 01 - PCI-X 66 3137 ** 10 - PCI-X 100 3138 ** 11 - PCI-X 133 3139 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3140 ** Revision 1.0a, the operating 3141 ** mode is determined by an initialization pattern on the PCI bus during 3142 ** P_RST# assertion: 3143 ** DEVSEL# STOP# TRDY# Mode 3144 ** Deasserted Deasserted Deasserted Conventional 3145 ** Deasserted Deasserted Asserted PCI-X 66 3146 ** Deasserted Asserted Deasserted PCI-X 100 3147 ** Deasserted Asserted Asserted PCI-X 133 3148 ** All other patterns are reserved. 3149 ** 15 0 2 3150 ** Outbound Transaction Queue Busy: 3151 ** 0=Outbound Transaction Queue Empty 3152 ** 1=Outbound Transaction Queue Busy 3153 ** 14 0 2 3154 ** Inbound Transaction Queue Busy: 3155 ** 0=Inbound Transaction Queue Empty 3156 ** 1=Inbound Transaction Queue Busy 3157 ** 13 0 2 Reserved. 3158 ** 12 0 2 Discard Timer Value - This bit controls the time-out value 3159 ** for the four discard timers attached to the queues holding read data. 3160 ** A value of 0 indicates the time-out value is 2 15 clocks. 3161 ** A value of 1 indicates the time-out value is 2 10 clocks. 3162 ** 11 0 2 Reserved. 3163 ** 10 Varies with 3164 ** external state 3165 ** of M66EN 3166 ** during 3167 ** P_RST# 3168 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3169 ** Conventional PCI mode by the assertion of M66EN during bus initialization. 3170 ** When clear, the interface 3171 ** has been initialized as a 33 MHz bus. 3172 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3173 ** 09 0 2 Reserved 3174 ** 08 Varies with 3175 ** external state 3176 ** of REQ64# 3177 ** during 3178 ** P_RST# 3179 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3180 ** configured as 64-bit capable by 3181 ** the assertion of REQ64# on the rising edge of P_RST#. When set, 3182 ** the PCI interface is configured as 3183 ** 32-bit only. 3184 ** 07:06 00 2 Reserved. 3185 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3186 ** and all units on the internal 3187 ** bus. In addition to the internal bus initialization, 3188 ** this bit triggers the assertion of the M_RST# pin for 3189 ** initialization of registered DIMMs. When set: 3190 ** When operating in the conventional PCI mode: 3191 ** �E All current PCI transactions being mastered by the ATU completes, 3192 ** and the ATU master interfaces 3193 ** proceeds to an idle state. No additional transactions is mastered by these units 3194 ** until the internal bus reset is complete. 3195 ** �E All current transactions being slaved by the ATU on either the PCI bus 3196 ** or the internal bus 3197 ** completes, and the ATU target interfaces proceeds to an idle state. 3198 ** All future slave transactions master aborts, 3199 ** with the exception of the completion cycle for the transaction that set the Reset 3200 ** Internal Bus bit in the PCSR. 3201 ** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3202 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3203 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3204 ** Internal Bus clocks. 3205 ** �E The 80331 hardware clears this bit after the reset operation completes. 3206 ** When operating in the PCI-X mode: 3207 ** The ATU hardware responds the same as in Conventional PCI-X mode. 3208 ** However, this may create a problem in PCI-X mode for split requests in 3209 ** that there may still be an outstanding split completion that the 3210 ** ATU is either waiting to receive (Outbound Request) or initiate 3211 ** (Inbound Read Request). For a cleaner 3212 ** internal bus reset, host software can take the following steps prior 3213 ** to asserting Reset Internal bus: 3214 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3215 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3216 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3217 ** queue busy bits to be clear. 3218 ** 3. Set the Reset Internal Bus bit 3219 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3220 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3221 ** completion transactions. 3222 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3223 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 3224 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3225 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3226 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3227 ** Bus Master Indicator signal P_BMI used 3228 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3229 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3230 ** 03 Varies with external state of PRIVDEV during 3231 ** P_RST# 3232 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3233 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3234 ** 0=Private Device control Disabled - SISR register bits default to zero 3235 ** 1=Private Device control Enabled - SISR register bits default to one 3236 ** 02 Varies with external state of RETRY during P_RST# 3237 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3238 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3239 ** configuration cycles. 3240 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3241 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3242 ** low, the bit is cleared. 3243 ** 01 Varies with external state of CORE_RST# during P_RST# 3244 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3245 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3246 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3247 ** XScale core reset. 3248 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3249 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3250 ** high, the bit is clear. 3251 ** 00 Varies with external state of PRIVMEM during P_RST# 3252 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3253 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3254 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3255 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 3256 *********************************************************************************** 3257 */ 3258 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3259 /* 3260 *********************************************************************************** 3261 ** ATU Interrupt Status Register - ATUISR 3262 ** 3263 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3264 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3265 ** of the 80331. All bits in this register are Read/Clear. 3266 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3267 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3268 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3269 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3270 ** register. 3271 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3272 ** ----------------------------------------------------------------- 3273 ** Bit Default Description 3274 ** 31:18 0000H Reserved 3275 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3276 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3277 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3278 ** 16 0 2 Reserved 3279 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3280 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3281 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3282 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3283 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3284 ** Configure Register Write Interrupt. 3285 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3286 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 3287 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3288 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 3289 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3290 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3291 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3292 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3293 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3294 ** register��s Parity Error Response bit is cleared. Set under the following conditions: 3295 ** �E Write Data Parity Error when the ATU is a target (inbound write). 3296 ** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3297 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3298 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3299 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3300 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3301 ** register bits 3:0. 3302 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3303 ** of the ATU Configure Register Write Interrupt. 3304 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3305 ** 06:05 00 2 Reserved. 3306 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3307 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3308 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3309 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3310 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3311 ** conditions: 3312 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3313 ** �E And the ATU acted as the requester for the operation in which the error occurred. 3314 ** �E And the ATUCMD register��s Parity Error Response bit is set 3315 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3316 ** �E And the ATUCMD register��s Parity Error Response bit is set 3317 *********************************************************************************** 3318 */ 3319 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3320 /* 3321 *********************************************************************************** 3322 ** ATU Interrupt Mask Register - ATUIMR 3323 ** 3324 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3325 ** generated by the ATU. 3326 ** ----------------------------------------------------------------- 3327 ** Bit Default Description 3328 ** 31:15 0 0000H Reserved 3329 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3330 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3331 ** 0=Not Masked 3332 ** 1=Masked 3333 ** 13 0 2 Reserved 3334 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3335 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3336 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3337 ** 0=Not Masked 3338 ** 1=Masked 3339 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3340 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3341 ** IABAR1 register or the IAUBAR1 register. 3342 ** 0=Not Masked 3343 ** 1=Masked 3344 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3345 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3346 ** 0=Not Masked 3347 ** 1=Masked 3348 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3349 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3350 ** PCIXSR being set. 3351 ** 0=Not Masked 3352 ** 1=Masked 3353 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3354 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3355 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3356 ** 0=Not Masked 3357 ** 1=Masked 3358 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3359 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3360 ** 0=Not Masked 3361 ** 1=Masked 3362 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3363 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3364 ** 0=Not Masked 3365 ** 1=Masked 3366 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3367 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3368 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3369 ** 0=Not Masked 3370 ** 1=Masked 3371 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3372 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3373 ** 0=Not Masked 3374 ** 1=Masked 3375 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3376 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3377 ** 0=Not Masked 3378 ** 1=Masked 3379 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3380 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3381 ** 0=Not Masked 3382 ** 1=Masked 3383 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3384 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3385 ** inbound write transaction. 3386 ** 0=SERR# Not Asserted due to error 3387 ** 1=SERR# Asserted due to error 3388 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3389 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3390 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3391 ** actually requested from the inbound read queue. 3392 ** 0=Disconnect with data 3393 ** (the data being up to 64 bits of 1��s) 3394 ** 1=Target Abort 3395 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3396 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3397 ** independent of the setting of this bit. 3398 *********************************************************************************** 3399 */ 3400 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3401 /* 3402 *********************************************************************************** 3403 ** Inbound ATU Base Address Register 3 - IABAR3 3404 ** 3405 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3406 ** of memory addresses where the inbound translation window 3 begins. 3407 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3408 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3409 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3410 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3411 ** Note: 3412 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3413 ** IABAR3 is not configured by the host during normal system initialization. 3414 ** Warning: 3415 ** When a non-zero value is not written to IALR3, 3416 ** the user should not set either the Prefetchable Indicator 3417 ** or the Type Indicator for 64 bit addressability. 3418 ** This is the default for IABAR3. 3419 ** Assuming a non-zero value is written to IALR3, 3420 ** the user may set the Prefetchable Indicator 3421 ** or the Type Indicator: 3422 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3423 ** when the Prefetchable Indicator is not set, 3424 ** the user should also leave the Type Indicator set for 32 bit addressability. 3425 ** This is the default for IABAR3. 3426 ** b. when the Prefetchable Indicator is set, 3427 ** the user should also set the Type Indicator for 64 bit addressability. 3428 ** ----------------------------------------------------------------- 3429 ** Bit Default Description 3430 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3431 ** the translation function is to respond to when addressed from the PCI bus. 3432 ** 11:04 00H Reserved. 3433 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3434 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3435 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3436 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3437 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3438 ** The ATU does not occupy I/O space, 3439 ** thus this bit must be zero. 3440 *********************************************************************************** 3441 */ 3442 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3443 /* 3444 *********************************************************************************** 3445 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3446 ** 3447 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3448 ** Together with the Translation Base Address this register defines the actual location 3449 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3450 ** The programmed value within the base address register must comply with the PCI programming 3451 ** requirements for address alignment. 3452 ** Note: 3453 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3454 ** the IAUBAR3 register attributes are read-only. 3455 ** This is the default for IABAR3. 3456 ** ----------------------------------------------------------------- 3457 ** Bit Default Description 3458 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3459 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3460 *********************************************************************************** 3461 */ 3462 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3463 /* 3464 *********************************************************************************** 3465 ** Inbound ATU Limit Register 3 - IALR3 3466 ** 3467 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3468 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3469 ** PCI addresses to internal bus addresses. 3470 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3471 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3472 ** register provides the block size requirements for the base address register. The remaining registers 3473 ** used for performing address translation are discussed in Section 3.2.1.1. 3474 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3475 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3476 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3477 ** Specification, Revision 2.3 for additional information on programming base address registers. 3478 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3479 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3480 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3481 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3482 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3483 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3484 ** register. 3485 ** ----------------------------------------------------------------- 3486 ** Bit Default Description 3487 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3488 ** for the ATUs memory window 3. 3489 ** 11:00 000H Reserved 3490 *********************************************************************************** 3491 */ 3492 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3493 /* 3494 *********************************************************************************** 3495 ** Inbound ATU Translate Value Register 3 - IATVR3 3496 ** 3497 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3498 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3499 ** inbound ATU address translation. 3500 ** ----------------------------------------------------------------- 3501 ** Bit Default Description 3502 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3503 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3504 ** access the internal 80331 memory-mapped registers. 3505 ** 11:00 000H Reserved 3506 *********************************************************************************** 3507 */ 3508 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3509 /* 3510 *********************************************************************************** 3511 ** Outbound Configuration Cycle Address Register - OCCAR 3512 ** 3513 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3514 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3515 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3516 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3517 ** PCI bus. 3518 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3519 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3520 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3521 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3522 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3523 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3524 ** ----------------------------------------------------------------- 3525 ** Bit Default Description 3526 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3527 ** configuration read or write cycle. 3528 *********************************************************************************** 3529 */ 3530 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3531 /* 3532 *********************************************************************************** 3533 ** Outbound Configuration Cycle Data Register - OCCDR 3534 ** 3535 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3536 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3537 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3538 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3539 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3540 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3541 ** actually entered into the data register (which does not physically exist). 3542 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3543 ** within the ATU configuration space. 3544 ** ----------------------------------------------------------------- 3545 ** Bit Default Description 3546 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3547 ** or write cycle. 3548 *********************************************************************************** 3549 */ 3550 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3551 /* 3552 *********************************************************************************** 3553 ** VPD Capability Identifier Register - VPD_CAPID 3554 ** 3555 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3556 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3557 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3558 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3559 ** ----------------------------------------------------------------- 3560 ** Bit Default Description 3561 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3562 ** Headers as being the VPD capability registers. 3563 *********************************************************************************** 3564 */ 3565 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3566 /* 3567 *********************************************************************************** 3568 ** VPD Next Item Pointer Register - VPD_NXTP 3569 ** 3570 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3571 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3572 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 3573 ** ----------------------------------------------------------------- 3574 ** Bit Default Description 3575 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3576 ** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 3577 ** extended capabilities in the 80331, the register is set to 00H. 3578 *********************************************************************************** 3579 */ 3580 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 3581 /* 3582 *********************************************************************************** 3583 ** VPD Address Register - VPD_AR 3584 ** 3585 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 3586 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 3587 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 3588 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 3589 ** write of the VPD through the VPD Data Register. 3590 ** ----------------------------------------------------------------- 3591 ** Bit Default Description 3592 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 3593 ** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 3594 ** how the 80331 handles the data transfer. 3595 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 3596 ** Vital Product Data from the VPD storage component. 3597 *********************************************************************************** 3598 */ 3599 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 3600 /* 3601 *********************************************************************************** 3602 ** VPD Data Register - VPD_DR 3603 ** 3604 ** This register is used to transfer data between the 80331 and the VPD storage component. 3605 ** ----------------------------------------------------------------- 3606 ** Bit Default Description 3607 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 3608 *********************************************************************************** 3609 */ 3610 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 3611 /* 3612 *********************************************************************************** 3613 ** Power Management Capability Identifier Register -PM_CAPID 3614 ** 3615 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3616 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3617 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 3618 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 3619 ** Interface Specification, Revision 1.1. 3620 ** ----------------------------------------------------------------- 3621 ** Bit Default Description 3622 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 3623 ** Headers as being the PCI Power Management Registers. 3624 *********************************************************************************** 3625 */ 3626 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 3627 /* 3628 *********************************************************************************** 3629 ** Power Management Next Item Pointer Register - PM_NXTP 3630 ** 3631 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3632 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3633 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 3634 ** ----------------------------------------------------------------- 3635 ** Bit Default Description 3636 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3637 ** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 3638 *********************************************************************************** 3639 */ 3640 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 3641 /* 3642 *********************************************************************************** 3643 ** Power Management Capabilities Register - PM_CAP 3644 ** 3645 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 3646 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 3647 ** information on the capabilities of the ATU function related to power management. 3648 ** ----------------------------------------------------------------- 3649 ** Bit Default Description 3650 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 3651 ** is not supported by the 80331. 3652 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 3653 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 3654 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 3655 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 3656 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 3657 ** following the transition to the D0 uninitialized state. 3658 ** 4 0 2 Reserved. 3659 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 3660 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 3661 ** Interface Specification, Revision 1.1 3662 *********************************************************************************** 3663 */ 3664 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 3665 /* 3666 *********************************************************************************** 3667 ** Power Management Control/Status Register - PM_CSR 3668 ** 3669 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 3670 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 3671 ** interface for the power management extended capability. 3672 ** ----------------------------------------------------------------- 3673 ** Bit Default Description 3674 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 3675 ** supported by the 80331. 3676 ** 14:9 00H Reserved 3677 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 3678 ** generation from any power state. 3679 ** 7:2 000000 2 Reserved 3680 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 3681 ** of a function and to set the function into a new power state. The definition of the values is: 3682 ** 00 2 - D0 3683 ** 01 2 - D1 3684 ** 10 2 - D2 (Unsupported) 3685 ** 11 2 - D3 hot 3686 ** The 80331 supports only the D0 and D3 hot states. 3687 ** 3688 *********************************************************************************** 3689 */ 3690 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 3691 /* 3692 *********************************************************************************** 3693 ** PCI-X Capability Identifier Register - PX_CAPID 3694 ** 3695 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3696 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3697 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 3698 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 3699 ** ----------------------------------------------------------------- 3700 ** Bit Default Description 3701 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 3702 ** Headers as being the PCI-X capability registers. 3703 *********************************************************************************** 3704 */ 3705 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 3706 /* 3707 *********************************************************************************** 3708 ** PCI-X Next Item Pointer Register - PX_NXTP 3709 ** 3710 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3711 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3712 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 3713 ** to 00H. 3714 ** However, this register may be written to B8H prior to host configuration to include the VPD 3715 ** capability located at off-set B8H. 3716 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 3717 ** produce unpredictable system behavior. 3718 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 3719 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 3720 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 3721 ** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 3722 ** PCSR�� on page 253 for more details on the 80331 initialization modes. 3723 ** ----------------------------------------------------------------- 3724 ** Bit Default Description 3725 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3726 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 3727 ** extended capabilities in the 80331, the register is set to 00H. 3728 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 3729 ** VPD extended capabilities header. 3730 *********************************************************************************** 3731 */ 3732 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 3733 /* 3734 *********************************************************************************** 3735 ** PCI-X Command Register - PX_CMD 3736 ** 3737 ** This register controls various modes and features of ATU and Message Unit when operating in the 3738 ** PCI-X mode. 3739 ** ----------------------------------------------------------------- 3740 ** Bit Default Description 3741 ** 15:7 000000000 2 Reserved. 3742 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 3743 ** the device is permitted to have outstanding at one time. 3744 ** Register Maximum Outstanding 3745 ** 0 1 3746 ** 1 2 3747 ** 2 3 3748 ** 3 4 3749 ** 4 8 3750 ** 5 12 3751 ** 6 16 3752 ** 7 32 3753 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 3754 ** initiating a Sequence with one of the burst memory read commands. 3755 ** Register Maximum Byte Count 3756 ** 0 512 3757 ** 1 1024 3758 ** 2 2048 3759 ** 3 4096 3760 ** 1 0 2 3761 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 3762 ** of Transactions. 3763 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 3764 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 3765 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 3766 *********************************************************************************** 3767 */ 3768 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 3769 /* 3770 *********************************************************************************** 3771 ** PCI-X Status Register - PX_SR 3772 ** 3773 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 3774 ** Unit when operating in the PCI-X mode. 3775 ** ----------------------------------------------------------------- 3776 ** Bit Default Description 3777 ** 31:30 00 2 Reserved 3778 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3779 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 3780 ** writes a 1 to this location. 3781 ** 0=no Split Completion error message received. 3782 ** 1=a Split Completion error message has been received. 3783 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 3784 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 3785 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 3786 ** 1 16 512 (Default) 3787 ** 2 32 1024 3788 ** 2 32 2048 3789 ** 2 32 4096 3790 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 3791 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 3792 ** to 1024 bytes. 3793 ** 20 1 2 80331 is a complex device. 3794 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 3795 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 3796 ** 0=no unexpected Split Completion has been received. 3797 ** 1=an unexpected Split Completion has been received. 3798 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 3799 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 3800 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 3801 ** location. 3802 ** 0=no Split Completion has been discarded. 3803 ** 1=a Split Completion has been discarded. 3804 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 3805 ** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 3806 ** 17 1 2 80331 is a 133 MHz capable device. 3807 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 3808 ** therefore this bit is always set. 3809 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 3810 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 3811 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled 3812 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 3813 ** 0=The bus is 32 bits wide. 3814 ** 1=The bus is 64 bits wide. 3815 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 3816 ** segment for the device containing this function. The function uses this number as part of its Requester 3817 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 3818 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 3819 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 3820 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 3821 ** the following are true: 3822 ** 1. The transaction uses a Configuration Write command. 3823 ** 2. IDSEL is asserted during the address phase. 3824 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3825 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 3826 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 3827 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 3828 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 3829 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 3830 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 3831 ** time the function is addressed by a Configuration Write transaction, the device must update this register 3832 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 3833 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 3834 ** Write transaction when all of the following are true: 3835 ** 1. The transaction uses a Configuration Write command. 3836 ** 2. IDSEL is asserted during the address phase. 3837 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3838 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 3839 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 3840 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 3841 ** configuration transaction to which this function responds. The function uses this number as part of its 3842 ** Requester ID and Completer ID. 3843 ** 3844 ************************************************************************** 3845 */ 3846 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 3847 3848 /* 3849 ************************************************************************** 3850 ** Inbound Read Transaction 3851 ** ======================================================================== 3852 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 3853 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 3854 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 3855 ** (IRQ). 3856 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 3857 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 3858 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 3859 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 3860 ** an inbound read transaction on the PCI bus is summarized in the following statements: 3861 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 3862 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 3863 ** Address Register during DACs) and Inbound Limit Register. 3864 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 3865 ** information from a previous delayed read, the current transaction information is compared to 3866 ** the previous transaction information (based on the setting of the DRC Alias bit in 3867 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 3868 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 3869 ** match and the data is not available, a Retry is signaled with no other action taken. When there 3870 ** is not a match and when the ITQ has less than eight entries, capture the transaction 3871 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 3872 ** when the ITQ is full, then signal a Retry with no other action taken. 3873 ** �X When an address parity error is detected, the address parity response defined in 3874 ** Section 3.7 is used. 3875 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 3876 ** the IRQ, it continues until one of the following is true: 3877 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 3878 ** data is flushed. 3879 ** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 3880 ** Target Abort is never entered into the IRQ, and therefore is never returned. 3881 ** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 3882 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 3883 ** the initiator on the last data word available. 3884 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 3885 ** command are latched into the available ITQ and a Split Response Termination is signalled to 3886 ** the initiator. 3887 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 3888 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 3889 ** before returning read data by generating the split completion transaction on the PCI-X bus. 3890 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 3891 ** transfer by returning data in 1024 byte aligned chunks. 3892 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it 3893 ** continues until one of the following is true: 3894 ** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 3895 ** ADB (when the requester is a bridge) 3896 ** �X The byte count is satisfied. 3897 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 3898 ** Message (message class=2h - completer error, and message index=81h - target abort) to 3899 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3900 ** Refer to Section 3.7.1. 3901 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 3902 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 3903 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3904 ** Refer to Section 3.7.1 3905 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 3906 ** bus, the ATU PCI slave interface waits with no premature disconnects. 3907 ** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 3908 ** taken by the target interface. Refer to Section 3.7.2.5. 3909 ** �E When operating in the conventional PCI mode, when the read on the internal bus is 3910 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 3911 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 3912 ** target abort is used, when clear, a disconnect is used. 3913 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 3914 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 3915 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 3916 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 3917 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 3918 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 3919 ** transaction is flushed. Refer to Section 3.7.1. 3920 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus 3921 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 3922 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 3923 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 3924 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 3925 ** error, and message index=80h - internal bus master abort) to inform the requester about the 3926 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 3927 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 3928 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 3929 ** prevents it from accepting the completion it requested. In this case, since the Split Request 3930 ** addresses a location that has no read side effects, the completer must discard the Split 3931 ** Completion and take no further action. 3932 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 3933 ** statements: 3934 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 3935 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 3936 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 3937 ** always uses conventional PCI ordering rules. 3938 ** �E Once the internal bus is granted, the internal bus master interface drives the translated address 3939 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 3940 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 3941 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 3942 ** master has been delivered the target abort). 3943 ** �E Once the translated address is on the bus and the transaction has been accepted, the internal 3944 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 3945 ** received by the IRQ until one of the following is true: 3946 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus 3947 ** initiator interface performs a initiator completion in this case. 3948 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 3949 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 3950 ** informed. 3951 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 3952 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 3953 ** Completion Message (message class=2h - completer error, and message index=81h - 3954 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 3955 ** ITQ for this transaction is flushed. 3956 ** �X When operating in the conventional PCI mode, a single data phase disconnection is 3957 ** received from the internal bus target. When the data has not been received up to the next 3958 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 3959 ** When not, the bus returns to idle. 3960 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from 3961 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 3962 ** obtain remaining data. 3963 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 3964 ** from the internal bus target. The bus returns to idle. 3965 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 3966 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 3967 ** remaining data. 3968 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 3969 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 3970 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 3971 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 3972 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 3973 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 3974 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 3975 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 3976 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 3977 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 3978 ** commands did not match, only the address. 3979 ************************************************************************** 3980 */ 3981 /* 3982 ************************************************************************** 3983 ** Inbound Write Transaction 3984 **======================================================================== 3985 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 3986 ** memory or a 80331 memory-mapped register. 3987 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 3988 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 3989 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 3990 ** Base Address Register during DACs) and Inbound Limit Register. 3991 ** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 3992 ** available, the address is captured and the first data phase is accepted. 3993 ** �E The PCI interface continues to accept write data until one of the following is true: 3994 ** �X The initiator performs a disconnect. 3995 ** �X The transaction crosses a buffer boundary. 3996 ** �E When an address parity error is detected during the address phase of the transaction, the 3997 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 3998 ** parity error response. 3999 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4000 ** parity error mechanism described in Section 3.7.1 is used. 4001 ** �E When a data parity error is detected while accepting data, the slave interface sets the 4002 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4003 ** for details of the inbound write data parity error response. 4004 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4005 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4006 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 4007 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4008 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4009 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4010 ** interface, when operating in the PCI mode. 4011 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 4012 ** configuration write transactions are processed as split transactions. The ATU generates a Split 4013 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4014 ** 00h - Write Completion Message) once a configuration write is successfully executed. 4015 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4016 ** The ATU handles such transactions as independent transactions. 4017 ** Data flow for the inbound write transaction on the internal bus is summarized as: 4018 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4019 ** with associated data in the IWQ. 4020 ** �E When the internal bus is granted, the internal bus master interface initiates the write 4021 ** transaction by driving the translated address onto the internal bus. For details on inbound 4022 ** address translation. 4023 ** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4024 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4025 ** interface. 4026 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4027 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4028 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4029 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 4030 ** internal bus ownership. 4031 ** �E The internal bus interface stops transferring data from the current transaction to the internal 4032 ** bus when one of the following conditions becomes true: 4033 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4034 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4035 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4036 ** complete the delivery of remaining data using the same sequence ID but with the 4037 ** modified starting address and byte count. 4038 ** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4039 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4040 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4041 ** complete the delivery of remaining data using the same sequence ID but with the 4042 ** modified starting address and byte count. 4043 ** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4044 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4045 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4046 ** bus to complete the delivery of remaining data using the same sequence ID but with the 4047 ** modified starting address and byte count. 4048 ** �X The data from the current transaction has completed (satisfaction of byte count). An 4049 ** initiator termination is performed and the bus returns to idle. 4050 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4051 ** Data is flushed from the IWQ. 4052 ***************************************************************** 4053 */ 4054 4055 4056 4057 /* 4058 ************************************************************************** 4059 ** Inbound Read Completions Data Parity Errors 4060 **======================================================================== 4061 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4062 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4063 ** completion transaction, the ATU attempts to complete the transaction normally and no further 4064 ** action is taken. 4065 ************************************************************************** 4066 */ 4067 4068 /* 4069 ************************************************************************** 4070 ** Inbound Configuration Write Completion Message Data Parity Errors 4071 **======================================================================== 4072 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4073 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4074 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 4075 ** normally and no further action is taken. 4076 ************************************************************************** 4077 */ 4078 4079 /* 4080 ************************************************************************** 4081 ** Inbound Read Request Data Parity Errors 4082 **===================== Immediate Data Transfer ========================== 4083 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4084 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4085 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4086 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4087 ** required and no error bits are set. 4088 **=====================Split Response Termination========================= 4089 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4090 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4091 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4092 ** action is required and no error bits are set. 4093 ************************************************************************** 4094 */ 4095 4096 /* 4097 ************************************************************************** 4098 ** Inbound Write Request Data Parity Errors 4099 **======================================================================== 4100 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4101 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4102 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4103 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4104 ** the given constraints are taken by the ATU: 4105 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4106 ** following the data phase in which the data parity error is detected on the bus. This is only 4107 ** done when the Parity Error Response bit in the ATUCMD is set. 4108 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4109 ** actions is taken: 4110 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4111 ** Detected Parity Error bit in the ATUISR. When set, no action. 4112 *************************************************************************** 4113 */ 4114 4115 4116 /* 4117 *************************************************************************** 4118 ** Inbound Configuration Write Request 4119 ** ===================================================================== 4120 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4121 ** =============================================== 4122 ** Conventional PCI Mode 4123 ** =============================================== 4124 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4125 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4126 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4127 ** parts of the transactions: 4128 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4129 ** address/command and data for delayed delivery to the internal configuration register. 4130 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4131 ** of the operation back to the original master. 4132 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4133 ** inbound transactions during Delayed Write Request cycles with the given constraints: 4134 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4135 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4136 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4137 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4138 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4139 ** forwarded to the internal bus. PERR# is not asserted. 4140 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4141 ** actions is taken: 4142 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4143 ** Detected Parity Error bit in the ATUISR. When set, no action. 4144 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4145 ** bus and the ATU returns the status from the internal bus, completing the transaction. 4146 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4147 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 4148 ** returned is normal completion) the ATU performs the following actions with the given constraints: 4149 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4150 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4151 ** the IDWQ remains since the data of retried command did not match the data within the queue. 4152 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4153 ** actions is taken: 4154 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4155 ** Detected Parity Error bit in the ATUISR. When set, no action. 4156 ** =================================================== 4157 ** PCI-X Mode 4158 ** =================================================== 4159 ** Data parity errors occurring during configuration write operations received by the ATU may cause 4160 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4161 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4162 ** Specifically, the following actions with the given constraints are then taken by the ATU: 4163 ** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4164 ** cycles following the Split Response Termination in which the data parity error is detected on 4165 ** the bus. When the ATU asserts PERR#, additional actions is taken: 4166 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4167 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4168 ** that addresses the requester of the configuration write. 4169 ** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4170 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4171 ** action. 4172 ** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4173 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4174 ** actions is taken: 4175 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4176 ** Detected Parity Error bit in the ATUISR. When set, no action. 4177 ** 4178 *************************************************************************** 4179 */ 4180 4181 /* 4182 *************************************************************************** 4183 ** Split Completion Messages 4184 ** ======================================================================= 4185 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4186 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4187 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4188 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 4189 ** constraints are taken by the ATU: 4190 ** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4191 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4192 ** is set. When the ATU asserts PERR#, additional actions is taken: 4193 ** �X The Master Parity Error bit in the ATUSR is set. 4194 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4195 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 4196 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4197 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4198 ** When the ATU asserts SERR#, additional actions is taken: 4199 ** Set the SERR# Asserted bit in the ATUSR. 4200 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4201 ** SERR# Asserted bit in the ATUISR. When set, no action. 4202 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4203 ** SERR# Detected bit in the ATUISR. When clear, no action. 4204 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4205 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4206 ** When the ATU sets this bit, additional actions is taken: 4207 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4208 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4209 ** When set, no action. 4210 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4211 ** actions is taken: 4212 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4213 ** Detected Parity Error bit in the ATUISR. When set, no action. 4214 ** �E The transaction associated with the Split Completion Message is discarded. 4215 ** �E When the discarded transaction was a read, a completion error message (with message 4216 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4217 ** the internal bus of the 80331. 4218 ***************************************************************************** 4219 */ 4220 4221 4222 /* 4223 ****************************************************************************************************** 4224 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4225 ** ================================================================================================== 4226 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4227 ** notifies the respective system when new data arrives. 4228 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4229 ** window defined by: 4230 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 4231 ** 2.Inbound ATU Limit Register 0 (IALR0) 4232 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4233 ** Error conditions and status can be found in : 4234 ** 1.ATUSR 4235 ** 2.ATUISR 4236 **==================================================================================================== 4237 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4238 **---------------------------------------------------------------------------------------------------- 4239 ** Message Registers 2 Inbound Optional Optional 4240 ** 2 Outbound 4241 **---------------------------------------------------------------------------------------------------- 4242 ** Doorbell Registers 1 Inbound Optional Optional 4243 ** 1 Outbound 4244 **---------------------------------------------------------------------------------------------------- 4245 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4246 **---------------------------------------------------------------------------------------------------- 4247 ** Index Registers 1004 32-bit Memory Locations No Optional 4248 **==================================================================================================== 4249 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4250 **==================================================================================================== 4251 ** 0000H Reserved 4252 ** 0004H Reserved 4253 ** 0008H Reserved 4254 ** 000CH Reserved 4255 **------------------------------------------------------------------------ 4256 ** 0010H Inbound Message Register 0 ] 4257 ** 0014H Inbound Message Register 1 ] 4258 ** 0018H Outbound Message Register 0 ] 4259 ** 001CH Outbound Message Register 1 ] 4 Message Registers 4260 **------------------------------------------------------------------------ 4261 ** 0020H Inbound Doorbell Register ] 4262 ** 0024H Inbound Interrupt Status Register ] 4263 ** 0028H Inbound Interrupt Mask Register ] 4264 ** 002CH Outbound Doorbell Register ] 4265 ** 0030H Outbound Interrupt Status Register ] 4266 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4267 **------------------------------------------------------------------------ 4268 ** 0038H Reserved 4269 ** 003CH Reserved 4270 **------------------------------------------------------------------------ 4271 ** 0040H Inbound Queue Port ] 4272 ** 0044H Outbound Queue Port ] 2 Queue Ports 4273 **------------------------------------------------------------------------ 4274 ** 0048H Reserved 4275 ** 004CH Reserved 4276 **------------------------------------------------------------------------ 4277 ** 0050H ] 4278 ** : ] 4279 ** : Intel Xscale Microarchitecture Local Memory ] 4280 ** : ] 4281 ** 0FFCH ] 1004 Index Registers 4282 ******************************************************************************* 4283 */ 4284 /* 4285 ***************************************************************************** 4286 ** Theory of MU Operation 4287 ***************************************************************************** 4288 **-------------------- 4289 ** inbound_msgaddr0: 4290 ** inbound_msgaddr1: 4291 ** outbound_msgaddr0: 4292 ** outbound_msgaddr1: 4293 ** . The MU has four independent messaging mechanisms. 4294 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4295 ** Each holds a 32-bit value and generates an interrupt when written. 4296 **-------------------- 4297 ** inbound_doorbell: 4298 ** outbound_doorbell: 4299 ** . The two Doorbell Registers support software interrupts. 4300 ** When a bit is set in a Doorbell Register, an interrupt is generated. 4301 **-------------------- 4302 ** inbound_queueport: 4303 ** outbound_queueport: 4304 ** 4305 ** 4306 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4307 ** The 4 circular queues are implemented in 80331 local memory. 4308 ** Two queues are used for inbound messages and two are used for outbound messages. 4309 ** Interrupts may be generated when the queue is written. 4310 **-------------------- 4311 ** local_buffer 0x0050 ....0x0FFF 4312 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4313 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4314 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4315 ** Each interrupt generated by the Messaging Unit can be masked. 4316 **-------------------- 4317 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4318 ** with the exception of Multi-DWORD reads to the index registers. 4319 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4320 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4321 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4322 ** and the data is returned through split completion transaction(s). 4323 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4324 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4325 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4326 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4327 **-------------------- 4328 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4329 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4330 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 4331 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4332 **-------------------- 4333 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4334 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4335 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4336 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 4337 **-------------------- 4338 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4339 ** The register interface, message registers, doorbell registers, 4340 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4341 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4342 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4343 ************************************************************************** 4344 */ 4345 /* 4346 ************************************************************************** 4347 ** Message Registers 4348 ** ============================== 4349 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4350 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4351 ** . Inbound messages are sent by the host processor and received by the 80331. 4352 ** Outbound messages are sent by the 80331 and received by the host processor. 4353 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4354 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4355 ** 4356 ** Inbound Messages: 4357 ** ----------------- 4358 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4359 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4360 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4361 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4362 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4363 ** The interrupt is cleared when the Intel XScale core writes a value of 4364 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4365 ** ------------------------------------------------------------------------ 4366 ** Inbound Message Register - IMRx 4367 ** 4368 ** . There are two Inbound Message Registers: IMR0 and IMR1. 4369 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4370 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4371 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4372 ** ----------------------------------------------------------------- 4373 ** Bit Default Description 4374 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4375 ** When written, an interrupt to the Intel XScale core may be generated. 4376 ************************************************************************** 4377 */ 4378 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4379 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4380 /* 4381 ************************************************************************** 4382 ** Outbound Message Register - OMRx 4383 ** -------------------------------- 4384 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4385 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4386 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4387 ** Interrupt Mask Register. 4388 ** 4389 ** Bit Default Description 4390 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4391 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4392 ************************************************************************** 4393 */ 4394 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4395 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4396 /* 4397 ************************************************************************** 4398 ** Doorbell Registers 4399 ** ============================== 4400 ** There are two Doorbell Registers: 4401 ** Inbound Doorbell Register 4402 ** Outbound Doorbell Register 4403 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4404 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4405 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4406 ** 4407 ** Inbound Doorbells: 4408 ** ------------------ 4409 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4410 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4411 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4412 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4413 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4414 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4415 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4416 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4417 ** and not the values written to the Inbound Doorbell Register. 4418 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4419 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4420 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4421 ** ------------------------------------------------------------------------ 4422 ** Inbound Doorbell Register - IDR 4423 ** 4424 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4425 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4426 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4427 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4428 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4429 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4430 ** ------------------------------------------------------------------------ 4431 ** Bit Default Description 4432 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4433 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4434 ** When all bits are clear, do not generate a Normal Interrupt. 4435 ************************************************************************** 4436 */ 4437 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4438 /* 4439 ************************************************************************** 4440 ** Inbound Interrupt Status Register - IISR 4441 ** 4442 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4443 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4444 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4445 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4446 ** these two are routed to the Messaging Unit Error interrupt input. 4447 ** The generation of interrupts recorded in the Inbound Interrupt Status Register 4448 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4449 ** Some of the bits in this register are Read Only. 4450 ** For those bits, the interrupt must be cleared through another register. 4451 ** 4452 ** Bit Default Description 4453 ** 31:07 0000000H 0 2 Reserved 4454 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4455 ** when an Index Register has been written after a PCI transaction. 4456 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4457 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4458 ** An Error interrupt is generated for this condition. 4459 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4460 ** Once cleared, an interrupt does NOT be generated 4461 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4462 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4463 ** software must retain the information that the Inbound Post queue status is not empty. 4464 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4465 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4466 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4467 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4468 ** Normal Interrupt bit in the Inbound Doorbell Register is set. 4469 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4470 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4471 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4472 ************************************************************************** 4473 */ 4474 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4475 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4476 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4477 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4478 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4479 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4480 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4481 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4482 /* 4483 ************************************************************************** 4484 ** Inbound Interrupt Mask Register - IIMR 4485 ** 4486 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4487 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4488 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4489 ** They only affect the generation of the Intel XScale core interrupt. 4490 ** ------------------------------------------------------------------------ 4491 ** Bit Default Description 4492 ** 31:07 000000H 0 2 Reserved 4493 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4494 ** when an Index Register has been written after a PCI transaction. 4495 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4496 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4497 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4498 ** by the MU hardware when the Inbound Post Queue has been written. 4499 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4500 ** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4501 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4502 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4503 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4504 ** Interrupt generated by a write to the Inbound Message 1 Register. 4505 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4506 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4507 ************************************************************************** 4508 */ 4509 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4510 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4511 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4512 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4513 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4514 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4515 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4516 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4517 /* 4518 ************************************************************************** 4519 ** Outbound Doorbell Register - ODR 4520 ** 4521 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4522 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4523 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4524 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4525 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4526 ** be cleared by an external PCI agent. 4527 ** ---------------------------------------------------------------------- 4528 ** Bit Default Description 4529 ** 31 0 2 Reserved 4530 ** 30 0 2 Reserved. 4531 ** 29 0 2 Reserved 4532 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4533 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4534 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4535 ** When this bit is cleared, the P_INTC# interrupt output 4536 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4537 ** signal is deasserted. 4538 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4539 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4540 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4541 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4542 ** signal is deasserted. 4543 ************************************************************************** 4544 */ 4545 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4546 /* 4547 ************************************************************************** 4548 ** Outbound Interrupt Status Register - OISR 4549 ** 4550 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4551 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4552 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4553 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4554 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4555 ** register. 4556 ** ---------------------------------------------------------------------- 4557 ** Bit Default Description 4558 ** 31:05 000000H 000 2 Reserved 4559 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4560 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4561 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4562 ** cleared when any prefetch data has been read from the Outbound Queue Port. 4563 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4564 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4565 ** Doorbell Register must all be clear. 4566 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4567 ** written. Clearing this bit clears the interrupt. 4568 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4569 ** written. Clearing this bit clears the interrupt. 4570 ************************************************************************** 4571 */ 4572 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4573 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4574 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4575 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4576 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4577 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4578 /* 4579 ************************************************************************** 4580 ** Outbound Interrupt Mask Register - OIMR 4581 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 4582 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 4583 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 4584 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 4585 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 4586 ** only affect the generation of the PCI interrupt. 4587 ** ---------------------------------------------------------------------- 4588 ** Bit Default Description 4589 ** 31:05 000000H Reserved 4590 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 4591 ** in the Outbound Doorbell Register is set. 4592 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 4593 ** the prefetch buffer is valid. 4594 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 4595 ** Doorbell Register. 4596 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 4597 ** generated by a write to the Outbound Message 1 Register. 4598 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 4599 ** generated by a write to the Outbound Message 0 Register. 4600 ************************************************************************** 4601 */ 4602 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 4603 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 4604 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 4605 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 4606 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 4607 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 4608 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 4609 /* 4610 ************************************************************************** 4611 ** 4612 ************************************************************************** 4613 */ 4614 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 4615 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 4616 /* 4617 ************************************************************************** 4618 ** Circular Queues 4619 ** ====================================================================== 4620 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 4621 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 4622 ** Inbound messages are either: 4623 ** �E posted messages by other processors for the Intel XScale core to process or 4624 ** �E free (or empty) messages that can be reused by other processors. 4625 ** Outbound messages are either: 4626 ** �E posted messages by the Intel XScale core for other processors to process or 4627 ** �E free (or empty) messages that can be reused by the Intel XScale core. 4628 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 4629 ** The four Circular Queues are used to pass messages in the following manner. 4630 ** . The two inbound queues are used to handle inbound messages 4631 ** and the two outbound queues are used to handle outbound messages. 4632 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 4633 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 4634 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 4635 ** 4636 ** ============================================================================================================= 4637 ** Circular Queue Summary 4638 ** _____________________________________________________________________________________________________________ 4639 ** | Queue Name | Purpose | Action on PCI Interface| 4640 ** |______________________|____________________________________________________________|_________________________| 4641 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 4642 ** | | waiting to be processed by the 80331 | | 4643 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 4644 ** | | available for use by other processors | | 4645 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 4646 ** | | that are being posted to the other processors | | 4647 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 4648 ** | | available for use by the 80331 | | 4649 ** |______________________|____________________________________________________________|_________________________| 4650 ** 4651 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 4652 ** queue and to receive free messages returning from the 80331. 4653 ** The host processor posts inbound messages, 4654 ** the Intel XScale core receives the posted message and when it is finished with the message, 4655 ** places it back on the inbound free queue for reuse by the host processor. 4656 ** 4657 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 4658 ** address space: 4659 ** Inbound Queue Port 4660 ** and Outbound Queue Port. 4661 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 4662 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 4663 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 4664 ** does not cause the MU hardware to increment the queue pointers. 4665 ** This is treated as when the PCI transaction did not occur. 4666 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 4667 ** ====================================================================================== 4668 ** Overview of Circular Queue Operation 4669 ** ====================================================================================== 4670 ** . The data storage for the circular queues must be provided by the 80331 local memory. 4671 ** . The base address of the circular queues is contained in the Queue Base Address Register. 4672 ** Each entry in the queue is a 32-bit data value. 4673 ** . Each read from or write to the queue may access only one queue entry. 4674 ** . Multi-DWORD accesses to the circular queues are not allowed. 4675 ** Sub-DWORD accesses are promoted to DWORD accesses. 4676 ** . Each circular queue has a head pointer and a tail pointer. 4677 ** The pointers are offsets from the Queue Base Address. 4678 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 4679 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 4680 ** Which unit maintains the pointer is determined by the writer of the queue. 4681 ** More details about the pointers are given in the queue descriptions below. 4682 ** The pointers are incremented after the queue access. 4683 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 4684 ** 4685 ** Messaging Unit... 4686 ** 4687 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 4688 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 4689 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 4690 ** . All four queues must be the same size and may be contiguous. 4691 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 4692 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 4693 ** . There is one base address for all four queues. 4694 ** It is stored in the Queue Base Address Register (QBAR). 4695 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 4696 ** here shows an example of how the circular queues should be set up based on the 4697 ** Intelligent I/O (I 2 O) Architecture Specification. 4698 ** Other ordering of the circular queues is possible. 4699 ** 4700 ** Queue Starting Address 4701 ** Inbound Free Queue QBAR 4702 ** Inbound Post Queue QBAR + Queue Size 4703 ** Outbound Post Queue QBAR + 2 * Queue Size 4704 ** Outbound Free Queue QBAR + 3 * Queue Size 4705 ** =================================================================================== 4706 ** Inbound Post Queue 4707 ** ------------------ 4708 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 4709 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 4710 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 4711 ** For a PCI write transaction that accesses the Inbound Queue Port, 4712 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 4713 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 4714 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 4715 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 4716 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 4717 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 4718 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 4719 ** that the full condition is recognized by the core processor. 4720 ** In addition, to guarantee that the queue does not get overwritten, 4721 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 4722 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4723 ** Only a new message posting the in the inbound queue generates a new interrupt. 4724 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4725 ** software must retain the information that the Inbound Post queue status. 4726 ** From the time that the PCI write transaction is received until the data is written 4727 ** in local memory and the Inbound Post Head Pointer Register is incremented, 4728 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 4729 ** The Intel XScale core may read messages from the Inbound Post Queue 4730 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 4731 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 4732 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 4733 ** the hardware retries any PCI writes until a slot in the queue becomes available. 4734 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 4735 ** =================================================================================== 4736 ** Inbound Free Queue 4737 ** ------------------ 4738 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 4739 ** This queue is read from the queue tail by external PCI agents. 4740 ** It is written to the queue head by the Intel XScale core. 4741 ** The tail pointer is maintained by the MU hardware. 4742 ** The head pointer is maintained by the Intel XScale core. 4743 ** For a PCI read transaction that accesses the Inbound Queue Port, 4744 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 4745 ** When the queue is not empty (head and tail pointers are not equal) 4746 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 4747 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 4748 ** the value of -1 (FFFF.FFFFH) is returned. 4749 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 4750 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 4751 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 4752 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 4753 ** When the PCI read access occurs, the data is read directly from the prefetch register. 4754 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 4755 ** when the head and tail pointers are equal and the queue is empty. 4756 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 4757 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 4758 ** and the Inbound Free Head Pointer Register is written. 4759 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 4760 ** A prefetch must appear atomic from the perspective of the external PCI agent. 4761 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 4762 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 4763 ** local memory location pointed to by the Inbound Free Head Pointer Register. 4764 ** The processor must then increment the Inbound Free Head Pointer Register. 4765 ** ================================================================================== 4766 ** Outbound Post Queue 4767 ** ------------------- 4768 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 4769 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 4770 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 4771 ** MU hardware. The head pointer is maintained by the Intel XScale core. 4772 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 4773 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 4774 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 4775 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 4776 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 4777 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 4778 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 4779 ** Register. 4780 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 4781 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 4782 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 4783 ** occurs, the data is read directly from the prefetch register. 4784 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 4785 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 4786 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 4787 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 4788 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 4789 ** Pointer Register when it adds messages to the queue. 4790 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 4791 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 4792 ** until the prefetch is completed. 4793 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 4794 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 4795 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 4796 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 4797 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 4798 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 4799 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 4800 ** increment the Outbound Post Head Pointer Register. 4801 ** ================================================== 4802 ** Outbound Free Queue 4803 ** ----------------------- 4804 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 4805 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 4806 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 4807 ** XScale core. The head pointer is maintained by the MU hardware. 4808 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 4809 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 4810 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 4811 ** Head Pointer Register. 4812 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 4813 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 4814 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 4815 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 4816 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 4817 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 4818 ** core processor. 4819 ** From the time that a PCI write transaction is received until the data is written in local memory and 4820 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 4821 ** access the Outbound Free Queue Port is signalled a retry. 4822 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 4823 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 4824 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 4825 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 4826 ** 4827 ** ================================================================================== 4828 ** Circular Queue Summary 4829 ** ---------------------- 4830 ** ________________________________________________________________________________________________________________________________________________ 4831 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 4832 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4833 ** |Inbound Post | Inbound Queue | | | | | 4834 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 4835 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4836 ** |Inbound Free | Inbound Queue | | | | | 4837 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 4838 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4839 ** ================================================================================== 4840 ** Circular Queue Status Summary 4841 ** ---------------------- 4842 ** ____________________________________________________________________________________________________ 4843 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 4844 ** |_____________________|________________|_____________________|_______________________________________| 4845 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 4846 ** |_____________________|________________|_____________________|_______________________________________| 4847 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 4848 ** |_____________________|________________|_____________________|_______________________________________| 4849 ************************************************************************** 4850 */ 4851 4852 /* 4853 ************************************************************************** 4854 ** Index Registers 4855 ** ======================== 4856 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 4857 ** These registers are for inbound messages only. 4858 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4859 ** The storage for the Index Registers is allocated from the 80331 local memory. 4860 ** PCI write accesses to the Index Registers write the data to local memory. 4861 ** PCI read accesses to the Index Registers read the data from local memory. 4862 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 4863 ** to Inbound ATU Translate Value Register + FFFH. 4864 ** . The address of the first write access is stored in the Index Address Register. 4865 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 4866 ** Once updated by the MU, the Index Address Register is not updated until the Index Register 4867 ** Interrupt bit in the Inbound Interrupt Status Register is cleared. 4868 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 4869 ** Writes by the Intel XScale core to the local memory used by the Index Registers 4870 ** does not cause an interrupt and does not update the Index Address Register. 4871 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 4872 ************************************************************************** 4873 */ 4874 /* 4875 ************************************************************************** 4876 ** Messaging Unit Internal Bus Memory Map 4877 ** ======================================= 4878 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 4879 ** FFFF E300H reserved | 4880 ** .. .. | 4881 ** FFFF E30CH reserved | 4882 ** FFFF E310H Inbound Message Register 0 | Available through 4883 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 4884 ** FFFF E318H Outbound Message Register 0 | 4885 ** FFFF E31CH Outbound Message Register 1 | or 4886 ** FFFF E320H Inbound Doorbell Register | 4887 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 4888 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 4889 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 4890 ** FFFF E330H Outbound Interrupt Status Register | 4891 ** FFFF E334H Outbound Interrupt Mask Register | 4892 ** ______________________________________________________________________|________________________________________ 4893 ** FFFF E338H reserved | 4894 ** FFFF E33CH reserved | 4895 ** FFFF E340H reserved | 4896 ** FFFF E344H reserved | 4897 ** FFFF E348H reserved | 4898 ** FFFF E34CH reserved | 4899 ** FFFF E350H MU Configuration Register | 4900 ** FFFF E354H Queue Base Address Register | 4901 ** FFFF E358H reserved | 4902 ** FFFF E35CH reserved | must translate PCI address to 4903 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 4904 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 4905 ** FFFF E368H Inbound Post Head pointer Register | 4906 ** FFFF E36CH Inbound Post Tail Pointer Register | 4907 ** FFFF E370H Outbound Free Head Pointer Register | 4908 ** FFFF E374H Outbound Free Tail Pointer Register | 4909 ** FFFF E378H Outbound Post Head pointer Register | 4910 ** FFFF E37CH Outbound Post Tail Pointer Register | 4911 ** FFFF E380H Index Address Register | 4912 ** FFFF E384H reserved | 4913 ** .. .. | 4914 ** FFFF E3FCH reserved | 4915 ** ______________________________________________________________________|_______________________________________ 4916 ************************************************************************** 4917 */ 4918 /* 4919 ************************************************************************** 4920 ** MU Configuration Register - MUCR FFFF.E350H 4921 ** 4922 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 4923 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 4924 ** The Circular Queues are disabled at reset to allow the software to initialize the head 4925 ** and tail pointer registers before any PCI accesses to the Queue Ports. 4926 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 4927 ** ------------------------------------------------------------------------ 4928 ** Bit Default Description 4929 ** 31:06 000000H 00 2 Reserved 4930 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 4931 ** All four queues are the same size. 4932 ** �E 00001 2 - 4K Entries (16 Kbytes) 4933 ** �E 00010 2 - 8K Entries (32 Kbytes) 4934 ** �E 00100 2 - 16K Entries (64 Kbytes) 4935 ** �E 01000 2 - 32K Entries (128 Kbytes) 4936 ** �E 10000 2 - 64K Entries (256 Kbytes) 4937 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 4938 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 4939 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 4940 ** disabled. When set, the Circular Queues are fully enabled. 4941 ************************************************************************** 4942 */ 4943 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 4944 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 4945 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 4946 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 4947 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 4948 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 4949 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 4950 /* 4951 ************************************************************************** 4952 ** Queue Base Address Register - QBAR 4953 ** 4954 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 4955 ** The base address is required to be located on a 1 Mbyte address boundary. 4956 ** . All Circular Queue head and tail pointers are based on the QBAR. 4957 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 4958 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 4959 ** Warning: 4960 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 4961 ** ------------------------------------------------------------------------ 4962 ** Bit Default Description 4963 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4964 ** 19:00 00000H Reserved 4965 ************************************************************************** 4966 */ 4967 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 4968 /* 4969 ************************************************************************** 4970 ** Inbound Free Head Pointer Register - IFHPR 4971 ** 4972 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 4973 ** the Queue Base Address of the head pointer for the Inbound Free Queue. 4974 ** The Head Pointer must be aligned on a DWORD address boundary. 4975 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 4976 ** Writes to the upper 12 bits of the register are ignored. 4977 ** This register is maintained by software. 4978 ** ------------------------------------------------------------------------ 4979 ** Bit Default Description 4980 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4981 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 4982 ** 01:00 00 2 Reserved 4983 ************************************************************************** 4984 */ 4985 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 4986 /* 4987 ************************************************************************** 4988 ** Inbound Free Tail Pointer Register - IFTPR 4989 ** 4990 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 4991 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 4992 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 4993 ** of the register. Writes to the upper 12 bits of the register are ignored. 4994 ** ------------------------------------------------------------------------ 4995 ** Bit Default Description 4996 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4997 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 4998 ** 01:00 00 2 Reserved 4999 ************************************************************************** 5000 */ 5001 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5002 /* 5003 ************************************************************************** 5004 ** Inbound Post Head Pointer Register - IPHPR 5005 ** 5006 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5007 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5008 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5009 ** of the register. Writes to the upper 12 bits of the register are ignored. 5010 ** ------------------------------------------------------------------------ 5011 ** Bit Default Description 5012 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5013 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5014 ** 01:00 00 2 Reserved 5015 ************************************************************************** 5016 */ 5017 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5018 /* 5019 ************************************************************************** 5020 ** Inbound Post Tail Pointer Register - IPTPR 5021 ** 5022 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5023 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5024 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5025 ** of the register. Writes to the upper 12 bits of the register are ignored. 5026 ** ------------------------------------------------------------------------ 5027 ** Bit Default Description 5028 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5029 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5030 ** 01:00 00 2 Reserved 5031 ************************************************************************** 5032 */ 5033 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5034 /* 5035 ************************************************************************** 5036 ** Index Address Register - IAR 5037 ** 5038 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5039 ** It is written by the MU when the Index Registers are written by a PCI agent. 5040 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5041 ** . The local memory address of the Index Register least recently accessed is computed 5042 ** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5043 ** ------------------------------------------------------------------------ 5044 ** Bit Default Description 5045 ** 31:12 000000H Reserved 5046 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5047 ** 01:00 00 2 Reserved 5048 ************************************************************************** 5049 */ 5050 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5051 /* 5052 ********************************************************************************************************** 5053 ** RS-232 Interface for Areca Raid Controller 5054 ** The low level command interface is exclusive with VT100 terminal 5055 ** -------------------------------------------------------------------- 5056 ** 1. Sequence of command execution 5057 ** -------------------------------------------------------------------- 5058 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5059 ** (B) Command block : variable length of data including length, command code, data and checksum byte 5060 ** (C) Return data : variable length of data 5061 ** -------------------------------------------------------------------- 5062 ** 2. Command block 5063 ** -------------------------------------------------------------------- 5064 ** (A) 1st byte : command block length (low byte) 5065 ** (B) 2nd byte : command block length (high byte) 5066 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5067 ** (C) 3rd byte : command code 5068 ** (D) 4th and following bytes : variable length data bytes depends on command code 5069 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5070 ** -------------------------------------------------------------------- 5071 ** 3. Command code and associated data 5072 ** -------------------------------------------------------------------- 5073 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5074 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5075 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5076 ** enum 5077 ** { 5078 ** GUI_SET_SERIAL=0x10, 5079 ** GUI_SET_VENDOR, 5080 ** GUI_SET_MODEL, 5081 ** GUI_IDENTIFY, 5082 ** GUI_CHECK_PASSWORD, 5083 ** GUI_LOGOUT, 5084 ** GUI_HTTP, 5085 ** GUI_SET_ETHERNET_ADDR, 5086 ** GUI_SET_LOGO, 5087 ** GUI_POLL_EVENT, 5088 ** GUI_GET_EVENT, 5089 ** GUI_GET_HW_MONITOR, 5090 ** 5091 ** // GUI_QUICK_CREATE=0x20, (function removed) 5092 ** GUI_GET_INFO_R=0x20, 5093 ** GUI_GET_INFO_V, 5094 ** GUI_GET_INFO_P, 5095 ** GUI_GET_INFO_S, 5096 ** GUI_CLEAR_EVENT, 5097 ** 5098 ** GUI_MUTE_BEEPER=0x30, 5099 ** GUI_BEEPER_SETTING, 5100 ** GUI_SET_PASSWORD, 5101 ** GUI_HOST_INTERFACE_MODE, 5102 ** GUI_REBUILD_PRIORITY, 5103 ** GUI_MAX_ATA_MODE, 5104 ** GUI_RESET_CONTROLLER, 5105 ** GUI_COM_PORT_SETTING, 5106 ** GUI_NO_OPERATION, 5107 ** GUI_DHCP_IP, 5108 ** 5109 ** GUI_CREATE_PASS_THROUGH=0x40, 5110 ** GUI_MODIFY_PASS_THROUGH, 5111 ** GUI_DELETE_PASS_THROUGH, 5112 ** GUI_IDENTIFY_DEVICE, 5113 ** 5114 ** GUI_CREATE_RAIDSET=0x50, 5115 ** GUI_DELETE_RAIDSET, 5116 ** GUI_EXPAND_RAIDSET, 5117 ** GUI_ACTIVATE_RAIDSET, 5118 ** GUI_CREATE_HOT_SPARE, 5119 ** GUI_DELETE_HOT_SPARE, 5120 ** 5121 ** GUI_CREATE_VOLUME=0x60, 5122 ** GUI_MODIFY_VOLUME, 5123 ** GUI_DELETE_VOLUME, 5124 ** GUI_START_CHECK_VOLUME, 5125 ** GUI_STOP_CHECK_VOLUME 5126 ** }; 5127 ** 5128 ** Command description : 5129 ** 5130 ** GUI_SET_SERIAL : Set the controller serial# 5131 ** byte 0,1 : length 5132 ** byte 2 : command code 0x10 5133 ** byte 3 : password length (should be 0x0f) 5134 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 5135 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5136 ** GUI_SET_VENDOR : Set vendor string for the controller 5137 ** byte 0,1 : length 5138 ** byte 2 : command code 0x11 5139 ** byte 3 : password length (should be 0x08) 5140 ** byte 4-0x13 : should be "ArEcAvAr" 5141 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 5142 ** GUI_SET_MODEL : Set the model name of the controller 5143 ** byte 0,1 : length 5144 ** byte 2 : command code 0x12 5145 ** byte 3 : password length (should be 0x08) 5146 ** byte 4-0x13 : should be "ArEcAvAr" 5147 ** byte 0x14--0x1B : model string (must be 8 bytes) 5148 ** GUI_IDENTIFY : Identify device 5149 ** byte 0,1 : length 5150 ** byte 2 : command code 0x13 5151 ** return "Areca RAID Subsystem " 5152 ** GUI_CHECK_PASSWORD : Verify password 5153 ** byte 0,1 : length 5154 ** byte 2 : command code 0x14 5155 ** byte 3 : password length 5156 ** byte 4-0x?? : user password to be checked 5157 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 5158 ** byte 0,1 : length 5159 ** byte 2 : command code 0x15 5160 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5161 ** 5162 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5163 ** byte 0,1 : length 5164 ** byte 2 : command code 0x17 5165 ** byte 3 : password length (should be 0x08) 5166 ** byte 4-0x13 : should be "ArEcAvAr" 5167 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5168 ** GUI_SET_LOGO : Set logo in HTTP 5169 ** byte 0,1 : length 5170 ** byte 2 : command code 0x18 5171 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5172 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5173 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5174 ** note .... page0 1st 2 byte must be actual length of the JPG file 5175 ** GUI_POLL_EVENT : Poll If Event Log Changed 5176 ** byte 0,1 : length 5177 ** byte 2 : command code 0x19 5178 ** GUI_GET_EVENT : Read Event 5179 ** byte 0,1 : length 5180 ** byte 2 : command code 0x1a 5181 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 5182 ** GUI_GET_HW_MONITOR : Get HW monitor data 5183 ** byte 0,1 : length 5184 ** byte 2 : command code 0x1b 5185 ** byte 3 : # of FANs(example 2) 5186 ** byte 4 : # of Voltage sensor(example 3) 5187 ** byte 5 : # of temperature sensor(example 2) 5188 ** byte 6 : # of power 5189 ** byte 7/8 : Fan#0 (RPM) 5190 ** byte 9/10 : Fan#1 5191 ** byte 11/12 : Voltage#0 original value in *1000 5192 ** byte 13/14 : Voltage#0 value 5193 ** byte 15/16 : Voltage#1 org 5194 ** byte 17/18 : Voltage#1 5195 ** byte 19/20 : Voltage#2 org 5196 ** byte 21/22 : Voltage#2 5197 ** byte 23 : Temp#0 5198 ** byte 24 : Temp#1 5199 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5200 ** byte 26 : UPS indicator 5201 ** GUI_QUICK_CREATE : Quick create raid/volume set 5202 ** byte 0,1 : length 5203 ** byte 2 : command code 0x20 5204 ** byte 3/4/5/6 : raw capacity 5205 ** byte 7 : raid level 5206 ** byte 8 : stripe size 5207 ** byte 9 : spare 5208 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 5209 ** This function is removed, application like to implement quick create function 5210 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5211 ** GUI_GET_INFO_R : Get Raid Set Information 5212 ** byte 0,1 : length 5213 ** byte 2 : command code 0x20 5214 ** byte 3 : raidset# 5215 ** 5216 ** typedef struct sGUI_RAIDSET 5217 ** { 5218 ** BYTE grsRaidSetName[16]; 5219 ** DWORD grsCapacity; 5220 ** DWORD grsCapacityX; 5221 ** DWORD grsFailMask; 5222 ** BYTE grsDevArray[32]; 5223 ** BYTE grsMemberDevices; 5224 ** BYTE grsNewMemberDevices; 5225 ** BYTE grsRaidState; 5226 ** BYTE grsVolumes; 5227 ** BYTE grsVolumeList[16]; 5228 ** BYTE grsRes1; 5229 ** BYTE grsRes2; 5230 ** BYTE grsRes3; 5231 ** BYTE grsFreeSegments; 5232 ** DWORD grsRawStripes[8]; 5233 ** DWORD grsRes4; 5234 ** DWORD grsRes5; // Total to 128 bytes 5235 ** DWORD grsRes6; // Total to 128 bytes 5236 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 5237 ** GUI_GET_INFO_V : Get Volume Set Information 5238 ** byte 0,1 : length 5239 ** byte 2 : command code 0x21 5240 ** byte 3 : volumeset# 5241 ** 5242 ** typedef struct sGUI_VOLUMESET 5243 ** { 5244 ** BYTE gvsVolumeName[16]; // 16 5245 ** DWORD gvsCapacity; 5246 ** DWORD gvsCapacityX; 5247 ** DWORD gvsFailMask; 5248 ** DWORD gvsStripeSize; 5249 ** DWORD gvsNewFailMask; 5250 ** DWORD gvsNewStripeSize; 5251 ** DWORD gvsVolumeStatus; 5252 ** DWORD gvsProgress; // 32 5253 ** sSCSI_ATTR gvsScsi; 5254 ** BYTE gvsMemberDisks; 5255 ** BYTE gvsRaidLevel; // 8 5256 ** 5257 ** BYTE gvsNewMemberDisks; 5258 ** BYTE gvsNewRaidLevel; 5259 ** BYTE gvsRaidSetNumber; 5260 ** BYTE gvsRes0; // 4 5261 ** BYTE gvsRes1[4]; // 64 bytes 5262 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5263 ** 5264 ** GUI_GET_INFO_P : Get Physical Drive Information 5265 ** byte 0,1 : length 5266 ** byte 2 : command code 0x22 5267 ** byte 3 : drive # (from 0 to max-channels - 1) 5268 ** 5269 ** typedef struct sGUI_PHY_DRV 5270 ** { 5271 ** BYTE gpdModelName[40]; 5272 ** BYTE gpdSerialNumber[20]; 5273 ** BYTE gpdFirmRev[8]; 5274 ** DWORD gpdCapacity; 5275 ** DWORD gpdCapacityX; // Reserved for expansion 5276 ** BYTE gpdDeviceState; 5277 ** BYTE gpdPioMode; 5278 ** BYTE gpdCurrentUdmaMode; 5279 ** BYTE gpdUdmaMode; 5280 ** BYTE gpdDriveSelect; 5281 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5282 ** sSCSI_ATTR gpdScsi; 5283 ** BYTE gpdReserved[40]; // Total to 128 bytes 5284 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5285 ** 5286 ** GUI_GET_INFO_S : Get System Information 5287 ** byte 0,1 : length 5288 ** byte 2 : command code 0x23 5289 ** 5290 ** typedef struct sCOM_ATTR 5291 ** { 5292 ** BYTE comBaudRate; 5293 ** BYTE comDataBits; 5294 ** BYTE comStopBits; 5295 ** BYTE comParity; 5296 ** BYTE comFlowControl; 5297 ** } sCOM_ATTR, *pCOM_ATTR; 5298 ** 5299 ** typedef struct sSYSTEM_INFO 5300 ** { 5301 ** BYTE gsiVendorName[40]; 5302 ** BYTE gsiSerialNumber[16]; 5303 ** BYTE gsiFirmVersion[16]; 5304 ** BYTE gsiBootVersion[16]; 5305 ** BYTE gsiMbVersion[16]; 5306 ** BYTE gsiModelName[8]; 5307 ** BYTE gsiLocalIp[4]; 5308 ** BYTE gsiCurrentIp[4]; 5309 ** DWORD gsiTimeTick; 5310 ** DWORD gsiCpuSpeed; 5311 ** DWORD gsiICache; 5312 ** DWORD gsiDCache; 5313 ** DWORD gsiScache; 5314 ** DWORD gsiMemorySize; 5315 ** DWORD gsiMemorySpeed; 5316 ** DWORD gsiEvents; 5317 ** BYTE gsiMacAddress[6]; 5318 ** BYTE gsiDhcp; 5319 ** BYTE gsiBeeper; 5320 ** BYTE gsiChannelUsage; 5321 ** BYTE gsiMaxAtaMode; 5322 ** BYTE gsiSdramEcc; // 1:if ECC enabled 5323 ** BYTE gsiRebuildPriority; 5324 ** sCOM_ATTR gsiComA; // 5 bytes 5325 ** sCOM_ATTR gsiComB; // 5 bytes 5326 ** BYTE gsiIdeChannels; 5327 ** BYTE gsiScsiHostChannels; 5328 ** BYTE gsiIdeHostChannels; 5329 ** BYTE gsiMaxVolumeSet; 5330 ** BYTE gsiMaxRaidSet; 5331 ** BYTE gsiEtherPort; // 1:if ether net port supported 5332 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5333 ** BYTE gsiRes[75]; 5334 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 5335 ** 5336 ** GUI_CLEAR_EVENT : Clear System Event 5337 ** byte 0,1 : length 5338 ** byte 2 : command code 0x24 5339 ** 5340 ** GUI_MUTE_BEEPER : Mute current beeper 5341 ** byte 0,1 : length 5342 ** byte 2 : command code 0x30 5343 ** 5344 ** GUI_BEEPER_SETTING : Disable beeper 5345 ** byte 0,1 : length 5346 ** byte 2 : command code 0x31 5347 ** byte 3 : 0->disable, 1->enable 5348 ** 5349 ** GUI_SET_PASSWORD : Change password 5350 ** byte 0,1 : length 5351 ** byte 2 : command code 0x32 5352 ** byte 3 : pass word length ( must <= 15 ) 5353 ** byte 4 : password (must be alpha-numerical) 5354 ** 5355 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 5356 ** byte 0,1 : length 5357 ** byte 2 : command code 0x33 5358 ** byte 3 : 0->Independent, 1->cluster 5359 ** 5360 ** GUI_REBUILD_PRIORITY : Set rebuild priority 5361 ** byte 0,1 : length 5362 ** byte 2 : command code 0x34 5363 ** byte 3 : 0/1/2/3 (low->high) 5364 ** 5365 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5366 ** byte 0,1 : length 5367 ** byte 2 : command code 0x35 5368 ** byte 3 : 0/1/2/3 (133/100/66/33) 5369 ** 5370 ** GUI_RESET_CONTROLLER : Reset Controller 5371 ** byte 0,1 : length 5372 ** byte 2 : command code 0x36 5373 ** *Response with VT100 screen (discard it) 5374 ** 5375 ** GUI_COM_PORT_SETTING : COM port setting 5376 ** byte 0,1 : length 5377 ** byte 2 : command code 0x37 5378 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5379 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5380 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5381 ** byte 6 : stop bit (0:1, 1:2 stop bits) 5382 ** byte 7 : parity (0:none, 1:off, 2:even) 5383 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5384 ** 5385 ** GUI_NO_OPERATION : No operation 5386 ** byte 0,1 : length 5387 ** byte 2 : command code 0x38 5388 ** 5389 ** GUI_DHCP_IP : Set DHCP option and local IP address 5390 ** byte 0,1 : length 5391 ** byte 2 : command code 0x39 5392 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5393 ** byte 4/5/6/7 : IP address 5394 ** 5395 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 5396 ** byte 0,1 : length 5397 ** byte 2 : command code 0x40 5398 ** byte 3 : device # 5399 ** byte 4 : scsi channel (0/1) 5400 ** byte 5 : scsi id (0-->15) 5401 ** byte 6 : scsi lun (0-->7) 5402 ** byte 7 : tagged queue (1 : enabled) 5403 ** byte 8 : cache mode (1 : enabled) 5404 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5405 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5406 ** 5407 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5408 ** byte 0,1 : length 5409 ** byte 2 : command code 0x41 5410 ** byte 3 : device # 5411 ** byte 4 : scsi channel (0/1) 5412 ** byte 5 : scsi id (0-->15) 5413 ** byte 6 : scsi lun (0-->7) 5414 ** byte 7 : tagged queue (1 : enabled) 5415 ** byte 8 : cache mode (1 : enabled) 5416 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5417 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5418 ** 5419 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5420 ** byte 0,1 : length 5421 ** byte 2 : command code 0x42 5422 ** byte 3 : device# to be deleted 5423 ** 5424 ** GUI_IDENTIFY_DEVICE : Identify Device 5425 ** byte 0,1 : length 5426 ** byte 2 : command code 0x43 5427 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5428 ** byte 4/5/6/7 : IDE device mask to be flashed 5429 ** note .... no response data available 5430 ** 5431 ** GUI_CREATE_RAIDSET : Create Raid Set 5432 ** byte 0,1 : length 5433 ** byte 2 : command code 0x50 5434 ** byte 3/4/5/6 : device mask 5435 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 5436 ** 5437 ** GUI_DELETE_RAIDSET : Delete Raid Set 5438 ** byte 0,1 : length 5439 ** byte 2 : command code 0x51 5440 ** byte 3 : raidset# 5441 ** 5442 ** GUI_EXPAND_RAIDSET : Expand Raid Set 5443 ** byte 0,1 : length 5444 ** byte 2 : command code 0x52 5445 ** byte 3 : raidset# 5446 ** byte 4/5/6/7 : device mask for expansion 5447 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5448 ** byte 11/12/13 : repeat for each volume in the raidset .... 5449 ** 5450 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5451 ** byte 0,1 : length 5452 ** byte 2 : command code 0x53 5453 ** byte 3 : raidset# 5454 ** 5455 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 5456 ** byte 0,1 : length 5457 ** byte 2 : command code 0x54 5458 ** byte 3/4/5/6 : device mask for hot spare creation 5459 ** 5460 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5461 ** byte 0,1 : length 5462 ** byte 2 : command code 0x55 5463 ** byte 3/4/5/6 : device mask for hot spare deletion 5464 ** 5465 ** GUI_CREATE_VOLUME : Create volume set 5466 ** byte 0,1 : length 5467 ** byte 2 : command code 0x60 5468 ** byte 3 : raidset# 5469 ** byte 4-19 : volume set name (if byte4 == 0, use default) 5470 ** byte 20-27 : volume capacity (blocks) 5471 ** byte 28 : raid level 5472 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5473 ** byte 30 : channel 5474 ** byte 31 : ID 5475 ** byte 32 : LUN 5476 ** byte 33 : 1 enable tag 5477 ** byte 34 : 1 enable cache 5478 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5479 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5480 ** byte 36 : 1 to select quick init 5481 ** 5482 ** GUI_MODIFY_VOLUME : Modify volume Set 5483 ** byte 0,1 : length 5484 ** byte 2 : command code 0x61 5485 ** byte 3 : volumeset# 5486 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 5487 ** byte 20-27 : new volume capacity (reserved) 5488 ** byte 28 : new raid level 5489 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5490 ** byte 30 : new channel 5491 ** byte 31 : new ID 5492 ** byte 32 : new LUN 5493 ** byte 33 : 1 enable tag 5494 ** byte 34 : 1 enable cache 5495 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5496 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5497 ** 5498 ** GUI_DELETE_VOLUME : Delete volume set 5499 ** byte 0,1 : length 5500 ** byte 2 : command code 0x62 5501 ** byte 3 : volumeset# 5502 ** 5503 ** GUI_START_CHECK_VOLUME : Start volume consistency check 5504 ** byte 0,1 : length 5505 ** byte 2 : command code 0x63 5506 ** byte 3 : volumeset# 5507 ** 5508 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5509 ** byte 0,1 : length 5510 ** byte 2 : command code 0x64 5511 ** --------------------------------------------------------------------- 5512 ** 4. Returned data 5513 ** --------------------------------------------------------------------- 5514 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5515 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5516 ** (C) status or data : 5517 ** <1> If length == 1 ==> 1 byte status code 5518 ** #define GUI_OK 0x41 5519 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 5520 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5521 ** #define GUI_NO_RAIDSET 0x44 5522 ** #define GUI_NO_VOLUMESET 0x45 5523 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 5524 ** #define GUI_PARAMETER_ERROR 0x47 5525 ** #define GUI_UNSUPPORTED_COMMAND 0x48 5526 ** #define GUI_DISK_CONFIG_CHANGED 0x49 5527 ** #define GUI_INVALID_PASSWORD 0x4a 5528 ** #define GUI_NO_DISK_SPACE 0x4b 5529 ** #define GUI_CHECKSUM_ERROR 0x4c 5530 ** #define GUI_PASSWORD_REQUIRED 0x4d 5531 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5532 ** (E) Checksum : checksum of length and status or data byte 5533 ************************************************************************** 5534 */ 5535