1 /* 2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $ 27 */ 28 29 /* 30 * Device driver for Intel's On Die thermal sensor via MSR. 31 * First introduced in Intel's Core line of processors. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/systm.h> 37 #include <sys/types.h> 38 #include <sys/module.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/sensors.h> 42 #include <sys/proc.h> /* for curthread */ 43 #include <sys/sched.h> 44 #include <sys/thread2.h> 45 46 #include <machine/specialreg.h> 47 #include <machine/cpufunc.h> 48 #include <machine/cputypes.h> 49 #include <machine/md_var.h> 50 51 struct coretemp_softc { 52 struct ksensordev sc_sensordev; 53 struct ksensor sc_sensor; 54 device_t sc_dev; 55 int sc_tjmax; 56 57 struct globaldata *sc_gd; 58 int sc_cpu; 59 volatile uint32_t sc_flags; /* CORETEMP_FLAG_ */ 60 volatile uint64_t sc_msr; 61 }; 62 63 #define CORETEMP_FLAG_INITED 0x1 64 #define CORETEMP_FLAG_PENDING 0x2 65 #define CORETEMP_FLAG_CRIT 0x4 66 67 /* 68 * Device methods. 69 */ 70 static void coretemp_identify(driver_t *driver, device_t parent); 71 static int coretemp_probe(device_t dev); 72 static int coretemp_attach(device_t dev); 73 static int coretemp_detach(device_t dev); 74 75 static int coretemp_get_temp(device_t dev); 76 static void coretemp_refresh(void *arg); 77 78 static device_method_t coretemp_methods[] = { 79 /* Device interface */ 80 DEVMETHOD(device_identify, coretemp_identify), 81 DEVMETHOD(device_probe, coretemp_probe), 82 DEVMETHOD(device_attach, coretemp_attach), 83 DEVMETHOD(device_detach, coretemp_detach), 84 85 DEVMETHOD_END 86 }; 87 88 static driver_t coretemp_driver = { 89 "coretemp", 90 coretemp_methods, 91 sizeof(struct coretemp_softc), 92 }; 93 94 static devclass_t coretemp_devclass; 95 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL); 96 MODULE_VERSION(coretemp, 1); 97 98 static void 99 coretemp_identify(driver_t *driver, device_t parent) 100 { 101 device_t child; 102 103 /* Make sure we're not being doubly invoked. */ 104 if (device_find_child(parent, "coretemp", -1) != NULL) 105 return; 106 107 /* Check that the vendor is Intel. */ 108 if (cpu_vendor_id != CPU_VENDOR_INTEL) 109 return; 110 111 /* 112 * Some Intel CPUs, namely the PIII, don't have thermal sensors, 113 * but report them in cpu_thermal_feature. This leads to a later 114 * GPF when the sensor is queried via a MSR, so we stop here. 115 */ 116 if (CPUID_TO_MODEL(cpu_id) < 0xe) 117 return; 118 119 if ((cpu_thermal_feature & CPUID_THERMAL_SENSOR) == 0) 120 return; 121 122 /* 123 * We add a child for each CPU since settings must be performed 124 * on each CPU in the SMP case. 125 */ 126 child = device_add_child(parent, "coretemp", -1); 127 if (child == NULL) 128 device_printf(parent, "add coretemp child failed\n"); 129 } 130 131 static int 132 coretemp_probe(device_t dev) 133 { 134 if (resource_disabled("coretemp", 0)) 135 return (ENXIO); 136 137 device_set_desc(dev, "CPU On-Die Thermal Sensors"); 138 139 return (BUS_PROBE_GENERIC); 140 } 141 142 static int 143 coretemp_attach(device_t dev) 144 { 145 struct coretemp_softc *sc = device_get_softc(dev); 146 device_t pdev; 147 uint64_t msr; 148 int cpu_model, cpu_stepping; 149 int ret, tjtarget; 150 151 sc->sc_dev = dev; 152 pdev = device_get_parent(dev); 153 cpu_model = CPUID_TO_MODEL(cpu_id); 154 cpu_stepping = cpu_id & CPUID_STEPPING; 155 156 #if 0 /* 157 * XXXrpaulo: I have this CPU model and when it returns from C3 158 * coretemp continues to function properly. 159 */ 160 161 /* 162 * Check for errata AE18. 163 * "Processor Digital Thermal Sensor (DTS) Readout stops 164 * updating upon returning from C3/C4 state." 165 * 166 * Adapted from the Linux coretemp driver. 167 */ 168 if (cpu_model == 0xe && cpu_stepping < 0xc) { 169 msr = rdmsr(MSR_BIOS_SIGN); 170 msr = msr >> 32; 171 if (msr < 0x39) { 172 device_printf(dev, "not supported (Intel errata " 173 "AE18), try updating your BIOS\n"); 174 return (ENXIO); 175 } 176 } 177 #endif 178 179 /* 180 * Use 100C as the initial value. 181 */ 182 sc->sc_tjmax = 100; 183 184 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) { 185 /* 186 * On some Core 2 CPUs, there's an undocumented MSR that 187 * can tell us if Tj(max) is 100 or 85. 188 * 189 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted 190 * from the Linux coretemp driver. 191 */ 192 msr = rdmsr(MSR_IA32_EXT_CONFIG); 193 if (msr & (1 << 30)) 194 sc->sc_tjmax = 85; 195 } else if (cpu_model == 0x17) { 196 switch (cpu_stepping) { 197 case 0x6: /* Mobile Core 2 Duo */ 198 sc->sc_tjmax = 105; 199 break; 200 default: /* Unknown stepping */ 201 break; 202 } 203 } else if (cpu_model == 0x1c) { 204 switch (cpu_stepping) { 205 case 0xa: /* 45nm Atom D400, N400 and D500 series */ 206 sc->sc_tjmax = 100; 207 break; 208 default: 209 sc->sc_tjmax = 90; 210 break; 211 } 212 } else { 213 /* 214 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET. 215 * 216 * This method is described in Intel white paper "CPU 217 * Monitoring With DTS/PECI". (#322683) 218 */ 219 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); 220 if (ret == 0) { 221 tjtarget = (msr >> 16) & 0xff; 222 223 /* 224 * On earlier generation of processors, the value 225 * obtained from IA32_TEMPERATURE_TARGET register is 226 * an offset that needs to be summed with a model 227 * specific base. It is however not clear what 228 * these numbers are, with the publicly available 229 * documents from Intel. 230 * 231 * For now, we consider [70, 110]C range, as 232 * described in #322683, as "reasonable" and accept 233 * these values whenever the MSR is available for 234 * read, regardless the CPU model. 235 */ 236 if (tjtarget >= 70 && tjtarget <= 110) 237 sc->sc_tjmax = tjtarget; 238 else 239 device_printf(dev, "Tj(target) value %d " 240 "does not seem right.\n", tjtarget); 241 } else 242 device_printf(dev, "Can not get Tj(target) " 243 "from your CPU, using 100C.\n"); 244 } 245 246 if (bootverbose) 247 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax); 248 249 sc->sc_cpu = device_get_unit(device_get_parent(dev)); 250 sc->sc_gd = globaldata_find(sc->sc_cpu); 251 252 /* 253 * Add hw.sensors.cpuN.temp0 MIB. 254 */ 255 strlcpy(sc->sc_sensordev.xname, device_get_nameunit(pdev), 256 sizeof(sc->sc_sensordev.xname)); 257 ksnprintf(sc->sc_sensor.desc, sizeof(sc->sc_sensor.desc), 258 "node%d core%d", get_chip_ID(sc->sc_cpu), 259 get_core_number_within_chip(sc->sc_cpu)); 260 sc->sc_sensor.type = SENSOR_TEMP; 261 sc->sc_sensor.status = SENSOR_S_UNSPEC; 262 sc->sc_sensor.flags |= SENSOR_FINVALID; 263 sc->sc_sensor.value = 0; 264 sensor_attach(&sc->sc_sensordev, &sc->sc_sensor); 265 sensor_task_register(sc, coretemp_refresh, 2); 266 sensordev_install(&sc->sc_sensordev); 267 268 return (0); 269 } 270 271 static int 272 coretemp_detach(device_t dev) 273 { 274 struct coretemp_softc *sc = device_get_softc(dev); 275 276 sensordev_deinstall(&sc->sc_sensordev); 277 sensor_task_unregister(sc); 278 279 lwkt_synchronize_ipiqs("coretemp"); 280 281 return (0); 282 } 283 284 static void 285 coretemp_ipifunc(void *xsc) 286 { 287 struct coretemp_softc *sc = xsc; 288 289 sc->sc_msr = rdmsr(MSR_THERM_STATUS); 290 cpu_sfence(); 291 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_PENDING); 292 } 293 294 static int 295 coretemp_get_temp(device_t dev) 296 { 297 uint64_t msr; 298 int temp, cpu; 299 struct coretemp_softc *sc = device_get_softc(dev); 300 301 cpu = sc->sc_cpu; 302 303 /* 304 * Send IPI to the specific CPU to read the correct 305 * temperature. If the IPI does not complete yet, 306 * i.e. CORETEMP_FLAG_PENDING is set, return -1. 307 */ 308 if (ncpus > 1 && cpu != mycpuid) { 309 if ((sc->sc_flags & CORETEMP_FLAG_INITED) == 0) { 310 /* The first time we are called */ 311 KASSERT((sc->sc_flags & CORETEMP_FLAG_PENDING) == 0, 312 ("has pending bit set")); 313 atomic_set_int(&sc->sc_flags, 314 CORETEMP_FLAG_INITED | CORETEMP_FLAG_PENDING); 315 cpu_mfence(); 316 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipifunc, sc); 317 return (-2); 318 } else { 319 if (sc->sc_flags & CORETEMP_FLAG_PENDING) { 320 /* IPI does not complete yet */ 321 return (-2); 322 } 323 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_PENDING); 324 msr = sc->sc_msr; 325 } 326 } else { 327 msr = rdmsr(MSR_THERM_STATUS); 328 } 329 330 /* 331 * Check for Thermal Status and Thermal Status Log. 332 */ 333 if ((msr & 0x3) == 0x3) 334 device_printf(dev, "PROCHOT asserted\n"); 335 336 /* 337 * Bit 31 contains "Reading valid" 338 */ 339 if (((msr >> 31) & 0x1) == 1) { 340 /* 341 * Starting on bit 16 and ending on bit 22. 342 */ 343 temp = sc->sc_tjmax - ((msr >> 16) & 0x7f); 344 } else 345 temp = -1; 346 347 /* 348 * Check for Critical Temperature Status and Critical 349 * Temperature Log. 350 * It doesn't really matter if the current temperature is 351 * invalid because the "Critical Temperature Log" bit will 352 * tell us if the Critical Temperature has been reached in 353 * past. It's not directly related to the current temperature. 354 * 355 * If we reach a critical level, allow devctl(4) to catch this 356 * and shutdown the system. 357 */ 358 if (((msr >> 4) & 0x3) == 0x3) { 359 if ((sc->sc_flags & CORETEMP_FLAG_CRIT) == 0) { 360 char stemp[16]; 361 362 device_printf(dev, "critical temperature detected, " 363 "suggest system shutdown\n"); 364 ksnprintf(stemp, sizeof(stemp), "%d", temp); 365 devctl_notify("coretemp", "Thermal", stemp, 366 "notify=0xcc"); 367 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_CRIT); 368 } 369 } else if (sc->sc_flags & CORETEMP_FLAG_CRIT) { 370 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_CRIT); 371 } 372 373 if (sc->sc_flags & CORETEMP_FLAG_PENDING) { 374 cpu_mfence(); 375 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipifunc, sc); 376 } 377 378 return (temp); 379 } 380 381 static void 382 coretemp_refresh(void *arg) 383 { 384 struct coretemp_softc *sc = arg; 385 device_t dev = sc->sc_dev; 386 struct ksensor *s = &sc->sc_sensor; 387 int temp; 388 389 temp = coretemp_get_temp(dev); 390 391 if (temp == -2) { 392 /* No updates; keep the previous value */ 393 } else if (temp == -1) { 394 s->status = SENSOR_S_UNSPEC; 395 s->flags |= SENSOR_FINVALID; 396 s->value = 0; 397 } else { 398 if (sc->sc_flags & CORETEMP_FLAG_CRIT) 399 s->status = SENSOR_S_CRIT; 400 else 401 s->status = SENSOR_S_OK; 402 s->flags &= ~SENSOR_FINVALID; 403 s->value = temp * 1000000 + 273150000; 404 } 405 } 406