1 /* 2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $ 27 */ 28 29 /* 30 * Device driver for Intel's On Die thermal sensor via MSR. 31 * First introduced in Intel's Core line of processors. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/systm.h> 37 #include <sys/types.h> 38 #include <sys/module.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/sensors.h> 42 #include <sys/proc.h> /* for curthread */ 43 #include <sys/sched.h> 44 #include <sys/thread2.h> 45 46 #include <machine/specialreg.h> 47 #include <machine/cpufunc.h> 48 #include <machine/cputypes.h> 49 #include <machine/md_var.h> 50 51 struct coretemp_softc { 52 struct ksensordev sc_sensordev; 53 struct ksensor sc_sensor; 54 device_t sc_dev; 55 int sc_tjmax; 56 57 struct globaldata *sc_gd; 58 int sc_cpu; 59 volatile uint32_t sc_flags; /* CORETEMP_FLAG_ */ 60 volatile uint64_t sc_msr; 61 }; 62 63 #define CORETEMP_FLAG_INITED 0x1 64 #define CORETEMP_FLAG_PENDING 0x2 65 66 /* 67 * Device methods. 68 */ 69 static void coretemp_identify(driver_t *driver, device_t parent); 70 static int coretemp_probe(device_t dev); 71 static int coretemp_attach(device_t dev); 72 static int coretemp_detach(device_t dev); 73 74 static int coretemp_get_temp(device_t dev); 75 static void coretemp_refresh(void *arg); 76 77 static device_method_t coretemp_methods[] = { 78 /* Device interface */ 79 DEVMETHOD(device_identify, coretemp_identify), 80 DEVMETHOD(device_probe, coretemp_probe), 81 DEVMETHOD(device_attach, coretemp_attach), 82 DEVMETHOD(device_detach, coretemp_detach), 83 84 DEVMETHOD_END 85 }; 86 87 static driver_t coretemp_driver = { 88 "coretemp", 89 coretemp_methods, 90 sizeof(struct coretemp_softc), 91 }; 92 93 static devclass_t coretemp_devclass; 94 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL); 95 MODULE_VERSION(coretemp, 1); 96 97 static void 98 coretemp_identify(driver_t *driver, device_t parent) 99 { 100 device_t child; 101 u_int regs[4]; 102 103 /* Make sure we're not being doubly invoked. */ 104 if (device_find_child(parent, "coretemp", -1) != NULL) 105 return; 106 107 /* Check that CPUID 0x06 is supported and the vendor is Intel.*/ 108 if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL) 109 return; 110 /* 111 * CPUID 0x06 returns 1 if the processor has on-die thermal 112 * sensors. EBX[0:3] contains the number of sensors. 113 */ 114 do_cpuid(0x06, regs); 115 if ((regs[0] & 0x1) != 1) 116 return; 117 118 /* 119 * We add a child for each CPU since settings must be performed 120 * on each CPU in the SMP case. 121 */ 122 child = device_add_child(parent, "coretemp", -1); 123 if (child == NULL) 124 device_printf(parent, "add coretemp child failed\n"); 125 } 126 127 static int 128 coretemp_probe(device_t dev) 129 { 130 if (resource_disabled("coretemp", 0)) 131 return (ENXIO); 132 133 device_set_desc(dev, "CPU On-Die Thermal Sensors"); 134 135 return (BUS_PROBE_GENERIC); 136 } 137 138 static int 139 coretemp_attach(device_t dev) 140 { 141 struct coretemp_softc *sc = device_get_softc(dev); 142 device_t pdev; 143 uint64_t msr; 144 int cpu_model, cpu_stepping; 145 int ret, tjtarget; 146 147 sc->sc_dev = dev; 148 pdev = device_get_parent(dev); 149 cpu_model = CPUID_TO_MODEL(cpu_id); 150 cpu_stepping = cpu_id & CPUID_STEPPING; 151 152 /* 153 * Some CPUs, namely the PIII, don't have thermal sensors, but 154 * report them when the CPUID check is performed in 155 * coretemp_identify(). This leads to a later GPF when the sensor 156 * is queried via a MSR, so we stop here. 157 */ 158 if (cpu_model < 0xe) 159 return (ENXIO); 160 161 #if 0 /* 162 * XXXrpaulo: I have this CPU model and when it returns from C3 163 * coretemp continues to function properly. 164 */ 165 166 /* 167 * Check for errata AE18. 168 * "Processor Digital Thermal Sensor (DTS) Readout stops 169 * updating upon returning from C3/C4 state." 170 * 171 * Adapted from the Linux coretemp driver. 172 */ 173 if (cpu_model == 0xe && cpu_stepping < 0xc) { 174 msr = rdmsr(MSR_BIOS_SIGN); 175 msr = msr >> 32; 176 if (msr < 0x39) { 177 device_printf(dev, "not supported (Intel errata " 178 "AE18), try updating your BIOS\n"); 179 return (ENXIO); 180 } 181 } 182 #endif 183 184 /* 185 * Use 100C as the initial value. 186 */ 187 sc->sc_tjmax = 100; 188 189 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) { 190 /* 191 * On some Core 2 CPUs, there's an undocumented MSR that 192 * can tell us if Tj(max) is 100 or 85. 193 * 194 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted 195 * from the Linux coretemp driver. 196 */ 197 msr = rdmsr(MSR_IA32_EXT_CONFIG); 198 if (msr & (1 << 30)) 199 sc->sc_tjmax = 85; 200 } else if (cpu_model == 0x17) { 201 switch (cpu_stepping) { 202 case 0x6: /* Mobile Core 2 Duo */ 203 sc->sc_tjmax = 105; 204 break; 205 default: /* Unknown stepping */ 206 break; 207 } 208 } else if (cpu_model == 0x1c) { 209 switch (cpu_stepping) { 210 case 0xa: /* 45nm Atom D400, N400 and D500 series */ 211 sc->sc_tjmax = 100; 212 break; 213 default: 214 sc->sc_tjmax = 90; 215 break; 216 } 217 } else { 218 /* 219 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET. 220 * 221 * This method is described in Intel white paper "CPU 222 * Monitoring With DTS/PECI". (#322683) 223 */ 224 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); 225 if (ret == 0) { 226 tjtarget = (msr >> 16) & 0xff; 227 228 /* 229 * On earlier generation of processors, the value 230 * obtained from IA32_TEMPERATURE_TARGET register is 231 * an offset that needs to be summed with a model 232 * specific base. It is however not clear what 233 * these numbers are, with the publicly available 234 * documents from Intel. 235 * 236 * For now, we consider [70, 100]C range, as 237 * described in #322683, as "reasonable" and accept 238 * these values whenever the MSR is available for 239 * read, regardless the CPU model. 240 */ 241 if (tjtarget >= 70 && tjtarget <= 100) 242 sc->sc_tjmax = tjtarget; 243 else 244 device_printf(dev, "Tj(target) value %d " 245 "does not seem right.\n", tjtarget); 246 } else 247 device_printf(dev, "Can not get Tj(target) " 248 "from your CPU, using 100C.\n"); 249 } 250 251 if (bootverbose) 252 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax); 253 254 sc->sc_cpu = device_get_unit(device_get_parent(dev)); 255 sc->sc_gd = globaldata_find(sc->sc_cpu); 256 257 /* 258 * Add hw.sensors.cpuN.temp0 MIB. 259 */ 260 strlcpy(sc->sc_sensordev.xname, device_get_nameunit(pdev), 261 sizeof(sc->sc_sensordev.xname)); 262 sc->sc_sensor.type = SENSOR_TEMP; 263 sensor_attach(&sc->sc_sensordev, &sc->sc_sensor); 264 sensor_task_register(sc, coretemp_refresh, 2); 265 sensordev_install(&sc->sc_sensordev); 266 267 return (0); 268 } 269 270 static int 271 coretemp_detach(device_t dev) 272 { 273 struct coretemp_softc *sc = device_get_softc(dev); 274 275 sensordev_deinstall(&sc->sc_sensordev); 276 sensor_task_unregister(sc); 277 278 lwkt_synchronize_ipiqs("coretemp"); 279 280 return (0); 281 } 282 283 static void 284 coretemp_ipifunc(void *xsc) 285 { 286 struct coretemp_softc *sc = xsc; 287 288 sc->sc_msr = rdmsr(MSR_THERM_STATUS); 289 cpu_sfence(); 290 sc->sc_flags &= ~CORETEMP_FLAG_PENDING; 291 } 292 293 static int 294 coretemp_get_temp(device_t dev) 295 { 296 uint64_t msr; 297 int temp, cpu; 298 struct coretemp_softc *sc = device_get_softc(dev); 299 char stemp[16]; 300 301 cpu = sc->sc_cpu; 302 303 /* 304 * Send IPI to the specific CPU to read the correct 305 * temperature. If the IPI does not complete yet, 306 * i.e. CORETEMP_FLAG_PENDING is set, return -1. 307 */ 308 if (ncpus > 1 && cpu != mycpuid) { 309 if ((sc->sc_flags & CORETEMP_FLAG_INITED) == 0) { 310 /* The first time we are called */ 311 KASSERT((sc->sc_flags & CORETEMP_FLAG_PENDING) == 0, 312 ("has pending bit set")); 313 sc->sc_flags |= CORETEMP_FLAG_INITED | 314 CORETEMP_FLAG_PENDING; 315 cpu_mfence(); 316 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipifunc, sc); 317 return (-1); 318 } else { 319 if (sc->sc_flags & CORETEMP_FLAG_PENDING) { 320 /* IPI does not complete yet */ 321 return (-1); 322 } 323 sc->sc_flags |= CORETEMP_FLAG_PENDING; 324 msr = sc->sc_msr; 325 } 326 } else { 327 msr = rdmsr(MSR_THERM_STATUS); 328 } 329 330 /* 331 * Check for Thermal Status and Thermal Status Log. 332 */ 333 if ((msr & 0x3) == 0x3) 334 device_printf(dev, "PROCHOT asserted\n"); 335 336 /* 337 * Bit 31 contains "Reading valid" 338 */ 339 if (((msr >> 31) & 0x1) == 1) { 340 /* 341 * Starting on bit 16 and ending on bit 22. 342 */ 343 temp = sc->sc_tjmax - ((msr >> 16) & 0x7f); 344 } else 345 temp = -1; 346 347 /* 348 * Check for Critical Temperature Status and Critical 349 * Temperature Log. 350 * It doesn't really matter if the current temperature is 351 * invalid because the "Critical Temperature Log" bit will 352 * tell us if the Critical Temperature has been reached in 353 * past. It's not directly related to the current temperature. 354 * 355 * If we reach a critical level, allow devctl(4) to catch this 356 * and shutdown the system. 357 */ 358 if (((msr >> 4) & 0x3) == 0x3) { 359 device_printf(dev, "critical temperature detected, " 360 "suggest system shutdown\n"); 361 ksnprintf(stemp, sizeof(stemp), "%d", temp); 362 devctl_notify("coretemp", "Thermal", stemp, "notify=0xcc"); 363 } 364 365 if (sc->sc_flags & CORETEMP_FLAG_PENDING) { 366 cpu_mfence(); 367 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipifunc, sc); 368 } 369 370 return (temp); 371 } 372 373 static void 374 coretemp_refresh(void *arg) 375 { 376 struct coretemp_softc *sc = arg; 377 device_t dev = sc->sc_dev; 378 struct ksensor *s = &sc->sc_sensor; 379 int temp; 380 381 temp = coretemp_get_temp(dev); 382 383 if (temp == -1) { 384 s->flags |= SENSOR_FINVALID; 385 s->value = 0; 386 } else { 387 s->flags &= ~SENSOR_FINVALID; 388 s->value = temp * 1000000 + 273150000; 389 } 390 } 391