1 /* 2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $ 27 */ 28 29 /* 30 * Device driver for Intel's On Die thermal sensor via MSR. 31 * First introduced in Intel's Core line of processors. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/systm.h> 37 #include <sys/module.h> 38 #include <sys/conf.h> 39 #include <sys/cpu_topology.h> 40 #include <sys/kernel.h> 41 #include <sys/sensors.h> 42 #include <sys/proc.h> /* for curthread */ 43 #include <sys/sched.h> 44 #include <sys/thread2.h> 45 #include <sys/bitops.h> 46 47 #include <machine/specialreg.h> 48 #include <machine/cpufunc.h> 49 #include <machine/cputypes.h> 50 #include <machine/md_var.h> 51 52 #define MSR_THERM_STATUS_TM_STATUS __BIT64(0) 53 #define MSR_THERM_STATUS_TM_STATUS_LOG __BIT64(1) 54 #define MSR_THERM_STATUS_PROCHOT __BIT64(2) 55 #define MSR_THERM_STATUS_PROCHOT_LOG __BIT64(3) 56 #define MSR_THERM_STATUS_CRIT __BIT64(4) 57 #define MSR_THERM_STATUS_CRIT_LOG __BIT64(5) 58 #define MSR_THERM_STATUS_THRESH1 __BIT64(6) 59 #define MSR_THERM_STATUS_THRESH1_LOG __BIT64(7) 60 #define MSR_THERM_STATUS_THRESH2 __BIT64(8) 61 #define MSR_THERM_STATUS_THRESH2_LOG __BIT64(9) 62 #define MSR_THERM_STATUS_PWRLIM __BIT64(10) 63 #define MSR_THERM_STATUS_PWRLIM_LOG __BIT64(11) 64 #define MSR_THERM_STATUS_READ __BITS64(16, 22) 65 #define MSR_THERM_STATUS_RES __BITS64(27, 30) 66 #define MSR_THERM_STATUS_READ_VALID __BIT64(31) 67 68 #define MSR_THERM_STATUS_HAS_STATUS(msr) \ 69 (((msr) & (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG)) ==\ 70 (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG)) 71 72 #define MSR_THERM_STATUS_IS_CRITICAL(msr) \ 73 (((msr) & (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG)) == \ 74 (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG)) 75 76 struct coretemp_sensor { 77 struct ksensordev c_sensdev; 78 struct ksensor c_sens; 79 }; 80 81 struct coretemp_softc { 82 device_t sc_dev; 83 int sc_tjmax; 84 85 int sc_nsens; 86 struct coretemp_sensor *sc_sens; 87 88 struct globaldata *sc_gd; 89 int sc_cpu; 90 volatile uint32_t sc_flags; /* CORETEMP_FLAG_ */ 91 volatile uint64_t sc_msr; 92 }; 93 94 #define CORETEMP_FLAG_INITED 0x1 95 #define CORETEMP_FLAG_PENDING 0x2 96 #define CORETEMP_FLAG_CRIT 0x4 97 98 /* 99 * Device methods. 100 */ 101 static void coretemp_identify(driver_t *driver, device_t parent); 102 static int coretemp_probe(device_t dev); 103 static int coretemp_attach(device_t dev); 104 static int coretemp_detach(device_t dev); 105 106 static int coretemp_get_temp(device_t dev); 107 static void coretemp_refresh(void *arg); 108 109 static device_method_t coretemp_methods[] = { 110 /* Device interface */ 111 DEVMETHOD(device_identify, coretemp_identify), 112 DEVMETHOD(device_probe, coretemp_probe), 113 DEVMETHOD(device_attach, coretemp_attach), 114 DEVMETHOD(device_detach, coretemp_detach), 115 116 DEVMETHOD_END 117 }; 118 119 static driver_t coretemp_driver = { 120 "coretemp", 121 coretemp_methods, 122 sizeof(struct coretemp_softc), 123 }; 124 125 static devclass_t coretemp_devclass; 126 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL); 127 MODULE_VERSION(coretemp, 1); 128 129 static void 130 coretemp_identify(driver_t *driver, device_t parent) 131 { 132 device_t child; 133 134 /* Make sure we're not being doubly invoked. */ 135 if (device_find_child(parent, "coretemp", -1) != NULL) 136 return; 137 138 /* Check that the vendor is Intel. */ 139 if (cpu_vendor_id != CPU_VENDOR_INTEL) 140 return; 141 142 /* 143 * Some Intel CPUs, namely the PIII, don't have thermal sensors, 144 * but report them in cpu_thermal_feature. This leads to a later 145 * GPF when the sensor is queried via a MSR, so we stop here. 146 */ 147 if (CPUID_TO_MODEL(cpu_id) < 0xe) 148 return; 149 150 if ((cpu_thermal_feature & CPUID_THERMAL_SENSOR) == 0) 151 return; 152 153 /* 154 * We add a child for each CPU since settings must be performed 155 * on each CPU in the SMP case. 156 */ 157 child = device_add_child(parent, "coretemp", -1); 158 if (child == NULL) 159 device_printf(parent, "add coretemp child failed\n"); 160 } 161 162 static int 163 coretemp_probe(device_t dev) 164 { 165 if (resource_disabled("coretemp", 0)) 166 return (ENXIO); 167 168 device_set_desc(dev, "CPU On-Die Thermal Sensors"); 169 170 return (BUS_PROBE_GENERIC); 171 } 172 173 static int 174 coretemp_attach(device_t dev) 175 { 176 struct coretemp_softc *sc = device_get_softc(dev); 177 const struct cpu_node *node, *start_node; 178 cpumask_t cpu_mask; 179 device_t pdev; 180 uint64_t msr; 181 int cpu_model, cpu_stepping; 182 int ret, tjtarget, cpu, sens_idx; 183 184 sc->sc_dev = dev; 185 pdev = device_get_parent(dev); 186 cpu_model = CPUID_TO_MODEL(cpu_id); 187 cpu_stepping = cpu_id & CPUID_STEPPING; 188 189 #if 0 190 /* 191 * XXXrpaulo: I have this CPU model and when it returns from C3 192 * coretemp continues to function properly. 193 */ 194 195 /* 196 * Check for errata AE18. 197 * "Processor Digital Thermal Sensor (DTS) Readout stops 198 * updating upon returning from C3/C4 state." 199 * 200 * Adapted from the Linux coretemp driver. 201 */ 202 if (cpu_model == 0xe && cpu_stepping < 0xc) { 203 msr = rdmsr(MSR_BIOS_SIGN); 204 msr = msr >> 32; 205 if (msr < 0x39) { 206 device_printf(dev, "not supported (Intel errata " 207 "AE18), try updating your BIOS\n"); 208 return (ENXIO); 209 } 210 } 211 #endif 212 213 /* 214 * Use 100C as the initial value. 215 */ 216 sc->sc_tjmax = 100; 217 218 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) { 219 /* 220 * On some Core 2 CPUs, there's an undocumented MSR that 221 * can tell us if Tj(max) is 100 or 85. 222 * 223 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG 224 * was adapted from the Linux coretemp driver. 225 */ 226 msr = rdmsr(MSR_IA32_EXT_CONFIG); 227 if (msr & (1 << 30)) 228 sc->sc_tjmax = 85; 229 } else if (cpu_model == 0x17) { 230 switch (cpu_stepping) { 231 case 0x6: /* Mobile Core 2 Duo */ 232 sc->sc_tjmax = 105; 233 break; 234 default: /* Unknown stepping */ 235 break; 236 } 237 } else if (cpu_model == 0x1c) { 238 switch (cpu_stepping) { 239 case 0xa: /* 45nm Atom D400, N400 and D500 series */ 240 sc->sc_tjmax = 100; 241 break; 242 default: 243 sc->sc_tjmax = 90; 244 break; 245 } 246 } else { 247 /* 248 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET. 249 * 250 * This method is described in Intel white paper "CPU 251 * Monitoring With DTS/PECI". (#322683) 252 */ 253 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); 254 if (ret == 0) { 255 tjtarget = (msr >> 16) & 0xff; 256 257 /* 258 * On earlier generation of processors, the value 259 * obtained from IA32_TEMPERATURE_TARGET register is 260 * an offset that needs to be summed with a model 261 * specific base. It is however not clear what 262 * these numbers are, with the publicly available 263 * documents from Intel. 264 * 265 * For now, we consider [70, 110]C range, as 266 * described in #322683, as "reasonable" and accept 267 * these values whenever the MSR is available for 268 * read, regardless the CPU model. 269 */ 270 if (tjtarget >= 70 && tjtarget <= 110) 271 sc->sc_tjmax = tjtarget; 272 else 273 device_printf(dev, "Tj(target) value %d " 274 "does not seem right.\n", tjtarget); 275 } else 276 device_printf(dev, "Can not get Tj(target) " 277 "from your CPU, using 100C.\n"); 278 } 279 280 if (bootverbose) 281 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax); 282 283 sc->sc_cpu = device_get_unit(device_get_parent(dev)); 284 sc->sc_gd = globaldata_find(sc->sc_cpu); 285 286 start_node = get_cpu_node_by_cpuid(sc->sc_cpu); 287 288 node = start_node; 289 while (node != NULL) { 290 if (node->type == CORE_LEVEL) 291 break; 292 node = node->parent_node; 293 } 294 if (node != NULL) { 295 int master_cpu = BSRCPUMASK(node->members); 296 297 if (bootverbose) { 298 device_printf(dev, "master cpu%d, count %u\n", 299 master_cpu, node->child_no); 300 } 301 302 if (sc->sc_cpu != master_cpu) 303 return (0); 304 305 KKASSERT(node->child_no > 0); 306 sc->sc_nsens = node->child_no; 307 cpu_mask = node->members; 308 } else { 309 sc->sc_nsens = 1; 310 CPUMASK_ASSBIT(cpu_mask, sc->sc_cpu); 311 } 312 sc->sc_sens = kmalloc(sizeof(struct coretemp_sensor) * sc->sc_nsens, 313 M_DEVBUF, M_WAITOK | M_ZERO); 314 315 sens_idx = 0; 316 CPUSET_FOREACH(cpu, cpu_mask) { 317 struct coretemp_sensor *csens; 318 319 KKASSERT(sens_idx < sc->sc_nsens); 320 csens = &sc->sc_sens[sens_idx]; 321 322 /* 323 * Add hw.sensors.cpuN.temp0 MIB. 324 */ 325 ksnprintf(csens->c_sensdev.xname, 326 sizeof(csens->c_sensdev.xname), "cpu%d", cpu); 327 ksnprintf(csens->c_sens.desc, sizeof(csens->c_sens.desc), 328 "node%d core%d", get_chip_ID(cpu), 329 get_core_number_within_chip(cpu)); 330 csens->c_sens.type = SENSOR_TEMP; 331 csens->c_sens.status = SENSOR_S_UNSPEC; 332 csens->c_sens.flags |= SENSOR_FINVALID; 333 csens->c_sens.value = 0; 334 sensor_attach(&csens->c_sensdev, &csens->c_sens); 335 sensordev_install(&csens->c_sensdev); 336 337 ++sens_idx; 338 } 339 sensor_task_register(sc, coretemp_refresh, 2); 340 341 return (0); 342 } 343 344 static int 345 coretemp_detach(device_t dev) 346 { 347 struct coretemp_softc *sc = device_get_softc(dev); 348 349 if (sc->sc_nsens > 0) { 350 int i; 351 352 sensor_task_unregister(sc); 353 lwkt_synchronize_ipiqs("coretemp"); 354 355 for (i = 0; i < sc->sc_nsens; ++i) 356 sensordev_deinstall(&sc->sc_sens[i].c_sensdev); 357 kfree(sc->sc_sens, M_DEVBUF); 358 } 359 return (0); 360 } 361 362 static void 363 coretemp_ipifunc(void *xsc) 364 { 365 struct coretemp_softc *sc = xsc; 366 367 sc->sc_msr = rdmsr(MSR_THERM_STATUS); 368 cpu_sfence(); 369 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_PENDING); 370 } 371 372 static int 373 coretemp_get_temp(device_t dev) 374 { 375 uint64_t msr; 376 int temp, cpu; 377 struct coretemp_softc *sc = device_get_softc(dev); 378 379 cpu = sc->sc_cpu; 380 381 /* 382 * Send IPI to the specific CPU to read the correct 383 * temperature. If the IPI does not complete yet, 384 * i.e. CORETEMP_FLAG_PENDING is set, return -1. 385 */ 386 if (cpu != mycpuid) { 387 if ((sc->sc_flags & CORETEMP_FLAG_INITED) == 0) { 388 /* The first time we are called */ 389 KASSERT((sc->sc_flags & CORETEMP_FLAG_PENDING) == 0, 390 ("has pending bit set")); 391 atomic_set_int(&sc->sc_flags, 392 CORETEMP_FLAG_INITED | CORETEMP_FLAG_PENDING); 393 cpu_mfence(); 394 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipifunc, sc); 395 return (-2); 396 } else { 397 if (sc->sc_flags & CORETEMP_FLAG_PENDING) { 398 /* IPI does not complete yet */ 399 return (-2); 400 } 401 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_PENDING); 402 msr = sc->sc_msr; 403 } 404 } else { 405 msr = rdmsr(MSR_THERM_STATUS); 406 } 407 408 /* 409 * Check for Thermal Status and Thermal Status Log. 410 */ 411 if (MSR_THERM_STATUS_HAS_STATUS(msr)) 412 device_printf(dev, "PROCHOT asserted\n"); 413 414 if (msr & MSR_THERM_STATUS_READ_VALID) 415 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_THERM_STATUS_READ); 416 else 417 temp = -1; 418 419 /* 420 * Check for Critical Temperature Status and Critical 421 * Temperature Log. 422 * It doesn't really matter if the current temperature is 423 * invalid because the "Critical Temperature Log" bit will 424 * tell us if the Critical Temperature has been reached in 425 * past. It's not directly related to the current temperature. 426 * 427 * If we reach a critical level, allow devctl(4) to catch this 428 * and shutdown the system. 429 */ 430 if (MSR_THERM_STATUS_IS_CRITICAL(msr)) { 431 if ((sc->sc_flags & CORETEMP_FLAG_CRIT) == 0) { 432 char stemp[16]; 433 434 device_printf(dev, "critical temperature detected, " 435 "suggest system shutdown\n"); 436 ksnprintf(stemp, sizeof(stemp), "%d", temp); 437 devctl_notify("coretemp", "Thermal", stemp, 438 "notify=0xcc"); 439 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_CRIT); 440 } 441 } else if (sc->sc_flags & CORETEMP_FLAG_CRIT) { 442 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_CRIT); 443 } 444 445 if (sc->sc_flags & CORETEMP_FLAG_PENDING) { 446 cpu_mfence(); 447 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipifunc, sc); 448 } 449 450 return (temp); 451 } 452 453 static void 454 coretemp_refresh(void *arg) 455 { 456 struct coretemp_softc *sc = arg; 457 device_t dev = sc->sc_dev; 458 struct ksensor *sens; 459 int temp, i; 460 461 temp = coretemp_get_temp(dev); 462 463 if (temp == -2) { 464 /* No updates; keep the previous value */ 465 } else if (temp == -1) { 466 for (i = 0; i < sc->sc_nsens; ++i) { 467 sens = &sc->sc_sens[i].c_sens; 468 469 sens->status = SENSOR_S_UNSPEC; 470 sens->flags |= SENSOR_FINVALID; 471 sens->value = 0; 472 } 473 } else { 474 for (i = 0; i < sc->sc_nsens; ++i) { 475 sens = &sc->sc_sens[i].c_sens; 476 if (sc->sc_flags & CORETEMP_FLAG_CRIT) 477 sens->status = SENSOR_S_CRIT; 478 else 479 sens->status = SENSOR_S_OK; 480 sens->flags &= ~SENSOR_FINVALID; 481 sens->value = temp * 1000000 + 273150000; 482 } 483 } 484 } 485