1 /* 2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $ 27 */ 28 29 /* 30 * Device driver for Intel's On Die thermal sensor via MSR. 31 * First introduced in Intel's Core line of processors. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/systm.h> 37 #include <sys/module.h> 38 #include <sys/conf.h> 39 #include <sys/cpu_topology.h> 40 #include <sys/kernel.h> 41 #include <sys/sensors.h> 42 #include <sys/proc.h> /* for curthread */ 43 #include <sys/sched.h> 44 #include <sys/thread2.h> 45 #include <sys/bitops.h> 46 47 #include <machine/specialreg.h> 48 #include <machine/cpufunc.h> 49 #include <machine/cputypes.h> 50 #include <machine/md_var.h> 51 52 #define MSR_THERM_STATUS_TM_STATUS __BIT64(0) 53 #define MSR_THERM_STATUS_TM_STATUS_LOG __BIT64(1) 54 #define MSR_THERM_STATUS_PROCHOT __BIT64(2) 55 #define MSR_THERM_STATUS_PROCHOT_LOG __BIT64(3) 56 #define MSR_THERM_STATUS_CRIT __BIT64(4) 57 #define MSR_THERM_STATUS_CRIT_LOG __BIT64(5) 58 #define MSR_THERM_STATUS_THRESH1 __BIT64(6) 59 #define MSR_THERM_STATUS_THRESH1_LOG __BIT64(7) 60 #define MSR_THERM_STATUS_THRESH2 __BIT64(8) 61 #define MSR_THERM_STATUS_THRESH2_LOG __BIT64(9) 62 #define MSR_THERM_STATUS_PWRLIM __BIT64(10) 63 #define MSR_THERM_STATUS_PWRLIM_LOG __BIT64(11) 64 #define MSR_THERM_STATUS_READ __BITS64(16, 22) 65 #define MSR_THERM_STATUS_RES __BITS64(27, 30) 66 #define MSR_THERM_STATUS_READ_VALID __BIT64(31) 67 68 #define MSR_THERM_STATUS_HAS_STATUS(msr) \ 69 (((msr) & (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG)) ==\ 70 (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG)) 71 72 #define MSR_THERM_STATUS_IS_CRITICAL(msr) \ 73 (((msr) & (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG)) == \ 74 (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG)) 75 76 #define MSR_PKGTM_STATUS_TM_STATUS __BIT64(0) 77 #define MSR_PKGTM_STATUS_TM_STATUS_LOG __BIT64(1) 78 #define MSR_PKGTM_STATUS_PROCHOT __BIT64(2) 79 #define MSR_PKGTM_STATUS_PROCHOT_LOG __BIT64(3) 80 #define MSR_PKGTM_STATUS_CRIT __BIT64(4) 81 #define MSR_PKGTM_STATUS_CRIT_LOG __BIT64(5) 82 #define MSR_PKGTM_STATUS_THRESH1 __BIT64(6) 83 #define MSR_PKGTM_STATUS_THRESH1_LOG __BIT64(7) 84 #define MSR_PKGTM_STATUS_THRESH2 __BIT64(8) 85 #define MSR_PKGTM_STATUS_THRESH2_LOG __BIT64(9) 86 #define MSR_PKGTM_STATUS_PWRLIM __BIT64(10) 87 #define MSR_PKGTM_STATUS_PWRLIM_LOG __BIT64(11) 88 #define MSR_PKGTM_STATUS_READ __BITS64(16, 22) 89 90 #define MSR_PKGTM_STATUS_HAS_STATUS(msr) \ 91 (((msr) & (MSR_PKGTM_STATUS_TM_STATUS | MSR_PKGTM_STATUS_TM_STATUS_LOG)) ==\ 92 (MSR_PKGTM_STATUS_TM_STATUS | MSR_PKGTM_STATUS_TM_STATUS_LOG)) 93 94 #define MSR_PKGTM_STATUS_IS_CRITICAL(msr) \ 95 (((msr) & (MSR_PKGTM_STATUS_CRIT | MSR_PKGTM_STATUS_CRIT_LOG)) == \ 96 (MSR_PKGTM_STATUS_CRIT | MSR_PKGTM_STATUS_CRIT_LOG)) 97 98 #define CORETEMP_TEMP_INVALID -1 99 #define CORETEMP_TEMP_NOUPDATE -2 100 101 struct coretemp_sensor { 102 struct ksensordev c_sensdev; 103 struct ksensor c_sens; 104 }; 105 106 struct coretemp_softc { 107 device_t sc_dev; 108 int sc_tjmax; 109 110 int sc_nsens; 111 struct coretemp_sensor *sc_sens; 112 struct coretemp_sensor *sc_pkg_sens; 113 114 struct globaldata *sc_gd; 115 int sc_cpu; 116 volatile uint32_t sc_flags; /* CORETEMP_FLAG_ */ 117 volatile uint64_t sc_msr; 118 volatile uint64_t sc_pkg_msr; 119 }; 120 121 #define CORETEMP_FLAG_INITED 0x1 122 #define CORETEMP_FLAG_PENDING 0x2 123 #define CORETEMP_FLAG_CRIT 0x4 124 #define CORETEMP_FLAG_PKGCRIT 0x8 125 126 #define CORETEMP_HAS_PKGSENSOR(sc) ((sc)->sc_pkg_sens != NULL) 127 128 /* 129 * Device methods. 130 */ 131 static void coretemp_identify(driver_t *driver, device_t parent); 132 static int coretemp_probe(device_t dev); 133 static int coretemp_attach(device_t dev); 134 static int coretemp_detach(device_t dev); 135 136 static void coretemp_ipi_func(void *sc); 137 static void coretemp_ipi_send(struct coretemp_softc *sc, uint32_t flags); 138 static boolean_t coretemp_msr_fetch(struct coretemp_softc *sc, uint64_t *msr, 139 uint64_t *pkg_msr); 140 static int coretemp_msr_temp(struct coretemp_softc *sc, uint64_t msr); 141 static void coretemp_sensor_update(struct coretemp_softc *sc, int temp); 142 static void coretemp_sensor_task(void *arg); 143 144 static void coretemp_pkg_sensor_task(void *arg); 145 static void coretemp_pkg_sensor_update(struct coretemp_softc *sc, int temp); 146 static int coretemp_pkg_msr_temp(struct coretemp_softc *sc, uint64_t msr); 147 148 static device_method_t coretemp_methods[] = { 149 /* Device interface */ 150 DEVMETHOD(device_identify, coretemp_identify), 151 DEVMETHOD(device_probe, coretemp_probe), 152 DEVMETHOD(device_attach, coretemp_attach), 153 DEVMETHOD(device_detach, coretemp_detach), 154 155 DEVMETHOD_END 156 }; 157 158 static driver_t coretemp_driver = { 159 "coretemp", 160 coretemp_methods, 161 sizeof(struct coretemp_softc), 162 }; 163 164 static devclass_t coretemp_devclass; 165 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL); 166 MODULE_VERSION(coretemp, 1); 167 168 static __inline void 169 coretemp_sensor_set_invalid(struct ksensor *sens) 170 { 171 sens->status = SENSOR_S_UNSPEC; 172 sens->flags &= ~SENSOR_FUNKNOWN; 173 sens->flags |= SENSOR_FINVALID; 174 sens->value = 0; 175 } 176 177 static __inline void 178 coretemp_sensor_set_unknown(struct ksensor *sens) 179 { 180 sens->status = SENSOR_S_UNSPEC; 181 sens->flags &= ~SENSOR_FINVALID; 182 sens->flags |= SENSOR_FUNKNOWN; 183 sens->value = 0; 184 } 185 186 static __inline void 187 coretemp_sensor_set(struct ksensor *sens, const struct coretemp_softc *sc, 188 uint32_t crit_flag, int temp) 189 { 190 if (sc->sc_flags & crit_flag) 191 sens->status = SENSOR_S_CRIT; 192 else 193 sens->status = SENSOR_S_OK; 194 sens->flags &= ~(SENSOR_FINVALID | SENSOR_FUNKNOWN); 195 sens->value = temp * 1000000 + 273150000; 196 } 197 198 static void 199 coretemp_identify(driver_t *driver, device_t parent) 200 { 201 device_t child; 202 203 /* Make sure we're not being doubly invoked. */ 204 if (device_find_child(parent, "coretemp", -1) != NULL) 205 return; 206 207 /* Check that the vendor is Intel. */ 208 if (cpu_vendor_id != CPU_VENDOR_INTEL) 209 return; 210 211 /* 212 * Some Intel CPUs, namely the PIII, don't have thermal sensors, 213 * but report them in cpu_thermal_feature. This leads to a later 214 * GPF when the sensor is queried via a MSR, so we stop here. 215 */ 216 if (CPUID_TO_MODEL(cpu_id) < 0xe) 217 return; 218 219 if ((cpu_thermal_feature & CPUID_THERMAL_SENSOR) == 0) 220 return; 221 222 /* 223 * We add a child for each CPU since settings must be performed 224 * on each CPU in the SMP case. 225 */ 226 child = device_add_child(parent, "coretemp", -1); 227 if (child == NULL) 228 device_printf(parent, "add coretemp child failed\n"); 229 } 230 231 static int 232 coretemp_probe(device_t dev) 233 { 234 if (resource_disabled("coretemp", 0)) 235 return (ENXIO); 236 237 device_set_desc(dev, "CPU On-Die Thermal Sensors"); 238 239 return (BUS_PROBE_GENERIC); 240 } 241 242 static int 243 coretemp_attach(device_t dev) 244 { 245 struct coretemp_softc *sc = device_get_softc(dev); 246 const struct cpu_node *node, *start_node; 247 cpumask_t cpu_mask; 248 device_t pdev; 249 uint64_t msr; 250 int cpu_model, cpu_stepping; 251 int ret, tjtarget, cpu, sens_idx; 252 int master_cpu; 253 struct coretemp_sensor *csens; 254 255 sc->sc_dev = dev; 256 pdev = device_get_parent(dev); 257 cpu_model = CPUID_TO_MODEL(cpu_id); 258 cpu_stepping = cpu_id & CPUID_STEPPING; 259 260 #if 0 261 /* 262 * XXXrpaulo: I have this CPU model and when it returns from C3 263 * coretemp continues to function properly. 264 */ 265 266 /* 267 * Check for errata AE18. 268 * "Processor Digital Thermal Sensor (DTS) Readout stops 269 * updating upon returning from C3/C4 state." 270 * 271 * Adapted from the Linux coretemp driver. 272 */ 273 if (cpu_model == 0xe && cpu_stepping < 0xc) { 274 msr = rdmsr(MSR_BIOS_SIGN); 275 msr = msr >> 32; 276 if (msr < 0x39) { 277 device_printf(dev, "not supported (Intel errata " 278 "AE18), try updating your BIOS\n"); 279 return (ENXIO); 280 } 281 } 282 #endif 283 284 /* 285 * Use 100C as the initial value. 286 */ 287 sc->sc_tjmax = 100; 288 289 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) { 290 /* 291 * On some Core 2 CPUs, there's an undocumented MSR that 292 * can tell us if Tj(max) is 100 or 85. 293 * 294 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG 295 * was adapted from the Linux coretemp driver. 296 */ 297 msr = rdmsr(MSR_IA32_EXT_CONFIG); 298 if (msr & (1 << 30)) 299 sc->sc_tjmax = 85; 300 } else if (cpu_model == 0x17) { 301 switch (cpu_stepping) { 302 case 0x6: /* Mobile Core 2 Duo */ 303 sc->sc_tjmax = 105; 304 break; 305 default: /* Unknown stepping */ 306 break; 307 } 308 } else if (cpu_model == 0x1c) { 309 switch (cpu_stepping) { 310 case 0xa: /* 45nm Atom D400, N400 and D500 series */ 311 sc->sc_tjmax = 100; 312 break; 313 default: 314 sc->sc_tjmax = 90; 315 break; 316 } 317 } else { 318 /* 319 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET. 320 * 321 * This method is described in Intel white paper "CPU 322 * Monitoring With DTS/PECI". (#322683) 323 */ 324 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); 325 if (ret == 0) { 326 tjtarget = (msr >> 16) & 0xff; 327 328 /* 329 * On earlier generation of processors, the value 330 * obtained from IA32_TEMPERATURE_TARGET register is 331 * an offset that needs to be summed with a model 332 * specific base. It is however not clear what 333 * these numbers are, with the publicly available 334 * documents from Intel. 335 * 336 * For now, we consider [70, 110]C range, as 337 * described in #322683, as "reasonable" and accept 338 * these values whenever the MSR is available for 339 * read, regardless the CPU model. 340 */ 341 if (tjtarget >= 70 && tjtarget <= 110) 342 sc->sc_tjmax = tjtarget; 343 else 344 device_printf(dev, "Tj(target) value %d " 345 "does not seem right.\n", tjtarget); 346 } else 347 device_printf(dev, "Can not get Tj(target) " 348 "from your CPU, using 100C.\n"); 349 } 350 351 if (bootverbose) 352 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax); 353 354 sc->sc_cpu = device_get_unit(device_get_parent(dev)); 355 sc->sc_gd = globaldata_find(sc->sc_cpu); 356 357 start_node = get_cpu_node_by_cpuid(sc->sc_cpu); 358 359 node = start_node; 360 while (node != NULL) { 361 if (node->type == CORE_LEVEL) { 362 if (node->child_no == 0) 363 node = NULL; 364 break; 365 } 366 node = node->parent_node; 367 } 368 if (node != NULL) { 369 master_cpu = BSRCPUMASK(node->members); 370 if (bootverbose) { 371 device_printf(dev, "master cpu%d, count %u\n", 372 master_cpu, node->child_no); 373 } 374 if (sc->sc_cpu != master_cpu) 375 return (0); 376 377 KKASSERT(node->child_no > 0); 378 sc->sc_nsens = node->child_no; 379 cpu_mask = node->members; 380 } else { 381 sc->sc_nsens = 1; 382 CPUMASK_ASSBIT(cpu_mask, sc->sc_cpu); 383 } 384 sc->sc_sens = kmalloc(sizeof(struct coretemp_sensor) * sc->sc_nsens, 385 M_DEVBUF, M_WAITOK | M_ZERO); 386 387 sens_idx = 0; 388 CPUSET_FOREACH(cpu, cpu_mask) { 389 KKASSERT(sens_idx < sc->sc_nsens); 390 csens = &sc->sc_sens[sens_idx]; 391 392 /* 393 * Add hw.sensors.cpuN.temp0 MIB. 394 */ 395 ksnprintf(csens->c_sensdev.xname, 396 sizeof(csens->c_sensdev.xname), "cpu%d", cpu); 397 ksnprintf(csens->c_sens.desc, sizeof(csens->c_sens.desc), 398 "node%d core%d", get_chip_ID(cpu), 399 get_core_number_within_chip(cpu)); 400 csens->c_sens.type = SENSOR_TEMP; 401 coretemp_sensor_set_unknown(&csens->c_sens); 402 sensor_attach(&csens->c_sensdev, &csens->c_sens); 403 sensordev_install(&csens->c_sensdev); 404 405 ++sens_idx; 406 } 407 408 if (cpu_thermal_feature & CPUID_THERMAL_PTM) { 409 boolean_t pkg_sens = TRUE; 410 411 /* 412 * Package thermal sensor 413 */ 414 415 node = start_node; 416 while (node != NULL) { 417 if (node->type == CHIP_LEVEL) { 418 if (node->child_no == 0) 419 node = NULL; 420 break; 421 } 422 node = node->parent_node; 423 } 424 if (node != NULL) { 425 master_cpu = BSRCPUMASK(node->members); 426 if (bootverbose) { 427 device_printf(dev, "pkg master cpu%d\n", 428 master_cpu); 429 } 430 if (sc->sc_cpu != master_cpu) 431 pkg_sens = FALSE; 432 } 433 434 if (pkg_sens) { 435 csens = sc->sc_pkg_sens = 436 kmalloc(sizeof(struct coretemp_sensor), M_DEVBUF, 437 M_WAITOK | M_ZERO); 438 439 /* 440 * Add hw.sensors.cpu_nodeN.temp0 MIB. 441 */ 442 ksnprintf(csens->c_sensdev.xname, 443 sizeof(csens->c_sensdev.xname), "cpu_node%d", 444 get_chip_ID(sc->sc_cpu)); 445 ksnprintf(csens->c_sens.desc, 446 sizeof(csens->c_sens.desc), "node%d", 447 get_chip_ID(sc->sc_cpu)); 448 csens->c_sens.type = SENSOR_TEMP; 449 coretemp_sensor_set_unknown(&csens->c_sens); 450 sensor_attach(&csens->c_sensdev, &csens->c_sens); 451 sensordev_install(&csens->c_sensdev); 452 } 453 } 454 455 if (CORETEMP_HAS_PKGSENSOR(sc)) 456 sensor_task_register(sc, coretemp_pkg_sensor_task, 2); 457 else 458 sensor_task_register(sc, coretemp_sensor_task, 2); 459 460 return (0); 461 } 462 463 static int 464 coretemp_detach(device_t dev) 465 { 466 struct coretemp_softc *sc = device_get_softc(dev); 467 468 if (sc->sc_nsens > 0) { 469 int i; 470 471 sensor_task_unregister(sc); 472 lwkt_synchronize_ipiqs("coretemp"); 473 474 for (i = 0; i < sc->sc_nsens; ++i) 475 sensordev_deinstall(&sc->sc_sens[i].c_sensdev); 476 kfree(sc->sc_sens, M_DEVBUF); 477 478 if (sc->sc_pkg_sens != NULL) { 479 sensordev_deinstall(&sc->sc_pkg_sens->c_sensdev); 480 kfree(sc->sc_pkg_sens, M_DEVBUF); 481 } 482 } 483 return (0); 484 } 485 486 static void 487 coretemp_ipi_func(void *xsc) 488 { 489 struct coretemp_softc *sc = xsc; 490 491 sc->sc_msr = rdmsr(MSR_THERM_STATUS); 492 if (CORETEMP_HAS_PKGSENSOR(sc)) 493 sc->sc_pkg_msr = rdmsr(MSR_PKG_THERM_STATUS); 494 cpu_sfence(); 495 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_PENDING); 496 } 497 498 static void 499 coretemp_ipi_send(struct coretemp_softc *sc, uint32_t flags) 500 { 501 KASSERT((sc->sc_flags & CORETEMP_FLAG_PENDING) == 0, 502 ("coretemp: cpu%d ipi is still pending", sc->sc_cpu)); 503 atomic_set_int(&sc->sc_flags, flags | CORETEMP_FLAG_PENDING); 504 cpu_mfence(); 505 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipi_func, sc); 506 } 507 508 static int 509 coretemp_msr_temp(struct coretemp_softc *sc, uint64_t msr) 510 { 511 int temp; 512 513 /* 514 * Check for Thermal Status and Thermal Status Log. 515 */ 516 if (MSR_THERM_STATUS_HAS_STATUS(msr)) 517 device_printf(sc->sc_dev, "PROCHOT asserted\n"); 518 519 if (msr & MSR_THERM_STATUS_READ_VALID) 520 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_THERM_STATUS_READ); 521 else 522 temp = CORETEMP_TEMP_INVALID; 523 524 /* 525 * Check for Critical Temperature Status and Critical 526 * Temperature Log. 527 * It doesn't really matter if the current temperature is 528 * invalid because the "Critical Temperature Log" bit will 529 * tell us if the Critical Temperature has been reached in 530 * past. It's not directly related to the current temperature. 531 * 532 * If we reach a critical level, allow devctl(4) to catch this 533 * and shutdown the system. 534 */ 535 if (MSR_THERM_STATUS_IS_CRITICAL(msr)) { 536 if ((sc->sc_flags & CORETEMP_FLAG_CRIT) == 0) { 537 char stemp[16], data[64]; 538 539 device_printf(sc->sc_dev, 540 "critical temperature detected, " 541 "suggest system shutdown\n"); 542 ksnprintf(stemp, sizeof(stemp), "%d", temp); 543 ksnprintf(data, sizeof(data), 544 "notify=0xcc node=%d core=%d", 545 get_chip_ID(sc->sc_cpu), 546 get_core_number_within_chip(sc->sc_cpu)); 547 devctl_notify("coretemp", "Thermal", stemp, data); 548 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_CRIT); 549 } 550 } else if (sc->sc_flags & CORETEMP_FLAG_CRIT) { 551 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_CRIT); 552 } 553 554 return temp; 555 } 556 557 static int 558 coretemp_pkg_msr_temp(struct coretemp_softc *sc, uint64_t msr) 559 { 560 int temp; 561 562 /* 563 * Check for Thermal Status and Thermal Status Log. 564 */ 565 if (MSR_PKGTM_STATUS_HAS_STATUS(msr)) 566 device_printf(sc->sc_dev, "package PROCHOT asserted\n"); 567 568 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_PKGTM_STATUS_READ); 569 570 /* 571 * Check for Critical Temperature Status and Critical 572 * Temperature Log. 573 * It doesn't really matter if the current temperature is 574 * invalid because the "Critical Temperature Log" bit will 575 * tell us if the Critical Temperature has been reached in 576 * past. It's not directly related to the current temperature. 577 * 578 * If we reach a critical level, allow devctl(4) to catch this 579 * and shutdown the system. 580 */ 581 if (MSR_PKGTM_STATUS_IS_CRITICAL(msr)) { 582 if ((sc->sc_flags & CORETEMP_FLAG_PKGCRIT) == 0) { 583 char stemp[16], data[64]; 584 585 device_printf(sc->sc_dev, 586 "critical temperature detected, " 587 "suggest system shutdown\n"); 588 ksnprintf(stemp, sizeof(stemp), "%d", temp); 589 ksnprintf(data, sizeof(data), "notify=0xcc node=%d", 590 get_chip_ID(sc->sc_cpu)); 591 devctl_notify("coretemp", "Thermal", stemp, data); 592 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_PKGCRIT); 593 } 594 } else if (sc->sc_flags & CORETEMP_FLAG_PKGCRIT) { 595 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_PKGCRIT); 596 } 597 598 return temp; 599 } 600 601 static boolean_t 602 coretemp_msr_fetch(struct coretemp_softc *sc, uint64_t *msr, uint64_t *pkg_msr) 603 { 604 /* 605 * Send IPI to the specific CPU to read the correct temperature. 606 * If the IPI does not complete yet, i.e. CORETEMP_FLAG_PENDING, 607 * return false. 608 */ 609 if (sc->sc_cpu != mycpuid) { 610 if ((sc->sc_flags & CORETEMP_FLAG_INITED) == 0) { 611 coretemp_ipi_send(sc, CORETEMP_FLAG_INITED); 612 return FALSE; 613 } else { 614 if (sc->sc_flags & CORETEMP_FLAG_PENDING) { 615 /* IPI does not complete yet */ 616 return FALSE; 617 } 618 *msr = sc->sc_msr; 619 if (pkg_msr != NULL) 620 *pkg_msr = sc->sc_pkg_msr; 621 coretemp_ipi_send(sc, 0); 622 } 623 } else { 624 *msr = rdmsr(MSR_THERM_STATUS); 625 if (pkg_msr != NULL) 626 *pkg_msr = rdmsr(MSR_PKG_THERM_STATUS); 627 } 628 return TRUE; 629 } 630 631 static void 632 coretemp_sensor_update(struct coretemp_softc *sc, int temp) 633 { 634 int i; 635 636 if (temp == CORETEMP_TEMP_NOUPDATE) { 637 /* No updates; keep the previous value */ 638 } else if (temp == CORETEMP_TEMP_INVALID) { 639 for (i = 0; i < sc->sc_nsens; ++i) 640 coretemp_sensor_set_invalid(&sc->sc_sens[i].c_sens); 641 } else { 642 for (i = 0; i < sc->sc_nsens; ++i) { 643 coretemp_sensor_set(&sc->sc_sens[i].c_sens, sc, 644 CORETEMP_FLAG_CRIT, temp); 645 } 646 } 647 } 648 649 static void 650 coretemp_pkg_sensor_update(struct coretemp_softc *sc, int temp) 651 { 652 KKASSERT(sc->sc_pkg_sens != NULL); 653 if (temp == CORETEMP_TEMP_NOUPDATE) { 654 /* No updates; keep the previous value */ 655 } else if (temp == CORETEMP_TEMP_INVALID) { 656 coretemp_sensor_set_invalid(&sc->sc_pkg_sens->c_sens); 657 } else { 658 coretemp_sensor_set(&sc->sc_pkg_sens->c_sens, sc, 659 CORETEMP_FLAG_PKGCRIT, temp); 660 } 661 } 662 663 static void 664 coretemp_sensor_task(void *arg) 665 { 666 struct coretemp_softc *sc = arg; 667 uint64_t msr; 668 int temp; 669 670 if (!coretemp_msr_fetch(sc, &msr, NULL)) 671 temp = CORETEMP_TEMP_NOUPDATE; 672 else 673 temp = coretemp_msr_temp(sc, msr); 674 675 coretemp_sensor_update(sc, temp); 676 } 677 678 static void 679 coretemp_pkg_sensor_task(void *arg) 680 { 681 struct coretemp_softc *sc = arg; 682 uint64_t msr, pkg_msr; 683 int temp, pkg_temp; 684 685 if (!coretemp_msr_fetch(sc, &msr, &pkg_msr)) { 686 temp = CORETEMP_TEMP_NOUPDATE; 687 pkg_temp = CORETEMP_TEMP_NOUPDATE; 688 } else { 689 temp = coretemp_msr_temp(sc, msr); 690 pkg_temp = coretemp_pkg_msr_temp(sc, pkg_msr); 691 } 692 693 coretemp_sensor_update(sc, temp); 694 coretemp_pkg_sensor_update(sc, pkg_temp); 695 } 696