1 /* 2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $ 27 */ 28 29 /* 30 * Device driver for Intel's On Die thermal sensor via MSR. 31 * First introduced in Intel's Core line of processors. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/systm.h> 37 #include <sys/types.h> 38 #include <sys/module.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/sensors.h> 42 #include <sys/proc.h> /* for curthread */ 43 #include <sys/sched.h> 44 45 #include <machine/specialreg.h> 46 #include <machine/cpufunc.h> 47 #include <machine/cputypes.h> 48 #include <machine/md_var.h> 49 50 struct coretemp_softc { 51 struct ksensordev sc_sensordev; 52 struct ksensor sc_sensor; 53 device_t sc_dev; 54 int sc_tjmax; 55 }; 56 57 /* 58 * Device methods. 59 */ 60 static void coretemp_identify(driver_t *driver, device_t parent); 61 static int coretemp_probe(device_t dev); 62 static int coretemp_attach(device_t dev); 63 static int coretemp_detach(device_t dev); 64 65 static int coretemp_get_temp(device_t dev); 66 static void coretemp_refresh(void *arg); 67 68 static device_method_t coretemp_methods[] = { 69 /* Device interface */ 70 DEVMETHOD(device_identify, coretemp_identify), 71 DEVMETHOD(device_probe, coretemp_probe), 72 DEVMETHOD(device_attach, coretemp_attach), 73 DEVMETHOD(device_detach, coretemp_detach), 74 75 DEVMETHOD_END 76 }; 77 78 static driver_t coretemp_driver = { 79 "coretemp", 80 coretemp_methods, 81 sizeof(struct coretemp_softc), 82 }; 83 84 static devclass_t coretemp_devclass; 85 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL); 86 MODULE_VERSION(coretemp, 1); 87 88 static void 89 coretemp_identify(driver_t *driver, device_t parent) 90 { 91 device_t child; 92 u_int regs[4]; 93 94 /* Make sure we're not being doubly invoked. */ 95 if (device_find_child(parent, "coretemp", -1) != NULL) 96 return; 97 98 /* Check that CPUID 0x06 is supported and the vendor is Intel.*/ 99 if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL) 100 return; 101 /* 102 * CPUID 0x06 returns 1 if the processor has on-die thermal 103 * sensors. EBX[0:3] contains the number of sensors. 104 */ 105 do_cpuid(0x06, regs); 106 if ((regs[0] & 0x1) != 1) 107 return; 108 109 /* 110 * We add a child for each CPU since settings must be performed 111 * on each CPU in the SMP case. 112 */ 113 child = device_add_child(parent, "coretemp", -1); 114 if (child == NULL) 115 device_printf(parent, "add coretemp child failed\n"); 116 } 117 118 static int 119 coretemp_probe(device_t dev) 120 { 121 if (resource_disabled("coretemp", 0)) 122 return (ENXIO); 123 124 device_set_desc(dev, "CPU On-Die Thermal Sensors"); 125 126 return (BUS_PROBE_GENERIC); 127 } 128 129 static int 130 coretemp_attach(device_t dev) 131 { 132 struct coretemp_softc *sc = device_get_softc(dev); 133 device_t pdev; 134 uint64_t msr; 135 int cpu_model, cpu_stepping; 136 int ret, tjtarget; 137 138 sc->sc_dev = dev; 139 pdev = device_get_parent(dev); 140 cpu_model = CPUID_TO_MODEL(cpu_id); 141 cpu_stepping = cpu_id & CPUID_STEPPING; 142 143 /* 144 * Some CPUs, namely the PIII, don't have thermal sensors, but 145 * report them when the CPUID check is performed in 146 * coretemp_identify(). This leads to a later GPF when the sensor 147 * is queried via a MSR, so we stop here. 148 */ 149 if (cpu_model < 0xe) 150 return (ENXIO); 151 152 #if 0 /* 153 * XXXrpaulo: I have this CPU model and when it returns from C3 154 * coretemp continues to function properly. 155 */ 156 157 /* 158 * Check for errata AE18. 159 * "Processor Digital Thermal Sensor (DTS) Readout stops 160 * updating upon returning from C3/C4 state." 161 * 162 * Adapted from the Linux coretemp driver. 163 */ 164 if (cpu_model == 0xe && cpu_stepping < 0xc) { 165 msr = rdmsr(MSR_BIOS_SIGN); 166 msr = msr >> 32; 167 if (msr < 0x39) { 168 device_printf(dev, "not supported (Intel errata " 169 "AE18), try updating your BIOS\n"); 170 return (ENXIO); 171 } 172 } 173 #endif 174 175 /* 176 * Use 100C as the initial value. 177 */ 178 sc->sc_tjmax = 100; 179 180 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) { 181 /* 182 * On some Core 2 CPUs, there's an undocumented MSR that 183 * can tell us if Tj(max) is 100 or 85. 184 * 185 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted 186 * from the Linux coretemp driver. 187 */ 188 msr = rdmsr(MSR_IA32_EXT_CONFIG); 189 if (msr & (1 << 30)) 190 sc->sc_tjmax = 85; 191 } else if (cpu_model == 0x17) { 192 switch (cpu_stepping) { 193 case 0x6: /* Mobile Core 2 Duo */ 194 sc->sc_tjmax = 105; 195 break; 196 default: /* Unknown stepping */ 197 break; 198 } 199 } else if (cpu_model == 0x1c) { 200 switch (cpu_stepping) { 201 case 0xa: /* 45nm Atom D400, N400 and D500 series */ 202 sc->sc_tjmax = 100; 203 break; 204 default: 205 sc->sc_tjmax = 90; 206 break; 207 } 208 } else { 209 /* 210 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET. 211 * 212 * This method is described in Intel white paper "CPU 213 * Monitoring With DTS/PECI". (#322683) 214 */ 215 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); 216 if (ret == 0) { 217 tjtarget = (msr >> 16) & 0xff; 218 219 /* 220 * On earlier generation of processors, the value 221 * obtained from IA32_TEMPERATURE_TARGET register is 222 * an offset that needs to be summed with a model 223 * specific base. It is however not clear what 224 * these numbers are, with the publicly available 225 * documents from Intel. 226 * 227 * For now, we consider [70, 100]C range, as 228 * described in #322683, as "reasonable" and accept 229 * these values whenever the MSR is available for 230 * read, regardless the CPU model. 231 */ 232 if (tjtarget >= 70 && tjtarget <= 100) 233 sc->sc_tjmax = tjtarget; 234 else 235 device_printf(dev, "Tj(target) value %d " 236 "does not seem right.\n", tjtarget); 237 } else 238 device_printf(dev, "Can not get Tj(target) " 239 "from your CPU, using 100C.\n"); 240 } 241 242 if (bootverbose) 243 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax); 244 245 /* 246 * Add hw.sensors.cpuN.temp0 MIB. 247 */ 248 strlcpy(sc->sc_sensordev.xname, device_get_nameunit(pdev), 249 sizeof(sc->sc_sensordev.xname)); 250 sc->sc_sensor.type = SENSOR_TEMP; 251 sensor_attach(&sc->sc_sensordev, &sc->sc_sensor); 252 if (sensor_task_register(sc, coretemp_refresh, 2)) { 253 device_printf(dev, "unable to register update task\n"); 254 return (ENXIO); 255 } 256 sensordev_install(&sc->sc_sensordev); 257 258 return (0); 259 } 260 261 static int 262 coretemp_detach(device_t dev) 263 { 264 struct coretemp_softc *sc = device_get_softc(dev); 265 266 sensordev_deinstall(&sc->sc_sensordev); 267 sensor_task_unregister(sc); 268 269 return (0); 270 } 271 272 273 static int 274 coretemp_get_temp(device_t dev) 275 { 276 uint64_t msr; 277 int temp, cpu, origcpu; 278 struct coretemp_softc *sc = device_get_softc(dev); 279 char stemp[16]; 280 281 cpu = device_get_unit(device_get_parent(dev)); 282 283 /* 284 * Bind to specific CPU to read the correct temperature. 285 * If not all CPUs are initialised, then only read from 286 * cpu0, returning -1 on all other CPUs. 287 */ 288 if (ncpus > 1) { 289 origcpu = mycpuid; 290 lwkt_migratecpu(cpu); 291 292 msr = rdmsr(MSR_THERM_STATUS); 293 294 lwkt_migratecpu(origcpu); 295 } else if (cpu != 0) 296 return (-1); 297 else 298 msr = rdmsr(MSR_THERM_STATUS); 299 300 /* 301 * Check for Thermal Status and Thermal Status Log. 302 */ 303 if ((msr & 0x3) == 0x3) 304 device_printf(dev, "PROCHOT asserted\n"); 305 306 /* 307 * Bit 31 contains "Reading valid" 308 */ 309 if (((msr >> 31) & 0x1) == 1) { 310 /* 311 * Starting on bit 16 and ending on bit 22. 312 */ 313 temp = sc->sc_tjmax - ((msr >> 16) & 0x7f); 314 } else 315 temp = -1; 316 317 /* 318 * Check for Critical Temperature Status and Critical 319 * Temperature Log. 320 * It doesn't really matter if the current temperature is 321 * invalid because the "Critical Temperature Log" bit will 322 * tell us if the Critical Temperature has been reached in 323 * past. It's not directly related to the current temperature. 324 * 325 * If we reach a critical level, allow devctl(4) to catch this 326 * and shutdown the system. 327 */ 328 if (((msr >> 4) & 0x3) == 0x3) { 329 device_printf(dev, "critical temperature detected, " 330 "suggest system shutdown\n"); 331 ksnprintf(stemp, sizeof(stemp), "%d", temp); 332 devctl_notify("coretemp", "Thermal", stemp, "notify=0xcc"); 333 } 334 335 return (temp); 336 } 337 338 static void 339 coretemp_refresh(void *arg) 340 { 341 struct coretemp_softc *sc = arg; 342 device_t dev = sc->sc_dev; 343 struct ksensor *s = &sc->sc_sensor; 344 int temp; 345 346 temp = coretemp_get_temp(dev); 347 348 if (temp == -1) { 349 s->flags |= SENSOR_FINVALID; 350 s->value = 0; 351 } else { 352 s->flags &= ~SENSOR_FINVALID; 353 s->value = temp * 1000000 + 273150000; 354 } 355 } 356