1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.37 2005/10/12 17:35:54 dillon Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 */ 101 102 #include <sys/param.h> 103 #include <sys/systm.h> 104 #include <sys/sockio.h> 105 #include <sys/endian.h> 106 #include <sys/mbuf.h> 107 #include <sys/kernel.h> 108 #include <sys/socket.h> 109 #include <sys/thread2.h> 110 111 #include <net/if.h> 112 #include <net/ifq_var.h> 113 #include <net/if_arp.h> 114 #include <net/ethernet.h> 115 #include <net/if_dl.h> 116 #include <net/if_media.h> 117 #include <net/vlan/if_vlan_var.h> 118 119 #include <net/bpf.h> 120 121 #include <machine/bus_memio.h> 122 #include <machine/bus_pio.h> 123 #include <machine/bus.h> 124 #include <machine/resource.h> 125 #include <sys/bus.h> 126 #include <sys/rman.h> 127 128 #include "../mii_layer/mii.h" 129 #include "../mii_layer/miivar.h" 130 131 #include <bus/pci/pcireg.h> 132 #include <bus/pci/pcivar.h> 133 134 /* "controller miibus0" required. See GENERIC if you get errors here. */ 135 #include "miibus_if.h" 136 137 #include "if_xlreg.h" 138 139 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 140 141 /* 142 * Various supported device vendors/types and their names. 143 */ 144 static struct xl_type xl_devs[] = { 145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 146 "3Com 3c900-TPO Etherlink XL" }, 147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 148 "3Com 3c900-COMBO Etherlink XL" }, 149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 150 "3Com 3c905-TX Fast Etherlink XL" }, 151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 152 "3Com 3c905-T4 Fast Etherlink XL" }, 153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 154 "3Com 3c900B-TPO Etherlink XL" }, 155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 156 "3Com 3c900B-COMBO Etherlink XL" }, 157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 158 "3Com 3c900B-TPC Etherlink XL" }, 159 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 160 "3Com 3c900B-FL Etherlink XL" }, 161 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 162 "3Com 3c905B-TX Fast Etherlink XL" }, 163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 164 "3Com 3c905B-T4 Fast Etherlink XL" }, 165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 166 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 168 "3Com 3c905B-COMBO Fast Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 170 "3Com 3c905C-TX Fast Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 172 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 174 "3Com 3c980 Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 176 "3Com 3c980C Fast Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 178 "3Com 3cSOHO100-TX OfficeConnect" }, 179 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 180 "3Com 3c450-TX HomeConnect" }, 181 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 182 "3Com 3c555 Fast Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 184 "3Com 3c556 Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 186 "3Com 3c556B Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 188 "3Com 3c575TX Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 190 "3Com 3c575B Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 192 "3Com 3c575C Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 194 "3Com 3c656 Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 196 "3Com 3c656B Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 198 "3Com 3c656C Fast Etherlink XL" }, 199 { 0, 0, NULL } 200 }; 201 202 static int xl_probe (device_t); 203 static int xl_attach (device_t); 204 static int xl_detach (device_t); 205 206 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 207 static void xl_stats_update (void *); 208 static int xl_encap (struct xl_softc *, struct xl_chain *, 209 struct mbuf *); 210 static void xl_rxeof (struct xl_softc *); 211 static int xl_rx_resync (struct xl_softc *); 212 static void xl_txeof (struct xl_softc *); 213 static void xl_txeof_90xB (struct xl_softc *); 214 static void xl_txeoc (struct xl_softc *); 215 static void xl_intr (void *); 216 static void xl_start (struct ifnet *); 217 static void xl_start_90xB (struct ifnet *); 218 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 219 struct ucred *); 220 static void xl_init (void *); 221 static void xl_stop (struct xl_softc *); 222 static void xl_watchdog (struct ifnet *); 223 static void xl_shutdown (device_t); 224 static int xl_suspend (device_t); 225 static int xl_resume (device_t); 226 227 static int xl_ifmedia_upd (struct ifnet *); 228 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 229 230 static int xl_eeprom_wait (struct xl_softc *); 231 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 232 static void xl_mii_sync (struct xl_softc *); 233 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 234 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 235 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 236 237 static void xl_setcfg (struct xl_softc *); 238 static void xl_setmode (struct xl_softc *, int); 239 static void xl_setmulti (struct xl_softc *); 240 static void xl_setmulti_hash (struct xl_softc *); 241 static void xl_reset (struct xl_softc *); 242 static int xl_list_rx_init (struct xl_softc *); 243 static void xl_list_tx_init (struct xl_softc *); 244 static void xl_list_tx_init_90xB(struct xl_softc *); 245 static void xl_wait (struct xl_softc *); 246 static void xl_mediacheck (struct xl_softc *); 247 static void xl_choose_xcvr (struct xl_softc *, int); 248 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 249 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 250 int); 251 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 252 int); 253 254 static int xl_dma_alloc (device_t); 255 static void xl_dma_free (device_t); 256 257 #ifdef notdef 258 static void xl_testpacket (struct xl_softc *); 259 #endif 260 261 static int xl_miibus_readreg (device_t, int, int); 262 static int xl_miibus_writereg (device_t, int, int, int); 263 static void xl_miibus_statchg (device_t); 264 static void xl_miibus_mediainit (device_t); 265 266 static device_method_t xl_methods[] = { 267 /* Device interface */ 268 DEVMETHOD(device_probe, xl_probe), 269 DEVMETHOD(device_attach, xl_attach), 270 DEVMETHOD(device_detach, xl_detach), 271 DEVMETHOD(device_shutdown, xl_shutdown), 272 DEVMETHOD(device_suspend, xl_suspend), 273 DEVMETHOD(device_resume, xl_resume), 274 275 /* bus interface */ 276 DEVMETHOD(bus_print_child, bus_generic_print_child), 277 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 278 279 /* MII interface */ 280 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 281 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 282 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 283 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 284 285 { 0, 0 } 286 }; 287 288 static driver_t xl_driver = { 289 "xl", 290 xl_methods, 291 sizeof(struct xl_softc) 292 }; 293 294 static devclass_t xl_devclass; 295 296 DECLARE_DUMMY_MODULE(if_xl); 297 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 298 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 299 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0); 300 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 301 302 static void 303 xl_dma_map_addr(arg, segs, nseg, error) 304 void *arg; 305 bus_dma_segment_t *segs; 306 int nseg, error; 307 { 308 u_int32_t *paddr; 309 310 paddr = arg; 311 *paddr = segs->ds_addr; 312 } 313 314 static void 315 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 316 void *arg; 317 bus_dma_segment_t *segs; 318 int nseg; 319 bus_size_t mapsize; 320 int error; 321 { 322 u_int32_t *paddr; 323 324 if (error) 325 return; 326 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 327 paddr = arg; 328 *paddr = segs->ds_addr; 329 } 330 331 static void 332 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error) 333 void *arg; 334 bus_dma_segment_t *segs; 335 int nseg; 336 bus_size_t mapsize; 337 int error; 338 { 339 struct xl_list *l; 340 int i, total_len; 341 342 if (error) 343 return; 344 345 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 346 347 total_len = 0; 348 l = arg; 349 for (i = 0; i < nseg; i++) { 350 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 351 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 352 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 353 total_len += segs[i].ds_len; 354 } 355 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 356 XL_LAST_FRAG); 357 l->xl_status = htole32(total_len); 358 l->xl_next = 0; 359 } 360 361 /* 362 * Murphy's law says that it's possible the chip can wedge and 363 * the 'command in progress' bit may never clear. Hence, we wait 364 * only a finite amount of time to avoid getting caught in an 365 * infinite loop. Normally this delay routine would be a macro, 366 * but it isn't called during normal operation so we can afford 367 * to make it a function. 368 */ 369 static void 370 xl_wait(sc) 371 struct xl_softc *sc; 372 { 373 int i; 374 375 for (i = 0; i < XL_TIMEOUT; i++) { 376 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 377 break; 378 } 379 380 if (i == XL_TIMEOUT) 381 if_printf(&sc->arpcom.ac_if, "command never completed!"); 382 383 return; 384 } 385 386 /* 387 * MII access routines are provided for adapters with external 388 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 389 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 390 * Note: if you don't perform the MDIO operations just right, 391 * it's possible to end up with code that works correctly with 392 * some chips/CPUs/processor speeds/bus speeds/etc but not 393 * with others. 394 */ 395 #define MII_SET(x) \ 396 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 397 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 398 399 #define MII_CLR(x) \ 400 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 401 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 402 403 /* 404 * Sync the PHYs by setting data bit and strobing the clock 32 times. 405 */ 406 static void 407 xl_mii_sync(sc) 408 struct xl_softc *sc; 409 { 410 int i; 411 412 XL_SEL_WIN(4); 413 MII_SET(XL_MII_DIR|XL_MII_DATA); 414 415 for (i = 0; i < 32; i++) { 416 MII_SET(XL_MII_CLK); 417 MII_SET(XL_MII_DATA); 418 MII_SET(XL_MII_DATA); 419 MII_CLR(XL_MII_CLK); 420 MII_SET(XL_MII_DATA); 421 MII_SET(XL_MII_DATA); 422 } 423 424 return; 425 } 426 427 /* 428 * Clock a series of bits through the MII. 429 */ 430 static void 431 xl_mii_send(sc, bits, cnt) 432 struct xl_softc *sc; 433 u_int32_t bits; 434 int cnt; 435 { 436 int i; 437 438 XL_SEL_WIN(4); 439 MII_CLR(XL_MII_CLK); 440 441 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 442 if (bits & i) { 443 MII_SET(XL_MII_DATA); 444 } else { 445 MII_CLR(XL_MII_DATA); 446 } 447 MII_CLR(XL_MII_CLK); 448 MII_SET(XL_MII_CLK); 449 } 450 } 451 452 /* 453 * Read an PHY register through the MII. 454 */ 455 static int 456 xl_mii_readreg(sc, frame) 457 struct xl_softc *sc; 458 struct xl_mii_frame *frame; 459 460 { 461 int i, ack; 462 463 crit_enter(); 464 465 /* 466 * Set up frame for RX. 467 */ 468 frame->mii_stdelim = XL_MII_STARTDELIM; 469 frame->mii_opcode = XL_MII_READOP; 470 frame->mii_turnaround = 0; 471 frame->mii_data = 0; 472 473 /* 474 * Select register window 4. 475 */ 476 477 XL_SEL_WIN(4); 478 479 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 480 /* 481 * Turn on data xmit. 482 */ 483 MII_SET(XL_MII_DIR); 484 485 xl_mii_sync(sc); 486 487 /* 488 * Send command/address info. 489 */ 490 xl_mii_send(sc, frame->mii_stdelim, 2); 491 xl_mii_send(sc, frame->mii_opcode, 2); 492 xl_mii_send(sc, frame->mii_phyaddr, 5); 493 xl_mii_send(sc, frame->mii_regaddr, 5); 494 495 /* Idle bit */ 496 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 497 MII_SET(XL_MII_CLK); 498 499 /* Turn off xmit. */ 500 MII_CLR(XL_MII_DIR); 501 502 /* Check for ack */ 503 MII_CLR(XL_MII_CLK); 504 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 505 MII_SET(XL_MII_CLK); 506 507 /* 508 * Now try reading data bits. If the ack failed, we still 509 * need to clock through 16 cycles to keep the PHY(s) in sync. 510 */ 511 if (ack) { 512 for(i = 0; i < 16; i++) { 513 MII_CLR(XL_MII_CLK); 514 MII_SET(XL_MII_CLK); 515 } 516 goto fail; 517 } 518 519 for (i = 0x8000; i; i >>= 1) { 520 MII_CLR(XL_MII_CLK); 521 if (!ack) { 522 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 523 frame->mii_data |= i; 524 } 525 MII_SET(XL_MII_CLK); 526 } 527 528 fail: 529 530 MII_CLR(XL_MII_CLK); 531 MII_SET(XL_MII_CLK); 532 533 crit_exit(); 534 535 if (ack) 536 return(1); 537 return(0); 538 } 539 540 /* 541 * Write to a PHY register through the MII. 542 */ 543 static int 544 xl_mii_writereg(sc, frame) 545 struct xl_softc *sc; 546 struct xl_mii_frame *frame; 547 548 { 549 crit_enter(); 550 551 /* 552 * Set up frame for TX. 553 */ 554 555 frame->mii_stdelim = XL_MII_STARTDELIM; 556 frame->mii_opcode = XL_MII_WRITEOP; 557 frame->mii_turnaround = XL_MII_TURNAROUND; 558 559 /* 560 * Select the window 4. 561 */ 562 XL_SEL_WIN(4); 563 564 /* 565 * Turn on data output. 566 */ 567 MII_SET(XL_MII_DIR); 568 569 xl_mii_sync(sc); 570 571 xl_mii_send(sc, frame->mii_stdelim, 2); 572 xl_mii_send(sc, frame->mii_opcode, 2); 573 xl_mii_send(sc, frame->mii_phyaddr, 5); 574 xl_mii_send(sc, frame->mii_regaddr, 5); 575 xl_mii_send(sc, frame->mii_turnaround, 2); 576 xl_mii_send(sc, frame->mii_data, 16); 577 578 /* Idle bit. */ 579 MII_SET(XL_MII_CLK); 580 MII_CLR(XL_MII_CLK); 581 582 /* 583 * Turn off xmit. 584 */ 585 MII_CLR(XL_MII_DIR); 586 587 crit_exit(); 588 589 return(0); 590 } 591 592 static int 593 xl_miibus_readreg(dev, phy, reg) 594 device_t dev; 595 int phy, reg; 596 { 597 struct xl_softc *sc; 598 struct xl_mii_frame frame; 599 600 sc = device_get_softc(dev); 601 602 /* 603 * Pretend that PHYs are only available at MII address 24. 604 * This is to guard against problems with certain 3Com ASIC 605 * revisions that incorrectly map the internal transceiver 606 * control registers at all MII addresses. This can cause 607 * the miibus code to attach the same PHY several times over. 608 */ 609 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 610 return(0); 611 612 bzero((char *)&frame, sizeof(frame)); 613 614 frame.mii_phyaddr = phy; 615 frame.mii_regaddr = reg; 616 xl_mii_readreg(sc, &frame); 617 618 return(frame.mii_data); 619 } 620 621 static int 622 xl_miibus_writereg(dev, phy, reg, data) 623 device_t dev; 624 int phy, reg, data; 625 { 626 struct xl_softc *sc; 627 struct xl_mii_frame frame; 628 629 sc = device_get_softc(dev); 630 631 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 632 return(0); 633 634 bzero((char *)&frame, sizeof(frame)); 635 636 frame.mii_phyaddr = phy; 637 frame.mii_regaddr = reg; 638 frame.mii_data = data; 639 640 xl_mii_writereg(sc, &frame); 641 642 return(0); 643 } 644 645 static void 646 xl_miibus_statchg(dev) 647 device_t dev; 648 { 649 struct xl_softc *sc; 650 struct mii_data *mii; 651 652 653 sc = device_get_softc(dev); 654 mii = device_get_softc(sc->xl_miibus); 655 656 xl_setcfg(sc); 657 658 /* Set ASIC's duplex mode to match the PHY. */ 659 XL_SEL_WIN(3); 660 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 661 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 662 else 663 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 664 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 665 666 return; 667 } 668 669 /* 670 * Special support for the 3c905B-COMBO. This card has 10/100 support 671 * plus BNC and AUI ports. This means we will have both an miibus attached 672 * plus some non-MII media settings. In order to allow this, we have to 673 * add the extra media to the miibus's ifmedia struct, but we can't do 674 * that during xl_attach() because the miibus hasn't been attached yet. 675 * So instead, we wait until the miibus probe/attach is done, at which 676 * point we will get a callback telling is that it's safe to add our 677 * extra media. 678 */ 679 static void 680 xl_miibus_mediainit(dev) 681 device_t dev; 682 { 683 struct xl_softc *sc; 684 struct mii_data *mii; 685 struct ifmedia *ifm; 686 687 sc = device_get_softc(dev); 688 mii = device_get_softc(sc->xl_miibus); 689 ifm = &mii->mii_media; 690 691 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 692 /* 693 * Check for a 10baseFL board in disguise. 694 */ 695 if (sc->xl_type == XL_TYPE_905B && 696 sc->xl_media == XL_MEDIAOPT_10FL) { 697 if (bootverbose) 698 device_printf(dev, "found 10baseFL\n"); 699 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 700 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 701 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 702 ifmedia_add(ifm, 703 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 704 } else { 705 if (bootverbose) 706 device_printf(dev, "found AUI\n"); 707 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 708 } 709 } 710 711 if (sc->xl_media & XL_MEDIAOPT_BNC) { 712 if (bootverbose) 713 device_printf(dev, "found BNC\n"); 714 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 715 } 716 717 return; 718 } 719 720 /* 721 * The EEPROM is slow: give it time to come ready after issuing 722 * it a command. 723 */ 724 static int 725 xl_eeprom_wait(sc) 726 struct xl_softc *sc; 727 { 728 int i; 729 730 for (i = 0; i < 100; i++) { 731 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 732 DELAY(162); 733 else 734 break; 735 } 736 737 if (i == 100) { 738 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 739 return(1); 740 } 741 742 return(0); 743 } 744 745 /* 746 * Read a sequence of words from the EEPROM. Note that ethernet address 747 * data is stored in the EEPROM in network byte order. 748 */ 749 static int 750 xl_read_eeprom(sc, dest, off, cnt, swap) 751 struct xl_softc *sc; 752 caddr_t dest; 753 int off; 754 int cnt; 755 int swap; 756 { 757 int err = 0, i; 758 u_int16_t word = 0, *ptr; 759 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 760 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 761 /* WARNING! DANGER! 762 * It's easy to accidentally overwrite the rom content! 763 * Note: the 3c575 uses 8bit EEPROM offsets. 764 */ 765 XL_SEL_WIN(0); 766 767 if (xl_eeprom_wait(sc)) 768 return(1); 769 770 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 771 off += 0x30; 772 773 for (i = 0; i < cnt; i++) { 774 if (sc->xl_flags & XL_FLAG_8BITROM) 775 CSR_WRITE_2(sc, XL_W0_EE_CMD, 776 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 777 else 778 CSR_WRITE_2(sc, XL_W0_EE_CMD, 779 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 780 err = xl_eeprom_wait(sc); 781 if (err) 782 break; 783 word = CSR_READ_2(sc, XL_W0_EE_DATA); 784 ptr = (u_int16_t *)(dest + (i * 2)); 785 if (swap) 786 *ptr = ntohs(word); 787 else 788 *ptr = word; 789 } 790 791 return(err ? 1 : 0); 792 } 793 794 /* 795 * NICs older than the 3c905B have only one multicast option, which 796 * is to enable reception of all multicast frames. 797 */ 798 static void 799 xl_setmulti(sc) 800 struct xl_softc *sc; 801 { 802 struct ifnet *ifp; 803 struct ifmultiaddr *ifma; 804 u_int8_t rxfilt; 805 int mcnt = 0; 806 807 ifp = &sc->arpcom.ac_if; 808 809 XL_SEL_WIN(5); 810 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 811 812 if (ifp->if_flags & IFF_ALLMULTI) { 813 rxfilt |= XL_RXFILTER_ALLMULTI; 814 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 815 return; 816 } 817 818 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 819 mcnt++; 820 821 if (mcnt) 822 rxfilt |= XL_RXFILTER_ALLMULTI; 823 else 824 rxfilt &= ~XL_RXFILTER_ALLMULTI; 825 826 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 827 828 return; 829 } 830 831 /* 832 * 3c905B adapters have a hash filter that we can program. 833 */ 834 static void 835 xl_setmulti_hash(sc) 836 struct xl_softc *sc; 837 { 838 struct ifnet *ifp; 839 int h = 0, i; 840 struct ifmultiaddr *ifma; 841 u_int8_t rxfilt; 842 int mcnt = 0; 843 844 ifp = &sc->arpcom.ac_if; 845 846 XL_SEL_WIN(5); 847 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 848 849 if (ifp->if_flags & IFF_ALLMULTI) { 850 rxfilt |= XL_RXFILTER_ALLMULTI; 851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 852 return; 853 } else 854 rxfilt &= ~XL_RXFILTER_ALLMULTI; 855 856 857 /* first, zot all the existing hash bits */ 858 for (i = 0; i < XL_HASHFILT_SIZE; i++) 859 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 860 861 /* now program new ones */ 862 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 863 if (ifma->ifma_addr->sa_family != AF_LINK) 864 continue; 865 866 /* 867 * Note: the 3c905B currently only supports a 64-bit 868 * hash table, which means we really only need 6 bits, 869 * but the manual indicates that future chip revisions 870 * will have a 256-bit hash table, hence the routine is 871 * set up to calculate 8 bits of position info in case 872 * we need it some day. 873 * Note II, The Sequel: _CURRENT_ versions of the 3c905B 874 * have a 256 bit hash table. This means we have to use 875 * all 8 bits regardless. On older cards, the upper 2 876 * bits will be ignored. Grrrr.... 877 */ 878 h = ether_crc32_be( 879 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 880 ETHER_ADDR_LEN) & 0xff; 881 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 882 mcnt++; 883 } 884 885 if (mcnt) 886 rxfilt |= XL_RXFILTER_MULTIHASH; 887 else 888 rxfilt &= ~XL_RXFILTER_MULTIHASH; 889 890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 891 892 return; 893 } 894 895 #ifdef notdef 896 static void 897 xl_testpacket(sc) 898 struct xl_softc *sc; 899 { 900 struct mbuf *m; 901 struct ifnet *ifp; 902 903 ifp = &sc->arpcom.ac_if; 904 905 MGETHDR(m, MB_DONTWAIT, MT_DATA); 906 907 if (m == NULL) 908 return; 909 910 bcopy(&sc->arpcom.ac_enaddr, 911 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 912 bcopy(&sc->arpcom.ac_enaddr, 913 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 914 mtod(m, struct ether_header *)->ether_type = htons(3); 915 mtod(m, unsigned char *)[14] = 0; 916 mtod(m, unsigned char *)[15] = 0; 917 mtod(m, unsigned char *)[16] = 0xE3; 918 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 919 IF_ENQUEUE(&ifp->if_snd, m); 920 xl_start(ifp); 921 922 return; 923 } 924 #endif 925 926 static void 927 xl_setcfg(sc) 928 struct xl_softc *sc; 929 { 930 u_int32_t icfg; 931 932 XL_SEL_WIN(3); 933 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 934 icfg &= ~XL_ICFG_CONNECTOR_MASK; 935 if (sc->xl_media & XL_MEDIAOPT_MII || 936 sc->xl_media & XL_MEDIAOPT_BT4) 937 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 938 if (sc->xl_media & XL_MEDIAOPT_BTX) 939 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 940 941 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 942 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 943 944 return; 945 } 946 947 static void 948 xl_setmode(sc, media) 949 struct xl_softc *sc; 950 int media; 951 { 952 struct ifnet *ifp = &sc->arpcom.ac_if; 953 u_int32_t icfg; 954 u_int16_t mediastat; 955 956 if_printf(ifp, "selecting "); 957 958 XL_SEL_WIN(4); 959 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 960 XL_SEL_WIN(3); 961 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 962 963 if (sc->xl_media & XL_MEDIAOPT_BT) { 964 if (IFM_SUBTYPE(media) == IFM_10_T) { 965 printf("10baseT transceiver, "); 966 sc->xl_xcvr = XL_XCVR_10BT; 967 icfg &= ~XL_ICFG_CONNECTOR_MASK; 968 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 969 mediastat |= XL_MEDIASTAT_LINKBEAT| 970 XL_MEDIASTAT_JABGUARD; 971 mediastat &= ~XL_MEDIASTAT_SQEENB; 972 } 973 } 974 975 if (sc->xl_media & XL_MEDIAOPT_BFX) { 976 if (IFM_SUBTYPE(media) == IFM_100_FX) { 977 printf("100baseFX port, "); 978 sc->xl_xcvr = XL_XCVR_100BFX; 979 icfg &= ~XL_ICFG_CONNECTOR_MASK; 980 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 981 mediastat |= XL_MEDIASTAT_LINKBEAT; 982 mediastat &= ~XL_MEDIASTAT_SQEENB; 983 } 984 } 985 986 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 987 if (IFM_SUBTYPE(media) == IFM_10_5) { 988 printf("AUI port, "); 989 sc->xl_xcvr = XL_XCVR_AUI; 990 icfg &= ~XL_ICFG_CONNECTOR_MASK; 991 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 992 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 993 XL_MEDIASTAT_JABGUARD); 994 mediastat |= ~XL_MEDIASTAT_SQEENB; 995 } 996 if (IFM_SUBTYPE(media) == IFM_10_FL) { 997 printf("10baseFL transceiver, "); 998 sc->xl_xcvr = XL_XCVR_AUI; 999 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1000 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1001 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1002 XL_MEDIASTAT_JABGUARD); 1003 mediastat |= ~XL_MEDIASTAT_SQEENB; 1004 } 1005 } 1006 1007 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1008 if (IFM_SUBTYPE(media) == IFM_10_2) { 1009 printf("BNC port, "); 1010 sc->xl_xcvr = XL_XCVR_COAX; 1011 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1012 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 1013 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1014 XL_MEDIASTAT_JABGUARD| 1015 XL_MEDIASTAT_SQEENB); 1016 } 1017 } 1018 1019 if ((media & IFM_GMASK) == IFM_FDX || 1020 IFM_SUBTYPE(media) == IFM_100_FX) { 1021 printf("full duplex\n"); 1022 XL_SEL_WIN(3); 1023 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1024 } else { 1025 printf("half duplex\n"); 1026 XL_SEL_WIN(3); 1027 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1028 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1029 } 1030 1031 if (IFM_SUBTYPE(media) == IFM_10_2) 1032 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1033 else 1034 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1035 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1036 XL_SEL_WIN(4); 1037 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1038 DELAY(800); 1039 XL_SEL_WIN(7); 1040 } 1041 1042 static void 1043 xl_reset(sc) 1044 struct xl_softc *sc; 1045 { 1046 int i; 1047 1048 XL_SEL_WIN(0); 1049 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1050 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1051 XL_RESETOPT_DISADVFD:0)); 1052 1053 /* 1054 * If we're using memory mapped register mode, pause briefly 1055 * after issuing the reset command before trying to access any 1056 * other registers. With my 3c575C cardbus card, failing to do 1057 * this results in the system locking up while trying to poll 1058 * the command busy bit in the status register. 1059 */ 1060 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1061 DELAY(100000); 1062 1063 for (i = 0; i < XL_TIMEOUT; i++) { 1064 DELAY(10); 1065 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1066 break; 1067 } 1068 1069 if (i == XL_TIMEOUT) 1070 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 1071 1072 /* Reset TX and RX. */ 1073 /* Note: the RX reset takes an absurd amount of time 1074 * on newer versions of the Tornado chips such as those 1075 * on the 3c905CX and newer 3c908C cards. We wait an 1076 * extra amount of time so that xl_wait() doesn't complain 1077 * and annoy the users. 1078 */ 1079 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1080 DELAY(100000); 1081 xl_wait(sc); 1082 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1083 xl_wait(sc); 1084 1085 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1086 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1087 XL_SEL_WIN(2); 1088 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1089 XL_W2_RESET_OPTIONS) 1090 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1091 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1092 ); 1093 } 1094 1095 /* Wait a little while for the chip to get its brains in order. */ 1096 DELAY(100000); 1097 return; 1098 } 1099 1100 /* 1101 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1102 * IDs against our list and return a device name if we find a match. 1103 */ 1104 static int 1105 xl_probe(device_t dev) 1106 { 1107 struct xl_type *t; 1108 uint16_t vid, did; 1109 1110 vid = pci_get_vendor(dev); 1111 did = pci_get_device(dev); 1112 for (t = xl_devs; t->xl_name != NULL; t++) { 1113 if (vid == t->xl_vid && did == t->xl_did) { 1114 device_set_desc(dev, t->xl_name); 1115 return(0); 1116 } 1117 } 1118 return(ENXIO); 1119 } 1120 1121 /* 1122 * This routine is a kludge to work around possible hardware faults 1123 * or manufacturing defects that can cause the media options register 1124 * (or reset options register, as it's called for the first generation 1125 * 3c90x adapters) to return an incorrect result. I have encountered 1126 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1127 * which doesn't have any of the 'mediaopt' bits set. This screws up 1128 * the attach routine pretty badly because it doesn't know what media 1129 * to look for. If we find ourselves in this predicament, this routine 1130 * will try to guess the media options values and warn the user of a 1131 * possible manufacturing defect with his adapter/system/whatever. 1132 */ 1133 static void 1134 xl_mediacheck(sc) 1135 struct xl_softc *sc; 1136 { 1137 struct ifnet *ifp = &sc->arpcom.ac_if; 1138 1139 /* 1140 * If some of the media options bits are set, assume they are 1141 * correct. If not, try to figure it out down below. 1142 * XXX I should check for 10baseFL, but I don't have an adapter 1143 * to test with. 1144 */ 1145 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1146 /* 1147 * Check the XCVR value. If it's not in the normal range 1148 * of values, we need to fake it up here. 1149 */ 1150 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1151 return; 1152 else { 1153 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1154 sc->xl_xcvr); 1155 if_printf(ifp, 1156 "choosing new default based on card type\n"); 1157 } 1158 } else { 1159 if (sc->xl_type == XL_TYPE_905B && 1160 sc->xl_media & XL_MEDIAOPT_10FL) 1161 return; 1162 if_printf(ifp, "WARNING: no media options bits set in " 1163 "the media options register!!\n"); 1164 if_printf(ifp, "this could be a manufacturing defect in " 1165 "your adapter or system\n"); 1166 if_printf(ifp, "attempting to guess media type; you " 1167 "should probably consult your vendor\n"); 1168 } 1169 1170 xl_choose_xcvr(sc, 1); 1171 } 1172 1173 static void 1174 xl_choose_xcvr(sc, verbose) 1175 struct xl_softc *sc; 1176 int verbose; 1177 { 1178 struct ifnet *ifp = &sc->arpcom.ac_if; 1179 u_int16_t devid; 1180 1181 /* 1182 * Read the device ID from the EEPROM. 1183 * This is what's loaded into the PCI device ID register, so it has 1184 * to be correct otherwise we wouldn't have gotten this far. 1185 */ 1186 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1187 1188 switch(devid) { 1189 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1190 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1191 sc->xl_media = XL_MEDIAOPT_BT; 1192 sc->xl_xcvr = XL_XCVR_10BT; 1193 if (verbose) 1194 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1195 break; 1196 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1197 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1198 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1199 sc->xl_xcvr = XL_XCVR_10BT; 1200 if (verbose) 1201 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1202 break; 1203 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1204 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1205 sc->xl_xcvr = XL_XCVR_10BT; 1206 if (verbose) 1207 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1208 break; 1209 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1210 sc->xl_media = XL_MEDIAOPT_10FL; 1211 sc->xl_xcvr = XL_XCVR_AUI; 1212 if (verbose) 1213 if_printf(ifp, "guessing 10baseFL\n"); 1214 break; 1215 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1216 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1217 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1218 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1219 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1220 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1221 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1222 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1223 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1224 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1225 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1226 sc->xl_media = XL_MEDIAOPT_MII; 1227 sc->xl_xcvr = XL_XCVR_MII; 1228 if (verbose) 1229 if_printf(ifp, "guessing MII\n"); 1230 break; 1231 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1232 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1233 sc->xl_media = XL_MEDIAOPT_BT4; 1234 sc->xl_xcvr = XL_XCVR_MII; 1235 if (verbose) 1236 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1237 break; 1238 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1239 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1240 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1241 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1242 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1243 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1244 sc->xl_media = XL_MEDIAOPT_BTX; 1245 sc->xl_xcvr = XL_XCVR_AUTO; 1246 if (verbose) 1247 if_printf(ifp, "guessing 10/100 internal\n"); 1248 break; 1249 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1250 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1251 sc->xl_xcvr = XL_XCVR_AUTO; 1252 if (verbose) 1253 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1254 break; 1255 default: 1256 if_printf(ifp, 1257 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1258 sc->xl_media = XL_MEDIAOPT_BT; 1259 break; 1260 } 1261 1262 return; 1263 } 1264 1265 /* 1266 * Attach the interface. Allocate softc structures, do ifmedia 1267 * setup and ethernet/BPF attach. 1268 */ 1269 static int 1270 xl_attach(dev) 1271 device_t dev; 1272 { 1273 u_char eaddr[ETHER_ADDR_LEN]; 1274 u_int16_t xcvr[2]; 1275 struct xl_softc *sc; 1276 struct ifnet *ifp; 1277 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1278 int error = 0, rid, res; 1279 1280 sc = device_get_softc(dev); 1281 1282 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1283 1284 sc->xl_flags = 0; 1285 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1286 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1287 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1288 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1289 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1290 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1291 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1292 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 || 1293 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1294 sc->xl_flags |= XL_FLAG_8BITROM; 1295 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1296 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1297 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1298 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1299 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1300 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1301 sc->xl_flags |= XL_FLAG_FUNCREG; 1302 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1303 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1304 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1305 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1306 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1307 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1308 XL_FLAG_8BITROM; 1309 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1310 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1311 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1312 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1313 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1314 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1315 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1316 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1317 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1318 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1319 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1320 XL_FLAG_INVERT_LED_PWR; 1321 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1322 sc->xl_flags |= XL_FLAG_PHYOK; 1323 #ifndef BURN_BRIDGES 1324 /* 1325 * If this is a 3c905B, we have to check one extra thing. 1326 * The 905B supports power management and may be placed in 1327 * a low-power mode (D3 mode), typically by certain operating 1328 * systems which shall not be named. The PCI BIOS is supposed 1329 * to reset the NIC and bring it out of low-power mode, but 1330 * some do not. Consequently, we have to see if this chip 1331 * supports power management, and if so, make sure it's not 1332 * in low-power mode. If power management is available, the 1333 * capid byte will be 0x01. 1334 * 1335 * I _think_ that what actually happens is that the chip 1336 * loses its PCI configuration during the transition from 1337 * D3 back to D0; this means that it should be possible for 1338 * us to save the PCI iobase, membase and IRQ, put the chip 1339 * back in the D0 state, then restore the PCI config ourselves. 1340 */ 1341 1342 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1343 u_int32_t iobase, membase, irq; 1344 1345 /* Save important PCI config data. */ 1346 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1347 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1348 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1349 1350 /* Reset the power state. */ 1351 device_printf(dev, "chip is in D%d power mode " 1352 "-- setting to D0\n", pci_get_powerstate(dev)); 1353 1354 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1355 1356 /* Restore PCI config data. */ 1357 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1358 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1359 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1360 } 1361 #endif 1362 /* 1363 * Map control/status registers. 1364 */ 1365 pci_enable_busmaster(dev); 1366 1367 rid = XL_PCI_LOMEM; 1368 res = SYS_RES_MEMORY; 1369 1370 #if 0 1371 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1372 #endif 1373 1374 if (sc->xl_res != NULL) { 1375 sc->xl_flags |= XL_FLAG_USE_MMIO; 1376 if (bootverbose) 1377 device_printf(dev, "using memory mapped I/O\n"); 1378 } else { 1379 rid = XL_PCI_LOIO; 1380 res = SYS_RES_IOPORT; 1381 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1382 if (sc->xl_res == NULL) { 1383 device_printf(dev, "couldn't map ports/memory\n"); 1384 error = ENXIO; 1385 goto fail; 1386 } 1387 if (bootverbose) 1388 device_printf(dev, "using port I/O\n"); 1389 } 1390 1391 sc->xl_btag = rman_get_bustag(sc->xl_res); 1392 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1393 1394 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1395 rid = XL_PCI_FUNCMEM; 1396 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1397 RF_ACTIVE); 1398 1399 if (sc->xl_fres == NULL) { 1400 device_printf(dev, "couldn't map funcreg memory\n"); 1401 error = ENXIO; 1402 goto fail; 1403 } 1404 1405 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1406 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1407 } 1408 1409 /* Allocate interrupt */ 1410 rid = 0; 1411 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1412 RF_SHAREABLE | RF_ACTIVE); 1413 if (sc->xl_irq == NULL) { 1414 device_printf(dev, "couldn't map interrupt\n"); 1415 error = ENXIO; 1416 goto fail; 1417 } 1418 1419 ifp = &sc->arpcom.ac_if; 1420 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1421 1422 /* Reset the adapter. */ 1423 xl_reset(sc); 1424 1425 /* 1426 * Get station address from the EEPROM. 1427 */ 1428 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1429 device_printf(dev, "failed to read station address\n"); 1430 error = ENXIO; 1431 goto fail; 1432 } 1433 1434 callout_init(&sc->xl_stat_timer); 1435 1436 error = xl_dma_alloc(dev); 1437 if (error) 1438 goto fail; 1439 1440 /* 1441 * Figure out the card type. 3c905B adapters have the 1442 * 'supportsNoTxLength' bit set in the capabilities 1443 * word in the EEPROM. 1444 * Note: my 3c575C cardbus card lies. It returns a value 1445 * of 0x1578 for its capabilities word, which is somewhat 1446 * nonsensical. Another way to distinguish a 3c90x chip 1447 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1448 * bit. This will only be set for 3c90x boomerage chips. 1449 */ 1450 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1451 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1452 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1453 sc->xl_type = XL_TYPE_905B; 1454 else 1455 sc->xl_type = XL_TYPE_90X; 1456 if (bootverbose) { 1457 device_printf(dev, "type %s\n", 1458 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X"); 1459 } 1460 1461 ifp->if_softc = sc; 1462 ifp->if_mtu = ETHERMTU; 1463 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1464 ifp->if_ioctl = xl_ioctl; 1465 ifp->if_capabilities = 0; 1466 if (sc->xl_type == XL_TYPE_905B) { 1467 ifp->if_start = xl_start_90xB; 1468 ifp->if_capabilities |= IFCAP_HWCSUM; 1469 } else { 1470 ifp->if_start = xl_start; 1471 } 1472 ifp->if_watchdog = xl_watchdog; 1473 ifp->if_init = xl_init; 1474 ifp->if_baudrate = 10000000; 1475 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1476 ifq_set_ready(&ifp->if_snd); 1477 /* 1478 * NOTE: features disabled by default. This seems to corrupt 1479 * tx packet data one out of a million packets or so and then 1480 * generates a good checksum so the receiver doesn't 1481 * know the packet is bad 1482 */ 1483 ifp->if_capenable = 0; /*ifp->if_capabilities;*/ 1484 if (ifp->if_capenable & IFCAP_TXCSUM) 1485 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1486 1487 /* 1488 * Now we have to see what sort of media we have. 1489 * This includes probing for an MII interace and a 1490 * possible PHY. 1491 */ 1492 XL_SEL_WIN(3); 1493 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1494 if (bootverbose) 1495 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1496 1497 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1498 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1499 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1500 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1501 1502 xl_mediacheck(sc); 1503 1504 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1505 || sc->xl_media & XL_MEDIAOPT_BT4) { 1506 if (bootverbose) 1507 if_printf(ifp, "found MII/AUTO\n"); 1508 xl_setcfg(sc); 1509 1510 error = mii_phy_probe(dev, &sc->xl_miibus, 1511 xl_ifmedia_upd, xl_ifmedia_sts); 1512 if (error) { 1513 if_printf(ifp, "no PHY found!\n"); 1514 goto fail; 1515 } 1516 1517 goto done; 1518 } 1519 1520 /* 1521 * Sanity check. If the user has selected "auto" and this isn't 1522 * a 10/100 card of some kind, we need to force the transceiver 1523 * type to something sane. 1524 */ 1525 if (sc->xl_xcvr == XL_XCVR_AUTO) 1526 xl_choose_xcvr(sc, bootverbose); 1527 1528 /* 1529 * Do ifmedia setup. 1530 */ 1531 if (sc->xl_media & XL_MEDIAOPT_BT) { 1532 if (bootverbose) 1533 if_printf(ifp, "found 10baseT\n"); 1534 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1535 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1536 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1537 ifmedia_add(&sc->ifmedia, 1538 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1539 } 1540 1541 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1542 /* 1543 * Check for a 10baseFL board in disguise. 1544 */ 1545 if (sc->xl_type == XL_TYPE_905B && 1546 sc->xl_media == XL_MEDIAOPT_10FL) { 1547 if (bootverbose) 1548 if_printf(ifp, "found 10baseFL\n"); 1549 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1550 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1551 0, NULL); 1552 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1553 ifmedia_add(&sc->ifmedia, 1554 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1555 } else { 1556 if (bootverbose) 1557 if_printf(ifp, "found AUI\n"); 1558 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1559 } 1560 } 1561 1562 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1563 if (bootverbose) 1564 if_printf(ifp, "found BNC\n"); 1565 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1566 } 1567 1568 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1569 if (bootverbose) 1570 if_printf(ifp, "found 100baseFX\n"); 1571 ifp->if_baudrate = 100000000; 1572 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1573 } 1574 1575 /* Choose a default media. */ 1576 switch(sc->xl_xcvr) { 1577 case XL_XCVR_10BT: 1578 media = IFM_ETHER|IFM_10_T; 1579 xl_setmode(sc, media); 1580 break; 1581 case XL_XCVR_AUI: 1582 if (sc->xl_type == XL_TYPE_905B && 1583 sc->xl_media == XL_MEDIAOPT_10FL) { 1584 media = IFM_ETHER|IFM_10_FL; 1585 xl_setmode(sc, media); 1586 } else { 1587 media = IFM_ETHER|IFM_10_5; 1588 xl_setmode(sc, media); 1589 } 1590 break; 1591 case XL_XCVR_COAX: 1592 media = IFM_ETHER|IFM_10_2; 1593 xl_setmode(sc, media); 1594 break; 1595 case XL_XCVR_AUTO: 1596 case XL_XCVR_100BTX: 1597 case XL_XCVR_MII: 1598 /* Chosen by miibus */ 1599 break; 1600 case XL_XCVR_100BFX: 1601 media = IFM_ETHER|IFM_100_FX; 1602 break; 1603 default: 1604 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1605 /* 1606 * This will probably be wrong, but it prevents 1607 * the ifmedia code from panicking. 1608 */ 1609 media = IFM_ETHER|IFM_10_T; 1610 break; 1611 } 1612 1613 if (sc->xl_miibus == NULL) 1614 ifmedia_set(&sc->ifmedia, media); 1615 1616 done: 1617 1618 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1619 XL_SEL_WIN(0); 1620 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1621 } 1622 1623 /* 1624 * Call MI attach routine. 1625 */ 1626 ether_ifattach(ifp, eaddr); 1627 1628 /* 1629 * Tell the upper layer(s) we support long frames. 1630 */ 1631 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1632 1633 /* Hook interrupt last to avoid having to lock softc */ 1634 error = bus_setup_intr(dev, sc->xl_irq, 0, 1635 xl_intr, sc, &sc->xl_intrhand, NULL); 1636 if (error) { 1637 if_printf(ifp, "couldn't set up irq\n"); 1638 ether_ifdetach(ifp); 1639 goto fail; 1640 } 1641 1642 return 0; 1643 1644 fail: 1645 xl_detach(dev); 1646 return error; 1647 } 1648 1649 /* 1650 * Shutdown hardware and free up resources. This can be called any 1651 * time after the mutex has been initialized. It is called in both 1652 * the error case in attach and the normal detach case so it needs 1653 * to be careful about only freeing resources that have actually been 1654 * allocated. 1655 */ 1656 static int 1657 xl_detach(dev) 1658 device_t dev; 1659 { 1660 struct xl_softc *sc; 1661 struct ifnet *ifp; 1662 int rid, res; 1663 1664 sc = device_get_softc(dev); 1665 ifp = &sc->arpcom.ac_if; 1666 1667 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1668 rid = XL_PCI_LOMEM; 1669 res = SYS_RES_MEMORY; 1670 } else { 1671 rid = XL_PCI_LOIO; 1672 res = SYS_RES_IOPORT; 1673 } 1674 1675 crit_enter(); 1676 1677 if (device_is_attached(dev)) { 1678 xl_reset(sc); 1679 xl_stop(sc); 1680 ether_ifdetach(ifp); 1681 } 1682 1683 if (sc->xl_miibus) 1684 device_delete_child(dev, sc->xl_miibus); 1685 bus_generic_detach(dev); 1686 ifmedia_removeall(&sc->ifmedia); 1687 1688 if (sc->xl_intrhand) 1689 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1690 1691 crit_exit(); 1692 1693 if (sc->xl_irq) 1694 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1695 if (sc->xl_fres != NULL) 1696 bus_release_resource(dev, SYS_RES_MEMORY, 1697 XL_PCI_FUNCMEM, sc->xl_fres); 1698 if (sc->xl_res) 1699 bus_release_resource(dev, res, rid, sc->xl_res); 1700 1701 xl_dma_free(dev); 1702 1703 return(0); 1704 } 1705 1706 static int 1707 xl_dma_alloc(device_t dev) 1708 { 1709 struct xl_softc *sc; 1710 struct xl_chain_data *cd; 1711 struct xl_list_data *ld; 1712 int i, error; 1713 1714 sc = device_get_softc(dev); 1715 cd = &sc->xl_cdata; 1716 ld = &sc->xl_ldata; 1717 1718 /* 1719 * Now allocate a tag for the DMA descriptor lists and a chunk 1720 * of DMA-able memory based on the tag. Also obtain the DMA 1721 * addresses of the RX and TX ring, which we'll need later. 1722 * All of our lists are allocated as a contiguous block 1723 * of memory. 1724 */ 1725 error = bus_dma_tag_create(NULL, 8, 0, 1726 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1727 NULL, NULL, 1728 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 1729 0, &ld->xl_rx_tag); 1730 if (error) { 1731 device_printf(dev, "failed to allocate rx dma tag\n"); 1732 return error; 1733 } 1734 1735 error = bus_dmamem_alloc(ld->xl_rx_tag, (void **)&ld->xl_rx_list, 1736 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1737 &ld->xl_rx_dmamap); 1738 if (error) { 1739 device_printf(dev, "no memory for rx list buffers!\n"); 1740 bus_dma_tag_destroy(ld->xl_rx_tag); 1741 ld->xl_rx_tag = NULL; 1742 return error; 1743 } 1744 1745 error = bus_dmamap_load(ld->xl_rx_tag, ld->xl_rx_dmamap, 1746 ld->xl_rx_list, XL_RX_LIST_SZ, 1747 xl_dma_map_addr, &ld->xl_rx_dmaaddr, 1748 BUS_DMA_WAITOK); 1749 if (error) { 1750 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1751 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1752 ld->xl_rx_dmamap); 1753 bus_dma_tag_destroy(ld->xl_rx_tag); 1754 ld->xl_rx_tag = NULL; 1755 return error; 1756 } 1757 1758 error = bus_dma_tag_create(NULL, 8, 0, 1759 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1760 NULL, NULL, 1761 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 1762 0, &ld->xl_tx_tag); 1763 if (error) { 1764 device_printf(dev, "failed to allocate tx dma tag\n"); 1765 return error; 1766 } 1767 1768 error = bus_dmamem_alloc(ld->xl_tx_tag, (void **)&ld->xl_tx_list, 1769 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1770 &ld->xl_tx_dmamap); 1771 if (error) { 1772 device_printf(dev, "no memory for list buffers!\n"); 1773 bus_dma_tag_destroy(ld->xl_tx_tag); 1774 ld->xl_tx_tag = NULL; 1775 return error; 1776 } 1777 1778 error = bus_dmamap_load(ld->xl_tx_tag, ld->xl_tx_dmamap, 1779 ld->xl_tx_list, XL_TX_LIST_SZ, 1780 xl_dma_map_addr, &ld->xl_tx_dmaaddr, 1781 BUS_DMA_WAITOK); 1782 if (error) { 1783 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1784 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1785 ld->xl_tx_dmamap); 1786 bus_dma_tag_destroy(ld->xl_tx_tag); 1787 ld->xl_tx_tag = NULL; 1788 return error; 1789 } 1790 1791 /* 1792 * Allocate a DMA tag for the mapping of mbufs. 1793 */ 1794 error = bus_dma_tag_create(NULL, 1, 0, 1795 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1796 NULL, NULL, 1797 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, 1798 MCLBYTES, 0, &sc->xl_mtag); 1799 if (error) { 1800 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1801 return error; 1802 } 1803 1804 /* 1805 * Allocate a spare DMA map for the RX ring. 1806 */ 1807 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1808 if (error) { 1809 device_printf(dev, "failed to create mbuf dma map\n"); 1810 bus_dma_tag_destroy(sc->xl_mtag); 1811 sc->xl_mtag = NULL; 1812 return error; 1813 } 1814 1815 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1816 error = bus_dmamap_create(sc->xl_mtag, 0, 1817 &cd->xl_rx_chain[i].xl_map); 1818 if (error) { 1819 device_printf(dev, "failed to create %dth " 1820 "rx descriptor dma map!\n", i); 1821 return error; 1822 } 1823 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1824 } 1825 1826 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1827 error = bus_dmamap_create(sc->xl_mtag, 0, 1828 &cd->xl_tx_chain[i].xl_map); 1829 if (error) { 1830 device_printf(dev, "failed to create %dth " 1831 "tx descriptor dma map!\n", i); 1832 return error; 1833 } 1834 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1835 } 1836 return 0; 1837 } 1838 1839 static void 1840 xl_dma_free(device_t dev) 1841 { 1842 struct xl_softc *sc; 1843 struct xl_chain_data *cd; 1844 struct xl_list_data *ld; 1845 int i; 1846 1847 sc = device_get_softc(dev); 1848 cd = &sc->xl_cdata; 1849 ld = &sc->xl_ldata; 1850 1851 for (i = 0; i < XL_RX_LIST_CNT; ++i) { 1852 if (cd->xl_rx_chain[i].xl_ptr != NULL) { 1853 if (cd->xl_rx_chain[i].xl_mbuf != NULL) { 1854 bus_dmamap_unload(sc->xl_mtag, 1855 cd->xl_rx_chain[i].xl_map); 1856 m_free(cd->xl_rx_chain[i].xl_mbuf); 1857 } 1858 bus_dmamap_destroy(sc->xl_mtag, 1859 cd->xl_rx_chain[i].xl_map); 1860 } 1861 } 1862 1863 for (i = 0; i < XL_TX_LIST_CNT; ++i) { 1864 if (cd->xl_tx_chain[i].xl_ptr != NULL) { 1865 if (cd->xl_tx_chain[i].xl_mbuf != NULL) { 1866 bus_dmamap_unload(sc->xl_mtag, 1867 cd->xl_tx_chain[i].xl_map); 1868 m_free(cd->xl_tx_chain[i].xl_mbuf); 1869 } 1870 bus_dmamap_destroy(sc->xl_mtag, 1871 cd->xl_tx_chain[i].xl_map); 1872 } 1873 } 1874 1875 if (ld->xl_rx_tag) { 1876 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap); 1877 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1878 ld->xl_rx_dmamap); 1879 bus_dma_tag_destroy(ld->xl_rx_tag); 1880 } 1881 1882 if (ld->xl_tx_tag) { 1883 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap); 1884 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1885 ld->xl_tx_dmamap); 1886 bus_dma_tag_destroy(ld->xl_tx_tag); 1887 } 1888 1889 if (sc->xl_mtag) { 1890 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1891 bus_dma_tag_destroy(sc->xl_mtag); 1892 } 1893 } 1894 1895 /* 1896 * Initialize the transmit descriptors. 1897 */ 1898 static void 1899 xl_list_tx_init(struct xl_softc *sc) 1900 { 1901 struct xl_chain_data *cd; 1902 struct xl_list_data *ld; 1903 int i; 1904 1905 cd = &sc->xl_cdata; 1906 ld = &sc->xl_ldata; 1907 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1908 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1909 i * sizeof(struct xl_list); 1910 if (i == (XL_TX_LIST_CNT - 1)) 1911 cd->xl_tx_chain[i].xl_next = NULL; 1912 else 1913 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1914 } 1915 1916 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1917 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1918 1919 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1920 } 1921 1922 /* 1923 * Initialize the transmit descriptors. 1924 */ 1925 static void 1926 xl_list_tx_init_90xB(struct xl_softc *sc) 1927 { 1928 struct xl_chain_data *cd; 1929 struct xl_list_data *ld; 1930 int i; 1931 1932 cd = &sc->xl_cdata; 1933 ld = &sc->xl_ldata; 1934 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1935 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1936 i * sizeof(struct xl_list); 1937 if (i == (XL_TX_LIST_CNT - 1)) 1938 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1939 else 1940 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1941 if (i == 0) { 1942 cd->xl_tx_chain[i].xl_prev = 1943 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1944 } else { 1945 cd->xl_tx_chain[i].xl_prev = 1946 &cd->xl_tx_chain[i - 1]; 1947 } 1948 } 1949 1950 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1951 1952 cd->xl_tx_prod = 1; 1953 cd->xl_tx_cons = 1; 1954 cd->xl_tx_cnt = 0; 1955 1956 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1957 } 1958 1959 /* 1960 * Initialize the RX descriptors and allocate mbufs for them. Note that 1961 * we arrange the descriptors in a closed ring, so that the last descriptor 1962 * points back to the first. 1963 */ 1964 static int 1965 xl_list_rx_init(sc) 1966 struct xl_softc *sc; 1967 { 1968 struct xl_chain_data *cd; 1969 struct xl_list_data *ld; 1970 int error, i, next; 1971 u_int32_t nextptr; 1972 1973 cd = &sc->xl_cdata; 1974 ld = &sc->xl_ldata; 1975 1976 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1977 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1978 if (error) 1979 return(error); 1980 if (i == (XL_RX_LIST_CNT - 1)) 1981 next = 0; 1982 else 1983 next = i + 1; 1984 nextptr = ld->xl_rx_dmaaddr + 1985 next * sizeof(struct xl_list_onefrag); 1986 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1987 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1988 } 1989 1990 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1991 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1992 1993 return(0); 1994 } 1995 1996 /* 1997 * Initialize an RX descriptor and attach an MBUF cluster. 1998 * If we fail to do so, we need to leave the old mbuf and 1999 * the old DMA map untouched so that it can be reused. 2000 */ 2001 static int 2002 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 2003 { 2004 struct mbuf *m_new; 2005 bus_dmamap_t map; 2006 int error; 2007 u_int32_t baddr; 2008 2009 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2010 if (m_new == NULL) 2011 return(ENOBUFS); 2012 2013 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2014 2015 /* Force longword alignment for packet payload. */ 2016 m_adj(m_new, ETHER_ALIGN); 2017 2018 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 2019 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 2020 if (error) { 2021 m_freem(m_new); 2022 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 2023 error); 2024 return(error); 2025 } 2026 2027 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 2028 map = c->xl_map; 2029 c->xl_map = sc->xl_tmpmap; 2030 sc->xl_tmpmap = map; 2031 c->xl_mbuf = m_new; 2032 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 2033 c->xl_ptr->xl_status = 0; 2034 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 2035 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 2036 return(0); 2037 } 2038 2039 static int 2040 xl_rx_resync(sc) 2041 struct xl_softc *sc; 2042 { 2043 struct xl_chain_onefrag *pos; 2044 int i; 2045 2046 pos = sc->xl_cdata.xl_rx_head; 2047 2048 for (i = 0; i < XL_RX_LIST_CNT; i++) { 2049 if (pos->xl_ptr->xl_status) 2050 break; 2051 pos = pos->xl_next; 2052 } 2053 2054 if (i == XL_RX_LIST_CNT) 2055 return(0); 2056 2057 sc->xl_cdata.xl_rx_head = pos; 2058 2059 return(EAGAIN); 2060 } 2061 2062 /* 2063 * A frame has been uploaded: pass the resulting mbuf chain up to 2064 * the higher level protocols. 2065 */ 2066 static void 2067 xl_rxeof(sc) 2068 struct xl_softc *sc; 2069 { 2070 struct mbuf *m; 2071 struct ifnet *ifp; 2072 struct xl_chain_onefrag *cur_rx; 2073 int total_len = 0; 2074 u_int32_t rxstat; 2075 2076 ifp = &sc->arpcom.ac_if; 2077 2078 again: 2079 2080 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2081 BUS_DMASYNC_POSTREAD); 2082 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2083 cur_rx = sc->xl_cdata.xl_rx_head; 2084 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2085 total_len = rxstat & XL_RXSTAT_LENMASK; 2086 2087 /* 2088 * Since we have told the chip to allow large frames, 2089 * we need to trap giant frame errors in software. We allow 2090 * a little more than the normal frame size to account for 2091 * frames with VLAN tags. 2092 */ 2093 if (total_len > XL_MAX_FRAMELEN) 2094 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2095 2096 /* 2097 * If an error occurs, update stats, clear the 2098 * status word and leave the mbuf cluster in place: 2099 * it should simply get re-used next time this descriptor 2100 * comes up in the ring. 2101 */ 2102 if (rxstat & XL_RXSTAT_UP_ERROR) { 2103 ifp->if_ierrors++; 2104 cur_rx->xl_ptr->xl_status = 0; 2105 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2106 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2107 continue; 2108 } 2109 2110 /* 2111 * If the error bit was not set, the upload complete 2112 * bit should be set which means we have a valid packet. 2113 * If not, something truly strange has happened. 2114 */ 2115 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2116 if_printf(ifp, 2117 "bad receive status -- packet dropped\n"); 2118 ifp->if_ierrors++; 2119 cur_rx->xl_ptr->xl_status = 0; 2120 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2121 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2122 continue; 2123 } 2124 2125 /* No errors; receive the packet. */ 2126 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2127 BUS_DMASYNC_POSTREAD); 2128 m = cur_rx->xl_mbuf; 2129 2130 /* 2131 * Try to conjure up a new mbuf cluster. If that 2132 * fails, it means we have an out of memory condition and 2133 * should leave the buffer in place and continue. This will 2134 * result in a lost packet, but there's little else we 2135 * can do in this situation. 2136 */ 2137 if (xl_newbuf(sc, cur_rx)) { 2138 ifp->if_ierrors++; 2139 cur_rx->xl_ptr->xl_status = 0; 2140 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2141 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2142 continue; 2143 } 2144 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2145 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2146 2147 ifp->if_ipackets++; 2148 m->m_pkthdr.rcvif = ifp; 2149 m->m_pkthdr.len = m->m_len = total_len; 2150 2151 if (ifp->if_capenable & IFCAP_RXCSUM) { 2152 /* Do IP checksum checking. */ 2153 if (rxstat & XL_RXSTAT_IPCKOK) 2154 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2155 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2156 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2157 if ((rxstat & XL_RXSTAT_TCPCOK && 2158 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2159 (rxstat & XL_RXSTAT_UDPCKOK && 2160 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2161 m->m_pkthdr.csum_flags |= 2162 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2163 m->m_pkthdr.csum_data = 0xffff; 2164 } 2165 } 2166 2167 (*ifp->if_input)(ifp, m); 2168 } 2169 2170 if (sc->xl_type != XL_TYPE_905B) { 2171 /* 2172 * Handle the 'end of channel' condition. When the upload 2173 * engine hits the end of the RX ring, it will stall. This 2174 * is our cue to flush the RX ring, reload the uplist pointer 2175 * register and unstall the engine. 2176 * XXX This is actually a little goofy. With the ThunderLAN 2177 * chip, you get an interrupt when the receiver hits the end 2178 * of the receive ring, which tells you exactly when you 2179 * you need to reload the ring pointer. Here we have to 2180 * fake it. I'm mad at myself for not being clever enough 2181 * to avoid the use of a goto here. 2182 */ 2183 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2184 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2185 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2186 xl_wait(sc); 2187 CSR_WRITE_4(sc, XL_UPLIST_PTR, 2188 sc->xl_ldata.xl_rx_dmaaddr); 2189 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2190 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2191 goto again; 2192 } 2193 } 2194 } 2195 2196 /* 2197 * A frame was downloaded to the chip. It's safe for us to clean up 2198 * the list buffers. 2199 */ 2200 static void 2201 xl_txeof(sc) 2202 struct xl_softc *sc; 2203 { 2204 struct xl_chain *cur_tx; 2205 struct ifnet *ifp; 2206 2207 ifp = &sc->arpcom.ac_if; 2208 2209 /* Clear the timeout timer. */ 2210 ifp->if_timer = 0; 2211 2212 /* 2213 * Go through our tx list and free mbufs for those 2214 * frames that have been uploaded. Note: the 3c905B 2215 * sets a special bit in the status word to let us 2216 * know that a frame has been downloaded, but the 2217 * original 3c900/3c905 adapters don't do that. 2218 * Consequently, we have to use a different test if 2219 * xl_type != XL_TYPE_905B. 2220 */ 2221 while(sc->xl_cdata.xl_tx_head != NULL) { 2222 cur_tx = sc->xl_cdata.xl_tx_head; 2223 2224 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2225 break; 2226 2227 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2228 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2229 BUS_DMASYNC_POSTWRITE); 2230 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2231 m_freem(cur_tx->xl_mbuf); 2232 cur_tx->xl_mbuf = NULL; 2233 ifp->if_opackets++; 2234 2235 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2236 sc->xl_cdata.xl_tx_free = cur_tx; 2237 } 2238 2239 if (sc->xl_cdata.xl_tx_head == NULL) { 2240 ifp->if_flags &= ~IFF_OACTIVE; 2241 sc->xl_cdata.xl_tx_tail = NULL; 2242 } else { 2243 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2244 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2245 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2246 sc->xl_cdata.xl_tx_head->xl_phys); 2247 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2248 } 2249 } 2250 2251 return; 2252 } 2253 2254 static void 2255 xl_txeof_90xB(sc) 2256 struct xl_softc *sc; 2257 { 2258 struct xl_chain *cur_tx = NULL; 2259 struct ifnet *ifp; 2260 int idx; 2261 2262 ifp = &sc->arpcom.ac_if; 2263 2264 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2265 BUS_DMASYNC_POSTREAD); 2266 idx = sc->xl_cdata.xl_tx_cons; 2267 while(idx != sc->xl_cdata.xl_tx_prod) { 2268 2269 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2270 2271 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2272 XL_TXSTAT_DL_COMPLETE)) 2273 break; 2274 2275 if (cur_tx->xl_mbuf != NULL) { 2276 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2277 BUS_DMASYNC_POSTWRITE); 2278 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2279 m_freem(cur_tx->xl_mbuf); 2280 cur_tx->xl_mbuf = NULL; 2281 } 2282 2283 ifp->if_opackets++; 2284 2285 sc->xl_cdata.xl_tx_cnt--; 2286 XL_INC(idx, XL_TX_LIST_CNT); 2287 ifp->if_timer = 0; 2288 } 2289 2290 sc->xl_cdata.xl_tx_cons = idx; 2291 2292 if (cur_tx != NULL) 2293 ifp->if_flags &= ~IFF_OACTIVE; 2294 2295 return; 2296 } 2297 2298 /* 2299 * TX 'end of channel' interrupt handler. Actually, we should 2300 * only get a 'TX complete' interrupt if there's a transmit error, 2301 * so this is really TX error handler. 2302 */ 2303 static void 2304 xl_txeoc(sc) 2305 struct xl_softc *sc; 2306 { 2307 struct ifnet *ifp = &sc->arpcom.ac_if; 2308 u_int8_t txstat; 2309 2310 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2311 if (txstat & XL_TXSTATUS_UNDERRUN || 2312 txstat & XL_TXSTATUS_JABBER || 2313 txstat & XL_TXSTATUS_RECLAIM) { 2314 if_printf(ifp, "transmission error: %x\n", txstat); 2315 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2316 xl_wait(sc); 2317 if (sc->xl_type == XL_TYPE_905B) { 2318 if (sc->xl_cdata.xl_tx_cnt) { 2319 int i; 2320 struct xl_chain *c; 2321 i = sc->xl_cdata.xl_tx_cons; 2322 c = &sc->xl_cdata.xl_tx_chain[i]; 2323 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2324 c->xl_phys); 2325 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2326 } 2327 } else { 2328 if (sc->xl_cdata.xl_tx_head != NULL) 2329 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2330 sc->xl_cdata.xl_tx_head->xl_phys); 2331 } 2332 /* 2333 * Remember to set this for the 2334 * first generation 3c90X chips. 2335 */ 2336 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2337 if (txstat & XL_TXSTATUS_UNDERRUN && 2338 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2339 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2340 if_printf(ifp, "tx underrun, increasing tx start" 2341 " threshold to %d bytes\n", 2342 sc->xl_tx_thresh); 2343 } 2344 CSR_WRITE_2(sc, XL_COMMAND, 2345 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2346 if (sc->xl_type == XL_TYPE_905B) { 2347 CSR_WRITE_2(sc, XL_COMMAND, 2348 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2349 } 2350 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2351 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2352 } else { 2353 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2354 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2355 } 2356 /* 2357 * Write an arbitrary byte to the TX_STATUS register 2358 * to clear this interrupt/error and advance to the next. 2359 */ 2360 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2361 } 2362 2363 return; 2364 } 2365 2366 static void 2367 xl_intr(arg) 2368 void *arg; 2369 { 2370 struct xl_softc *sc; 2371 struct ifnet *ifp; 2372 u_int16_t status; 2373 2374 sc = arg; 2375 ifp = &sc->arpcom.ac_if; 2376 2377 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2378 2379 CSR_WRITE_2(sc, XL_COMMAND, 2380 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2381 2382 if (status & XL_STAT_UP_COMPLETE) { 2383 int curpkts; 2384 2385 curpkts = ifp->if_ipackets; 2386 xl_rxeof(sc); 2387 if (curpkts == ifp->if_ipackets) { 2388 while (xl_rx_resync(sc)) 2389 xl_rxeof(sc); 2390 } 2391 } 2392 2393 if (status & XL_STAT_DOWN_COMPLETE) { 2394 if (sc->xl_type == XL_TYPE_905B) 2395 xl_txeof_90xB(sc); 2396 else 2397 xl_txeof(sc); 2398 } 2399 2400 if (status & XL_STAT_TX_COMPLETE) { 2401 ifp->if_oerrors++; 2402 xl_txeoc(sc); 2403 } 2404 2405 if (status & XL_STAT_ADFAIL) { 2406 xl_reset(sc); 2407 xl_init(sc); 2408 } 2409 2410 if (status & XL_STAT_STATSOFLOW) { 2411 sc->xl_stats_no_timeout = 1; 2412 xl_stats_update(sc); 2413 sc->xl_stats_no_timeout = 0; 2414 } 2415 } 2416 2417 if (!ifq_is_empty(&ifp->if_snd)) 2418 (*ifp->if_start)(ifp); 2419 2420 return; 2421 } 2422 2423 static void 2424 xl_stats_update(xsc) 2425 void *xsc; 2426 { 2427 struct xl_softc *sc; 2428 struct ifnet *ifp; 2429 struct xl_stats xl_stats; 2430 u_int8_t *p; 2431 int i; 2432 struct mii_data *mii = NULL; 2433 2434 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2435 2436 sc = xsc; 2437 ifp = &sc->arpcom.ac_if; 2438 if (sc->xl_miibus != NULL) 2439 mii = device_get_softc(sc->xl_miibus); 2440 2441 p = (u_int8_t *)&xl_stats; 2442 2443 /* Read all the stats registers. */ 2444 XL_SEL_WIN(6); 2445 2446 for (i = 0; i < 16; i++) 2447 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2448 2449 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2450 2451 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2452 xl_stats.xl_tx_single_collision + 2453 xl_stats.xl_tx_late_collision; 2454 2455 /* 2456 * Boomerang and cyclone chips have an extra stats counter 2457 * in window 4 (BadSSD). We have to read this too in order 2458 * to clear out all the stats registers and avoid a statsoflow 2459 * interrupt. 2460 */ 2461 XL_SEL_WIN(4); 2462 CSR_READ_1(sc, XL_W4_BADSSD); 2463 2464 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2465 mii_tick(mii); 2466 2467 XL_SEL_WIN(7); 2468 2469 if (!sc->xl_stats_no_timeout) 2470 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2471 2472 return; 2473 } 2474 2475 /* 2476 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2477 * pointers to the fragment pointers. 2478 */ 2479 static int 2480 xl_encap(sc, c, m_head) 2481 struct xl_softc *sc; 2482 struct xl_chain *c; 2483 struct mbuf *m_head; 2484 { 2485 int error; 2486 u_int32_t status; 2487 struct ifnet *ifp; 2488 2489 ifp = &sc->arpcom.ac_if; 2490 2491 /* 2492 * Start packing the mbufs in this chain into 2493 * the fragment pointers. Stop when we run out 2494 * of fragments or hit the end of the mbuf chain. 2495 */ 2496 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2497 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2498 2499 if (error && error != EFBIG) { 2500 m_freem(m_head); 2501 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2502 return(1); 2503 } 2504 2505 /* 2506 * Handle special case: we used up all 63 fragments, 2507 * but we have more mbufs left in the chain. Copy the 2508 * data into an mbuf cluster. Note that we don't 2509 * bother clearing the values in the other fragment 2510 * pointers/counters; it wouldn't gain us anything, 2511 * and would waste cycles. 2512 */ 2513 if (error) { 2514 struct mbuf *m_new; 2515 2516 m_new = m_defrag(m_head, MB_DONTWAIT); 2517 if (m_new == NULL) { 2518 m_freem(m_head); 2519 return(1); 2520 } else { 2521 m_head = m_new; 2522 } 2523 2524 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2525 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2526 if (error) { 2527 m_freem(m_head); 2528 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2529 return(1); 2530 } 2531 } 2532 2533 if (sc->xl_type == XL_TYPE_905B) { 2534 status = XL_TXSTAT_RND_DEFEAT; 2535 2536 if (m_head->m_pkthdr.csum_flags) { 2537 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2538 status |= XL_TXSTAT_IPCKSUM; 2539 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2540 status |= XL_TXSTAT_TCPCKSUM; 2541 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2542 status |= XL_TXSTAT_UDPCKSUM; 2543 } 2544 c->xl_ptr->xl_status = htole32(status); 2545 } 2546 2547 c->xl_mbuf = m_head; 2548 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2549 return(0); 2550 } 2551 2552 /* 2553 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2554 * to the mbuf data regions directly in the transmit lists. We also save a 2555 * copy of the pointers since the transmit list fragment pointers are 2556 * physical addresses. 2557 */ 2558 static void 2559 xl_start(ifp) 2560 struct ifnet *ifp; 2561 { 2562 struct xl_softc *sc; 2563 struct mbuf *m_head = NULL; 2564 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2565 struct xl_chain *prev_tx; 2566 u_int32_t status; 2567 int error; 2568 2569 sc = ifp->if_softc; 2570 /* 2571 * Check for an available queue slot. If there are none, 2572 * punt. 2573 */ 2574 if (sc->xl_cdata.xl_tx_free == NULL) { 2575 xl_txeoc(sc); 2576 xl_txeof(sc); 2577 if (sc->xl_cdata.xl_tx_free == NULL) { 2578 ifp->if_flags |= IFF_OACTIVE; 2579 return; 2580 } 2581 } 2582 2583 start_tx = sc->xl_cdata.xl_tx_free; 2584 2585 while(sc->xl_cdata.xl_tx_free != NULL) { 2586 m_head = ifq_dequeue(&ifp->if_snd); 2587 if (m_head == NULL) 2588 break; 2589 2590 /* Pick a descriptor off the free list. */ 2591 prev_tx = cur_tx; 2592 cur_tx = sc->xl_cdata.xl_tx_free; 2593 2594 /* Pack the data into the descriptor. */ 2595 error = xl_encap(sc, cur_tx, m_head); 2596 if (error) { 2597 cur_tx = prev_tx; 2598 continue; 2599 } 2600 2601 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2602 cur_tx->xl_next = NULL; 2603 2604 /* Chain it together. */ 2605 if (prev != NULL) { 2606 prev->xl_next = cur_tx; 2607 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2608 } 2609 prev = cur_tx; 2610 2611 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2612 } 2613 2614 /* 2615 * If there are no packets queued, bail. 2616 */ 2617 if (cur_tx == NULL) { 2618 return; 2619 } 2620 2621 /* 2622 * Place the request for the upload interrupt 2623 * in the last descriptor in the chain. This way, if 2624 * we're chaining several packets at once, we'll only 2625 * get an interupt once for the whole chain rather than 2626 * once for each packet. 2627 */ 2628 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2629 XL_TXSTAT_DL_INTR); 2630 2631 /* 2632 * Queue the packets. If the TX channel is clear, update 2633 * the downlist pointer register. 2634 */ 2635 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2636 xl_wait(sc); 2637 2638 if (sc->xl_cdata.xl_tx_head != NULL) { 2639 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2640 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2641 htole32(start_tx->xl_phys); 2642 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2643 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2644 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2645 sc->xl_cdata.xl_tx_tail = cur_tx; 2646 } else { 2647 sc->xl_cdata.xl_tx_head = start_tx; 2648 sc->xl_cdata.xl_tx_tail = cur_tx; 2649 } 2650 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2651 BUS_DMASYNC_PREWRITE); 2652 2653 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2654 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2655 2656 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2657 2658 XL_SEL_WIN(7); 2659 2660 /* 2661 * Set a timeout in case the chip goes out to lunch. 2662 */ 2663 ifp->if_timer = 5; 2664 2665 /* 2666 * XXX Under certain conditions, usually on slower machines 2667 * where interrupts may be dropped, it's possible for the 2668 * adapter to chew up all the buffers in the receive ring 2669 * and stall, without us being able to do anything about it. 2670 * To guard against this, we need to make a pass over the 2671 * RX queue to make sure there aren't any packets pending. 2672 * Doing it here means we can flush the receive ring at the 2673 * same time the chip is DMAing the transmit descriptors we 2674 * just gave it. 2675 * 2676 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2677 * nature of their chips in all their marketing literature; 2678 * we may as well take advantage of it. :) 2679 */ 2680 xl_rxeof(sc); 2681 } 2682 2683 static void 2684 xl_start_90xB(ifp) 2685 struct ifnet *ifp; 2686 { 2687 struct xl_softc *sc; 2688 struct mbuf *m_head = NULL; 2689 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2690 struct xl_chain *prev_tx; 2691 int error, idx; 2692 2693 sc = ifp->if_softc; 2694 2695 if (ifp->if_flags & IFF_OACTIVE) { 2696 return; 2697 } 2698 2699 idx = sc->xl_cdata.xl_tx_prod; 2700 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2701 2702 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2703 2704 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2705 ifp->if_flags |= IFF_OACTIVE; 2706 break; 2707 } 2708 2709 m_head = ifq_dequeue(&ifp->if_snd); 2710 if (m_head == NULL) 2711 break; 2712 2713 prev_tx = cur_tx; 2714 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2715 2716 /* Pack the data into the descriptor. */ 2717 error = xl_encap(sc, cur_tx, m_head); 2718 if (error) { 2719 cur_tx = prev_tx; 2720 continue; 2721 } 2722 2723 /* Chain it together. */ 2724 if (prev != NULL) 2725 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2726 prev = cur_tx; 2727 2728 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2729 2730 XL_INC(idx, XL_TX_LIST_CNT); 2731 sc->xl_cdata.xl_tx_cnt++; 2732 } 2733 2734 /* 2735 * If there are no packets queued, bail. 2736 */ 2737 if (cur_tx == NULL) { 2738 return; 2739 } 2740 2741 /* 2742 * Place the request for the upload interrupt 2743 * in the last descriptor in the chain. This way, if 2744 * we're chaining several packets at once, we'll only 2745 * get an interupt once for the whole chain rather than 2746 * once for each packet. 2747 */ 2748 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2749 XL_TXSTAT_DL_INTR); 2750 2751 /* Start transmission */ 2752 sc->xl_cdata.xl_tx_prod = idx; 2753 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2754 2755 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2756 BUS_DMASYNC_PREWRITE); 2757 2758 /* 2759 * Set a timeout in case the chip goes out to lunch. 2760 */ 2761 ifp->if_timer = 5; 2762 } 2763 2764 static void 2765 xl_init(xsc) 2766 void *xsc; 2767 { 2768 struct xl_softc *sc = xsc; 2769 struct ifnet *ifp = &sc->arpcom.ac_if; 2770 int error, i; 2771 u_int16_t rxfilt = 0; 2772 struct mii_data *mii = NULL; 2773 2774 crit_enter(); 2775 2776 /* 2777 * Cancel pending I/O and free all RX/TX buffers. 2778 */ 2779 xl_stop(sc); 2780 2781 if (sc->xl_miibus == NULL) { 2782 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2783 xl_wait(sc); 2784 } 2785 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2786 xl_wait(sc); 2787 DELAY(10000); 2788 2789 if (sc->xl_miibus != NULL) 2790 mii = device_get_softc(sc->xl_miibus); 2791 2792 /* Init our MAC address */ 2793 XL_SEL_WIN(2); 2794 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2795 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2796 sc->arpcom.ac_enaddr[i]); 2797 } 2798 2799 /* Clear the station mask. */ 2800 for (i = 0; i < 3; i++) 2801 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2802 #ifdef notdef 2803 /* Reset TX and RX. */ 2804 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2805 xl_wait(sc); 2806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2807 xl_wait(sc); 2808 #endif 2809 /* Init circular RX list. */ 2810 error = xl_list_rx_init(sc); 2811 if (error) { 2812 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2813 error); 2814 xl_stop(sc); 2815 crit_exit(); 2816 return; 2817 } 2818 2819 /* Init TX descriptors. */ 2820 if (sc->xl_type == XL_TYPE_905B) 2821 xl_list_tx_init_90xB(sc); 2822 else 2823 xl_list_tx_init(sc); 2824 2825 /* 2826 * Set the TX freethresh value. 2827 * Note that this has no effect on 3c905B "cyclone" 2828 * cards but is required for 3c900/3c905 "boomerang" 2829 * cards in order to enable the download engine. 2830 */ 2831 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2832 2833 /* Set the TX start threshold for best performance. */ 2834 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2835 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2836 2837 /* 2838 * If this is a 3c905B, also set the tx reclaim threshold. 2839 * This helps cut down on the number of tx reclaim errors 2840 * that could happen on a busy network. The chip multiplies 2841 * the register value by 16 to obtain the actual threshold 2842 * in bytes, so we divide by 16 when setting the value here. 2843 * The existing threshold value can be examined by reading 2844 * the register at offset 9 in window 5. 2845 */ 2846 if (sc->xl_type == XL_TYPE_905B) { 2847 CSR_WRITE_2(sc, XL_COMMAND, 2848 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2849 } 2850 2851 /* Set RX filter bits. */ 2852 XL_SEL_WIN(5); 2853 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2854 2855 /* Set the individual bit to receive frames for this host only. */ 2856 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2857 2858 /* If we want promiscuous mode, set the allframes bit. */ 2859 if (ifp->if_flags & IFF_PROMISC) { 2860 rxfilt |= XL_RXFILTER_ALLFRAMES; 2861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2862 } else { 2863 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2865 } 2866 2867 /* 2868 * Set capture broadcast bit to capture broadcast frames. 2869 */ 2870 if (ifp->if_flags & IFF_BROADCAST) { 2871 rxfilt |= XL_RXFILTER_BROADCAST; 2872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2873 } else { 2874 rxfilt &= ~XL_RXFILTER_BROADCAST; 2875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2876 } 2877 2878 /* 2879 * Program the multicast filter, if necessary. 2880 */ 2881 if (sc->xl_type == XL_TYPE_905B) 2882 xl_setmulti_hash(sc); 2883 else 2884 xl_setmulti(sc); 2885 2886 if (sc->xl_type == XL_TYPE_905B) { 2887 /* Set UP polling interval */ 2888 CSR_WRITE_1(sc, XL_UP_POLL, 64); 2889 } 2890 2891 /* 2892 * Load the address of the RX list. We have to 2893 * stall the upload engine before we can manipulate 2894 * the uplist pointer register, then unstall it when 2895 * we're finished. We also have to wait for the 2896 * stall command to complete before proceeding. 2897 * Note that we have to do this after any RX resets 2898 * have completed since the uplist register is cleared 2899 * by a reset. 2900 */ 2901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2902 xl_wait(sc); 2903 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2905 xl_wait(sc); 2906 2907 2908 if (sc->xl_type == XL_TYPE_905B) { 2909 /* Set DN polling interval */ 2910 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2911 2912 /* Load the address of the TX list */ 2913 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2914 xl_wait(sc); 2915 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2916 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2917 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2918 xl_wait(sc); 2919 } 2920 2921 /* 2922 * If the coax transceiver is on, make sure to enable 2923 * the DC-DC converter. 2924 */ 2925 XL_SEL_WIN(3); 2926 if (sc->xl_xcvr == XL_XCVR_COAX) 2927 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2928 else 2929 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2930 2931 /* 2932 * increase packet size to allow reception of 802.1q or ISL packets. 2933 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2934 * control register. For 3c90xB/C chips, use the RX packet size 2935 * register. 2936 */ 2937 2938 if (sc->xl_type == XL_TYPE_905B) 2939 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2940 else { 2941 u_int8_t macctl; 2942 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2943 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2944 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2945 } 2946 2947 /* Clear out the stats counters. */ 2948 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2949 sc->xl_stats_no_timeout = 1; 2950 xl_stats_update(sc); 2951 sc->xl_stats_no_timeout = 0; 2952 XL_SEL_WIN(4); 2953 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2954 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2955 2956 /* 2957 * Enable interrupts. 2958 */ 2959 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2962 if (sc->xl_flags & XL_FLAG_FUNCREG) 2963 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2964 2965 /* Set the RX early threshold */ 2966 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2967 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2968 2969 /* Enable receiver and transmitter. */ 2970 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2971 xl_wait(sc); 2972 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2973 xl_wait(sc); 2974 2975 if (mii != NULL) 2976 mii_mediachg(mii); 2977 2978 /* Select window 7 for normal operations. */ 2979 XL_SEL_WIN(7); 2980 2981 ifp->if_flags |= IFF_RUNNING; 2982 ifp->if_flags &= ~IFF_OACTIVE; 2983 2984 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2985 2986 crit_exit(); 2987 } 2988 2989 /* 2990 * Set media options. 2991 */ 2992 static int 2993 xl_ifmedia_upd(ifp) 2994 struct ifnet *ifp; 2995 { 2996 struct xl_softc *sc; 2997 struct ifmedia *ifm = NULL; 2998 struct mii_data *mii = NULL; 2999 3000 sc = ifp->if_softc; 3001 if (sc->xl_miibus != NULL) 3002 mii = device_get_softc(sc->xl_miibus); 3003 if (mii == NULL) 3004 ifm = &sc->ifmedia; 3005 else 3006 ifm = &mii->mii_media; 3007 3008 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3009 case IFM_100_FX: 3010 case IFM_10_FL: 3011 case IFM_10_2: 3012 case IFM_10_5: 3013 xl_setmode(sc, ifm->ifm_media); 3014 return(0); 3015 break; 3016 default: 3017 break; 3018 } 3019 3020 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 3021 || sc->xl_media & XL_MEDIAOPT_BT4) { 3022 xl_init(sc); 3023 } else { 3024 xl_setmode(sc, ifm->ifm_media); 3025 } 3026 3027 return(0); 3028 } 3029 3030 /* 3031 * Report current media status. 3032 */ 3033 static void 3034 xl_ifmedia_sts(ifp, ifmr) 3035 struct ifnet *ifp; 3036 struct ifmediareq *ifmr; 3037 { 3038 struct xl_softc *sc; 3039 u_int32_t icfg; 3040 struct mii_data *mii = NULL; 3041 3042 sc = ifp->if_softc; 3043 if (sc->xl_miibus != NULL) 3044 mii = device_get_softc(sc->xl_miibus); 3045 3046 XL_SEL_WIN(3); 3047 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3048 icfg >>= XL_ICFG_CONNECTOR_BITS; 3049 3050 ifmr->ifm_active = IFM_ETHER; 3051 3052 switch(icfg) { 3053 case XL_XCVR_10BT: 3054 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3055 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3056 ifmr->ifm_active |= IFM_FDX; 3057 else 3058 ifmr->ifm_active |= IFM_HDX; 3059 break; 3060 case XL_XCVR_AUI: 3061 if (sc->xl_type == XL_TYPE_905B && 3062 sc->xl_media == XL_MEDIAOPT_10FL) { 3063 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3064 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3065 ifmr->ifm_active |= IFM_FDX; 3066 else 3067 ifmr->ifm_active |= IFM_HDX; 3068 } else 3069 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3070 break; 3071 case XL_XCVR_COAX: 3072 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3073 break; 3074 /* 3075 * XXX MII and BTX/AUTO should be separate cases. 3076 */ 3077 3078 case XL_XCVR_100BTX: 3079 case XL_XCVR_AUTO: 3080 case XL_XCVR_MII: 3081 if (mii != NULL) { 3082 mii_pollstat(mii); 3083 ifmr->ifm_active = mii->mii_media_active; 3084 ifmr->ifm_status = mii->mii_media_status; 3085 } 3086 break; 3087 case XL_XCVR_100BFX: 3088 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3089 break; 3090 default: 3091 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3092 break; 3093 } 3094 3095 return; 3096 } 3097 3098 static int 3099 xl_ioctl(ifp, command, data, cr) 3100 struct ifnet *ifp; 3101 u_long command; 3102 caddr_t data; 3103 struct ucred *cr; 3104 { 3105 struct xl_softc *sc = ifp->if_softc; 3106 struct ifreq *ifr = (struct ifreq *) data; 3107 int error = 0; 3108 struct mii_data *mii = NULL; 3109 u_int8_t rxfilt; 3110 3111 crit_enter(); 3112 3113 switch(command) { 3114 case SIOCSIFFLAGS: 3115 XL_SEL_WIN(5); 3116 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3117 if (ifp->if_flags & IFF_UP) { 3118 if (ifp->if_flags & IFF_RUNNING && 3119 ifp->if_flags & IFF_PROMISC && 3120 !(sc->xl_if_flags & IFF_PROMISC)) { 3121 rxfilt |= XL_RXFILTER_ALLFRAMES; 3122 CSR_WRITE_2(sc, XL_COMMAND, 3123 XL_CMD_RX_SET_FILT|rxfilt); 3124 XL_SEL_WIN(7); 3125 } else if (ifp->if_flags & IFF_RUNNING && 3126 !(ifp->if_flags & IFF_PROMISC) && 3127 sc->xl_if_flags & IFF_PROMISC) { 3128 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3129 CSR_WRITE_2(sc, XL_COMMAND, 3130 XL_CMD_RX_SET_FILT|rxfilt); 3131 XL_SEL_WIN(7); 3132 } else 3133 xl_init(sc); 3134 } else { 3135 if (ifp->if_flags & IFF_RUNNING) 3136 xl_stop(sc); 3137 } 3138 sc->xl_if_flags = ifp->if_flags; 3139 error = 0; 3140 break; 3141 case SIOCADDMULTI: 3142 case SIOCDELMULTI: 3143 if (sc->xl_type == XL_TYPE_905B) 3144 xl_setmulti_hash(sc); 3145 else 3146 xl_setmulti(sc); 3147 error = 0; 3148 break; 3149 case SIOCGIFMEDIA: 3150 case SIOCSIFMEDIA: 3151 if (sc->xl_miibus != NULL) 3152 mii = device_get_softc(sc->xl_miibus); 3153 if (mii == NULL) 3154 error = ifmedia_ioctl(ifp, ifr, 3155 &sc->ifmedia, command); 3156 else 3157 error = ifmedia_ioctl(ifp, ifr, 3158 &mii->mii_media, command); 3159 break; 3160 case SIOCSIFCAP: 3161 ifp->if_capenable = ifr->ifr_reqcap; 3162 if (ifp->if_capenable & IFCAP_TXCSUM) 3163 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3164 else 3165 ifp->if_hwassist = 0; 3166 break; 3167 default: 3168 error = ether_ioctl(ifp, command, data); 3169 break; 3170 } 3171 3172 crit_exit(); 3173 3174 return(error); 3175 } 3176 3177 static void 3178 xl_watchdog(ifp) 3179 struct ifnet *ifp; 3180 { 3181 struct xl_softc *sc; 3182 u_int16_t status = 0; 3183 3184 sc = ifp->if_softc; 3185 3186 ifp->if_oerrors++; 3187 XL_SEL_WIN(4); 3188 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3189 if_printf(ifp, "watchdog timeout\n"); 3190 3191 if (status & XL_MEDIASTAT_CARRIER) 3192 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3193 xl_txeoc(sc); 3194 xl_txeof(sc); 3195 xl_rxeof(sc); 3196 xl_reset(sc); 3197 xl_init(sc); 3198 3199 if (!ifq_is_empty(&ifp->if_snd)) 3200 (*ifp->if_start)(ifp); 3201 } 3202 3203 /* 3204 * Stop the adapter and free any mbufs allocated to the 3205 * RX and TX lists. 3206 */ 3207 static void 3208 xl_stop(sc) 3209 struct xl_softc *sc; 3210 { 3211 int i; 3212 struct ifnet *ifp; 3213 3214 ifp = &sc->arpcom.ac_if; 3215 ifp->if_timer = 0; 3216 3217 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3218 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3219 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3220 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3221 xl_wait(sc); 3222 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3223 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3224 DELAY(800); 3225 3226 #ifdef foo 3227 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3228 xl_wait(sc); 3229 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3230 xl_wait(sc); 3231 #endif 3232 3233 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3234 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3235 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3236 if (sc->xl_flags & XL_FLAG_FUNCREG) 3237 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3238 3239 /* Stop the stats updater. */ 3240 callout_stop(&sc->xl_stat_timer); 3241 3242 /* 3243 * Free data in the RX lists. 3244 */ 3245 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3246 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3247 bus_dmamap_unload(sc->xl_mtag, 3248 sc->xl_cdata.xl_rx_chain[i].xl_map); 3249 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3250 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3251 } 3252 } 3253 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3254 3255 /* 3256 * Free the TX list buffers. 3257 */ 3258 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3259 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3260 bus_dmamap_unload(sc->xl_mtag, 3261 sc->xl_cdata.xl_tx_chain[i].xl_map); 3262 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3263 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3264 } 3265 } 3266 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3267 3268 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3269 } 3270 3271 /* 3272 * Stop all chip I/O so that the kernel's probe routines don't 3273 * get confused by errant DMAs when rebooting. 3274 */ 3275 static void 3276 xl_shutdown(dev) 3277 device_t dev; 3278 { 3279 struct xl_softc *sc; 3280 3281 sc = device_get_softc(dev); 3282 3283 xl_reset(sc); 3284 xl_stop(sc); 3285 3286 return; 3287 } 3288 3289 static int 3290 xl_suspend(dev) 3291 device_t dev; 3292 { 3293 struct xl_softc *sc = device_get_softc(dev); 3294 3295 crit_enter(); 3296 3297 xl_stop(sc); 3298 3299 crit_exit(); 3300 3301 return(0); 3302 } 3303 3304 static int 3305 xl_resume(dev) 3306 device_t dev; 3307 { 3308 struct xl_softc *sc; 3309 struct ifnet *ifp; 3310 3311 sc = device_get_softc(dev); 3312 ifp = &sc->arpcom.ac_if; 3313 3314 crit_enter(); 3315 3316 xl_reset(sc); 3317 if (ifp->if_flags & IFF_UP) 3318 xl_init(sc); 3319 3320 crit_exit(); 3321 3322 return(0); 3323 } 3324