1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.27 2005/06/20 15:10:41 joerg Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 */ 101 102 #include <sys/param.h> 103 #include <sys/systm.h> 104 #include <sys/sockio.h> 105 #include <sys/endian.h> 106 #include <sys/mbuf.h> 107 #include <sys/kernel.h> 108 #include <sys/socket.h> 109 #include <sys/thread2.h> 110 111 #include <net/if.h> 112 #include <net/ifq_var.h> 113 #include <net/if_arp.h> 114 #include <net/ethernet.h> 115 #include <net/if_dl.h> 116 #include <net/if_media.h> 117 #include <net/vlan/if_vlan_var.h> 118 119 #include <net/bpf.h> 120 121 #include <machine/bus_memio.h> 122 #include <machine/bus_pio.h> 123 #include <machine/bus.h> 124 #include <machine/clock.h> /* for DELAY */ 125 #include <machine/resource.h> 126 #include <sys/bus.h> 127 #include <sys/rman.h> 128 129 #include "../mii_layer/mii.h" 130 #include "../mii_layer/miivar.h" 131 132 #include <bus/pci/pcireg.h> 133 #include <bus/pci/pcivar.h> 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 #include "if_xlreg.h" 139 140 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 141 142 /* 143 * Various supported device vendors/types and their names. 144 */ 145 static struct xl_type xl_devs[] = { 146 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 147 "3Com 3c900-TPO Etherlink XL" }, 148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 149 "3Com 3c900-COMBO Etherlink XL" }, 150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 151 "3Com 3c905-TX Fast Etherlink XL" }, 152 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 153 "3Com 3c905-T4 Fast Etherlink XL" }, 154 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 155 "3Com 3c900B-TPO Etherlink XL" }, 156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 157 "3Com 3c900B-COMBO Etherlink XL" }, 158 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 159 "3Com 3c900B-TPC Etherlink XL" }, 160 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 161 "3Com 3c900B-FL Etherlink XL" }, 162 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 163 "3Com 3c905B-TX Fast Etherlink XL" }, 164 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 165 "3Com 3c905B-T4 Fast Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 167 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 169 "3Com 3c905B-COMBO Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 171 "3Com 3c905C-TX Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 173 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 175 "3Com 3c980 Fast Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 177 "3Com 3c980C Fast Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 179 "3Com 3cSOHO100-TX OfficeConnect" }, 180 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 181 "3Com 3c450-TX HomeConnect" }, 182 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 183 "3Com 3c555 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 185 "3Com 3c556 Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 187 "3Com 3c556B Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 189 "3Com 3c575TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 191 "3Com 3c575B Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 193 "3Com 3c575C Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 195 "3Com 3c656 Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 197 "3Com 3c656B Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 199 "3Com 3c656C Fast Etherlink XL" }, 200 { 0, 0, NULL } 201 }; 202 203 static int xl_probe (device_t); 204 static int xl_attach (device_t); 205 static int xl_detach (device_t); 206 207 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 208 static void xl_stats_update (void *); 209 static int xl_encap (struct xl_softc *, struct xl_chain *, 210 struct mbuf *); 211 static void xl_rxeof (struct xl_softc *); 212 static int xl_rx_resync (struct xl_softc *); 213 static void xl_txeof (struct xl_softc *); 214 static void xl_txeof_90xB (struct xl_softc *); 215 static void xl_txeoc (struct xl_softc *); 216 static void xl_intr (void *); 217 static void xl_start (struct ifnet *); 218 static void xl_start_90xB (struct ifnet *); 219 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 220 struct ucred *); 221 static void xl_init (void *); 222 static void xl_stop (struct xl_softc *); 223 static void xl_watchdog (struct ifnet *); 224 static void xl_shutdown (device_t); 225 static int xl_suspend (device_t); 226 static int xl_resume (device_t); 227 228 static int xl_ifmedia_upd (struct ifnet *); 229 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 230 231 static int xl_eeprom_wait (struct xl_softc *); 232 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 233 static void xl_mii_sync (struct xl_softc *); 234 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 235 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 236 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 237 238 static void xl_setcfg (struct xl_softc *); 239 static void xl_setmode (struct xl_softc *, int); 240 static u_int8_t xl_calchash (caddr_t); 241 static void xl_setmulti (struct xl_softc *); 242 static void xl_setmulti_hash (struct xl_softc *); 243 static void xl_reset (struct xl_softc *); 244 static int xl_list_rx_init (struct xl_softc *); 245 static int xl_list_tx_init (struct xl_softc *); 246 static int xl_list_tx_init_90xB (struct xl_softc *); 247 static void xl_wait (struct xl_softc *); 248 static void xl_mediacheck (struct xl_softc *); 249 static void xl_choose_xcvr (struct xl_softc *, int); 250 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 251 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 252 int); 253 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 254 int); 255 #ifdef notdef 256 static void xl_testpacket (struct xl_softc *); 257 #endif 258 259 static int xl_miibus_readreg (device_t, int, int); 260 static int xl_miibus_writereg (device_t, int, int, int); 261 static void xl_miibus_statchg (device_t); 262 static void xl_miibus_mediainit (device_t); 263 264 static device_method_t xl_methods[] = { 265 /* Device interface */ 266 DEVMETHOD(device_probe, xl_probe), 267 DEVMETHOD(device_attach, xl_attach), 268 DEVMETHOD(device_detach, xl_detach), 269 DEVMETHOD(device_shutdown, xl_shutdown), 270 DEVMETHOD(device_suspend, xl_suspend), 271 DEVMETHOD(device_resume, xl_resume), 272 273 /* bus interface */ 274 DEVMETHOD(bus_print_child, bus_generic_print_child), 275 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 276 277 /* MII interface */ 278 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 279 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 280 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 281 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 282 283 { 0, 0 } 284 }; 285 286 static driver_t xl_driver = { 287 "xl", 288 xl_methods, 289 sizeof(struct xl_softc) 290 }; 291 292 static devclass_t xl_devclass; 293 294 DECLARE_DUMMY_MODULE(if_xl); 295 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 296 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 297 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 298 299 static void 300 xl_dma_map_addr(arg, segs, nseg, error) 301 void *arg; 302 bus_dma_segment_t *segs; 303 int nseg, error; 304 { 305 u_int32_t *paddr; 306 307 paddr = arg; 308 *paddr = segs->ds_addr; 309 } 310 311 static void 312 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 313 void *arg; 314 bus_dma_segment_t *segs; 315 int nseg; 316 bus_size_t mapsize; 317 int error; 318 { 319 u_int32_t *paddr; 320 321 if (error) 322 return; 323 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 324 paddr = arg; 325 *paddr = segs->ds_addr; 326 } 327 328 static void 329 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error) 330 void *arg; 331 bus_dma_segment_t *segs; 332 int nseg; 333 bus_size_t mapsize; 334 int error; 335 { 336 struct xl_list *l; 337 int i, total_len; 338 339 if (error) 340 return; 341 342 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 343 344 total_len = 0; 345 l = arg; 346 for (i = 0; i < nseg; i++) { 347 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 348 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 349 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 350 total_len += segs[i].ds_len; 351 } 352 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 353 XL_LAST_FRAG); 354 l->xl_status = htole32(total_len); 355 l->xl_next = 0; 356 } 357 358 /* 359 * Murphy's law says that it's possible the chip can wedge and 360 * the 'command in progress' bit may never clear. Hence, we wait 361 * only a finite amount of time to avoid getting caught in an 362 * infinite loop. Normally this delay routine would be a macro, 363 * but it isn't called during normal operation so we can afford 364 * to make it a function. 365 */ 366 static void 367 xl_wait(sc) 368 struct xl_softc *sc; 369 { 370 int i; 371 372 for (i = 0; i < XL_TIMEOUT; i++) { 373 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 374 break; 375 } 376 377 if (i == XL_TIMEOUT) 378 if_printf(&sc->arpcom.ac_if, "command never completed!"); 379 380 return; 381 } 382 383 /* 384 * MII access routines are provided for adapters with external 385 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 386 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 387 * Note: if you don't perform the MDIO operations just right, 388 * it's possible to end up with code that works correctly with 389 * some chips/CPUs/processor speeds/bus speeds/etc but not 390 * with others. 391 */ 392 #define MII_SET(x) \ 393 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 394 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 395 396 #define MII_CLR(x) \ 397 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 398 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 399 400 /* 401 * Sync the PHYs by setting data bit and strobing the clock 32 times. 402 */ 403 static void 404 xl_mii_sync(sc) 405 struct xl_softc *sc; 406 { 407 int i; 408 409 XL_SEL_WIN(4); 410 MII_SET(XL_MII_DIR|XL_MII_DATA); 411 412 for (i = 0; i < 32; i++) { 413 MII_SET(XL_MII_CLK); 414 MII_SET(XL_MII_DATA); 415 MII_SET(XL_MII_DATA); 416 MII_CLR(XL_MII_CLK); 417 MII_SET(XL_MII_DATA); 418 MII_SET(XL_MII_DATA); 419 } 420 421 return; 422 } 423 424 /* 425 * Clock a series of bits through the MII. 426 */ 427 static void 428 xl_mii_send(sc, bits, cnt) 429 struct xl_softc *sc; 430 u_int32_t bits; 431 int cnt; 432 { 433 int i; 434 435 XL_SEL_WIN(4); 436 MII_CLR(XL_MII_CLK); 437 438 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 439 if (bits & i) { 440 MII_SET(XL_MII_DATA); 441 } else { 442 MII_CLR(XL_MII_DATA); 443 } 444 MII_CLR(XL_MII_CLK); 445 MII_SET(XL_MII_CLK); 446 } 447 } 448 449 /* 450 * Read an PHY register through the MII. 451 */ 452 static int 453 xl_mii_readreg(sc, frame) 454 struct xl_softc *sc; 455 struct xl_mii_frame *frame; 456 457 { 458 int i, ack; 459 460 crit_enter(); 461 462 /* 463 * Set up frame for RX. 464 */ 465 frame->mii_stdelim = XL_MII_STARTDELIM; 466 frame->mii_opcode = XL_MII_READOP; 467 frame->mii_turnaround = 0; 468 frame->mii_data = 0; 469 470 /* 471 * Select register window 4. 472 */ 473 474 XL_SEL_WIN(4); 475 476 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 477 /* 478 * Turn on data xmit. 479 */ 480 MII_SET(XL_MII_DIR); 481 482 xl_mii_sync(sc); 483 484 /* 485 * Send command/address info. 486 */ 487 xl_mii_send(sc, frame->mii_stdelim, 2); 488 xl_mii_send(sc, frame->mii_opcode, 2); 489 xl_mii_send(sc, frame->mii_phyaddr, 5); 490 xl_mii_send(sc, frame->mii_regaddr, 5); 491 492 /* Idle bit */ 493 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 494 MII_SET(XL_MII_CLK); 495 496 /* Turn off xmit. */ 497 MII_CLR(XL_MII_DIR); 498 499 /* Check for ack */ 500 MII_CLR(XL_MII_CLK); 501 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 502 MII_SET(XL_MII_CLK); 503 504 /* 505 * Now try reading data bits. If the ack failed, we still 506 * need to clock through 16 cycles to keep the PHY(s) in sync. 507 */ 508 if (ack) { 509 for(i = 0; i < 16; i++) { 510 MII_CLR(XL_MII_CLK); 511 MII_SET(XL_MII_CLK); 512 } 513 goto fail; 514 } 515 516 for (i = 0x8000; i; i >>= 1) { 517 MII_CLR(XL_MII_CLK); 518 if (!ack) { 519 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 520 frame->mii_data |= i; 521 } 522 MII_SET(XL_MII_CLK); 523 } 524 525 fail: 526 527 MII_CLR(XL_MII_CLK); 528 MII_SET(XL_MII_CLK); 529 530 crit_exit(); 531 532 if (ack) 533 return(1); 534 return(0); 535 } 536 537 /* 538 * Write to a PHY register through the MII. 539 */ 540 static int 541 xl_mii_writereg(sc, frame) 542 struct xl_softc *sc; 543 struct xl_mii_frame *frame; 544 545 { 546 crit_enter(); 547 548 /* 549 * Set up frame for TX. 550 */ 551 552 frame->mii_stdelim = XL_MII_STARTDELIM; 553 frame->mii_opcode = XL_MII_WRITEOP; 554 frame->mii_turnaround = XL_MII_TURNAROUND; 555 556 /* 557 * Select the window 4. 558 */ 559 XL_SEL_WIN(4); 560 561 /* 562 * Turn on data output. 563 */ 564 MII_SET(XL_MII_DIR); 565 566 xl_mii_sync(sc); 567 568 xl_mii_send(sc, frame->mii_stdelim, 2); 569 xl_mii_send(sc, frame->mii_opcode, 2); 570 xl_mii_send(sc, frame->mii_phyaddr, 5); 571 xl_mii_send(sc, frame->mii_regaddr, 5); 572 xl_mii_send(sc, frame->mii_turnaround, 2); 573 xl_mii_send(sc, frame->mii_data, 16); 574 575 /* Idle bit. */ 576 MII_SET(XL_MII_CLK); 577 MII_CLR(XL_MII_CLK); 578 579 /* 580 * Turn off xmit. 581 */ 582 MII_CLR(XL_MII_DIR); 583 584 crit_exit(); 585 586 return(0); 587 } 588 589 static int 590 xl_miibus_readreg(dev, phy, reg) 591 device_t dev; 592 int phy, reg; 593 { 594 struct xl_softc *sc; 595 struct xl_mii_frame frame; 596 597 sc = device_get_softc(dev); 598 599 /* 600 * Pretend that PHYs are only available at MII address 24. 601 * This is to guard against problems with certain 3Com ASIC 602 * revisions that incorrectly map the internal transceiver 603 * control registers at all MII addresses. This can cause 604 * the miibus code to attach the same PHY several times over. 605 */ 606 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 607 return(0); 608 609 bzero((char *)&frame, sizeof(frame)); 610 611 frame.mii_phyaddr = phy; 612 frame.mii_regaddr = reg; 613 xl_mii_readreg(sc, &frame); 614 615 return(frame.mii_data); 616 } 617 618 static int 619 xl_miibus_writereg(dev, phy, reg, data) 620 device_t dev; 621 int phy, reg, data; 622 { 623 struct xl_softc *sc; 624 struct xl_mii_frame frame; 625 626 sc = device_get_softc(dev); 627 628 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 629 return(0); 630 631 bzero((char *)&frame, sizeof(frame)); 632 633 frame.mii_phyaddr = phy; 634 frame.mii_regaddr = reg; 635 frame.mii_data = data; 636 637 xl_mii_writereg(sc, &frame); 638 639 return(0); 640 } 641 642 static void 643 xl_miibus_statchg(dev) 644 device_t dev; 645 { 646 struct xl_softc *sc; 647 struct mii_data *mii; 648 649 650 sc = device_get_softc(dev); 651 mii = device_get_softc(sc->xl_miibus); 652 653 xl_setcfg(sc); 654 655 /* Set ASIC's duplex mode to match the PHY. */ 656 XL_SEL_WIN(3); 657 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 658 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 659 else 660 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 661 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 662 663 return; 664 } 665 666 /* 667 * Special support for the 3c905B-COMBO. This card has 10/100 support 668 * plus BNC and AUI ports. This means we will have both an miibus attached 669 * plus some non-MII media settings. In order to allow this, we have to 670 * add the extra media to the miibus's ifmedia struct, but we can't do 671 * that during xl_attach() because the miibus hasn't been attached yet. 672 * So instead, we wait until the miibus probe/attach is done, at which 673 * point we will get a callback telling is that it's safe to add our 674 * extra media. 675 */ 676 static void 677 xl_miibus_mediainit(dev) 678 device_t dev; 679 { 680 struct xl_softc *sc; 681 struct mii_data *mii; 682 struct ifmedia *ifm; 683 684 sc = device_get_softc(dev); 685 mii = device_get_softc(sc->xl_miibus); 686 ifm = &mii->mii_media; 687 688 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 689 /* 690 * Check for a 10baseFL board in disguise. 691 */ 692 if (sc->xl_type == XL_TYPE_905B && 693 sc->xl_media == XL_MEDIAOPT_10FL) { 694 if (bootverbose) 695 device_printf(dev, "found 10baseFL\n"); 696 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 697 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 698 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 699 ifmedia_add(ifm, 700 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 701 } else { 702 if (bootverbose) 703 device_printf(dev, "found AUI\n"); 704 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 705 } 706 } 707 708 if (sc->xl_media & XL_MEDIAOPT_BNC) { 709 if (bootverbose) 710 device_printf(dev, "found BNC\n"); 711 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 712 } 713 714 return; 715 } 716 717 /* 718 * The EEPROM is slow: give it time to come ready after issuing 719 * it a command. 720 */ 721 static int 722 xl_eeprom_wait(sc) 723 struct xl_softc *sc; 724 { 725 int i; 726 727 for (i = 0; i < 100; i++) { 728 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 729 DELAY(162); 730 else 731 break; 732 } 733 734 if (i == 100) { 735 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 736 return(1); 737 } 738 739 return(0); 740 } 741 742 /* 743 * Read a sequence of words from the EEPROM. Note that ethernet address 744 * data is stored in the EEPROM in network byte order. 745 */ 746 static int 747 xl_read_eeprom(sc, dest, off, cnt, swap) 748 struct xl_softc *sc; 749 caddr_t dest; 750 int off; 751 int cnt; 752 int swap; 753 { 754 int err = 0, i; 755 u_int16_t word = 0, *ptr; 756 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 757 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 758 /* WARNING! DANGER! 759 * It's easy to accidentally overwrite the rom content! 760 * Note: the 3c575 uses 8bit EEPROM offsets. 761 */ 762 XL_SEL_WIN(0); 763 764 if (xl_eeprom_wait(sc)) 765 return(1); 766 767 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 768 off += 0x30; 769 770 for (i = 0; i < cnt; i++) { 771 if (sc->xl_flags & XL_FLAG_8BITROM) 772 CSR_WRITE_2(sc, XL_W0_EE_CMD, 773 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 774 else 775 CSR_WRITE_2(sc, XL_W0_EE_CMD, 776 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 777 err = xl_eeprom_wait(sc); 778 if (err) 779 break; 780 word = CSR_READ_2(sc, XL_W0_EE_DATA); 781 ptr = (u_int16_t *)(dest + (i * 2)); 782 if (swap) 783 *ptr = ntohs(word); 784 else 785 *ptr = word; 786 } 787 788 return(err ? 1 : 0); 789 } 790 791 /* 792 * This routine is taken from the 3Com Etherlink XL manual, 793 * page 10-7. It calculates a CRC of the supplied multicast 794 * group address and returns the lower 8 bits, which are used 795 * as the multicast filter position. 796 * Note: the 3c905B currently only supports a 64-bit hash table, 797 * which means we really only need 6 bits, but the manual indicates 798 * that future chip revisions will have a 256-bit hash table, 799 * hence the routine is set up to calculate 8 bits of position 800 * info in case we need it some day. 801 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a 802 * 256 bit hash table. This means we have to use all 8 bits regardless. 803 * On older cards, the upper 2 bits will be ignored. Grrrr.... 804 */ 805 static u_int8_t xl_calchash(addr) 806 caddr_t addr; 807 { 808 u_int32_t crc, carry; 809 int i, j; 810 u_int8_t c; 811 812 /* Compute CRC for the address value. */ 813 crc = 0xFFFFFFFF; /* initial value */ 814 815 for (i = 0; i < 6; i++) { 816 c = *(addr + i); 817 for (j = 0; j < 8; j++) { 818 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 819 crc <<= 1; 820 c >>= 1; 821 if (carry) 822 crc = (crc ^ 0x04c11db6) | carry; 823 } 824 } 825 826 /* return the filter bit position */ 827 return(crc & 0x000000FF); 828 } 829 830 /* 831 * NICs older than the 3c905B have only one multicast option, which 832 * is to enable reception of all multicast frames. 833 */ 834 static void 835 xl_setmulti(sc) 836 struct xl_softc *sc; 837 { 838 struct ifnet *ifp; 839 struct ifmultiaddr *ifma; 840 u_int8_t rxfilt; 841 int mcnt = 0; 842 843 ifp = &sc->arpcom.ac_if; 844 845 XL_SEL_WIN(5); 846 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 847 848 if (ifp->if_flags & IFF_ALLMULTI) { 849 rxfilt |= XL_RXFILTER_ALLMULTI; 850 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 851 return; 852 } 853 854 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 855 mcnt++; 856 857 if (mcnt) 858 rxfilt |= XL_RXFILTER_ALLMULTI; 859 else 860 rxfilt &= ~XL_RXFILTER_ALLMULTI; 861 862 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 863 864 return; 865 } 866 867 /* 868 * 3c905B adapters have a hash filter that we can program. 869 */ 870 static void 871 xl_setmulti_hash(sc) 872 struct xl_softc *sc; 873 { 874 struct ifnet *ifp; 875 int h = 0, i; 876 struct ifmultiaddr *ifma; 877 u_int8_t rxfilt; 878 int mcnt = 0; 879 880 ifp = &sc->arpcom.ac_if; 881 882 XL_SEL_WIN(5); 883 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 884 885 if (ifp->if_flags & IFF_ALLMULTI) { 886 rxfilt |= XL_RXFILTER_ALLMULTI; 887 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 888 return; 889 } else 890 rxfilt &= ~XL_RXFILTER_ALLMULTI; 891 892 893 /* first, zot all the existing hash bits */ 894 for (i = 0; i < XL_HASHFILT_SIZE; i++) 895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 896 897 /* now program new ones */ 898 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 899 if (ifma->ifma_addr->sa_family != AF_LINK) 900 continue; 901 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 902 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 903 mcnt++; 904 } 905 906 if (mcnt) 907 rxfilt |= XL_RXFILTER_MULTIHASH; 908 else 909 rxfilt &= ~XL_RXFILTER_MULTIHASH; 910 911 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 912 913 return; 914 } 915 916 #ifdef notdef 917 static void 918 xl_testpacket(sc) 919 struct xl_softc *sc; 920 { 921 struct mbuf *m; 922 struct ifnet *ifp; 923 924 ifp = &sc->arpcom.ac_if; 925 926 MGETHDR(m, MB_DONTWAIT, MT_DATA); 927 928 if (m == NULL) 929 return; 930 931 bcopy(&sc->arpcom.ac_enaddr, 932 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 933 bcopy(&sc->arpcom.ac_enaddr, 934 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 935 mtod(m, struct ether_header *)->ether_type = htons(3); 936 mtod(m, unsigned char *)[14] = 0; 937 mtod(m, unsigned char *)[15] = 0; 938 mtod(m, unsigned char *)[16] = 0xE3; 939 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 940 IF_ENQUEUE(&ifp->if_snd, m); 941 xl_start(ifp); 942 943 return; 944 } 945 #endif 946 947 static void 948 xl_setcfg(sc) 949 struct xl_softc *sc; 950 { 951 u_int32_t icfg; 952 953 XL_SEL_WIN(3); 954 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 955 icfg &= ~XL_ICFG_CONNECTOR_MASK; 956 if (sc->xl_media & XL_MEDIAOPT_MII || 957 sc->xl_media & XL_MEDIAOPT_BT4) 958 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 959 if (sc->xl_media & XL_MEDIAOPT_BTX) 960 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 961 962 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 963 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 964 965 return; 966 } 967 968 static void 969 xl_setmode(sc, media) 970 struct xl_softc *sc; 971 int media; 972 { 973 struct ifnet *ifp = &sc->arpcom.ac_if; 974 u_int32_t icfg; 975 u_int16_t mediastat; 976 977 if_printf(ifp, "selecting "); 978 979 XL_SEL_WIN(4); 980 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 981 XL_SEL_WIN(3); 982 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 983 984 if (sc->xl_media & XL_MEDIAOPT_BT) { 985 if (IFM_SUBTYPE(media) == IFM_10_T) { 986 printf("10baseT transceiver, "); 987 sc->xl_xcvr = XL_XCVR_10BT; 988 icfg &= ~XL_ICFG_CONNECTOR_MASK; 989 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 990 mediastat |= XL_MEDIASTAT_LINKBEAT| 991 XL_MEDIASTAT_JABGUARD; 992 mediastat &= ~XL_MEDIASTAT_SQEENB; 993 } 994 } 995 996 if (sc->xl_media & XL_MEDIAOPT_BFX) { 997 if (IFM_SUBTYPE(media) == IFM_100_FX) { 998 printf("100baseFX port, "); 999 sc->xl_xcvr = XL_XCVR_100BFX; 1000 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1001 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 1002 mediastat |= XL_MEDIASTAT_LINKBEAT; 1003 mediastat &= ~XL_MEDIASTAT_SQEENB; 1004 } 1005 } 1006 1007 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1008 if (IFM_SUBTYPE(media) == IFM_10_5) { 1009 printf("AUI port, "); 1010 sc->xl_xcvr = XL_XCVR_AUI; 1011 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1012 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1013 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1014 XL_MEDIASTAT_JABGUARD); 1015 mediastat |= ~XL_MEDIASTAT_SQEENB; 1016 } 1017 if (IFM_SUBTYPE(media) == IFM_10_FL) { 1018 printf("10baseFL transceiver, "); 1019 sc->xl_xcvr = XL_XCVR_AUI; 1020 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1021 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1022 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1023 XL_MEDIASTAT_JABGUARD); 1024 mediastat |= ~XL_MEDIASTAT_SQEENB; 1025 } 1026 } 1027 1028 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1029 if (IFM_SUBTYPE(media) == IFM_10_2) { 1030 printf("BNC port, "); 1031 sc->xl_xcvr = XL_XCVR_COAX; 1032 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1033 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 1034 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1035 XL_MEDIASTAT_JABGUARD| 1036 XL_MEDIASTAT_SQEENB); 1037 } 1038 } 1039 1040 if ((media & IFM_GMASK) == IFM_FDX || 1041 IFM_SUBTYPE(media) == IFM_100_FX) { 1042 printf("full duplex\n"); 1043 XL_SEL_WIN(3); 1044 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1045 } else { 1046 printf("half duplex\n"); 1047 XL_SEL_WIN(3); 1048 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1049 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1050 } 1051 1052 if (IFM_SUBTYPE(media) == IFM_10_2) 1053 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1054 else 1055 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1056 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1057 XL_SEL_WIN(4); 1058 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1059 DELAY(800); 1060 XL_SEL_WIN(7); 1061 } 1062 1063 static void 1064 xl_reset(sc) 1065 struct xl_softc *sc; 1066 { 1067 int i; 1068 1069 XL_SEL_WIN(0); 1070 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1071 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1072 XL_RESETOPT_DISADVFD:0)); 1073 1074 /* 1075 * If we're using memory mapped register mode, pause briefly 1076 * after issuing the reset command before trying to access any 1077 * other registers. With my 3c575C cardbus card, failing to do 1078 * this results in the system locking up while trying to poll 1079 * the command busy bit in the status register. 1080 */ 1081 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1082 DELAY(100000); 1083 1084 for (i = 0; i < XL_TIMEOUT; i++) { 1085 DELAY(10); 1086 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1087 break; 1088 } 1089 1090 if (i == XL_TIMEOUT) 1091 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 1092 1093 /* Reset TX and RX. */ 1094 /* Note: the RX reset takes an absurd amount of time 1095 * on newer versions of the Tornado chips such as those 1096 * on the 3c905CX and newer 3c908C cards. We wait an 1097 * extra amount of time so that xl_wait() doesn't complain 1098 * and annoy the users. 1099 */ 1100 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1101 DELAY(100000); 1102 xl_wait(sc); 1103 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1104 xl_wait(sc); 1105 1106 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1107 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1108 XL_SEL_WIN(2); 1109 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1110 XL_W2_RESET_OPTIONS) 1111 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1112 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1113 ); 1114 } 1115 1116 /* Wait a little while for the chip to get its brains in order. */ 1117 DELAY(100000); 1118 return; 1119 } 1120 1121 /* 1122 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1123 * IDs against our list and return a device name if we find a match. 1124 */ 1125 static int 1126 xl_probe(dev) 1127 device_t dev; 1128 { 1129 struct xl_type *t; 1130 1131 t = xl_devs; 1132 1133 while(t->xl_name != NULL) { 1134 if ((pci_get_vendor(dev) == t->xl_vid) && 1135 (pci_get_device(dev) == t->xl_did)) { 1136 device_set_desc(dev, t->xl_name); 1137 return(0); 1138 } 1139 t++; 1140 } 1141 1142 return(ENXIO); 1143 } 1144 1145 /* 1146 * This routine is a kludge to work around possible hardware faults 1147 * or manufacturing defects that can cause the media options register 1148 * (or reset options register, as it's called for the first generation 1149 * 3c90x adapters) to return an incorrect result. I have encountered 1150 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1151 * which doesn't have any of the 'mediaopt' bits set. This screws up 1152 * the attach routine pretty badly because it doesn't know what media 1153 * to look for. If we find ourselves in this predicament, this routine 1154 * will try to guess the media options values and warn the user of a 1155 * possible manufacturing defect with his adapter/system/whatever. 1156 */ 1157 static void 1158 xl_mediacheck(sc) 1159 struct xl_softc *sc; 1160 { 1161 struct ifnet *ifp = &sc->arpcom.ac_if; 1162 1163 /* 1164 * If some of the media options bits are set, assume they are 1165 * correct. If not, try to figure it out down below. 1166 * XXX I should check for 10baseFL, but I don't have an adapter 1167 * to test with. 1168 */ 1169 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1170 /* 1171 * Check the XCVR value. If it's not in the normal range 1172 * of values, we need to fake it up here. 1173 */ 1174 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1175 return; 1176 else { 1177 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1178 sc->xl_xcvr); 1179 if_printf(ifp, 1180 "choosing new default based on card type\n"); 1181 } 1182 } else { 1183 if (sc->xl_type == XL_TYPE_905B && 1184 sc->xl_media & XL_MEDIAOPT_10FL) 1185 return; 1186 if_printf(ifp, "WARNING: no media options bits set in " 1187 "the media options register!!\n"); 1188 if_printf(ifp, "this could be a manufacturing defect in " 1189 "your adapter or system\n"); 1190 if_printf(ifp, "attempting to guess media type; you " 1191 "should probably consult your vendor\n"); 1192 } 1193 1194 xl_choose_xcvr(sc, 1); 1195 } 1196 1197 static void 1198 xl_choose_xcvr(sc, verbose) 1199 struct xl_softc *sc; 1200 int verbose; 1201 { 1202 struct ifnet *ifp = &sc->arpcom.ac_if; 1203 u_int16_t devid; 1204 1205 /* 1206 * Read the device ID from the EEPROM. 1207 * This is what's loaded into the PCI device ID register, so it has 1208 * to be correct otherwise we wouldn't have gotten this far. 1209 */ 1210 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1211 1212 switch(devid) { 1213 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1214 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1215 sc->xl_media = XL_MEDIAOPT_BT; 1216 sc->xl_xcvr = XL_XCVR_10BT; 1217 if (verbose) 1218 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1219 break; 1220 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1221 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1222 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1223 sc->xl_xcvr = XL_XCVR_10BT; 1224 if (verbose) 1225 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1226 break; 1227 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1228 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1229 sc->xl_xcvr = XL_XCVR_10BT; 1230 if (verbose) 1231 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1232 break; 1233 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1234 sc->xl_media = XL_MEDIAOPT_10FL; 1235 sc->xl_xcvr = XL_XCVR_AUI; 1236 if (verbose) 1237 if_printf(ifp, "guessing 10baseFL\n"); 1238 break; 1239 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1240 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1241 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1242 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1243 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1244 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1245 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1246 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1247 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1248 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1249 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1250 sc->xl_media = XL_MEDIAOPT_MII; 1251 sc->xl_xcvr = XL_XCVR_MII; 1252 if (verbose) 1253 if_printf(ifp, "guessing MII\n"); 1254 break; 1255 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1256 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1257 sc->xl_media = XL_MEDIAOPT_BT4; 1258 sc->xl_xcvr = XL_XCVR_MII; 1259 if (verbose) 1260 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1261 break; 1262 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1263 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1264 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1265 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1266 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1267 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1268 sc->xl_media = XL_MEDIAOPT_BTX; 1269 sc->xl_xcvr = XL_XCVR_AUTO; 1270 if (verbose) 1271 if_printf(ifp, "guessing 10/100 internal\n"); 1272 break; 1273 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1274 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1275 sc->xl_xcvr = XL_XCVR_AUTO; 1276 if (verbose) 1277 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1278 break; 1279 default: 1280 if_printf(ifp, 1281 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1282 sc->xl_media = XL_MEDIAOPT_BT; 1283 break; 1284 } 1285 1286 return; 1287 } 1288 1289 /* 1290 * Attach the interface. Allocate softc structures, do ifmedia 1291 * setup and ethernet/BPF attach. 1292 */ 1293 static int 1294 xl_attach(dev) 1295 device_t dev; 1296 { 1297 u_char eaddr[ETHER_ADDR_LEN]; 1298 u_int16_t xcvr[2]; 1299 struct xl_softc *sc; 1300 struct ifnet *ifp; 1301 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1302 int unit, error = 0, rid, res; 1303 1304 sc = device_get_softc(dev); 1305 unit = device_get_unit(dev); 1306 1307 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1308 1309 sc->xl_flags = 0; 1310 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1311 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1312 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1313 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1314 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1315 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1316 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1317 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 || 1318 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1319 sc->xl_flags |= XL_FLAG_8BITROM; 1320 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1321 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1322 1323 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1324 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1325 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1326 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1327 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1328 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1329 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1330 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1331 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1332 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1333 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1334 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1335 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1336 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1337 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1338 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1339 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1340 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1341 XL_FLAG_INVERT_LED_PWR; 1342 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1343 sc->xl_flags |= XL_FLAG_PHYOK; 1344 #ifndef BURN_BRIDGES 1345 /* 1346 * If this is a 3c905B, we have to check one extra thing. 1347 * The 905B supports power management and may be placed in 1348 * a low-power mode (D3 mode), typically by certain operating 1349 * systems which shall not be named. The PCI BIOS is supposed 1350 * to reset the NIC and bring it out of low-power mode, but 1351 * some do not. Consequently, we have to see if this chip 1352 * supports power management, and if so, make sure it's not 1353 * in low-power mode. If power management is available, the 1354 * capid byte will be 0x01. 1355 * 1356 * I _think_ that what actually happens is that the chip 1357 * loses its PCI configuration during the transition from 1358 * D3 back to D0; this means that it should be possible for 1359 * us to save the PCI iobase, membase and IRQ, put the chip 1360 * back in the D0 state, then restore the PCI config ourselves. 1361 */ 1362 1363 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1364 u_int32_t iobase, membase, irq; 1365 1366 /* Save important PCI config data. */ 1367 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1368 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1369 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1370 1371 /* Reset the power state. */ 1372 device_printf(dev, "chip is in D%d power mode " 1373 "-- setting to D0\n", pci_get_powerstate(dev)); 1374 1375 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1376 1377 /* Restore PCI config data. */ 1378 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1379 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1380 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1381 } 1382 #endif 1383 /* 1384 * Map control/status registers. 1385 */ 1386 pci_enable_busmaster(dev); 1387 1388 rid = XL_PCI_LOMEM; 1389 res = SYS_RES_MEMORY; 1390 1391 #if 0 1392 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1393 #endif 1394 1395 if (sc->xl_res != NULL) { 1396 sc->xl_flags |= XL_FLAG_USE_MMIO; 1397 if (bootverbose) 1398 device_printf(dev, "using memory mapped I/O\n"); 1399 } else { 1400 rid = XL_PCI_LOIO; 1401 res = SYS_RES_IOPORT; 1402 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1403 if (sc->xl_res == NULL) { 1404 device_printf(dev, "couldn't map ports/memory\n"); 1405 error = ENXIO; 1406 goto fail; 1407 } 1408 if (bootverbose) 1409 device_printf(dev, "using port I/O\n"); 1410 } 1411 1412 sc->xl_btag = rman_get_bustag(sc->xl_res); 1413 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1414 1415 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1416 rid = XL_PCI_FUNCMEM; 1417 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1418 RF_ACTIVE); 1419 1420 if (sc->xl_fres == NULL) { 1421 device_printf(dev, "couldn't map ports/memory\n"); 1422 error = ENXIO; 1423 goto fail; 1424 } 1425 1426 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1427 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1428 } 1429 1430 /* Allocate interrupt */ 1431 rid = 0; 1432 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1433 RF_SHAREABLE | RF_ACTIVE); 1434 if (sc->xl_irq == NULL) { 1435 device_printf(dev, "couldn't map interrupt\n"); 1436 error = ENXIO; 1437 goto fail; 1438 } 1439 1440 sc->xl_flags |= XL_FLAG_ATTACH_MAPPED; 1441 1442 ifp = &sc->arpcom.ac_if; 1443 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1444 1445 /* Reset the adapter. */ 1446 xl_reset(sc); 1447 1448 /* 1449 * Get station address from the EEPROM. 1450 */ 1451 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1452 device_printf(dev, "failed to read station address\n"); 1453 error = ENXIO; 1454 goto fail; 1455 } 1456 1457 callout_init(&sc->xl_stat_timer); 1458 1459 /* 1460 * Now allocate a tag for the DMA descriptor lists and a chunk 1461 * of DMA-able memory based on the tag. Also obtain the DMA 1462 * addresses of the RX and TX ring, which we'll need later. 1463 * All of our lists are allocated as a contiguous block 1464 * of memory. 1465 */ 1466 error = bus_dma_tag_create(NULL, 8, 0, 1467 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1468 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, 1469 &sc->xl_ldata.xl_rx_tag); 1470 if (error) { 1471 device_printf(dev, "failed to allocate rx dma tag\n"); 1472 goto fail; 1473 } 1474 1475 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1476 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT, 1477 &sc->xl_ldata.xl_rx_dmamap); 1478 if (error) { 1479 device_printf(dev, "no memory for rx list buffers!\n"); 1480 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1481 sc->xl_ldata.xl_rx_tag = NULL; 1482 goto fail; 1483 } 1484 1485 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1486 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1487 XL_RX_LIST_SZ, xl_dma_map_addr, 1488 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1489 if (error) { 1490 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1491 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1492 sc->xl_ldata.xl_rx_dmamap); 1493 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1494 sc->xl_ldata.xl_rx_tag = NULL; 1495 goto fail; 1496 } 1497 1498 error = bus_dma_tag_create(NULL, 8, 0, 1499 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1500 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, 1501 &sc->xl_ldata.xl_tx_tag); 1502 if (error) { 1503 device_printf(dev, "failed to allocate tx dma tag\n"); 1504 goto fail; 1505 } 1506 1507 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1508 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT, 1509 &sc->xl_ldata.xl_tx_dmamap); 1510 if (error) { 1511 device_printf(dev, "no memory for list buffers!\n"); 1512 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1513 sc->xl_ldata.xl_tx_tag = NULL; 1514 goto fail; 1515 } 1516 1517 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1518 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1519 XL_TX_LIST_SZ, xl_dma_map_addr, 1520 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1521 if (error) { 1522 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1523 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1524 sc->xl_ldata.xl_tx_dmamap); 1525 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1526 sc->xl_ldata.xl_tx_tag = NULL; 1527 goto fail; 1528 } 1529 1530 /* 1531 * Allocate a DMA tag for the mapping of mbufs. 1532 */ 1533 error = bus_dma_tag_create(NULL, 1, 0, 1534 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1535 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, 1536 &sc->xl_mtag); 1537 if (error) { 1538 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1539 goto fail; 1540 } 1541 1542 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 1543 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 1544 1545 /* We need a spare DMA map for the RX ring. */ 1546 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1547 if (error) 1548 goto fail; 1549 1550 /* 1551 * Figure out the card type. 3c905B adapters have the 1552 * 'supportsNoTxLength' bit set in the capabilities 1553 * word in the EEPROM. 1554 * Note: my 3c575C cardbus card lies. It returns a value 1555 * of 0x1578 for its capabilities word, which is somewhat 1556 * nonsensical. Another way to distinguish a 3c90x chip 1557 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1558 * bit. This will only be set for 3c90x boomerage chips. 1559 */ 1560 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1561 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1562 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1563 sc->xl_type = XL_TYPE_905B; 1564 else 1565 sc->xl_type = XL_TYPE_90X; 1566 1567 ifp->if_softc = sc; 1568 ifp->if_mtu = ETHERMTU; 1569 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1570 ifp->if_ioctl = xl_ioctl; 1571 ifp->if_capabilities = 0; 1572 if (sc->xl_type == XL_TYPE_905B) { 1573 ifp->if_start = xl_start_90xB; 1574 ifp->if_capabilities |= IFCAP_HWCSUM; 1575 } else { 1576 ifp->if_start = xl_start; 1577 } 1578 ifp->if_watchdog = xl_watchdog; 1579 ifp->if_init = xl_init; 1580 ifp->if_baudrate = 10000000; 1581 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1582 ifq_set_ready(&ifp->if_snd); 1583 /* 1584 * NOTE: features disabled by default. This seems to corrupt 1585 * tx packet data one out of a million packets or so and then 1586 * generates a good checksum so the receiver doesn't 1587 * know the packet is bad 1588 */ 1589 ifp->if_capenable = 0; /*ifp->if_capabilities;*/ 1590 if (ifp->if_capenable & IFCAP_TXCSUM) 1591 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1592 1593 /* 1594 * Now we have to see what sort of media we have. 1595 * This includes probing for an MII interace and a 1596 * possible PHY. 1597 */ 1598 XL_SEL_WIN(3); 1599 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1600 if (bootverbose) 1601 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1602 1603 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1604 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1605 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1606 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1607 1608 xl_mediacheck(sc); 1609 1610 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1611 || sc->xl_media & XL_MEDIAOPT_BT4) { 1612 if (bootverbose) 1613 if_printf(ifp, "found MII/AUTO\n"); 1614 xl_setcfg(sc); 1615 if (mii_phy_probe(dev, &sc->xl_miibus, 1616 xl_ifmedia_upd, xl_ifmedia_sts)) { 1617 if_printf(ifp, "no PHY found!\n"); 1618 error = ENXIO; 1619 goto fail; 1620 } 1621 1622 goto done; 1623 } 1624 1625 /* 1626 * Sanity check. If the user has selected "auto" and this isn't 1627 * a 10/100 card of some kind, we need to force the transceiver 1628 * type to something sane. 1629 */ 1630 if (sc->xl_xcvr == XL_XCVR_AUTO) 1631 xl_choose_xcvr(sc, bootverbose); 1632 1633 /* 1634 * Do ifmedia setup. 1635 */ 1636 if (sc->xl_media & XL_MEDIAOPT_BT) { 1637 if (bootverbose) 1638 if_printf(ifp, "found 10baseT\n"); 1639 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1640 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1641 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1642 ifmedia_add(&sc->ifmedia, 1643 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1644 } 1645 1646 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1647 /* 1648 * Check for a 10baseFL board in disguise. 1649 */ 1650 if (sc->xl_type == XL_TYPE_905B && 1651 sc->xl_media == XL_MEDIAOPT_10FL) { 1652 if (bootverbose) 1653 if_printf(ifp, "found 10baseFL\n"); 1654 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1655 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1656 0, NULL); 1657 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1658 ifmedia_add(&sc->ifmedia, 1659 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1660 } else { 1661 if (bootverbose) 1662 if_printf(ifp, "found AUI\n"); 1663 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1664 } 1665 } 1666 1667 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1668 if (bootverbose) 1669 if_printf(ifp, "found BNC\n"); 1670 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1671 } 1672 1673 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1674 if (bootverbose) 1675 if_printf(ifp, "found 100baseFX\n"); 1676 ifp->if_baudrate = 100000000; 1677 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1678 } 1679 1680 /* Choose a default media. */ 1681 switch(sc->xl_xcvr) { 1682 case XL_XCVR_10BT: 1683 media = IFM_ETHER|IFM_10_T; 1684 xl_setmode(sc, media); 1685 break; 1686 case XL_XCVR_AUI: 1687 if (sc->xl_type == XL_TYPE_905B && 1688 sc->xl_media == XL_MEDIAOPT_10FL) { 1689 media = IFM_ETHER|IFM_10_FL; 1690 xl_setmode(sc, media); 1691 } else { 1692 media = IFM_ETHER|IFM_10_5; 1693 xl_setmode(sc, media); 1694 } 1695 break; 1696 case XL_XCVR_COAX: 1697 media = IFM_ETHER|IFM_10_2; 1698 xl_setmode(sc, media); 1699 break; 1700 case XL_XCVR_AUTO: 1701 case XL_XCVR_100BTX: 1702 case XL_XCVR_MII: 1703 /* Chosen by miibus */ 1704 break; 1705 case XL_XCVR_100BFX: 1706 media = IFM_ETHER|IFM_100_FX; 1707 break; 1708 default: 1709 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1710 /* 1711 * This will probably be wrong, but it prevents 1712 * the ifmedia code from panicking. 1713 */ 1714 media = IFM_ETHER|IFM_10_T; 1715 break; 1716 } 1717 1718 if (sc->xl_miibus == NULL) 1719 ifmedia_set(&sc->ifmedia, media); 1720 1721 done: 1722 1723 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1724 XL_SEL_WIN(0); 1725 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1726 } 1727 1728 /* 1729 * Call MI attach routine. 1730 */ 1731 ether_ifattach(ifp, eaddr); 1732 1733 /* 1734 * Tell the upper layer(s) we support long frames. 1735 */ 1736 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1737 1738 /* Hook interrupt last to avoid having to lock softc */ 1739 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1740 xl_intr, sc, &sc->xl_intrhand, NULL); 1741 if (error) { 1742 if_printf(ifp, "couldn't set up irq\n"); 1743 ether_ifdetach(ifp); 1744 goto fail; 1745 } 1746 1747 fail: 1748 if (error) 1749 xl_detach(dev); 1750 1751 return(error); 1752 } 1753 1754 /* 1755 * Shutdown hardware and free up resources. This can be called any 1756 * time after the mutex has been initialized. It is called in both 1757 * the error case in attach and the normal detach case so it needs 1758 * to be careful about only freeing resources that have actually been 1759 * allocated. 1760 */ 1761 static int 1762 xl_detach(dev) 1763 device_t dev; 1764 { 1765 struct xl_softc *sc; 1766 struct ifnet *ifp; 1767 int rid, res; 1768 1769 sc = device_get_softc(dev); 1770 ifp = &sc->arpcom.ac_if; 1771 1772 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1773 rid = XL_PCI_LOMEM; 1774 res = SYS_RES_MEMORY; 1775 } else { 1776 rid = XL_PCI_LOIO; 1777 res = SYS_RES_IOPORT; 1778 } 1779 1780 crit_enter(); 1781 1782 /* 1783 * Only try to communicate with the device if we were able to map 1784 * the ports. This flag is set before ether_ifattach() so it also 1785 * governs our call to ether_ifdetach(). 1786 */ 1787 if (sc->xl_flags & XL_FLAG_ATTACH_MAPPED) { 1788 xl_reset(sc); 1789 xl_stop(sc); 1790 ether_ifdetach(ifp); 1791 } 1792 1793 if (sc->xl_miibus) 1794 device_delete_child(dev, sc->xl_miibus); 1795 bus_generic_detach(dev); 1796 ifmedia_removeall(&sc->ifmedia); 1797 1798 if (sc->xl_intrhand) 1799 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1800 1801 crit_exit(); 1802 1803 if (sc->xl_irq) 1804 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1805 if (sc->xl_fres != NULL) 1806 bus_release_resource(dev, SYS_RES_MEMORY, 1807 XL_PCI_FUNCMEM, sc->xl_fres); 1808 if (sc->xl_res) 1809 bus_release_resource(dev, res, rid, sc->xl_res); 1810 1811 if (sc->xl_mtag) { 1812 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1813 bus_dma_tag_destroy(sc->xl_mtag); 1814 } 1815 if (sc->xl_ldata.xl_rx_tag) { 1816 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1817 sc->xl_ldata.xl_rx_dmamap); 1818 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1819 sc->xl_ldata.xl_rx_dmamap); 1820 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1821 } 1822 if (sc->xl_ldata.xl_tx_tag) { 1823 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1824 sc->xl_ldata.xl_tx_dmamap); 1825 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1826 sc->xl_ldata.xl_tx_dmamap); 1827 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1828 } 1829 1830 return(0); 1831 } 1832 1833 /* 1834 * Initialize the transmit descriptors. 1835 */ 1836 static int 1837 xl_list_tx_init(sc) 1838 struct xl_softc *sc; 1839 { 1840 struct xl_chain_data *cd; 1841 struct xl_list_data *ld; 1842 int error, i; 1843 1844 cd = &sc->xl_cdata; 1845 ld = &sc->xl_ldata; 1846 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1847 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1848 error = bus_dmamap_create(sc->xl_mtag, 0, 1849 &cd->xl_tx_chain[i].xl_map); 1850 if (error) 1851 return(error); 1852 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1853 i * sizeof(struct xl_list); 1854 if (i == (XL_TX_LIST_CNT - 1)) 1855 cd->xl_tx_chain[i].xl_next = NULL; 1856 else 1857 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1858 } 1859 1860 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1861 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1862 1863 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1864 return(0); 1865 } 1866 1867 /* 1868 * Initialize the transmit descriptors. 1869 */ 1870 static int 1871 xl_list_tx_init_90xB(sc) 1872 struct xl_softc *sc; 1873 { 1874 struct xl_chain_data *cd; 1875 struct xl_list_data *ld; 1876 int error, i; 1877 1878 cd = &sc->xl_cdata; 1879 ld = &sc->xl_ldata; 1880 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1881 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1882 error = bus_dmamap_create(sc->xl_mtag, 0, 1883 &cd->xl_tx_chain[i].xl_map); 1884 if (error) 1885 return(error); 1886 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1887 i * sizeof(struct xl_list); 1888 if (i == (XL_TX_LIST_CNT - 1)) 1889 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1890 else 1891 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1892 if (i == 0) 1893 cd->xl_tx_chain[i].xl_prev = 1894 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1895 else 1896 cd->xl_tx_chain[i].xl_prev = 1897 &cd->xl_tx_chain[i - 1]; 1898 } 1899 1900 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1901 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1902 1903 cd->xl_tx_prod = 1; 1904 cd->xl_tx_cons = 1; 1905 cd->xl_tx_cnt = 0; 1906 1907 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1908 return(0); 1909 } 1910 1911 /* 1912 * Initialize the RX descriptors and allocate mbufs for them. Note that 1913 * we arrange the descriptors in a closed ring, so that the last descriptor 1914 * points back to the first. 1915 */ 1916 static int 1917 xl_list_rx_init(sc) 1918 struct xl_softc *sc; 1919 { 1920 struct xl_chain_data *cd; 1921 struct xl_list_data *ld; 1922 int error, i, next; 1923 u_int32_t nextptr; 1924 1925 cd = &sc->xl_cdata; 1926 ld = &sc->xl_ldata; 1927 1928 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1929 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1930 error = bus_dmamap_create(sc->xl_mtag, 0, 1931 &cd->xl_rx_chain[i].xl_map); 1932 if (error) 1933 return(error); 1934 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1935 if (error) 1936 return(error); 1937 if (i == (XL_RX_LIST_CNT - 1)) 1938 next = 0; 1939 else 1940 next = i + 1; 1941 nextptr = ld->xl_rx_dmaaddr + 1942 next * sizeof(struct xl_list_onefrag); 1943 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1944 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1945 } 1946 1947 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1948 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1949 1950 return(0); 1951 } 1952 1953 /* 1954 * Initialize an RX descriptor and attach an MBUF cluster. 1955 * If we fail to do so, we need to leave the old mbuf and 1956 * the old DMA map untouched so that it can be reused. 1957 */ 1958 static int 1959 xl_newbuf(sc, c) 1960 struct xl_softc *sc; 1961 struct xl_chain_onefrag *c; 1962 { 1963 struct mbuf *m_new = NULL; 1964 bus_dmamap_t map; 1965 int error; 1966 u_int32_t baddr; 1967 1968 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1969 if (m_new == NULL) 1970 return(ENOBUFS); 1971 1972 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1973 1974 /* Force longword alignment for packet payload. */ 1975 m_adj(m_new, ETHER_ALIGN); 1976 1977 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 1978 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 1979 if (error) { 1980 m_freem(m_new); 1981 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 1982 error); 1983 return(error); 1984 } 1985 1986 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1987 map = c->xl_map; 1988 c->xl_map = sc->xl_tmpmap; 1989 sc->xl_tmpmap = map; 1990 c->xl_mbuf = m_new; 1991 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1992 c->xl_ptr->xl_status = 0; 1993 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 1994 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1995 return(0); 1996 } 1997 1998 static int 1999 xl_rx_resync(sc) 2000 struct xl_softc *sc; 2001 { 2002 struct xl_chain_onefrag *pos; 2003 int i; 2004 2005 pos = sc->xl_cdata.xl_rx_head; 2006 2007 for (i = 0; i < XL_RX_LIST_CNT; i++) { 2008 if (pos->xl_ptr->xl_status) 2009 break; 2010 pos = pos->xl_next; 2011 } 2012 2013 if (i == XL_RX_LIST_CNT) 2014 return(0); 2015 2016 sc->xl_cdata.xl_rx_head = pos; 2017 2018 return(EAGAIN); 2019 } 2020 2021 /* 2022 * A frame has been uploaded: pass the resulting mbuf chain up to 2023 * the higher level protocols. 2024 */ 2025 static void 2026 xl_rxeof(sc) 2027 struct xl_softc *sc; 2028 { 2029 struct mbuf *m; 2030 struct ifnet *ifp; 2031 struct xl_chain_onefrag *cur_rx; 2032 int total_len = 0; 2033 u_int32_t rxstat; 2034 2035 ifp = &sc->arpcom.ac_if; 2036 2037 again: 2038 2039 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2040 BUS_DMASYNC_POSTREAD); 2041 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2042 cur_rx = sc->xl_cdata.xl_rx_head; 2043 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2044 total_len = rxstat & XL_RXSTAT_LENMASK; 2045 2046 /* 2047 * Since we have told the chip to allow large frames, 2048 * we need to trap giant frame errors in software. We allow 2049 * a little more than the normal frame size to account for 2050 * frames with VLAN tags. 2051 */ 2052 if (total_len > XL_MAX_FRAMELEN) 2053 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2054 2055 /* 2056 * If an error occurs, update stats, clear the 2057 * status word and leave the mbuf cluster in place: 2058 * it should simply get re-used next time this descriptor 2059 * comes up in the ring. 2060 */ 2061 if (rxstat & XL_RXSTAT_UP_ERROR) { 2062 ifp->if_ierrors++; 2063 cur_rx->xl_ptr->xl_status = 0; 2064 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2065 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2066 continue; 2067 } 2068 2069 /* 2070 * If the error bit was not set, the upload complete 2071 * bit should be set which means we have a valid packet. 2072 * If not, something truly strange has happened. 2073 */ 2074 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2075 if_printf(ifp, 2076 "bad receive status -- packet dropped\n"); 2077 ifp->if_ierrors++; 2078 cur_rx->xl_ptr->xl_status = 0; 2079 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2080 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2081 continue; 2082 } 2083 2084 /* No errors; receive the packet. */ 2085 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2086 BUS_DMASYNC_POSTREAD); 2087 m = cur_rx->xl_mbuf; 2088 2089 /* 2090 * Try to conjure up a new mbuf cluster. If that 2091 * fails, it means we have an out of memory condition and 2092 * should leave the buffer in place and continue. This will 2093 * result in a lost packet, but there's little else we 2094 * can do in this situation. 2095 */ 2096 if (xl_newbuf(sc, cur_rx)) { 2097 ifp->if_ierrors++; 2098 cur_rx->xl_ptr->xl_status = 0; 2099 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2100 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2101 continue; 2102 } 2103 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2104 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2105 2106 ifp->if_ipackets++; 2107 m->m_pkthdr.rcvif = ifp; 2108 m->m_pkthdr.len = m->m_len = total_len; 2109 2110 if (ifp->if_capenable & IFCAP_RXCSUM) { 2111 /* Do IP checksum checking. */ 2112 if (rxstat & XL_RXSTAT_IPCKOK) 2113 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2114 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2115 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2116 if ((rxstat & XL_RXSTAT_TCPCOK && 2117 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2118 (rxstat & XL_RXSTAT_UDPCKOK && 2119 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2120 m->m_pkthdr.csum_flags |= 2121 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2122 m->m_pkthdr.csum_data = 0xffff; 2123 } 2124 } 2125 2126 (*ifp->if_input)(ifp, m); 2127 } 2128 2129 /* 2130 * Handle the 'end of channel' condition. When the upload 2131 * engine hits the end of the RX ring, it will stall. This 2132 * is our cue to flush the RX ring, reload the uplist pointer 2133 * register and unstall the engine. 2134 * XXX This is actually a little goofy. With the ThunderLAN 2135 * chip, you get an interrupt when the receiver hits the end 2136 * of the receive ring, which tells you exactly when you 2137 * you need to reload the ring pointer. Here we have to 2138 * fake it. I'm mad at myself for not being clever enough 2139 * to avoid the use of a goto here. 2140 */ 2141 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2142 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2143 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2144 xl_wait(sc); 2145 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2146 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2147 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2148 goto again; 2149 } 2150 2151 return; 2152 } 2153 2154 /* 2155 * A frame was downloaded to the chip. It's safe for us to clean up 2156 * the list buffers. 2157 */ 2158 static void 2159 xl_txeof(sc) 2160 struct xl_softc *sc; 2161 { 2162 struct xl_chain *cur_tx; 2163 struct ifnet *ifp; 2164 2165 ifp = &sc->arpcom.ac_if; 2166 2167 /* Clear the timeout timer. */ 2168 ifp->if_timer = 0; 2169 2170 /* 2171 * Go through our tx list and free mbufs for those 2172 * frames that have been uploaded. Note: the 3c905B 2173 * sets a special bit in the status word to let us 2174 * know that a frame has been downloaded, but the 2175 * original 3c900/3c905 adapters don't do that. 2176 * Consequently, we have to use a different test if 2177 * xl_type != XL_TYPE_905B. 2178 */ 2179 while(sc->xl_cdata.xl_tx_head != NULL) { 2180 cur_tx = sc->xl_cdata.xl_tx_head; 2181 2182 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2183 break; 2184 2185 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2186 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2187 BUS_DMASYNC_POSTWRITE); 2188 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2189 m_freem(cur_tx->xl_mbuf); 2190 cur_tx->xl_mbuf = NULL; 2191 ifp->if_opackets++; 2192 2193 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2194 sc->xl_cdata.xl_tx_free = cur_tx; 2195 } 2196 2197 if (sc->xl_cdata.xl_tx_head == NULL) { 2198 ifp->if_flags &= ~IFF_OACTIVE; 2199 sc->xl_cdata.xl_tx_tail = NULL; 2200 } else { 2201 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2202 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2203 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2204 sc->xl_cdata.xl_tx_head->xl_phys); 2205 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2206 } 2207 } 2208 2209 return; 2210 } 2211 2212 static void 2213 xl_txeof_90xB(sc) 2214 struct xl_softc *sc; 2215 { 2216 struct xl_chain *cur_tx = NULL; 2217 struct ifnet *ifp; 2218 int idx; 2219 2220 ifp = &sc->arpcom.ac_if; 2221 2222 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2223 BUS_DMASYNC_POSTREAD); 2224 idx = sc->xl_cdata.xl_tx_cons; 2225 while(idx != sc->xl_cdata.xl_tx_prod) { 2226 2227 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2228 2229 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2230 XL_TXSTAT_DL_COMPLETE)) 2231 break; 2232 2233 if (cur_tx->xl_mbuf != NULL) { 2234 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2235 BUS_DMASYNC_POSTWRITE); 2236 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2237 m_freem(cur_tx->xl_mbuf); 2238 cur_tx->xl_mbuf = NULL; 2239 } 2240 2241 ifp->if_opackets++; 2242 2243 sc->xl_cdata.xl_tx_cnt--; 2244 XL_INC(idx, XL_TX_LIST_CNT); 2245 ifp->if_timer = 0; 2246 } 2247 2248 sc->xl_cdata.xl_tx_cons = idx; 2249 2250 if (cur_tx != NULL) 2251 ifp->if_flags &= ~IFF_OACTIVE; 2252 2253 return; 2254 } 2255 2256 /* 2257 * TX 'end of channel' interrupt handler. Actually, we should 2258 * only get a 'TX complete' interrupt if there's a transmit error, 2259 * so this is really TX error handler. 2260 */ 2261 static void 2262 xl_txeoc(sc) 2263 struct xl_softc *sc; 2264 { 2265 struct ifnet *ifp = &sc->arpcom.ac_if; 2266 u_int8_t txstat; 2267 2268 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2269 if (txstat & XL_TXSTATUS_UNDERRUN || 2270 txstat & XL_TXSTATUS_JABBER || 2271 txstat & XL_TXSTATUS_RECLAIM) { 2272 if_printf(ifp, "transmission error: %x\n", txstat); 2273 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2274 xl_wait(sc); 2275 if (sc->xl_type == XL_TYPE_905B) { 2276 if (sc->xl_cdata.xl_tx_cnt) { 2277 int i; 2278 struct xl_chain *c; 2279 i = sc->xl_cdata.xl_tx_cons; 2280 c = &sc->xl_cdata.xl_tx_chain[i]; 2281 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2282 c->xl_phys); 2283 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2284 } 2285 } else { 2286 if (sc->xl_cdata.xl_tx_head != NULL) 2287 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2288 sc->xl_cdata.xl_tx_head->xl_phys); 2289 } 2290 /* 2291 * Remember to set this for the 2292 * first generation 3c90X chips. 2293 */ 2294 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2295 if (txstat & XL_TXSTATUS_UNDERRUN && 2296 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2297 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2298 if_printf(ifp, "tx underrun, increasing tx start" 2299 " threshold to %d bytes\n", 2300 sc->xl_tx_thresh); 2301 } 2302 CSR_WRITE_2(sc, XL_COMMAND, 2303 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2304 if (sc->xl_type == XL_TYPE_905B) { 2305 CSR_WRITE_2(sc, XL_COMMAND, 2306 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2307 } 2308 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2309 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2310 } else { 2311 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2312 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2313 } 2314 /* 2315 * Write an arbitrary byte to the TX_STATUS register 2316 * to clear this interrupt/error and advance to the next. 2317 */ 2318 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2319 } 2320 2321 return; 2322 } 2323 2324 static void 2325 xl_intr(arg) 2326 void *arg; 2327 { 2328 struct xl_softc *sc; 2329 struct ifnet *ifp; 2330 u_int16_t status; 2331 2332 sc = arg; 2333 ifp = &sc->arpcom.ac_if; 2334 2335 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2336 2337 CSR_WRITE_2(sc, XL_COMMAND, 2338 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2339 2340 if (status & XL_STAT_UP_COMPLETE) { 2341 int curpkts; 2342 2343 curpkts = ifp->if_ipackets; 2344 xl_rxeof(sc); 2345 if (curpkts == ifp->if_ipackets) { 2346 while (xl_rx_resync(sc)) 2347 xl_rxeof(sc); 2348 } 2349 } 2350 2351 if (status & XL_STAT_DOWN_COMPLETE) { 2352 if (sc->xl_type == XL_TYPE_905B) 2353 xl_txeof_90xB(sc); 2354 else 2355 xl_txeof(sc); 2356 } 2357 2358 if (status & XL_STAT_TX_COMPLETE) { 2359 ifp->if_oerrors++; 2360 xl_txeoc(sc); 2361 } 2362 2363 if (status & XL_STAT_ADFAIL) { 2364 xl_reset(sc); 2365 xl_init(sc); 2366 } 2367 2368 if (status & XL_STAT_STATSOFLOW) { 2369 sc->xl_stats_no_timeout = 1; 2370 xl_stats_update(sc); 2371 sc->xl_stats_no_timeout = 0; 2372 } 2373 } 2374 2375 if (!ifq_is_empty(&ifp->if_snd)) 2376 (*ifp->if_start)(ifp); 2377 2378 return; 2379 } 2380 2381 static void 2382 xl_stats_update(xsc) 2383 void *xsc; 2384 { 2385 struct xl_softc *sc; 2386 struct ifnet *ifp; 2387 struct xl_stats xl_stats; 2388 u_int8_t *p; 2389 int i; 2390 struct mii_data *mii = NULL; 2391 2392 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2393 2394 sc = xsc; 2395 ifp = &sc->arpcom.ac_if; 2396 if (sc->xl_miibus != NULL) 2397 mii = device_get_softc(sc->xl_miibus); 2398 2399 p = (u_int8_t *)&xl_stats; 2400 2401 /* Read all the stats registers. */ 2402 XL_SEL_WIN(6); 2403 2404 for (i = 0; i < 16; i++) 2405 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2406 2407 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2408 2409 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2410 xl_stats.xl_tx_single_collision + 2411 xl_stats.xl_tx_late_collision; 2412 2413 /* 2414 * Boomerang and cyclone chips have an extra stats counter 2415 * in window 4 (BadSSD). We have to read this too in order 2416 * to clear out all the stats registers and avoid a statsoflow 2417 * interrupt. 2418 */ 2419 XL_SEL_WIN(4); 2420 CSR_READ_1(sc, XL_W4_BADSSD); 2421 2422 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2423 mii_tick(mii); 2424 2425 XL_SEL_WIN(7); 2426 2427 if (!sc->xl_stats_no_timeout) 2428 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2429 2430 return; 2431 } 2432 2433 /* 2434 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2435 * pointers to the fragment pointers. 2436 */ 2437 static int 2438 xl_encap(sc, c, m_head) 2439 struct xl_softc *sc; 2440 struct xl_chain *c; 2441 struct mbuf *m_head; 2442 { 2443 int error; 2444 u_int32_t status; 2445 struct ifnet *ifp; 2446 2447 ifp = &sc->arpcom.ac_if; 2448 2449 /* 2450 * Start packing the mbufs in this chain into 2451 * the fragment pointers. Stop when we run out 2452 * of fragments or hit the end of the mbuf chain. 2453 */ 2454 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2455 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2456 2457 if (error && error != EFBIG) { 2458 m_freem(m_head); 2459 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2460 return(1); 2461 } 2462 2463 /* 2464 * Handle special case: we used up all 63 fragments, 2465 * but we have more mbufs left in the chain. Copy the 2466 * data into an mbuf cluster. Note that we don't 2467 * bother clearing the values in the other fragment 2468 * pointers/counters; it wouldn't gain us anything, 2469 * and would waste cycles. 2470 */ 2471 if (error) { 2472 struct mbuf *m_new; 2473 2474 m_new = m_defrag(m_head, MB_DONTWAIT); 2475 if (m_new == NULL) { 2476 m_freem(m_head); 2477 return(1); 2478 } else { 2479 m_head = m_new; 2480 } 2481 2482 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2483 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2484 if (error) { 2485 m_freem(m_head); 2486 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2487 return(1); 2488 } 2489 } 2490 2491 if (sc->xl_type == XL_TYPE_905B) { 2492 status = XL_TXSTAT_RND_DEFEAT; 2493 2494 if (m_head->m_pkthdr.csum_flags) { 2495 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2496 status |= XL_TXSTAT_IPCKSUM; 2497 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2498 status |= XL_TXSTAT_TCPCKSUM; 2499 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2500 status |= XL_TXSTAT_UDPCKSUM; 2501 } 2502 c->xl_ptr->xl_status = htole32(status); 2503 } 2504 2505 c->xl_mbuf = m_head; 2506 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2507 return(0); 2508 } 2509 2510 /* 2511 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2512 * to the mbuf data regions directly in the transmit lists. We also save a 2513 * copy of the pointers since the transmit list fragment pointers are 2514 * physical addresses. 2515 */ 2516 static void 2517 xl_start(ifp) 2518 struct ifnet *ifp; 2519 { 2520 struct xl_softc *sc; 2521 struct mbuf *m_head = NULL; 2522 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2523 struct xl_chain *prev_tx; 2524 u_int32_t status; 2525 int error; 2526 2527 sc = ifp->if_softc; 2528 /* 2529 * Check for an available queue slot. If there are none, 2530 * punt. 2531 */ 2532 if (sc->xl_cdata.xl_tx_free == NULL) { 2533 xl_txeoc(sc); 2534 xl_txeof(sc); 2535 if (sc->xl_cdata.xl_tx_free == NULL) { 2536 ifp->if_flags |= IFF_OACTIVE; 2537 return; 2538 } 2539 } 2540 2541 start_tx = sc->xl_cdata.xl_tx_free; 2542 2543 while(sc->xl_cdata.xl_tx_free != NULL) { 2544 m_head = ifq_dequeue(&ifp->if_snd); 2545 if (m_head == NULL) 2546 break; 2547 2548 /* Pick a descriptor off the free list. */ 2549 prev_tx = cur_tx; 2550 cur_tx = sc->xl_cdata.xl_tx_free; 2551 2552 /* Pack the data into the descriptor. */ 2553 error = xl_encap(sc, cur_tx, m_head); 2554 if (error) { 2555 cur_tx = prev_tx; 2556 continue; 2557 } 2558 2559 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2560 cur_tx->xl_next = NULL; 2561 2562 /* Chain it together. */ 2563 if (prev != NULL) { 2564 prev->xl_next = cur_tx; 2565 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2566 } 2567 prev = cur_tx; 2568 2569 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2570 } 2571 2572 /* 2573 * If there are no packets queued, bail. 2574 */ 2575 if (cur_tx == NULL) { 2576 return; 2577 } 2578 2579 /* 2580 * Place the request for the upload interrupt 2581 * in the last descriptor in the chain. This way, if 2582 * we're chaining several packets at once, we'll only 2583 * get an interupt once for the whole chain rather than 2584 * once for each packet. 2585 */ 2586 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2587 XL_TXSTAT_DL_INTR); 2588 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2589 BUS_DMASYNC_PREWRITE); 2590 2591 /* 2592 * Queue the packets. If the TX channel is clear, update 2593 * the downlist pointer register. 2594 */ 2595 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2596 xl_wait(sc); 2597 2598 if (sc->xl_cdata.xl_tx_head != NULL) { 2599 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2600 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2601 htole32(start_tx->xl_phys); 2602 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2603 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2604 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2605 sc->xl_cdata.xl_tx_tail = cur_tx; 2606 } else { 2607 sc->xl_cdata.xl_tx_head = start_tx; 2608 sc->xl_cdata.xl_tx_tail = cur_tx; 2609 } 2610 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2611 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2612 2613 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2614 2615 XL_SEL_WIN(7); 2616 2617 /* 2618 * Set a timeout in case the chip goes out to lunch. 2619 */ 2620 ifp->if_timer = 5; 2621 2622 /* 2623 * XXX Under certain conditions, usually on slower machines 2624 * where interrupts may be dropped, it's possible for the 2625 * adapter to chew up all the buffers in the receive ring 2626 * and stall, without us being able to do anything about it. 2627 * To guard against this, we need to make a pass over the 2628 * RX queue to make sure there aren't any packets pending. 2629 * Doing it here means we can flush the receive ring at the 2630 * same time the chip is DMAing the transmit descriptors we 2631 * just gave it. 2632 * 2633 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2634 * nature of their chips in all their marketing literature; 2635 * we may as well take advantage of it. :) 2636 */ 2637 xl_rxeof(sc); 2638 2639 return; 2640 } 2641 2642 static void 2643 xl_start_90xB(ifp) 2644 struct ifnet *ifp; 2645 { 2646 struct xl_softc *sc; 2647 struct mbuf *m_head = NULL; 2648 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2649 struct xl_chain *prev_tx; 2650 int error, idx; 2651 2652 sc = ifp->if_softc; 2653 2654 if (ifp->if_flags & IFF_OACTIVE) { 2655 return; 2656 } 2657 2658 idx = sc->xl_cdata.xl_tx_prod; 2659 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2660 2661 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2662 2663 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2664 ifp->if_flags |= IFF_OACTIVE; 2665 break; 2666 } 2667 2668 m_head = ifq_dequeue(&ifp->if_snd); 2669 if (m_head == NULL) 2670 break; 2671 2672 prev_tx = cur_tx; 2673 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2674 2675 /* Pack the data into the descriptor. */ 2676 error = xl_encap(sc, cur_tx, m_head); 2677 if (error) { 2678 cur_tx = prev_tx; 2679 continue; 2680 } 2681 2682 /* Chain it together. */ 2683 if (prev != NULL) 2684 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2685 prev = cur_tx; 2686 2687 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2688 2689 XL_INC(idx, XL_TX_LIST_CNT); 2690 sc->xl_cdata.xl_tx_cnt++; 2691 } 2692 2693 /* 2694 * If there are no packets queued, bail. 2695 */ 2696 if (cur_tx == NULL) { 2697 return; 2698 } 2699 2700 /* 2701 * Place the request for the upload interrupt 2702 * in the last descriptor in the chain. This way, if 2703 * we're chaining several packets at once, we'll only 2704 * get an interupt once for the whole chain rather than 2705 * once for each packet. 2706 */ 2707 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2708 XL_TXSTAT_DL_INTR); 2709 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2710 BUS_DMASYNC_PREWRITE); 2711 2712 /* Start transmission */ 2713 sc->xl_cdata.xl_tx_prod = idx; 2714 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2715 2716 /* 2717 * Set a timeout in case the chip goes out to lunch. 2718 */ 2719 ifp->if_timer = 5; 2720 2721 return; 2722 } 2723 2724 static void 2725 xl_init(xsc) 2726 void *xsc; 2727 { 2728 struct xl_softc *sc = xsc; 2729 struct ifnet *ifp = &sc->arpcom.ac_if; 2730 int error, i; 2731 u_int16_t rxfilt = 0; 2732 struct mii_data *mii = NULL; 2733 2734 crit_enter(); 2735 2736 /* 2737 * Cancel pending I/O and free all RX/TX buffers. 2738 */ 2739 xl_stop(sc); 2740 2741 if (sc->xl_miibus == NULL) { 2742 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2743 xl_wait(sc); 2744 } 2745 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2746 xl_wait(sc); 2747 DELAY(10000); 2748 2749 if (sc->xl_miibus != NULL) 2750 mii = device_get_softc(sc->xl_miibus); 2751 2752 /* Init our MAC address */ 2753 XL_SEL_WIN(2); 2754 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2755 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2756 sc->arpcom.ac_enaddr[i]); 2757 } 2758 2759 /* Clear the station mask. */ 2760 for (i = 0; i < 3; i++) 2761 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2762 #ifdef notdef 2763 /* Reset TX and RX. */ 2764 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2765 xl_wait(sc); 2766 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2767 xl_wait(sc); 2768 #endif 2769 /* Init circular RX list. */ 2770 error = xl_list_rx_init(sc); 2771 if (error) { 2772 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2773 error); 2774 xl_stop(sc); 2775 crit_exit(); 2776 return; 2777 } 2778 2779 /* Init TX descriptors. */ 2780 if (sc->xl_type == XL_TYPE_905B) 2781 error = xl_list_tx_init_90xB(sc); 2782 else 2783 error = xl_list_tx_init(sc); 2784 if (error) { 2785 if_printf(ifp, "initialization of the tx ring failed (%d)\n", 2786 error); 2787 xl_stop(sc); 2788 crit_exit(); 2789 return; 2790 } 2791 2792 /* 2793 * Set the TX freethresh value. 2794 * Note that this has no effect on 3c905B "cyclone" 2795 * cards but is required for 3c900/3c905 "boomerang" 2796 * cards in order to enable the download engine. 2797 */ 2798 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2799 2800 /* Set the TX start threshold for best performance. */ 2801 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2802 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2803 2804 /* 2805 * If this is a 3c905B, also set the tx reclaim threshold. 2806 * This helps cut down on the number of tx reclaim errors 2807 * that could happen on a busy network. The chip multiplies 2808 * the register value by 16 to obtain the actual threshold 2809 * in bytes, so we divide by 16 when setting the value here. 2810 * The existing threshold value can be examined by reading 2811 * the register at offset 9 in window 5. 2812 */ 2813 if (sc->xl_type == XL_TYPE_905B) { 2814 CSR_WRITE_2(sc, XL_COMMAND, 2815 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2816 } 2817 2818 /* Set RX filter bits. */ 2819 XL_SEL_WIN(5); 2820 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2821 2822 /* Set the individual bit to receive frames for this host only. */ 2823 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2824 2825 /* If we want promiscuous mode, set the allframes bit. */ 2826 if (ifp->if_flags & IFF_PROMISC) { 2827 rxfilt |= XL_RXFILTER_ALLFRAMES; 2828 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2829 } else { 2830 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2831 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2832 } 2833 2834 /* 2835 * Set capture broadcast bit to capture broadcast frames. 2836 */ 2837 if (ifp->if_flags & IFF_BROADCAST) { 2838 rxfilt |= XL_RXFILTER_BROADCAST; 2839 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2840 } else { 2841 rxfilt &= ~XL_RXFILTER_BROADCAST; 2842 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2843 } 2844 2845 /* 2846 * Program the multicast filter, if necessary. 2847 */ 2848 if (sc->xl_type == XL_TYPE_905B) 2849 xl_setmulti_hash(sc); 2850 else 2851 xl_setmulti(sc); 2852 2853 /* 2854 * Load the address of the RX list. We have to 2855 * stall the upload engine before we can manipulate 2856 * the uplist pointer register, then unstall it when 2857 * we're finished. We also have to wait for the 2858 * stall command to complete before proceeding. 2859 * Note that we have to do this after any RX resets 2860 * have completed since the uplist register is cleared 2861 * by a reset. 2862 */ 2863 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2864 xl_wait(sc); 2865 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2866 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2867 xl_wait(sc); 2868 2869 2870 if (sc->xl_type == XL_TYPE_905B) { 2871 /* Set polling interval */ 2872 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2873 /* Load the address of the TX list */ 2874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2875 xl_wait(sc); 2876 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2877 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2879 xl_wait(sc); 2880 } 2881 2882 /* 2883 * If the coax transceiver is on, make sure to enable 2884 * the DC-DC converter. 2885 */ 2886 XL_SEL_WIN(3); 2887 if (sc->xl_xcvr == XL_XCVR_COAX) 2888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2889 else 2890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2891 2892 /* 2893 * increase packet size to allow reception of 802.1q or ISL packets. 2894 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2895 * control register. For 3c90xB/C chips, use the RX packet size 2896 * register. 2897 */ 2898 2899 if (sc->xl_type == XL_TYPE_905B) 2900 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2901 else { 2902 u_int8_t macctl; 2903 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2904 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2905 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2906 } 2907 2908 /* Clear out the stats counters. */ 2909 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2910 sc->xl_stats_no_timeout = 1; 2911 xl_stats_update(sc); 2912 sc->xl_stats_no_timeout = 0; 2913 XL_SEL_WIN(4); 2914 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2915 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2916 2917 /* 2918 * Enable interrupts. 2919 */ 2920 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2921 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2922 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2923 if (sc->xl_flags & XL_FLAG_FUNCREG) 2924 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2925 2926 /* Set the RX early threshold */ 2927 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2928 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2929 2930 /* Enable receiver and transmitter. */ 2931 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2932 xl_wait(sc); 2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2934 xl_wait(sc); 2935 2936 if (mii != NULL) 2937 mii_mediachg(mii); 2938 2939 /* Select window 7 for normal operations. */ 2940 XL_SEL_WIN(7); 2941 2942 ifp->if_flags |= IFF_RUNNING; 2943 ifp->if_flags &= ~IFF_OACTIVE; 2944 2945 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2946 2947 crit_exit(); 2948 } 2949 2950 /* 2951 * Set media options. 2952 */ 2953 static int 2954 xl_ifmedia_upd(ifp) 2955 struct ifnet *ifp; 2956 { 2957 struct xl_softc *sc; 2958 struct ifmedia *ifm = NULL; 2959 struct mii_data *mii = NULL; 2960 2961 sc = ifp->if_softc; 2962 if (sc->xl_miibus != NULL) 2963 mii = device_get_softc(sc->xl_miibus); 2964 if (mii == NULL) 2965 ifm = &sc->ifmedia; 2966 else 2967 ifm = &mii->mii_media; 2968 2969 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2970 case IFM_100_FX: 2971 case IFM_10_FL: 2972 case IFM_10_2: 2973 case IFM_10_5: 2974 xl_setmode(sc, ifm->ifm_media); 2975 return(0); 2976 break; 2977 default: 2978 break; 2979 } 2980 2981 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2982 || sc->xl_media & XL_MEDIAOPT_BT4) { 2983 xl_init(sc); 2984 } else { 2985 xl_setmode(sc, ifm->ifm_media); 2986 } 2987 2988 return(0); 2989 } 2990 2991 /* 2992 * Report current media status. 2993 */ 2994 static void 2995 xl_ifmedia_sts(ifp, ifmr) 2996 struct ifnet *ifp; 2997 struct ifmediareq *ifmr; 2998 { 2999 struct xl_softc *sc; 3000 u_int32_t icfg; 3001 struct mii_data *mii = NULL; 3002 3003 sc = ifp->if_softc; 3004 if (sc->xl_miibus != NULL) 3005 mii = device_get_softc(sc->xl_miibus); 3006 3007 XL_SEL_WIN(3); 3008 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3009 icfg >>= XL_ICFG_CONNECTOR_BITS; 3010 3011 ifmr->ifm_active = IFM_ETHER; 3012 3013 switch(icfg) { 3014 case XL_XCVR_10BT: 3015 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3016 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3017 ifmr->ifm_active |= IFM_FDX; 3018 else 3019 ifmr->ifm_active |= IFM_HDX; 3020 break; 3021 case XL_XCVR_AUI: 3022 if (sc->xl_type == XL_TYPE_905B && 3023 sc->xl_media == XL_MEDIAOPT_10FL) { 3024 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3025 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3026 ifmr->ifm_active |= IFM_FDX; 3027 else 3028 ifmr->ifm_active |= IFM_HDX; 3029 } else 3030 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3031 break; 3032 case XL_XCVR_COAX: 3033 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3034 break; 3035 /* 3036 * XXX MII and BTX/AUTO should be separate cases. 3037 */ 3038 3039 case XL_XCVR_100BTX: 3040 case XL_XCVR_AUTO: 3041 case XL_XCVR_MII: 3042 if (mii != NULL) { 3043 mii_pollstat(mii); 3044 ifmr->ifm_active = mii->mii_media_active; 3045 ifmr->ifm_status = mii->mii_media_status; 3046 } 3047 break; 3048 case XL_XCVR_100BFX: 3049 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3050 break; 3051 default: 3052 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3053 break; 3054 } 3055 3056 return; 3057 } 3058 3059 static int 3060 xl_ioctl(ifp, command, data, cr) 3061 struct ifnet *ifp; 3062 u_long command; 3063 caddr_t data; 3064 struct ucred *cr; 3065 { 3066 struct xl_softc *sc = ifp->if_softc; 3067 struct ifreq *ifr = (struct ifreq *) data; 3068 int error = 0; 3069 struct mii_data *mii = NULL; 3070 u_int8_t rxfilt; 3071 3072 crit_enter(); 3073 3074 switch(command) { 3075 case SIOCSIFFLAGS: 3076 XL_SEL_WIN(5); 3077 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3078 if (ifp->if_flags & IFF_UP) { 3079 if (ifp->if_flags & IFF_RUNNING && 3080 ifp->if_flags & IFF_PROMISC && 3081 !(sc->xl_if_flags & IFF_PROMISC)) { 3082 rxfilt |= XL_RXFILTER_ALLFRAMES; 3083 CSR_WRITE_2(sc, XL_COMMAND, 3084 XL_CMD_RX_SET_FILT|rxfilt); 3085 XL_SEL_WIN(7); 3086 } else if (ifp->if_flags & IFF_RUNNING && 3087 !(ifp->if_flags & IFF_PROMISC) && 3088 sc->xl_if_flags & IFF_PROMISC) { 3089 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3090 CSR_WRITE_2(sc, XL_COMMAND, 3091 XL_CMD_RX_SET_FILT|rxfilt); 3092 XL_SEL_WIN(7); 3093 } else 3094 xl_init(sc); 3095 } else { 3096 if (ifp->if_flags & IFF_RUNNING) 3097 xl_stop(sc); 3098 } 3099 sc->xl_if_flags = ifp->if_flags; 3100 error = 0; 3101 break; 3102 case SIOCADDMULTI: 3103 case SIOCDELMULTI: 3104 if (sc->xl_type == XL_TYPE_905B) 3105 xl_setmulti_hash(sc); 3106 else 3107 xl_setmulti(sc); 3108 error = 0; 3109 break; 3110 case SIOCGIFMEDIA: 3111 case SIOCSIFMEDIA: 3112 if (sc->xl_miibus != NULL) 3113 mii = device_get_softc(sc->xl_miibus); 3114 if (mii == NULL) 3115 error = ifmedia_ioctl(ifp, ifr, 3116 &sc->ifmedia, command); 3117 else 3118 error = ifmedia_ioctl(ifp, ifr, 3119 &mii->mii_media, command); 3120 break; 3121 case SIOCSIFCAP: 3122 ifp->if_capenable = ifr->ifr_reqcap; 3123 if (ifp->if_capenable & IFCAP_TXCSUM) 3124 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3125 else 3126 ifp->if_hwassist = 0; 3127 break; 3128 default: 3129 error = ether_ioctl(ifp, command, data); 3130 break; 3131 } 3132 3133 crit_exit(); 3134 3135 return(error); 3136 } 3137 3138 static void 3139 xl_watchdog(ifp) 3140 struct ifnet *ifp; 3141 { 3142 struct xl_softc *sc; 3143 u_int16_t status = 0; 3144 3145 sc = ifp->if_softc; 3146 3147 ifp->if_oerrors++; 3148 XL_SEL_WIN(4); 3149 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3150 if_printf(ifp, "watchdog timeout\n"); 3151 3152 if (status & XL_MEDIASTAT_CARRIER) 3153 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3154 xl_txeoc(sc); 3155 xl_txeof(sc); 3156 xl_rxeof(sc); 3157 xl_reset(sc); 3158 xl_init(sc); 3159 3160 if (!ifq_is_empty(&ifp->if_snd)) 3161 (*ifp->if_start)(ifp); 3162 } 3163 3164 /* 3165 * Stop the adapter and free any mbufs allocated to the 3166 * RX and TX lists. 3167 */ 3168 static void 3169 xl_stop(sc) 3170 struct xl_softc *sc; 3171 { 3172 int i; 3173 struct ifnet *ifp; 3174 3175 ifp = &sc->arpcom.ac_if; 3176 ifp->if_timer = 0; 3177 3178 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3179 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3181 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3182 xl_wait(sc); 3183 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3184 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3185 DELAY(800); 3186 3187 #ifdef foo 3188 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3189 xl_wait(sc); 3190 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3191 xl_wait(sc); 3192 #endif 3193 3194 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3195 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3196 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3197 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3198 3199 /* Stop the stats updater. */ 3200 callout_stop(&sc->xl_stat_timer); 3201 3202 /* 3203 * Free data in the RX lists. 3204 */ 3205 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3206 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3207 bus_dmamap_unload(sc->xl_mtag, 3208 sc->xl_cdata.xl_rx_chain[i].xl_map); 3209 bus_dmamap_destroy(sc->xl_mtag, 3210 sc->xl_cdata.xl_rx_chain[i].xl_map); 3211 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3212 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3213 } 3214 } 3215 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3216 /* 3217 * Free the TX list buffers. 3218 */ 3219 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3220 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3221 bus_dmamap_unload(sc->xl_mtag, 3222 sc->xl_cdata.xl_tx_chain[i].xl_map); 3223 bus_dmamap_destroy(sc->xl_mtag, 3224 sc->xl_cdata.xl_tx_chain[i].xl_map); 3225 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3226 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3227 } 3228 } 3229 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3230 3231 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3232 3233 return; 3234 } 3235 3236 /* 3237 * Stop all chip I/O so that the kernel's probe routines don't 3238 * get confused by errant DMAs when rebooting. 3239 */ 3240 static void 3241 xl_shutdown(dev) 3242 device_t dev; 3243 { 3244 struct xl_softc *sc; 3245 3246 sc = device_get_softc(dev); 3247 3248 xl_reset(sc); 3249 xl_stop(sc); 3250 3251 return; 3252 } 3253 3254 static int 3255 xl_suspend(dev) 3256 device_t dev; 3257 { 3258 struct xl_softc *sc = device_get_softc(dev); 3259 3260 crit_enter(); 3261 3262 xl_stop(sc); 3263 3264 crit_exit(); 3265 3266 return(0); 3267 } 3268 3269 static int 3270 xl_resume(dev) 3271 device_t dev; 3272 { 3273 struct xl_softc *sc; 3274 struct ifnet *ifp; 3275 3276 sc = device_get_softc(dev); 3277 ifp = &sc->arpcom.ac_if; 3278 3279 crit_enter(); 3280 3281 xl_reset(sc); 3282 if (ifp->if_flags & IFF_UP) 3283 xl_init(sc); 3284 3285 crit_exit(); 3286 3287 return(0); 3288 } 3289