1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.25 2005/06/06 15:42:18 joerg Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 */ 101 102 #include <sys/param.h> 103 #include <sys/systm.h> 104 #include <sys/sockio.h> 105 #include <sys/endian.h> 106 #include <sys/mbuf.h> 107 #include <sys/kernel.h> 108 #include <sys/socket.h> 109 #include <sys/thread2.h> 110 111 #include <net/if.h> 112 #include <net/ifq_var.h> 113 #include <net/if_arp.h> 114 #include <net/ethernet.h> 115 #include <net/if_dl.h> 116 #include <net/if_media.h> 117 #include <net/vlan/if_vlan_var.h> 118 119 #include <net/bpf.h> 120 121 #include <machine/bus_memio.h> 122 #include <machine/bus_pio.h> 123 #include <machine/bus.h> 124 #include <machine/clock.h> /* for DELAY */ 125 #include <machine/resource.h> 126 #include <sys/bus.h> 127 #include <sys/rman.h> 128 129 #include "../mii_layer/mii.h" 130 #include "../mii_layer/miivar.h" 131 132 #include <bus/pci/pcireg.h> 133 #include <bus/pci/pcivar.h> 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 #include "if_xlreg.h" 139 140 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 141 142 /* 143 * Various supported device vendors/types and their names. 144 */ 145 static struct xl_type xl_devs[] = { 146 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 147 "3Com 3c900-TPO Etherlink XL" }, 148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 149 "3Com 3c900-COMBO Etherlink XL" }, 150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 151 "3Com 3c905-TX Fast Etherlink XL" }, 152 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 153 "3Com 3c905-T4 Fast Etherlink XL" }, 154 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 155 "3Com 3c900B-TPO Etherlink XL" }, 156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 157 "3Com 3c900B-COMBO Etherlink XL" }, 158 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 159 "3Com 3c900B-TPC Etherlink XL" }, 160 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 161 "3Com 3c900B-FL Etherlink XL" }, 162 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 163 "3Com 3c905B-TX Fast Etherlink XL" }, 164 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 165 "3Com 3c905B-T4 Fast Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 167 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 169 "3Com 3c905B-COMBO Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 171 "3Com 3c905C-TX Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 173 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 175 "3Com 3c980 Fast Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 177 "3Com 3c980C Fast Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 179 "3Com 3cSOHO100-TX OfficeConnect" }, 180 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 181 "3Com 3c450-TX HomeConnect" }, 182 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 183 "3Com 3c555 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 185 "3Com 3c556 Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 187 "3Com 3c556B Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 189 "3Com 3c575TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 191 "3Com 3c575B Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 193 "3Com 3c575C Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 195 "3Com 3c656 Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 197 "3Com 3c656B Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 199 "3Com 3c656C Fast Etherlink XL" }, 200 { 0, 0, NULL } 201 }; 202 203 static int xl_probe (device_t); 204 static int xl_attach (device_t); 205 static int xl_detach (device_t); 206 207 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 208 static void xl_stats_update (void *); 209 static int xl_encap (struct xl_softc *, struct xl_chain *, 210 struct mbuf *); 211 static void xl_rxeof (struct xl_softc *); 212 static int xl_rx_resync (struct xl_softc *); 213 static void xl_txeof (struct xl_softc *); 214 static void xl_txeof_90xB (struct xl_softc *); 215 static void xl_txeoc (struct xl_softc *); 216 static void xl_intr (void *); 217 static void xl_start (struct ifnet *); 218 static void xl_start_90xB (struct ifnet *); 219 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 220 struct ucred *); 221 static void xl_init (void *); 222 static void xl_stop (struct xl_softc *); 223 static void xl_watchdog (struct ifnet *); 224 static void xl_shutdown (device_t); 225 static int xl_suspend (device_t); 226 static int xl_resume (device_t); 227 228 static int xl_ifmedia_upd (struct ifnet *); 229 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 230 231 static int xl_eeprom_wait (struct xl_softc *); 232 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 233 static void xl_mii_sync (struct xl_softc *); 234 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 235 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 236 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 237 238 static void xl_setcfg (struct xl_softc *); 239 static void xl_setmode (struct xl_softc *, int); 240 static u_int8_t xl_calchash (caddr_t); 241 static void xl_setmulti (struct xl_softc *); 242 static void xl_setmulti_hash (struct xl_softc *); 243 static void xl_reset (struct xl_softc *); 244 static int xl_list_rx_init (struct xl_softc *); 245 static int xl_list_tx_init (struct xl_softc *); 246 static int xl_list_tx_init_90xB (struct xl_softc *); 247 static void xl_wait (struct xl_softc *); 248 static void xl_mediacheck (struct xl_softc *); 249 static void xl_choose_xcvr (struct xl_softc *, int); 250 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 251 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 252 int); 253 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 254 int); 255 #ifdef notdef 256 static void xl_testpacket (struct xl_softc *); 257 #endif 258 259 static int xl_miibus_readreg (device_t, int, int); 260 static int xl_miibus_writereg (device_t, int, int, int); 261 static void xl_miibus_statchg (device_t); 262 static void xl_miibus_mediainit (device_t); 263 264 static device_method_t xl_methods[] = { 265 /* Device interface */ 266 DEVMETHOD(device_probe, xl_probe), 267 DEVMETHOD(device_attach, xl_attach), 268 DEVMETHOD(device_detach, xl_detach), 269 DEVMETHOD(device_shutdown, xl_shutdown), 270 DEVMETHOD(device_suspend, xl_suspend), 271 DEVMETHOD(device_resume, xl_resume), 272 273 /* bus interface */ 274 DEVMETHOD(bus_print_child, bus_generic_print_child), 275 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 276 277 /* MII interface */ 278 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 279 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 280 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 281 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 282 283 { 0, 0 } 284 }; 285 286 static driver_t xl_driver = { 287 "xl", 288 xl_methods, 289 sizeof(struct xl_softc) 290 }; 291 292 static devclass_t xl_devclass; 293 294 DECLARE_DUMMY_MODULE(if_xl); 295 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 296 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 297 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 298 299 static void 300 xl_dma_map_addr(arg, segs, nseg, error) 301 void *arg; 302 bus_dma_segment_t *segs; 303 int nseg, error; 304 { 305 u_int32_t *paddr; 306 307 paddr = arg; 308 *paddr = segs->ds_addr; 309 } 310 311 static void 312 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 313 void *arg; 314 bus_dma_segment_t *segs; 315 int nseg; 316 bus_size_t mapsize; 317 int error; 318 { 319 u_int32_t *paddr; 320 321 if (error) 322 return; 323 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 324 paddr = arg; 325 *paddr = segs->ds_addr; 326 } 327 328 static void 329 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error) 330 void *arg; 331 bus_dma_segment_t *segs; 332 int nseg; 333 bus_size_t mapsize; 334 int error; 335 { 336 struct xl_list *l; 337 int i, total_len; 338 339 if (error) 340 return; 341 342 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 343 344 total_len = 0; 345 l = arg; 346 for (i = 0; i < nseg; i++) { 347 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 348 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 349 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 350 total_len += segs[i].ds_len; 351 } 352 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 353 XL_LAST_FRAG); 354 l->xl_status = htole32(total_len); 355 l->xl_next = 0; 356 } 357 358 /* 359 * Murphy's law says that it's possible the chip can wedge and 360 * the 'command in progress' bit may never clear. Hence, we wait 361 * only a finite amount of time to avoid getting caught in an 362 * infinite loop. Normally this delay routine would be a macro, 363 * but it isn't called during normal operation so we can afford 364 * to make it a function. 365 */ 366 static void 367 xl_wait(sc) 368 struct xl_softc *sc; 369 { 370 int i; 371 372 for (i = 0; i < XL_TIMEOUT; i++) { 373 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 374 break; 375 } 376 377 if (i == XL_TIMEOUT) 378 if_printf(&sc->arpcom.ac_if, "command never completed!"); 379 380 return; 381 } 382 383 /* 384 * MII access routines are provided for adapters with external 385 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 386 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 387 * Note: if you don't perform the MDIO operations just right, 388 * it's possible to end up with code that works correctly with 389 * some chips/CPUs/processor speeds/bus speeds/etc but not 390 * with others. 391 */ 392 #define MII_SET(x) \ 393 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 394 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 395 396 #define MII_CLR(x) \ 397 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 398 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 399 400 /* 401 * Sync the PHYs by setting data bit and strobing the clock 32 times. 402 */ 403 static void 404 xl_mii_sync(sc) 405 struct xl_softc *sc; 406 { 407 int i; 408 409 XL_SEL_WIN(4); 410 MII_SET(XL_MII_DIR|XL_MII_DATA); 411 412 for (i = 0; i < 32; i++) { 413 MII_SET(XL_MII_CLK); 414 MII_SET(XL_MII_DATA); 415 MII_SET(XL_MII_DATA); 416 MII_CLR(XL_MII_CLK); 417 MII_SET(XL_MII_DATA); 418 MII_SET(XL_MII_DATA); 419 } 420 421 return; 422 } 423 424 /* 425 * Clock a series of bits through the MII. 426 */ 427 static void 428 xl_mii_send(sc, bits, cnt) 429 struct xl_softc *sc; 430 u_int32_t bits; 431 int cnt; 432 { 433 int i; 434 435 XL_SEL_WIN(4); 436 MII_CLR(XL_MII_CLK); 437 438 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 439 if (bits & i) { 440 MII_SET(XL_MII_DATA); 441 } else { 442 MII_CLR(XL_MII_DATA); 443 } 444 MII_CLR(XL_MII_CLK); 445 MII_SET(XL_MII_CLK); 446 } 447 } 448 449 /* 450 * Read an PHY register through the MII. 451 */ 452 static int 453 xl_mii_readreg(sc, frame) 454 struct xl_softc *sc; 455 struct xl_mii_frame *frame; 456 457 { 458 int i, ack; 459 460 crit_enter(); 461 462 /* 463 * Set up frame for RX. 464 */ 465 frame->mii_stdelim = XL_MII_STARTDELIM; 466 frame->mii_opcode = XL_MII_READOP; 467 frame->mii_turnaround = 0; 468 frame->mii_data = 0; 469 470 /* 471 * Select register window 4. 472 */ 473 474 XL_SEL_WIN(4); 475 476 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 477 /* 478 * Turn on data xmit. 479 */ 480 MII_SET(XL_MII_DIR); 481 482 xl_mii_sync(sc); 483 484 /* 485 * Send command/address info. 486 */ 487 xl_mii_send(sc, frame->mii_stdelim, 2); 488 xl_mii_send(sc, frame->mii_opcode, 2); 489 xl_mii_send(sc, frame->mii_phyaddr, 5); 490 xl_mii_send(sc, frame->mii_regaddr, 5); 491 492 /* Idle bit */ 493 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 494 MII_SET(XL_MII_CLK); 495 496 /* Turn off xmit. */ 497 MII_CLR(XL_MII_DIR); 498 499 /* Check for ack */ 500 MII_CLR(XL_MII_CLK); 501 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 502 MII_SET(XL_MII_CLK); 503 504 /* 505 * Now try reading data bits. If the ack failed, we still 506 * need to clock through 16 cycles to keep the PHY(s) in sync. 507 */ 508 if (ack) { 509 for(i = 0; i < 16; i++) { 510 MII_CLR(XL_MII_CLK); 511 MII_SET(XL_MII_CLK); 512 } 513 goto fail; 514 } 515 516 for (i = 0x8000; i; i >>= 1) { 517 MII_CLR(XL_MII_CLK); 518 if (!ack) { 519 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 520 frame->mii_data |= i; 521 } 522 MII_SET(XL_MII_CLK); 523 } 524 525 fail: 526 527 MII_CLR(XL_MII_CLK); 528 MII_SET(XL_MII_CLK); 529 530 crit_exit(); 531 532 if (ack) 533 return(1); 534 return(0); 535 } 536 537 /* 538 * Write to a PHY register through the MII. 539 */ 540 static int 541 xl_mii_writereg(sc, frame) 542 struct xl_softc *sc; 543 struct xl_mii_frame *frame; 544 545 { 546 crit_enter(); 547 548 /* 549 * Set up frame for TX. 550 */ 551 552 frame->mii_stdelim = XL_MII_STARTDELIM; 553 frame->mii_opcode = XL_MII_WRITEOP; 554 frame->mii_turnaround = XL_MII_TURNAROUND; 555 556 /* 557 * Select the window 4. 558 */ 559 XL_SEL_WIN(4); 560 561 /* 562 * Turn on data output. 563 */ 564 MII_SET(XL_MII_DIR); 565 566 xl_mii_sync(sc); 567 568 xl_mii_send(sc, frame->mii_stdelim, 2); 569 xl_mii_send(sc, frame->mii_opcode, 2); 570 xl_mii_send(sc, frame->mii_phyaddr, 5); 571 xl_mii_send(sc, frame->mii_regaddr, 5); 572 xl_mii_send(sc, frame->mii_turnaround, 2); 573 xl_mii_send(sc, frame->mii_data, 16); 574 575 /* Idle bit. */ 576 MII_SET(XL_MII_CLK); 577 MII_CLR(XL_MII_CLK); 578 579 /* 580 * Turn off xmit. 581 */ 582 MII_CLR(XL_MII_DIR); 583 584 crit_exit(); 585 586 return(0); 587 } 588 589 static int 590 xl_miibus_readreg(dev, phy, reg) 591 device_t dev; 592 int phy, reg; 593 { 594 struct xl_softc *sc; 595 struct xl_mii_frame frame; 596 597 sc = device_get_softc(dev); 598 599 /* 600 * Pretend that PHYs are only available at MII address 24. 601 * This is to guard against problems with certain 3Com ASIC 602 * revisions that incorrectly map the internal transceiver 603 * control registers at all MII addresses. This can cause 604 * the miibus code to attach the same PHY several times over. 605 */ 606 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 607 return(0); 608 609 bzero((char *)&frame, sizeof(frame)); 610 611 frame.mii_phyaddr = phy; 612 frame.mii_regaddr = reg; 613 xl_mii_readreg(sc, &frame); 614 615 return(frame.mii_data); 616 } 617 618 static int 619 xl_miibus_writereg(dev, phy, reg, data) 620 device_t dev; 621 int phy, reg, data; 622 { 623 struct xl_softc *sc; 624 struct xl_mii_frame frame; 625 626 sc = device_get_softc(dev); 627 628 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 629 return(0); 630 631 bzero((char *)&frame, sizeof(frame)); 632 633 frame.mii_phyaddr = phy; 634 frame.mii_regaddr = reg; 635 frame.mii_data = data; 636 637 xl_mii_writereg(sc, &frame); 638 639 return(0); 640 } 641 642 static void 643 xl_miibus_statchg(dev) 644 device_t dev; 645 { 646 struct xl_softc *sc; 647 struct mii_data *mii; 648 649 650 sc = device_get_softc(dev); 651 mii = device_get_softc(sc->xl_miibus); 652 653 xl_setcfg(sc); 654 655 /* Set ASIC's duplex mode to match the PHY. */ 656 XL_SEL_WIN(3); 657 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 658 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 659 else 660 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 661 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 662 663 return; 664 } 665 666 /* 667 * Special support for the 3c905B-COMBO. This card has 10/100 support 668 * plus BNC and AUI ports. This means we will have both an miibus attached 669 * plus some non-MII media settings. In order to allow this, we have to 670 * add the extra media to the miibus's ifmedia struct, but we can't do 671 * that during xl_attach() because the miibus hasn't been attached yet. 672 * So instead, we wait until the miibus probe/attach is done, at which 673 * point we will get a callback telling is that it's safe to add our 674 * extra media. 675 */ 676 static void 677 xl_miibus_mediainit(dev) 678 device_t dev; 679 { 680 struct xl_softc *sc; 681 struct mii_data *mii; 682 struct ifmedia *ifm; 683 684 sc = device_get_softc(dev); 685 mii = device_get_softc(sc->xl_miibus); 686 ifm = &mii->mii_media; 687 688 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 689 /* 690 * Check for a 10baseFL board in disguise. 691 */ 692 if (sc->xl_type == XL_TYPE_905B && 693 sc->xl_media == XL_MEDIAOPT_10FL) { 694 if (bootverbose) 695 device_printf(dev, "found 10baseFL\n"); 696 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 697 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 698 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 699 ifmedia_add(ifm, 700 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 701 } else { 702 if (bootverbose) 703 device_printf(dev, "found AUI\n"); 704 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 705 } 706 } 707 708 if (sc->xl_media & XL_MEDIAOPT_BNC) { 709 if (bootverbose) 710 device_printf(dev, "found BNC\n"); 711 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 712 } 713 714 return; 715 } 716 717 /* 718 * The EEPROM is slow: give it time to come ready after issuing 719 * it a command. 720 */ 721 static int 722 xl_eeprom_wait(sc) 723 struct xl_softc *sc; 724 { 725 int i; 726 727 for (i = 0; i < 100; i++) { 728 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 729 DELAY(162); 730 else 731 break; 732 } 733 734 if (i == 100) { 735 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 736 return(1); 737 } 738 739 return(0); 740 } 741 742 /* 743 * Read a sequence of words from the EEPROM. Note that ethernet address 744 * data is stored in the EEPROM in network byte order. 745 */ 746 static int 747 xl_read_eeprom(sc, dest, off, cnt, swap) 748 struct xl_softc *sc; 749 caddr_t dest; 750 int off; 751 int cnt; 752 int swap; 753 { 754 int err = 0, i; 755 u_int16_t word = 0, *ptr; 756 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 757 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 758 /* WARNING! DANGER! 759 * It's easy to accidentally overwrite the rom content! 760 * Note: the 3c575 uses 8bit EEPROM offsets. 761 */ 762 XL_SEL_WIN(0); 763 764 if (xl_eeprom_wait(sc)) 765 return(1); 766 767 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 768 off += 0x30; 769 770 for (i = 0; i < cnt; i++) { 771 if (sc->xl_flags & XL_FLAG_8BITROM) 772 CSR_WRITE_2(sc, XL_W0_EE_CMD, 773 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 774 else 775 CSR_WRITE_2(sc, XL_W0_EE_CMD, 776 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 777 err = xl_eeprom_wait(sc); 778 if (err) 779 break; 780 word = CSR_READ_2(sc, XL_W0_EE_DATA); 781 ptr = (u_int16_t *)(dest + (i * 2)); 782 if (swap) 783 *ptr = ntohs(word); 784 else 785 *ptr = word; 786 } 787 788 return(err ? 1 : 0); 789 } 790 791 /* 792 * This routine is taken from the 3Com Etherlink XL manual, 793 * page 10-7. It calculates a CRC of the supplied multicast 794 * group address and returns the lower 8 bits, which are used 795 * as the multicast filter position. 796 * Note: the 3c905B currently only supports a 64-bit hash table, 797 * which means we really only need 6 bits, but the manual indicates 798 * that future chip revisions will have a 256-bit hash table, 799 * hence the routine is set up to calculate 8 bits of position 800 * info in case we need it some day. 801 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a 802 * 256 bit hash table. This means we have to use all 8 bits regardless. 803 * On older cards, the upper 2 bits will be ignored. Grrrr.... 804 */ 805 static u_int8_t xl_calchash(addr) 806 caddr_t addr; 807 { 808 u_int32_t crc, carry; 809 int i, j; 810 u_int8_t c; 811 812 /* Compute CRC for the address value. */ 813 crc = 0xFFFFFFFF; /* initial value */ 814 815 for (i = 0; i < 6; i++) { 816 c = *(addr + i); 817 for (j = 0; j < 8; j++) { 818 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 819 crc <<= 1; 820 c >>= 1; 821 if (carry) 822 crc = (crc ^ 0x04c11db6) | carry; 823 } 824 } 825 826 /* return the filter bit position */ 827 return(crc & 0x000000FF); 828 } 829 830 /* 831 * NICs older than the 3c905B have only one multicast option, which 832 * is to enable reception of all multicast frames. 833 */ 834 static void 835 xl_setmulti(sc) 836 struct xl_softc *sc; 837 { 838 struct ifnet *ifp; 839 struct ifmultiaddr *ifma; 840 u_int8_t rxfilt; 841 int mcnt = 0; 842 843 ifp = &sc->arpcom.ac_if; 844 845 XL_SEL_WIN(5); 846 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 847 848 if (ifp->if_flags & IFF_ALLMULTI) { 849 rxfilt |= XL_RXFILTER_ALLMULTI; 850 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 851 return; 852 } 853 854 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 855 ifma = ifma->ifma_link.le_next) 856 mcnt++; 857 858 if (mcnt) 859 rxfilt |= XL_RXFILTER_ALLMULTI; 860 else 861 rxfilt &= ~XL_RXFILTER_ALLMULTI; 862 863 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 864 865 return; 866 } 867 868 /* 869 * 3c905B adapters have a hash filter that we can program. 870 */ 871 static void 872 xl_setmulti_hash(sc) 873 struct xl_softc *sc; 874 { 875 struct ifnet *ifp; 876 int h = 0, i; 877 struct ifmultiaddr *ifma; 878 u_int8_t rxfilt; 879 int mcnt = 0; 880 881 ifp = &sc->arpcom.ac_if; 882 883 XL_SEL_WIN(5); 884 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 885 886 if (ifp->if_flags & IFF_ALLMULTI) { 887 rxfilt |= XL_RXFILTER_ALLMULTI; 888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 889 return; 890 } else 891 rxfilt &= ~XL_RXFILTER_ALLMULTI; 892 893 894 /* first, zot all the existing hash bits */ 895 for (i = 0; i < XL_HASHFILT_SIZE; i++) 896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 897 898 /* now program new ones */ 899 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 900 ifma = ifma->ifma_link.le_next) { 901 if (ifma->ifma_addr->sa_family != AF_LINK) 902 continue; 903 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 905 mcnt++; 906 } 907 908 if (mcnt) 909 rxfilt |= XL_RXFILTER_MULTIHASH; 910 else 911 rxfilt &= ~XL_RXFILTER_MULTIHASH; 912 913 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 914 915 return; 916 } 917 918 #ifdef notdef 919 static void 920 xl_testpacket(sc) 921 struct xl_softc *sc; 922 { 923 struct mbuf *m; 924 struct ifnet *ifp; 925 926 ifp = &sc->arpcom.ac_if; 927 928 MGETHDR(m, MB_DONTWAIT, MT_DATA); 929 930 if (m == NULL) 931 return; 932 933 bcopy(&sc->arpcom.ac_enaddr, 934 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 935 bcopy(&sc->arpcom.ac_enaddr, 936 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 937 mtod(m, struct ether_header *)->ether_type = htons(3); 938 mtod(m, unsigned char *)[14] = 0; 939 mtod(m, unsigned char *)[15] = 0; 940 mtod(m, unsigned char *)[16] = 0xE3; 941 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 942 IF_ENQUEUE(&ifp->if_snd, m); 943 xl_start(ifp); 944 945 return; 946 } 947 #endif 948 949 static void 950 xl_setcfg(sc) 951 struct xl_softc *sc; 952 { 953 u_int32_t icfg; 954 955 XL_SEL_WIN(3); 956 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 957 icfg &= ~XL_ICFG_CONNECTOR_MASK; 958 if (sc->xl_media & XL_MEDIAOPT_MII || 959 sc->xl_media & XL_MEDIAOPT_BT4) 960 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 961 if (sc->xl_media & XL_MEDIAOPT_BTX) 962 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 963 964 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 965 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 966 967 return; 968 } 969 970 static void 971 xl_setmode(sc, media) 972 struct xl_softc *sc; 973 int media; 974 { 975 struct ifnet *ifp = &sc->arpcom.ac_if; 976 u_int32_t icfg; 977 u_int16_t mediastat; 978 979 if_printf(ifp, "selecting "); 980 981 XL_SEL_WIN(4); 982 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 983 XL_SEL_WIN(3); 984 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 985 986 if (sc->xl_media & XL_MEDIAOPT_BT) { 987 if (IFM_SUBTYPE(media) == IFM_10_T) { 988 printf("10baseT transceiver, "); 989 sc->xl_xcvr = XL_XCVR_10BT; 990 icfg &= ~XL_ICFG_CONNECTOR_MASK; 991 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 992 mediastat |= XL_MEDIASTAT_LINKBEAT| 993 XL_MEDIASTAT_JABGUARD; 994 mediastat &= ~XL_MEDIASTAT_SQEENB; 995 } 996 } 997 998 if (sc->xl_media & XL_MEDIAOPT_BFX) { 999 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1000 printf("100baseFX port, "); 1001 sc->xl_xcvr = XL_XCVR_100BFX; 1002 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1003 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 1004 mediastat |= XL_MEDIASTAT_LINKBEAT; 1005 mediastat &= ~XL_MEDIASTAT_SQEENB; 1006 } 1007 } 1008 1009 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1010 if (IFM_SUBTYPE(media) == IFM_10_5) { 1011 printf("AUI port, "); 1012 sc->xl_xcvr = XL_XCVR_AUI; 1013 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1014 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1015 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1016 XL_MEDIASTAT_JABGUARD); 1017 mediastat |= ~XL_MEDIASTAT_SQEENB; 1018 } 1019 if (IFM_SUBTYPE(media) == IFM_10_FL) { 1020 printf("10baseFL transceiver, "); 1021 sc->xl_xcvr = XL_XCVR_AUI; 1022 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1023 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1024 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1025 XL_MEDIASTAT_JABGUARD); 1026 mediastat |= ~XL_MEDIASTAT_SQEENB; 1027 } 1028 } 1029 1030 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1031 if (IFM_SUBTYPE(media) == IFM_10_2) { 1032 printf("BNC port, "); 1033 sc->xl_xcvr = XL_XCVR_COAX; 1034 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1035 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 1036 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1037 XL_MEDIASTAT_JABGUARD| 1038 XL_MEDIASTAT_SQEENB); 1039 } 1040 } 1041 1042 if ((media & IFM_GMASK) == IFM_FDX || 1043 IFM_SUBTYPE(media) == IFM_100_FX) { 1044 printf("full duplex\n"); 1045 XL_SEL_WIN(3); 1046 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1047 } else { 1048 printf("half duplex\n"); 1049 XL_SEL_WIN(3); 1050 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1051 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1052 } 1053 1054 if (IFM_SUBTYPE(media) == IFM_10_2) 1055 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1056 else 1057 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1058 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1059 XL_SEL_WIN(4); 1060 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1061 DELAY(800); 1062 XL_SEL_WIN(7); 1063 } 1064 1065 static void 1066 xl_reset(sc) 1067 struct xl_softc *sc; 1068 { 1069 int i; 1070 1071 XL_SEL_WIN(0); 1072 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1073 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1074 XL_RESETOPT_DISADVFD:0)); 1075 1076 /* 1077 * If we're using memory mapped register mode, pause briefly 1078 * after issuing the reset command before trying to access any 1079 * other registers. With my 3c575C cardbus card, failing to do 1080 * this results in the system locking up while trying to poll 1081 * the command busy bit in the status register. 1082 */ 1083 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1084 DELAY(100000); 1085 1086 for (i = 0; i < XL_TIMEOUT; i++) { 1087 DELAY(10); 1088 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1089 break; 1090 } 1091 1092 if (i == XL_TIMEOUT) 1093 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 1094 1095 /* Reset TX and RX. */ 1096 /* Note: the RX reset takes an absurd amount of time 1097 * on newer versions of the Tornado chips such as those 1098 * on the 3c905CX and newer 3c908C cards. We wait an 1099 * extra amount of time so that xl_wait() doesn't complain 1100 * and annoy the users. 1101 */ 1102 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1103 DELAY(100000); 1104 xl_wait(sc); 1105 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1106 xl_wait(sc); 1107 1108 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1109 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1110 XL_SEL_WIN(2); 1111 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1112 XL_W2_RESET_OPTIONS) 1113 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1114 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1115 ); 1116 } 1117 1118 /* Wait a little while for the chip to get its brains in order. */ 1119 DELAY(100000); 1120 return; 1121 } 1122 1123 /* 1124 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1125 * IDs against our list and return a device name if we find a match. 1126 */ 1127 static int 1128 xl_probe(dev) 1129 device_t dev; 1130 { 1131 struct xl_type *t; 1132 1133 t = xl_devs; 1134 1135 while(t->xl_name != NULL) { 1136 if ((pci_get_vendor(dev) == t->xl_vid) && 1137 (pci_get_device(dev) == t->xl_did)) { 1138 device_set_desc(dev, t->xl_name); 1139 return(0); 1140 } 1141 t++; 1142 } 1143 1144 return(ENXIO); 1145 } 1146 1147 /* 1148 * This routine is a kludge to work around possible hardware faults 1149 * or manufacturing defects that can cause the media options register 1150 * (or reset options register, as it's called for the first generation 1151 * 3c90x adapters) to return an incorrect result. I have encountered 1152 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1153 * which doesn't have any of the 'mediaopt' bits set. This screws up 1154 * the attach routine pretty badly because it doesn't know what media 1155 * to look for. If we find ourselves in this predicament, this routine 1156 * will try to guess the media options values and warn the user of a 1157 * possible manufacturing defect with his adapter/system/whatever. 1158 */ 1159 static void 1160 xl_mediacheck(sc) 1161 struct xl_softc *sc; 1162 { 1163 struct ifnet *ifp = &sc->arpcom.ac_if; 1164 1165 /* 1166 * If some of the media options bits are set, assume they are 1167 * correct. If not, try to figure it out down below. 1168 * XXX I should check for 10baseFL, but I don't have an adapter 1169 * to test with. 1170 */ 1171 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1172 /* 1173 * Check the XCVR value. If it's not in the normal range 1174 * of values, we need to fake it up here. 1175 */ 1176 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1177 return; 1178 else { 1179 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1180 sc->xl_xcvr); 1181 if_printf(ifp, 1182 "choosing new default based on card type\n"); 1183 } 1184 } else { 1185 if (sc->xl_type == XL_TYPE_905B && 1186 sc->xl_media & XL_MEDIAOPT_10FL) 1187 return; 1188 if_printf(ifp, "WARNING: no media options bits set in " 1189 "the media options register!!\n"); 1190 if_printf(ifp, "this could be a manufacturing defect in " 1191 "your adapter or system\n"); 1192 if_printf(ifp, "attempting to guess media type; you " 1193 "should probably consult your vendor\n"); 1194 } 1195 1196 xl_choose_xcvr(sc, 1); 1197 } 1198 1199 static void 1200 xl_choose_xcvr(sc, verbose) 1201 struct xl_softc *sc; 1202 int verbose; 1203 { 1204 struct ifnet *ifp = &sc->arpcom.ac_if; 1205 u_int16_t devid; 1206 1207 /* 1208 * Read the device ID from the EEPROM. 1209 * This is what's loaded into the PCI device ID register, so it has 1210 * to be correct otherwise we wouldn't have gotten this far. 1211 */ 1212 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1213 1214 switch(devid) { 1215 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1216 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1217 sc->xl_media = XL_MEDIAOPT_BT; 1218 sc->xl_xcvr = XL_XCVR_10BT; 1219 if (verbose) 1220 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1221 break; 1222 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1223 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1224 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1225 sc->xl_xcvr = XL_XCVR_10BT; 1226 if (verbose) 1227 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1228 break; 1229 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1230 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1231 sc->xl_xcvr = XL_XCVR_10BT; 1232 if (verbose) 1233 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1234 break; 1235 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1236 sc->xl_media = XL_MEDIAOPT_10FL; 1237 sc->xl_xcvr = XL_XCVR_AUI; 1238 if (verbose) 1239 if_printf(ifp, "guessing 10baseFL\n"); 1240 break; 1241 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1242 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1243 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1244 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1245 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1246 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1247 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1248 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1249 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1250 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1251 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1252 sc->xl_media = XL_MEDIAOPT_MII; 1253 sc->xl_xcvr = XL_XCVR_MII; 1254 if (verbose) 1255 if_printf(ifp, "guessing MII\n"); 1256 break; 1257 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1258 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1259 sc->xl_media = XL_MEDIAOPT_BT4; 1260 sc->xl_xcvr = XL_XCVR_MII; 1261 if (verbose) 1262 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1263 break; 1264 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1265 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1266 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1267 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1268 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1269 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1270 sc->xl_media = XL_MEDIAOPT_BTX; 1271 sc->xl_xcvr = XL_XCVR_AUTO; 1272 if (verbose) 1273 if_printf(ifp, "guessing 10/100 internal\n"); 1274 break; 1275 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1276 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1277 sc->xl_xcvr = XL_XCVR_AUTO; 1278 if (verbose) 1279 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1280 break; 1281 default: 1282 if_printf(ifp, 1283 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1284 sc->xl_media = XL_MEDIAOPT_BT; 1285 break; 1286 } 1287 1288 return; 1289 } 1290 1291 /* 1292 * Attach the interface. Allocate softc structures, do ifmedia 1293 * setup and ethernet/BPF attach. 1294 */ 1295 static int 1296 xl_attach(dev) 1297 device_t dev; 1298 { 1299 u_char eaddr[ETHER_ADDR_LEN]; 1300 u_int16_t xcvr[2]; 1301 u_int32_t command; 1302 struct xl_softc *sc; 1303 struct ifnet *ifp; 1304 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1305 int unit, error = 0, rid, res; 1306 1307 sc = device_get_softc(dev); 1308 unit = device_get_unit(dev); 1309 1310 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1311 1312 sc->xl_flags = 0; 1313 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1314 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1315 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1316 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1317 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1318 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1319 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1320 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 || 1321 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1322 sc->xl_flags |= XL_FLAG_8BITROM; 1323 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1324 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1325 1326 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1327 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1328 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1329 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1330 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1331 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1332 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1333 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1334 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1335 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1336 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1337 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1338 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1339 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1340 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1341 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1342 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1343 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1344 XL_FLAG_INVERT_LED_PWR; 1345 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1346 sc->xl_flags |= XL_FLAG_PHYOK; 1347 #ifndef BURN_BRIDGES 1348 /* 1349 * If this is a 3c905B, we have to check one extra thing. 1350 * The 905B supports power management and may be placed in 1351 * a low-power mode (D3 mode), typically by certain operating 1352 * systems which shall not be named. The PCI BIOS is supposed 1353 * to reset the NIC and bring it out of low-power mode, but 1354 * some do not. Consequently, we have to see if this chip 1355 * supports power management, and if so, make sure it's not 1356 * in low-power mode. If power management is available, the 1357 * capid byte will be 0x01. 1358 * 1359 * I _think_ that what actually happens is that the chip 1360 * loses its PCI configuration during the transition from 1361 * D3 back to D0; this means that it should be possible for 1362 * us to save the PCI iobase, membase and IRQ, put the chip 1363 * back in the D0 state, then restore the PCI config ourselves. 1364 */ 1365 1366 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1367 u_int32_t iobase, membase, irq; 1368 1369 /* Save important PCI config data. */ 1370 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1371 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1372 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1373 1374 /* Reset the power state. */ 1375 device_printf(dev, "chip is in D%d power mode " 1376 "-- setting to D0\n", pci_get_powerstate(dev)); 1377 1378 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1379 1380 /* Restore PCI config data. */ 1381 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1382 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1383 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1384 } 1385 #endif 1386 /* 1387 * Map control/status registers. 1388 */ 1389 pci_enable_busmaster(dev); 1390 pci_enable_io(dev, SYS_RES_IOPORT); 1391 pci_enable_io(dev, SYS_RES_MEMORY); 1392 command = pci_read_config(dev, PCIR_COMMAND, 4); 1393 1394 if (!(command & PCIM_CMD_PORTEN) && !(command & PCIM_CMD_MEMEN)) { 1395 device_printf(dev, 1396 "failed to enable I/O ports and memory mappings!\n"); 1397 error = ENXIO; 1398 goto fail; 1399 } 1400 1401 rid = XL_PCI_LOMEM; 1402 res = SYS_RES_MEMORY; 1403 1404 #if 0 1405 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1406 #endif 1407 1408 if (sc->xl_res != NULL) { 1409 sc->xl_flags |= XL_FLAG_USE_MMIO; 1410 if (bootverbose) 1411 device_printf(dev, "using memory mapped I/O\n"); 1412 } else { 1413 rid = XL_PCI_LOIO; 1414 res = SYS_RES_IOPORT; 1415 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1416 if (sc->xl_res == NULL) { 1417 device_printf(dev, "couldn't map ports/memory\n"); 1418 error = ENXIO; 1419 goto fail; 1420 } 1421 if (bootverbose) 1422 device_printf(dev, "using port I/O\n"); 1423 } 1424 1425 sc->xl_btag = rman_get_bustag(sc->xl_res); 1426 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1427 1428 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1429 rid = XL_PCI_FUNCMEM; 1430 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1431 RF_ACTIVE); 1432 1433 if (sc->xl_fres == NULL) { 1434 device_printf(dev, "couldn't map ports/memory\n"); 1435 error = ENXIO; 1436 goto fail; 1437 } 1438 1439 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1440 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1441 } 1442 1443 /* Allocate interrupt */ 1444 rid = 0; 1445 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1446 RF_SHAREABLE | RF_ACTIVE); 1447 if (sc->xl_irq == NULL) { 1448 device_printf(dev, "couldn't map interrupt\n"); 1449 error = ENXIO; 1450 goto fail; 1451 } 1452 1453 sc->xl_flags |= XL_FLAG_ATTACH_MAPPED; 1454 1455 ifp = &sc->arpcom.ac_if; 1456 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1457 1458 /* Reset the adapter. */ 1459 xl_reset(sc); 1460 1461 /* 1462 * Get station address from the EEPROM. 1463 */ 1464 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1465 device_printf(dev, "failed to read station address\n"); 1466 error = ENXIO; 1467 goto fail; 1468 } 1469 1470 callout_init(&sc->xl_stat_timer); 1471 1472 /* 1473 * Now allocate a tag for the DMA descriptor lists and a chunk 1474 * of DMA-able memory based on the tag. Also obtain the DMA 1475 * addresses of the RX and TX ring, which we'll need later. 1476 * All of our lists are allocated as a contiguous block 1477 * of memory. 1478 */ 1479 error = bus_dma_tag_create(NULL, 8, 0, 1480 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1481 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, 1482 &sc->xl_ldata.xl_rx_tag); 1483 if (error) { 1484 device_printf(dev, "failed to allocate rx dma tag\n"); 1485 goto fail; 1486 } 1487 1488 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1489 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT, 1490 &sc->xl_ldata.xl_rx_dmamap); 1491 if (error) { 1492 device_printf(dev, "no memory for rx list buffers!\n"); 1493 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1494 sc->xl_ldata.xl_rx_tag = NULL; 1495 goto fail; 1496 } 1497 1498 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1499 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1500 XL_RX_LIST_SZ, xl_dma_map_addr, 1501 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1502 if (error) { 1503 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1504 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1505 sc->xl_ldata.xl_rx_dmamap); 1506 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1507 sc->xl_ldata.xl_rx_tag = NULL; 1508 goto fail; 1509 } 1510 1511 error = bus_dma_tag_create(NULL, 8, 0, 1512 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1513 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, 1514 &sc->xl_ldata.xl_tx_tag); 1515 if (error) { 1516 device_printf(dev, "failed to allocate tx dma tag\n"); 1517 goto fail; 1518 } 1519 1520 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1521 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT, 1522 &sc->xl_ldata.xl_tx_dmamap); 1523 if (error) { 1524 device_printf(dev, "no memory for list buffers!\n"); 1525 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1526 sc->xl_ldata.xl_tx_tag = NULL; 1527 goto fail; 1528 } 1529 1530 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1531 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1532 XL_TX_LIST_SZ, xl_dma_map_addr, 1533 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1534 if (error) { 1535 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1536 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1537 sc->xl_ldata.xl_tx_dmamap); 1538 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1539 sc->xl_ldata.xl_tx_tag = NULL; 1540 goto fail; 1541 } 1542 1543 /* 1544 * Allocate a DMA tag for the mapping of mbufs. 1545 */ 1546 error = bus_dma_tag_create(NULL, 1, 0, 1547 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1548 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, 1549 &sc->xl_mtag); 1550 if (error) { 1551 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1552 goto fail; 1553 } 1554 1555 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 1556 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 1557 1558 /* We need a spare DMA map for the RX ring. */ 1559 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1560 if (error) 1561 goto fail; 1562 1563 /* 1564 * Figure out the card type. 3c905B adapters have the 1565 * 'supportsNoTxLength' bit set in the capabilities 1566 * word in the EEPROM. 1567 * Note: my 3c575C cardbus card lies. It returns a value 1568 * of 0x1578 for its capabilities word, which is somewhat 1569 * nonsensical. Another way to distinguish a 3c90x chip 1570 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1571 * bit. This will only be set for 3c90x boomerage chips. 1572 */ 1573 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1574 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1575 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1576 sc->xl_type = XL_TYPE_905B; 1577 else 1578 sc->xl_type = XL_TYPE_90X; 1579 1580 ifp->if_softc = sc; 1581 ifp->if_mtu = ETHERMTU; 1582 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1583 ifp->if_ioctl = xl_ioctl; 1584 ifp->if_capabilities = 0; 1585 if (sc->xl_type == XL_TYPE_905B) { 1586 ifp->if_start = xl_start_90xB; 1587 ifp->if_capabilities |= IFCAP_HWCSUM; 1588 } else { 1589 ifp->if_start = xl_start; 1590 } 1591 ifp->if_watchdog = xl_watchdog; 1592 ifp->if_init = xl_init; 1593 ifp->if_baudrate = 10000000; 1594 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1595 ifq_set_ready(&ifp->if_snd); 1596 /* 1597 * NOTE: features disabled by default. This seems to corrupt 1598 * tx packet data one out of a million packets or so and then 1599 * generates a good checksum so the receiver doesn't 1600 * know the packet is bad 1601 */ 1602 ifp->if_capenable = 0; /*ifp->if_capabilities;*/ 1603 if (ifp->if_capenable & IFCAP_TXCSUM) 1604 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1605 1606 /* 1607 * Now we have to see what sort of media we have. 1608 * This includes probing for an MII interace and a 1609 * possible PHY. 1610 */ 1611 XL_SEL_WIN(3); 1612 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1613 if (bootverbose) 1614 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1615 1616 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1617 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1618 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1619 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1620 1621 xl_mediacheck(sc); 1622 1623 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1624 || sc->xl_media & XL_MEDIAOPT_BT4) { 1625 if (bootverbose) 1626 if_printf(ifp, "found MII/AUTO\n"); 1627 xl_setcfg(sc); 1628 if (mii_phy_probe(dev, &sc->xl_miibus, 1629 xl_ifmedia_upd, xl_ifmedia_sts)) { 1630 if_printf(ifp, "no PHY found!\n"); 1631 error = ENXIO; 1632 goto fail; 1633 } 1634 1635 goto done; 1636 } 1637 1638 /* 1639 * Sanity check. If the user has selected "auto" and this isn't 1640 * a 10/100 card of some kind, we need to force the transceiver 1641 * type to something sane. 1642 */ 1643 if (sc->xl_xcvr == XL_XCVR_AUTO) 1644 xl_choose_xcvr(sc, bootverbose); 1645 1646 /* 1647 * Do ifmedia setup. 1648 */ 1649 if (sc->xl_media & XL_MEDIAOPT_BT) { 1650 if (bootverbose) 1651 if_printf(ifp, "found 10baseT\n"); 1652 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1653 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1654 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1655 ifmedia_add(&sc->ifmedia, 1656 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1657 } 1658 1659 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1660 /* 1661 * Check for a 10baseFL board in disguise. 1662 */ 1663 if (sc->xl_type == XL_TYPE_905B && 1664 sc->xl_media == XL_MEDIAOPT_10FL) { 1665 if (bootverbose) 1666 if_printf(ifp, "found 10baseFL\n"); 1667 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1668 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1669 0, NULL); 1670 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1671 ifmedia_add(&sc->ifmedia, 1672 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1673 } else { 1674 if (bootverbose) 1675 if_printf(ifp, "found AUI\n"); 1676 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1677 } 1678 } 1679 1680 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1681 if (bootverbose) 1682 if_printf(ifp, "found BNC\n"); 1683 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1684 } 1685 1686 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1687 if (bootverbose) 1688 if_printf(ifp, "found 100baseFX\n"); 1689 ifp->if_baudrate = 100000000; 1690 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1691 } 1692 1693 /* Choose a default media. */ 1694 switch(sc->xl_xcvr) { 1695 case XL_XCVR_10BT: 1696 media = IFM_ETHER|IFM_10_T; 1697 xl_setmode(sc, media); 1698 break; 1699 case XL_XCVR_AUI: 1700 if (sc->xl_type == XL_TYPE_905B && 1701 sc->xl_media == XL_MEDIAOPT_10FL) { 1702 media = IFM_ETHER|IFM_10_FL; 1703 xl_setmode(sc, media); 1704 } else { 1705 media = IFM_ETHER|IFM_10_5; 1706 xl_setmode(sc, media); 1707 } 1708 break; 1709 case XL_XCVR_COAX: 1710 media = IFM_ETHER|IFM_10_2; 1711 xl_setmode(sc, media); 1712 break; 1713 case XL_XCVR_AUTO: 1714 case XL_XCVR_100BTX: 1715 case XL_XCVR_MII: 1716 /* Chosen by miibus */ 1717 break; 1718 case XL_XCVR_100BFX: 1719 media = IFM_ETHER|IFM_100_FX; 1720 break; 1721 default: 1722 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1723 /* 1724 * This will probably be wrong, but it prevents 1725 * the ifmedia code from panicking. 1726 */ 1727 media = IFM_ETHER|IFM_10_T; 1728 break; 1729 } 1730 1731 if (sc->xl_miibus == NULL) 1732 ifmedia_set(&sc->ifmedia, media); 1733 1734 done: 1735 1736 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1737 XL_SEL_WIN(0); 1738 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1739 } 1740 1741 /* 1742 * Call MI attach routine. 1743 */ 1744 ether_ifattach(ifp, eaddr); 1745 1746 /* 1747 * Tell the upper layer(s) we support long frames. 1748 */ 1749 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1750 1751 /* Hook interrupt last to avoid having to lock softc */ 1752 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1753 xl_intr, sc, &sc->xl_intrhand, NULL); 1754 if (error) { 1755 if_printf(ifp, "couldn't set up irq\n"); 1756 ether_ifdetach(ifp); 1757 goto fail; 1758 } 1759 1760 fail: 1761 if (error) 1762 xl_detach(dev); 1763 1764 return(error); 1765 } 1766 1767 /* 1768 * Shutdown hardware and free up resources. This can be called any 1769 * time after the mutex has been initialized. It is called in both 1770 * the error case in attach and the normal detach case so it needs 1771 * to be careful about only freeing resources that have actually been 1772 * allocated. 1773 */ 1774 static int 1775 xl_detach(dev) 1776 device_t dev; 1777 { 1778 struct xl_softc *sc; 1779 struct ifnet *ifp; 1780 int rid, res; 1781 1782 sc = device_get_softc(dev); 1783 ifp = &sc->arpcom.ac_if; 1784 1785 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1786 rid = XL_PCI_LOMEM; 1787 res = SYS_RES_MEMORY; 1788 } else { 1789 rid = XL_PCI_LOIO; 1790 res = SYS_RES_IOPORT; 1791 } 1792 1793 crit_enter(); 1794 1795 /* 1796 * Only try to communicate with the device if we were able to map 1797 * the ports. This flag is set before ether_ifattach() so it also 1798 * governs our call to ether_ifdetach(). 1799 */ 1800 if (sc->xl_flags & XL_FLAG_ATTACH_MAPPED) { 1801 xl_reset(sc); 1802 xl_stop(sc); 1803 ether_ifdetach(ifp); 1804 } 1805 1806 if (sc->xl_miibus) 1807 device_delete_child(dev, sc->xl_miibus); 1808 bus_generic_detach(dev); 1809 ifmedia_removeall(&sc->ifmedia); 1810 1811 if (sc->xl_intrhand) 1812 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1813 1814 crit_exit(); 1815 1816 if (sc->xl_irq) 1817 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1818 if (sc->xl_fres != NULL) 1819 bus_release_resource(dev, SYS_RES_MEMORY, 1820 XL_PCI_FUNCMEM, sc->xl_fres); 1821 if (sc->xl_res) 1822 bus_release_resource(dev, res, rid, sc->xl_res); 1823 1824 if (sc->xl_mtag) { 1825 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1826 bus_dma_tag_destroy(sc->xl_mtag); 1827 } 1828 if (sc->xl_ldata.xl_rx_tag) { 1829 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1830 sc->xl_ldata.xl_rx_dmamap); 1831 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1832 sc->xl_ldata.xl_rx_dmamap); 1833 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1834 } 1835 if (sc->xl_ldata.xl_tx_tag) { 1836 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1837 sc->xl_ldata.xl_tx_dmamap); 1838 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1839 sc->xl_ldata.xl_tx_dmamap); 1840 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1841 } 1842 1843 return(0); 1844 } 1845 1846 /* 1847 * Initialize the transmit descriptors. 1848 */ 1849 static int 1850 xl_list_tx_init(sc) 1851 struct xl_softc *sc; 1852 { 1853 struct xl_chain_data *cd; 1854 struct xl_list_data *ld; 1855 int error, i; 1856 1857 cd = &sc->xl_cdata; 1858 ld = &sc->xl_ldata; 1859 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1860 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1861 error = bus_dmamap_create(sc->xl_mtag, 0, 1862 &cd->xl_tx_chain[i].xl_map); 1863 if (error) 1864 return(error); 1865 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1866 i * sizeof(struct xl_list); 1867 if (i == (XL_TX_LIST_CNT - 1)) 1868 cd->xl_tx_chain[i].xl_next = NULL; 1869 else 1870 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1871 } 1872 1873 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1874 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1875 1876 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1877 return(0); 1878 } 1879 1880 /* 1881 * Initialize the transmit descriptors. 1882 */ 1883 static int 1884 xl_list_tx_init_90xB(sc) 1885 struct xl_softc *sc; 1886 { 1887 struct xl_chain_data *cd; 1888 struct xl_list_data *ld; 1889 int error, i; 1890 1891 cd = &sc->xl_cdata; 1892 ld = &sc->xl_ldata; 1893 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1894 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1895 error = bus_dmamap_create(sc->xl_mtag, 0, 1896 &cd->xl_tx_chain[i].xl_map); 1897 if (error) 1898 return(error); 1899 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1900 i * sizeof(struct xl_list); 1901 if (i == (XL_TX_LIST_CNT - 1)) 1902 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1903 else 1904 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1905 if (i == 0) 1906 cd->xl_tx_chain[i].xl_prev = 1907 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1908 else 1909 cd->xl_tx_chain[i].xl_prev = 1910 &cd->xl_tx_chain[i - 1]; 1911 } 1912 1913 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1914 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1915 1916 cd->xl_tx_prod = 1; 1917 cd->xl_tx_cons = 1; 1918 cd->xl_tx_cnt = 0; 1919 1920 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1921 return(0); 1922 } 1923 1924 /* 1925 * Initialize the RX descriptors and allocate mbufs for them. Note that 1926 * we arrange the descriptors in a closed ring, so that the last descriptor 1927 * points back to the first. 1928 */ 1929 static int 1930 xl_list_rx_init(sc) 1931 struct xl_softc *sc; 1932 { 1933 struct xl_chain_data *cd; 1934 struct xl_list_data *ld; 1935 int error, i, next; 1936 u_int32_t nextptr; 1937 1938 cd = &sc->xl_cdata; 1939 ld = &sc->xl_ldata; 1940 1941 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1942 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1943 error = bus_dmamap_create(sc->xl_mtag, 0, 1944 &cd->xl_rx_chain[i].xl_map); 1945 if (error) 1946 return(error); 1947 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1948 if (error) 1949 return(error); 1950 if (i == (XL_RX_LIST_CNT - 1)) 1951 next = 0; 1952 else 1953 next = i + 1; 1954 nextptr = ld->xl_rx_dmaaddr + 1955 next * sizeof(struct xl_list_onefrag); 1956 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1957 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1958 } 1959 1960 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1961 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1962 1963 return(0); 1964 } 1965 1966 /* 1967 * Initialize an RX descriptor and attach an MBUF cluster. 1968 * If we fail to do so, we need to leave the old mbuf and 1969 * the old DMA map untouched so that it can be reused. 1970 */ 1971 static int 1972 xl_newbuf(sc, c) 1973 struct xl_softc *sc; 1974 struct xl_chain_onefrag *c; 1975 { 1976 struct mbuf *m_new = NULL; 1977 bus_dmamap_t map; 1978 int error; 1979 u_int32_t baddr; 1980 1981 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1982 if (m_new == NULL) 1983 return(ENOBUFS); 1984 1985 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1986 1987 /* Force longword alignment for packet payload. */ 1988 m_adj(m_new, ETHER_ALIGN); 1989 1990 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 1991 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 1992 if (error) { 1993 m_freem(m_new); 1994 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 1995 error); 1996 return(error); 1997 } 1998 1999 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 2000 map = c->xl_map; 2001 c->xl_map = sc->xl_tmpmap; 2002 sc->xl_tmpmap = map; 2003 c->xl_mbuf = m_new; 2004 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 2005 c->xl_ptr->xl_status = 0; 2006 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 2007 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 2008 return(0); 2009 } 2010 2011 static int 2012 xl_rx_resync(sc) 2013 struct xl_softc *sc; 2014 { 2015 struct xl_chain_onefrag *pos; 2016 int i; 2017 2018 pos = sc->xl_cdata.xl_rx_head; 2019 2020 for (i = 0; i < XL_RX_LIST_CNT; i++) { 2021 if (pos->xl_ptr->xl_status) 2022 break; 2023 pos = pos->xl_next; 2024 } 2025 2026 if (i == XL_RX_LIST_CNT) 2027 return(0); 2028 2029 sc->xl_cdata.xl_rx_head = pos; 2030 2031 return(EAGAIN); 2032 } 2033 2034 /* 2035 * A frame has been uploaded: pass the resulting mbuf chain up to 2036 * the higher level protocols. 2037 */ 2038 static void 2039 xl_rxeof(sc) 2040 struct xl_softc *sc; 2041 { 2042 struct mbuf *m; 2043 struct ifnet *ifp; 2044 struct xl_chain_onefrag *cur_rx; 2045 int total_len = 0; 2046 u_int32_t rxstat; 2047 2048 ifp = &sc->arpcom.ac_if; 2049 2050 again: 2051 2052 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2053 BUS_DMASYNC_POSTREAD); 2054 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2055 cur_rx = sc->xl_cdata.xl_rx_head; 2056 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2057 total_len = rxstat & XL_RXSTAT_LENMASK; 2058 2059 /* 2060 * Since we have told the chip to allow large frames, 2061 * we need to trap giant frame errors in software. We allow 2062 * a little more than the normal frame size to account for 2063 * frames with VLAN tags. 2064 */ 2065 if (total_len > XL_MAX_FRAMELEN) 2066 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2067 2068 /* 2069 * If an error occurs, update stats, clear the 2070 * status word and leave the mbuf cluster in place: 2071 * it should simply get re-used next time this descriptor 2072 * comes up in the ring. 2073 */ 2074 if (rxstat & XL_RXSTAT_UP_ERROR) { 2075 ifp->if_ierrors++; 2076 cur_rx->xl_ptr->xl_status = 0; 2077 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2078 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2079 continue; 2080 } 2081 2082 /* 2083 * If the error bit was not set, the upload complete 2084 * bit should be set which means we have a valid packet. 2085 * If not, something truly strange has happened. 2086 */ 2087 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2088 if_printf(ifp, 2089 "bad receive status -- packet dropped\n"); 2090 ifp->if_ierrors++; 2091 cur_rx->xl_ptr->xl_status = 0; 2092 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2093 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2094 continue; 2095 } 2096 2097 /* No errors; receive the packet. */ 2098 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2099 BUS_DMASYNC_POSTREAD); 2100 m = cur_rx->xl_mbuf; 2101 2102 /* 2103 * Try to conjure up a new mbuf cluster. If that 2104 * fails, it means we have an out of memory condition and 2105 * should leave the buffer in place and continue. This will 2106 * result in a lost packet, but there's little else we 2107 * can do in this situation. 2108 */ 2109 if (xl_newbuf(sc, cur_rx)) { 2110 ifp->if_ierrors++; 2111 cur_rx->xl_ptr->xl_status = 0; 2112 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2113 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2114 continue; 2115 } 2116 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2117 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2118 2119 ifp->if_ipackets++; 2120 m->m_pkthdr.rcvif = ifp; 2121 m->m_pkthdr.len = m->m_len = total_len; 2122 2123 if (ifp->if_capenable & IFCAP_RXCSUM) { 2124 /* Do IP checksum checking. */ 2125 if (rxstat & XL_RXSTAT_IPCKOK) 2126 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2127 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2128 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2129 if ((rxstat & XL_RXSTAT_TCPCOK && 2130 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2131 (rxstat & XL_RXSTAT_UDPCKOK && 2132 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2133 m->m_pkthdr.csum_flags |= 2134 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2135 m->m_pkthdr.csum_data = 0xffff; 2136 } 2137 } 2138 2139 (*ifp->if_input)(ifp, m); 2140 } 2141 2142 /* 2143 * Handle the 'end of channel' condition. When the upload 2144 * engine hits the end of the RX ring, it will stall. This 2145 * is our cue to flush the RX ring, reload the uplist pointer 2146 * register and unstall the engine. 2147 * XXX This is actually a little goofy. With the ThunderLAN 2148 * chip, you get an interrupt when the receiver hits the end 2149 * of the receive ring, which tells you exactly when you 2150 * you need to reload the ring pointer. Here we have to 2151 * fake it. I'm mad at myself for not being clever enough 2152 * to avoid the use of a goto here. 2153 */ 2154 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2155 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2157 xl_wait(sc); 2158 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2159 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2160 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2161 goto again; 2162 } 2163 2164 return; 2165 } 2166 2167 /* 2168 * A frame was downloaded to the chip. It's safe for us to clean up 2169 * the list buffers. 2170 */ 2171 static void 2172 xl_txeof(sc) 2173 struct xl_softc *sc; 2174 { 2175 struct xl_chain *cur_tx; 2176 struct ifnet *ifp; 2177 2178 ifp = &sc->arpcom.ac_if; 2179 2180 /* Clear the timeout timer. */ 2181 ifp->if_timer = 0; 2182 2183 /* 2184 * Go through our tx list and free mbufs for those 2185 * frames that have been uploaded. Note: the 3c905B 2186 * sets a special bit in the status word to let us 2187 * know that a frame has been downloaded, but the 2188 * original 3c900/3c905 adapters don't do that. 2189 * Consequently, we have to use a different test if 2190 * xl_type != XL_TYPE_905B. 2191 */ 2192 while(sc->xl_cdata.xl_tx_head != NULL) { 2193 cur_tx = sc->xl_cdata.xl_tx_head; 2194 2195 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2196 break; 2197 2198 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2199 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2200 BUS_DMASYNC_POSTWRITE); 2201 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2202 m_freem(cur_tx->xl_mbuf); 2203 cur_tx->xl_mbuf = NULL; 2204 ifp->if_opackets++; 2205 2206 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2207 sc->xl_cdata.xl_tx_free = cur_tx; 2208 } 2209 2210 if (sc->xl_cdata.xl_tx_head == NULL) { 2211 ifp->if_flags &= ~IFF_OACTIVE; 2212 sc->xl_cdata.xl_tx_tail = NULL; 2213 } else { 2214 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2215 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2216 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2217 sc->xl_cdata.xl_tx_head->xl_phys); 2218 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2219 } 2220 } 2221 2222 return; 2223 } 2224 2225 static void 2226 xl_txeof_90xB(sc) 2227 struct xl_softc *sc; 2228 { 2229 struct xl_chain *cur_tx = NULL; 2230 struct ifnet *ifp; 2231 int idx; 2232 2233 ifp = &sc->arpcom.ac_if; 2234 2235 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2236 BUS_DMASYNC_POSTREAD); 2237 idx = sc->xl_cdata.xl_tx_cons; 2238 while(idx != sc->xl_cdata.xl_tx_prod) { 2239 2240 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2241 2242 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2243 XL_TXSTAT_DL_COMPLETE)) 2244 break; 2245 2246 if (cur_tx->xl_mbuf != NULL) { 2247 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2248 BUS_DMASYNC_POSTWRITE); 2249 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2250 m_freem(cur_tx->xl_mbuf); 2251 cur_tx->xl_mbuf = NULL; 2252 } 2253 2254 ifp->if_opackets++; 2255 2256 sc->xl_cdata.xl_tx_cnt--; 2257 XL_INC(idx, XL_TX_LIST_CNT); 2258 ifp->if_timer = 0; 2259 } 2260 2261 sc->xl_cdata.xl_tx_cons = idx; 2262 2263 if (cur_tx != NULL) 2264 ifp->if_flags &= ~IFF_OACTIVE; 2265 2266 return; 2267 } 2268 2269 /* 2270 * TX 'end of channel' interrupt handler. Actually, we should 2271 * only get a 'TX complete' interrupt if there's a transmit error, 2272 * so this is really TX error handler. 2273 */ 2274 static void 2275 xl_txeoc(sc) 2276 struct xl_softc *sc; 2277 { 2278 struct ifnet *ifp = &sc->arpcom.ac_if; 2279 u_int8_t txstat; 2280 2281 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2282 if (txstat & XL_TXSTATUS_UNDERRUN || 2283 txstat & XL_TXSTATUS_JABBER || 2284 txstat & XL_TXSTATUS_RECLAIM) { 2285 if_printf(ifp, "transmission error: %x\n", txstat); 2286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2287 xl_wait(sc); 2288 if (sc->xl_type == XL_TYPE_905B) { 2289 if (sc->xl_cdata.xl_tx_cnt) { 2290 int i; 2291 struct xl_chain *c; 2292 i = sc->xl_cdata.xl_tx_cons; 2293 c = &sc->xl_cdata.xl_tx_chain[i]; 2294 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2295 c->xl_phys); 2296 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2297 } 2298 } else { 2299 if (sc->xl_cdata.xl_tx_head != NULL) 2300 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2301 sc->xl_cdata.xl_tx_head->xl_phys); 2302 } 2303 /* 2304 * Remember to set this for the 2305 * first generation 3c90X chips. 2306 */ 2307 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2308 if (txstat & XL_TXSTATUS_UNDERRUN && 2309 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2310 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2311 if_printf(ifp, "tx underrun, increasing tx start" 2312 " threshold to %d bytes\n", 2313 sc->xl_tx_thresh); 2314 } 2315 CSR_WRITE_2(sc, XL_COMMAND, 2316 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2317 if (sc->xl_type == XL_TYPE_905B) { 2318 CSR_WRITE_2(sc, XL_COMMAND, 2319 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2320 } 2321 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2322 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2323 } else { 2324 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2325 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2326 } 2327 /* 2328 * Write an arbitrary byte to the TX_STATUS register 2329 * to clear this interrupt/error and advance to the next. 2330 */ 2331 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2332 } 2333 2334 return; 2335 } 2336 2337 static void 2338 xl_intr(arg) 2339 void *arg; 2340 { 2341 struct xl_softc *sc; 2342 struct ifnet *ifp; 2343 u_int16_t status; 2344 2345 sc = arg; 2346 ifp = &sc->arpcom.ac_if; 2347 2348 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2349 2350 CSR_WRITE_2(sc, XL_COMMAND, 2351 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2352 2353 if (status & XL_STAT_UP_COMPLETE) { 2354 int curpkts; 2355 2356 curpkts = ifp->if_ipackets; 2357 xl_rxeof(sc); 2358 if (curpkts == ifp->if_ipackets) { 2359 while (xl_rx_resync(sc)) 2360 xl_rxeof(sc); 2361 } 2362 } 2363 2364 if (status & XL_STAT_DOWN_COMPLETE) { 2365 if (sc->xl_type == XL_TYPE_905B) 2366 xl_txeof_90xB(sc); 2367 else 2368 xl_txeof(sc); 2369 } 2370 2371 if (status & XL_STAT_TX_COMPLETE) { 2372 ifp->if_oerrors++; 2373 xl_txeoc(sc); 2374 } 2375 2376 if (status & XL_STAT_ADFAIL) { 2377 xl_reset(sc); 2378 xl_init(sc); 2379 } 2380 2381 if (status & XL_STAT_STATSOFLOW) { 2382 sc->xl_stats_no_timeout = 1; 2383 xl_stats_update(sc); 2384 sc->xl_stats_no_timeout = 0; 2385 } 2386 } 2387 2388 if (!ifq_is_empty(&ifp->if_snd)) 2389 (*ifp->if_start)(ifp); 2390 2391 return; 2392 } 2393 2394 static void 2395 xl_stats_update(xsc) 2396 void *xsc; 2397 { 2398 struct xl_softc *sc; 2399 struct ifnet *ifp; 2400 struct xl_stats xl_stats; 2401 u_int8_t *p; 2402 int i; 2403 struct mii_data *mii = NULL; 2404 2405 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2406 2407 sc = xsc; 2408 ifp = &sc->arpcom.ac_if; 2409 if (sc->xl_miibus != NULL) 2410 mii = device_get_softc(sc->xl_miibus); 2411 2412 p = (u_int8_t *)&xl_stats; 2413 2414 /* Read all the stats registers. */ 2415 XL_SEL_WIN(6); 2416 2417 for (i = 0; i < 16; i++) 2418 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2419 2420 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2421 2422 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2423 xl_stats.xl_tx_single_collision + 2424 xl_stats.xl_tx_late_collision; 2425 2426 /* 2427 * Boomerang and cyclone chips have an extra stats counter 2428 * in window 4 (BadSSD). We have to read this too in order 2429 * to clear out all the stats registers and avoid a statsoflow 2430 * interrupt. 2431 */ 2432 XL_SEL_WIN(4); 2433 CSR_READ_1(sc, XL_W4_BADSSD); 2434 2435 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2436 mii_tick(mii); 2437 2438 XL_SEL_WIN(7); 2439 2440 if (!sc->xl_stats_no_timeout) 2441 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2442 2443 return; 2444 } 2445 2446 /* 2447 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2448 * pointers to the fragment pointers. 2449 */ 2450 static int 2451 xl_encap(sc, c, m_head) 2452 struct xl_softc *sc; 2453 struct xl_chain *c; 2454 struct mbuf *m_head; 2455 { 2456 int error; 2457 u_int32_t status; 2458 struct ifnet *ifp; 2459 2460 ifp = &sc->arpcom.ac_if; 2461 2462 /* 2463 * Start packing the mbufs in this chain into 2464 * the fragment pointers. Stop when we run out 2465 * of fragments or hit the end of the mbuf chain. 2466 */ 2467 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2468 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2469 2470 if (error && error != EFBIG) { 2471 m_freem(m_head); 2472 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2473 return(1); 2474 } 2475 2476 /* 2477 * Handle special case: we used up all 63 fragments, 2478 * but we have more mbufs left in the chain. Copy the 2479 * data into an mbuf cluster. Note that we don't 2480 * bother clearing the values in the other fragment 2481 * pointers/counters; it wouldn't gain us anything, 2482 * and would waste cycles. 2483 */ 2484 if (error) { 2485 struct mbuf *m_new; 2486 2487 m_new = m_defrag(m_head, MB_DONTWAIT); 2488 if (m_new == NULL) { 2489 m_freem(m_head); 2490 return(1); 2491 } else { 2492 m_head = m_new; 2493 } 2494 2495 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2496 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2497 if (error) { 2498 m_freem(m_head); 2499 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2500 return(1); 2501 } 2502 } 2503 2504 if (sc->xl_type == XL_TYPE_905B) { 2505 status = XL_TXSTAT_RND_DEFEAT; 2506 2507 if (m_head->m_pkthdr.csum_flags) { 2508 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2509 status |= XL_TXSTAT_IPCKSUM; 2510 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2511 status |= XL_TXSTAT_TCPCKSUM; 2512 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2513 status |= XL_TXSTAT_UDPCKSUM; 2514 } 2515 c->xl_ptr->xl_status = htole32(status); 2516 } 2517 2518 c->xl_mbuf = m_head; 2519 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2520 return(0); 2521 } 2522 2523 /* 2524 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2525 * to the mbuf data regions directly in the transmit lists. We also save a 2526 * copy of the pointers since the transmit list fragment pointers are 2527 * physical addresses. 2528 */ 2529 static void 2530 xl_start(ifp) 2531 struct ifnet *ifp; 2532 { 2533 struct xl_softc *sc; 2534 struct mbuf *m_head = NULL; 2535 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2536 struct xl_chain *prev_tx; 2537 u_int32_t status; 2538 int error; 2539 2540 sc = ifp->if_softc; 2541 /* 2542 * Check for an available queue slot. If there are none, 2543 * punt. 2544 */ 2545 if (sc->xl_cdata.xl_tx_free == NULL) { 2546 xl_txeoc(sc); 2547 xl_txeof(sc); 2548 if (sc->xl_cdata.xl_tx_free == NULL) { 2549 ifp->if_flags |= IFF_OACTIVE; 2550 return; 2551 } 2552 } 2553 2554 start_tx = sc->xl_cdata.xl_tx_free; 2555 2556 while(sc->xl_cdata.xl_tx_free != NULL) { 2557 m_head = ifq_dequeue(&ifp->if_snd); 2558 if (m_head == NULL) 2559 break; 2560 2561 /* Pick a descriptor off the free list. */ 2562 prev_tx = cur_tx; 2563 cur_tx = sc->xl_cdata.xl_tx_free; 2564 2565 /* Pack the data into the descriptor. */ 2566 error = xl_encap(sc, cur_tx, m_head); 2567 if (error) { 2568 cur_tx = prev_tx; 2569 continue; 2570 } 2571 2572 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2573 cur_tx->xl_next = NULL; 2574 2575 /* Chain it together. */ 2576 if (prev != NULL) { 2577 prev->xl_next = cur_tx; 2578 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2579 } 2580 prev = cur_tx; 2581 2582 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2583 } 2584 2585 /* 2586 * If there are no packets queued, bail. 2587 */ 2588 if (cur_tx == NULL) { 2589 return; 2590 } 2591 2592 /* 2593 * Place the request for the upload interrupt 2594 * in the last descriptor in the chain. This way, if 2595 * we're chaining several packets at once, we'll only 2596 * get an interupt once for the whole chain rather than 2597 * once for each packet. 2598 */ 2599 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2600 XL_TXSTAT_DL_INTR); 2601 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2602 BUS_DMASYNC_PREWRITE); 2603 2604 /* 2605 * Queue the packets. If the TX channel is clear, update 2606 * the downlist pointer register. 2607 */ 2608 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2609 xl_wait(sc); 2610 2611 if (sc->xl_cdata.xl_tx_head != NULL) { 2612 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2613 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2614 htole32(start_tx->xl_phys); 2615 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2616 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2617 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2618 sc->xl_cdata.xl_tx_tail = cur_tx; 2619 } else { 2620 sc->xl_cdata.xl_tx_head = start_tx; 2621 sc->xl_cdata.xl_tx_tail = cur_tx; 2622 } 2623 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2624 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2625 2626 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2627 2628 XL_SEL_WIN(7); 2629 2630 /* 2631 * Set a timeout in case the chip goes out to lunch. 2632 */ 2633 ifp->if_timer = 5; 2634 2635 /* 2636 * XXX Under certain conditions, usually on slower machines 2637 * where interrupts may be dropped, it's possible for the 2638 * adapter to chew up all the buffers in the receive ring 2639 * and stall, without us being able to do anything about it. 2640 * To guard against this, we need to make a pass over the 2641 * RX queue to make sure there aren't any packets pending. 2642 * Doing it here means we can flush the receive ring at the 2643 * same time the chip is DMAing the transmit descriptors we 2644 * just gave it. 2645 * 2646 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2647 * nature of their chips in all their marketing literature; 2648 * we may as well take advantage of it. :) 2649 */ 2650 xl_rxeof(sc); 2651 2652 return; 2653 } 2654 2655 static void 2656 xl_start_90xB(ifp) 2657 struct ifnet *ifp; 2658 { 2659 struct xl_softc *sc; 2660 struct mbuf *m_head = NULL; 2661 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2662 struct xl_chain *prev_tx; 2663 int error, idx; 2664 2665 sc = ifp->if_softc; 2666 2667 if (ifp->if_flags & IFF_OACTIVE) { 2668 return; 2669 } 2670 2671 idx = sc->xl_cdata.xl_tx_prod; 2672 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2673 2674 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2675 2676 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2677 ifp->if_flags |= IFF_OACTIVE; 2678 break; 2679 } 2680 2681 m_head = ifq_dequeue(&ifp->if_snd); 2682 if (m_head == NULL) 2683 break; 2684 2685 prev_tx = cur_tx; 2686 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2687 2688 /* Pack the data into the descriptor. */ 2689 error = xl_encap(sc, cur_tx, m_head); 2690 if (error) { 2691 cur_tx = prev_tx; 2692 continue; 2693 } 2694 2695 /* Chain it together. */ 2696 if (prev != NULL) 2697 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2698 prev = cur_tx; 2699 2700 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2701 2702 XL_INC(idx, XL_TX_LIST_CNT); 2703 sc->xl_cdata.xl_tx_cnt++; 2704 } 2705 2706 /* 2707 * If there are no packets queued, bail. 2708 */ 2709 if (cur_tx == NULL) { 2710 return; 2711 } 2712 2713 /* 2714 * Place the request for the upload interrupt 2715 * in the last descriptor in the chain. This way, if 2716 * we're chaining several packets at once, we'll only 2717 * get an interupt once for the whole chain rather than 2718 * once for each packet. 2719 */ 2720 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2721 XL_TXSTAT_DL_INTR); 2722 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2723 BUS_DMASYNC_PREWRITE); 2724 2725 /* Start transmission */ 2726 sc->xl_cdata.xl_tx_prod = idx; 2727 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2728 2729 /* 2730 * Set a timeout in case the chip goes out to lunch. 2731 */ 2732 ifp->if_timer = 5; 2733 2734 return; 2735 } 2736 2737 static void 2738 xl_init(xsc) 2739 void *xsc; 2740 { 2741 struct xl_softc *sc = xsc; 2742 struct ifnet *ifp = &sc->arpcom.ac_if; 2743 int error, i; 2744 u_int16_t rxfilt = 0; 2745 struct mii_data *mii = NULL; 2746 2747 crit_enter(); 2748 2749 /* 2750 * Cancel pending I/O and free all RX/TX buffers. 2751 */ 2752 xl_stop(sc); 2753 2754 if (sc->xl_miibus == NULL) { 2755 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2756 xl_wait(sc); 2757 } 2758 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2759 xl_wait(sc); 2760 DELAY(10000); 2761 2762 if (sc->xl_miibus != NULL) 2763 mii = device_get_softc(sc->xl_miibus); 2764 2765 /* Init our MAC address */ 2766 XL_SEL_WIN(2); 2767 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2768 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2769 sc->arpcom.ac_enaddr[i]); 2770 } 2771 2772 /* Clear the station mask. */ 2773 for (i = 0; i < 3; i++) 2774 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2775 #ifdef notdef 2776 /* Reset TX and RX. */ 2777 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2778 xl_wait(sc); 2779 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2780 xl_wait(sc); 2781 #endif 2782 /* Init circular RX list. */ 2783 error = xl_list_rx_init(sc); 2784 if (error) { 2785 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2786 error); 2787 xl_stop(sc); 2788 crit_exit(); 2789 return; 2790 } 2791 2792 /* Init TX descriptors. */ 2793 if (sc->xl_type == XL_TYPE_905B) 2794 error = xl_list_tx_init_90xB(sc); 2795 else 2796 error = xl_list_tx_init(sc); 2797 if (error) { 2798 if_printf(ifp, "initialization of the tx ring failed (%d)\n", 2799 error); 2800 xl_stop(sc); 2801 crit_exit(); 2802 return; 2803 } 2804 2805 /* 2806 * Set the TX freethresh value. 2807 * Note that this has no effect on 3c905B "cyclone" 2808 * cards but is required for 3c900/3c905 "boomerang" 2809 * cards in order to enable the download engine. 2810 */ 2811 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2812 2813 /* Set the TX start threshold for best performance. */ 2814 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2816 2817 /* 2818 * If this is a 3c905B, also set the tx reclaim threshold. 2819 * This helps cut down on the number of tx reclaim errors 2820 * that could happen on a busy network. The chip multiplies 2821 * the register value by 16 to obtain the actual threshold 2822 * in bytes, so we divide by 16 when setting the value here. 2823 * The existing threshold value can be examined by reading 2824 * the register at offset 9 in window 5. 2825 */ 2826 if (sc->xl_type == XL_TYPE_905B) { 2827 CSR_WRITE_2(sc, XL_COMMAND, 2828 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2829 } 2830 2831 /* Set RX filter bits. */ 2832 XL_SEL_WIN(5); 2833 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2834 2835 /* Set the individual bit to receive frames for this host only. */ 2836 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2837 2838 /* If we want promiscuous mode, set the allframes bit. */ 2839 if (ifp->if_flags & IFF_PROMISC) { 2840 rxfilt |= XL_RXFILTER_ALLFRAMES; 2841 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2842 } else { 2843 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2845 } 2846 2847 /* 2848 * Set capture broadcast bit to capture broadcast frames. 2849 */ 2850 if (ifp->if_flags & IFF_BROADCAST) { 2851 rxfilt |= XL_RXFILTER_BROADCAST; 2852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2853 } else { 2854 rxfilt &= ~XL_RXFILTER_BROADCAST; 2855 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2856 } 2857 2858 /* 2859 * Program the multicast filter, if necessary. 2860 */ 2861 if (sc->xl_type == XL_TYPE_905B) 2862 xl_setmulti_hash(sc); 2863 else 2864 xl_setmulti(sc); 2865 2866 /* 2867 * Load the address of the RX list. We have to 2868 * stall the upload engine before we can manipulate 2869 * the uplist pointer register, then unstall it when 2870 * we're finished. We also have to wait for the 2871 * stall command to complete before proceeding. 2872 * Note that we have to do this after any RX resets 2873 * have completed since the uplist register is cleared 2874 * by a reset. 2875 */ 2876 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2877 xl_wait(sc); 2878 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2879 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2880 xl_wait(sc); 2881 2882 2883 if (sc->xl_type == XL_TYPE_905B) { 2884 /* Set polling interval */ 2885 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2886 /* Load the address of the TX list */ 2887 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2888 xl_wait(sc); 2889 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2890 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2892 xl_wait(sc); 2893 } 2894 2895 /* 2896 * If the coax transceiver is on, make sure to enable 2897 * the DC-DC converter. 2898 */ 2899 XL_SEL_WIN(3); 2900 if (sc->xl_xcvr == XL_XCVR_COAX) 2901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2902 else 2903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2904 2905 /* 2906 * increase packet size to allow reception of 802.1q or ISL packets. 2907 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2908 * control register. For 3c90xB/C chips, use the RX packet size 2909 * register. 2910 */ 2911 2912 if (sc->xl_type == XL_TYPE_905B) 2913 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2914 else { 2915 u_int8_t macctl; 2916 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2917 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2918 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2919 } 2920 2921 /* Clear out the stats counters. */ 2922 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2923 sc->xl_stats_no_timeout = 1; 2924 xl_stats_update(sc); 2925 sc->xl_stats_no_timeout = 0; 2926 XL_SEL_WIN(4); 2927 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2928 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2929 2930 /* 2931 * Enable interrupts. 2932 */ 2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2934 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2936 if (sc->xl_flags & XL_FLAG_FUNCREG) 2937 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2938 2939 /* Set the RX early threshold */ 2940 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2941 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2942 2943 /* Enable receiver and transmitter. */ 2944 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2945 xl_wait(sc); 2946 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2947 xl_wait(sc); 2948 2949 if (mii != NULL) 2950 mii_mediachg(mii); 2951 2952 /* Select window 7 for normal operations. */ 2953 XL_SEL_WIN(7); 2954 2955 ifp->if_flags |= IFF_RUNNING; 2956 ifp->if_flags &= ~IFF_OACTIVE; 2957 2958 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2959 2960 crit_exit(); 2961 } 2962 2963 /* 2964 * Set media options. 2965 */ 2966 static int 2967 xl_ifmedia_upd(ifp) 2968 struct ifnet *ifp; 2969 { 2970 struct xl_softc *sc; 2971 struct ifmedia *ifm = NULL; 2972 struct mii_data *mii = NULL; 2973 2974 sc = ifp->if_softc; 2975 if (sc->xl_miibus != NULL) 2976 mii = device_get_softc(sc->xl_miibus); 2977 if (mii == NULL) 2978 ifm = &sc->ifmedia; 2979 else 2980 ifm = &mii->mii_media; 2981 2982 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2983 case IFM_100_FX: 2984 case IFM_10_FL: 2985 case IFM_10_2: 2986 case IFM_10_5: 2987 xl_setmode(sc, ifm->ifm_media); 2988 return(0); 2989 break; 2990 default: 2991 break; 2992 } 2993 2994 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2995 || sc->xl_media & XL_MEDIAOPT_BT4) { 2996 xl_init(sc); 2997 } else { 2998 xl_setmode(sc, ifm->ifm_media); 2999 } 3000 3001 return(0); 3002 } 3003 3004 /* 3005 * Report current media status. 3006 */ 3007 static void 3008 xl_ifmedia_sts(ifp, ifmr) 3009 struct ifnet *ifp; 3010 struct ifmediareq *ifmr; 3011 { 3012 struct xl_softc *sc; 3013 u_int32_t icfg; 3014 struct mii_data *mii = NULL; 3015 3016 sc = ifp->if_softc; 3017 if (sc->xl_miibus != NULL) 3018 mii = device_get_softc(sc->xl_miibus); 3019 3020 XL_SEL_WIN(3); 3021 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3022 icfg >>= XL_ICFG_CONNECTOR_BITS; 3023 3024 ifmr->ifm_active = IFM_ETHER; 3025 3026 switch(icfg) { 3027 case XL_XCVR_10BT: 3028 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3029 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3030 ifmr->ifm_active |= IFM_FDX; 3031 else 3032 ifmr->ifm_active |= IFM_HDX; 3033 break; 3034 case XL_XCVR_AUI: 3035 if (sc->xl_type == XL_TYPE_905B && 3036 sc->xl_media == XL_MEDIAOPT_10FL) { 3037 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3038 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3039 ifmr->ifm_active |= IFM_FDX; 3040 else 3041 ifmr->ifm_active |= IFM_HDX; 3042 } else 3043 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3044 break; 3045 case XL_XCVR_COAX: 3046 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3047 break; 3048 /* 3049 * XXX MII and BTX/AUTO should be separate cases. 3050 */ 3051 3052 case XL_XCVR_100BTX: 3053 case XL_XCVR_AUTO: 3054 case XL_XCVR_MII: 3055 if (mii != NULL) { 3056 mii_pollstat(mii); 3057 ifmr->ifm_active = mii->mii_media_active; 3058 ifmr->ifm_status = mii->mii_media_status; 3059 } 3060 break; 3061 case XL_XCVR_100BFX: 3062 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3063 break; 3064 default: 3065 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3066 break; 3067 } 3068 3069 return; 3070 } 3071 3072 static int 3073 xl_ioctl(ifp, command, data, cr) 3074 struct ifnet *ifp; 3075 u_long command; 3076 caddr_t data; 3077 struct ucred *cr; 3078 { 3079 struct xl_softc *sc = ifp->if_softc; 3080 struct ifreq *ifr = (struct ifreq *) data; 3081 int error = 0; 3082 struct mii_data *mii = NULL; 3083 u_int8_t rxfilt; 3084 3085 crit_enter(); 3086 3087 switch(command) { 3088 case SIOCSIFFLAGS: 3089 XL_SEL_WIN(5); 3090 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3091 if (ifp->if_flags & IFF_UP) { 3092 if (ifp->if_flags & IFF_RUNNING && 3093 ifp->if_flags & IFF_PROMISC && 3094 !(sc->xl_if_flags & IFF_PROMISC)) { 3095 rxfilt |= XL_RXFILTER_ALLFRAMES; 3096 CSR_WRITE_2(sc, XL_COMMAND, 3097 XL_CMD_RX_SET_FILT|rxfilt); 3098 XL_SEL_WIN(7); 3099 } else if (ifp->if_flags & IFF_RUNNING && 3100 !(ifp->if_flags & IFF_PROMISC) && 3101 sc->xl_if_flags & IFF_PROMISC) { 3102 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3103 CSR_WRITE_2(sc, XL_COMMAND, 3104 XL_CMD_RX_SET_FILT|rxfilt); 3105 XL_SEL_WIN(7); 3106 } else 3107 xl_init(sc); 3108 } else { 3109 if (ifp->if_flags & IFF_RUNNING) 3110 xl_stop(sc); 3111 } 3112 sc->xl_if_flags = ifp->if_flags; 3113 error = 0; 3114 break; 3115 case SIOCADDMULTI: 3116 case SIOCDELMULTI: 3117 if (sc->xl_type == XL_TYPE_905B) 3118 xl_setmulti_hash(sc); 3119 else 3120 xl_setmulti(sc); 3121 error = 0; 3122 break; 3123 case SIOCGIFMEDIA: 3124 case SIOCSIFMEDIA: 3125 if (sc->xl_miibus != NULL) 3126 mii = device_get_softc(sc->xl_miibus); 3127 if (mii == NULL) 3128 error = ifmedia_ioctl(ifp, ifr, 3129 &sc->ifmedia, command); 3130 else 3131 error = ifmedia_ioctl(ifp, ifr, 3132 &mii->mii_media, command); 3133 break; 3134 case SIOCSIFCAP: 3135 ifp->if_capenable = ifr->ifr_reqcap; 3136 if (ifp->if_capenable & IFCAP_TXCSUM) 3137 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3138 else 3139 ifp->if_hwassist = 0; 3140 break; 3141 default: 3142 error = ether_ioctl(ifp, command, data); 3143 break; 3144 } 3145 3146 crit_exit(); 3147 3148 return(error); 3149 } 3150 3151 static void 3152 xl_watchdog(ifp) 3153 struct ifnet *ifp; 3154 { 3155 struct xl_softc *sc; 3156 u_int16_t status = 0; 3157 3158 sc = ifp->if_softc; 3159 3160 ifp->if_oerrors++; 3161 XL_SEL_WIN(4); 3162 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3163 if_printf(ifp, "watchdog timeout\n"); 3164 3165 if (status & XL_MEDIASTAT_CARRIER) 3166 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3167 xl_txeoc(sc); 3168 xl_txeof(sc); 3169 xl_rxeof(sc); 3170 xl_reset(sc); 3171 xl_init(sc); 3172 3173 if (!ifq_is_empty(&ifp->if_snd)) 3174 (*ifp->if_start)(ifp); 3175 } 3176 3177 /* 3178 * Stop the adapter and free any mbufs allocated to the 3179 * RX and TX lists. 3180 */ 3181 static void 3182 xl_stop(sc) 3183 struct xl_softc *sc; 3184 { 3185 int i; 3186 struct ifnet *ifp; 3187 3188 ifp = &sc->arpcom.ac_if; 3189 ifp->if_timer = 0; 3190 3191 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3192 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3193 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3194 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3195 xl_wait(sc); 3196 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3197 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3198 DELAY(800); 3199 3200 #ifdef foo 3201 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3202 xl_wait(sc); 3203 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3204 xl_wait(sc); 3205 #endif 3206 3207 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3208 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3209 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3210 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3211 3212 /* Stop the stats updater. */ 3213 callout_stop(&sc->xl_stat_timer); 3214 3215 /* 3216 * Free data in the RX lists. 3217 */ 3218 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3219 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3220 bus_dmamap_unload(sc->xl_mtag, 3221 sc->xl_cdata.xl_rx_chain[i].xl_map); 3222 bus_dmamap_destroy(sc->xl_mtag, 3223 sc->xl_cdata.xl_rx_chain[i].xl_map); 3224 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3225 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3226 } 3227 } 3228 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3229 /* 3230 * Free the TX list buffers. 3231 */ 3232 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3233 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3234 bus_dmamap_unload(sc->xl_mtag, 3235 sc->xl_cdata.xl_tx_chain[i].xl_map); 3236 bus_dmamap_destroy(sc->xl_mtag, 3237 sc->xl_cdata.xl_tx_chain[i].xl_map); 3238 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3239 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3240 } 3241 } 3242 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3243 3244 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3245 3246 return; 3247 } 3248 3249 /* 3250 * Stop all chip I/O so that the kernel's probe routines don't 3251 * get confused by errant DMAs when rebooting. 3252 */ 3253 static void 3254 xl_shutdown(dev) 3255 device_t dev; 3256 { 3257 struct xl_softc *sc; 3258 3259 sc = device_get_softc(dev); 3260 3261 xl_reset(sc); 3262 xl_stop(sc); 3263 3264 return; 3265 } 3266 3267 static int 3268 xl_suspend(dev) 3269 device_t dev; 3270 { 3271 struct xl_softc *sc = device_get_softc(dev); 3272 3273 crit_enter(); 3274 3275 xl_stop(sc); 3276 3277 crit_exit(); 3278 3279 return(0); 3280 } 3281 3282 static int 3283 xl_resume(dev) 3284 device_t dev; 3285 { 3286 struct xl_softc *sc; 3287 struct ifnet *ifp; 3288 3289 sc = device_get_softc(dev); 3290 ifp = &sc->arpcom.ac_if; 3291 3292 crit_enter(); 3293 3294 xl_reset(sc); 3295 if (ifp->if_flags & IFF_UP) 3296 xl_init(sc); 3297 3298 crit_exit(); 3299 3300 return(0); 3301 } 3302