1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.40 2008/01/05 14:02:37 swildner Exp $ 34 */ 35 36 /* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Winbond W89C840F chip is a bus master; in some ways it resembles 50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 51 * one major difference which is that while the registers do many of 52 * the same things as a tulip adapter, the offsets are different: where 53 * tulip registers are typically spaced 8 bytes apart, the Winbond 54 * registers are spaced 4 bytes apart. The receiver filter is also 55 * programmed differently. 56 * 57 * Like the tulip, the Winbond chip uses small descriptors containing 58 * a status word, a control word and 32-bit areas that can either be used 59 * to point to two external data blocks, or to point to a single block 60 * and another descriptor in a linked list. Descriptors can be grouped 61 * together in blocks to form fixed length rings or can be chained 62 * together in linked lists. A single packet may be spread out over 63 * several descriptors if necessary. 64 * 65 * For the receive ring, this driver uses a linked list of descriptors, 66 * each pointing to a single mbuf cluster buffer, which us large enough 67 * to hold an entire packet. The link list is looped back to created a 68 * closed ring. 69 * 70 * For transmission, the driver creates a linked list of 'super descriptors' 71 * which each contain several individual descriptors linked toghether. 72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 73 * abuse as fragment pointers. This allows us to use a buffer managment 74 * scheme very similar to that used in the ThunderLAN and Etherlink XL 75 * drivers. 76 * 77 * Autonegotiation is performed using the external PHY via the MII bus. 78 * The sample boards I have all use a Davicom PHY. 79 * 80 * Note: the author of the Linux driver for the Winbond chip alludes 81 * to some sort of flaw in the chip's design that seems to mandate some 82 * drastic workaround which signigicantly impairs transmit performance. 83 * I have no idea what he's on about: transmit performance with all 84 * three of my test boards seems fine. 85 */ 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/queue.h> 95 #include <sys/serialize.h> 96 #include <sys/bus.h> 97 #include <sys/rman.h> 98 #include <sys/thread2.h> 99 100 #include <net/if.h> 101 #include <net/ifq_var.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #include <net/bpf.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 112 #include <bus/pci/pcidevs.h> 113 #include <bus/pci/pcireg.h> 114 #include <bus/pci/pcivar.h> 115 116 #include <dev/netif/mii_layer/mii.h> 117 #include <dev/netif/mii_layer/miivar.h> 118 119 /* "controller miibus0" required. See GENERIC if you get errors here. */ 120 #include "miibus_if.h" 121 122 #define WB_USEIOSPACE 123 124 #include "if_wbreg.h" 125 126 /* 127 * Various supported device vendors/types and their names. 128 */ 129 static struct wb_type wb_devs[] = { 130 { PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F, 131 "Winbond W89C840F 10/100BaseTX" }, 132 { PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX, 133 "Compex RL100-ATX 10/100baseTX" }, 134 { 0, 0, NULL } 135 }; 136 137 static int wb_probe(device_t); 138 static int wb_attach(device_t); 139 static int wb_detach(device_t); 140 141 static void wb_bfree(void *); 142 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 143 struct mbuf *); 144 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 145 146 static void wb_rxeof(struct wb_softc *); 147 static void wb_rxeoc(struct wb_softc *); 148 static void wb_txeof(struct wb_softc *); 149 static void wb_txeoc(struct wb_softc *); 150 static void wb_intr(void *); 151 static void wb_tick(void *); 152 static void wb_start(struct ifnet *); 153 static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 154 static void wb_init(void *); 155 static void wb_stop(struct wb_softc *); 156 static void wb_watchdog(struct ifnet *); 157 static void wb_shutdown(device_t); 158 static int wb_ifmedia_upd(struct ifnet *); 159 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 160 161 static void wb_eeprom_putbyte(struct wb_softc *, int); 162 static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *); 163 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int); 164 static void wb_mii_sync(struct wb_softc *); 165 static void wb_mii_send(struct wb_softc *, uint32_t, int); 166 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 167 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 168 169 static void wb_setcfg(struct wb_softc *, uint32_t); 170 static void wb_setmulti(struct wb_softc *); 171 static void wb_reset(struct wb_softc *); 172 static void wb_fixmedia(struct wb_softc *); 173 static int wb_list_rx_init(struct wb_softc *); 174 static int wb_list_tx_init(struct wb_softc *); 175 176 static int wb_miibus_readreg(device_t, int, int); 177 static int wb_miibus_writereg(device_t, int, int, int); 178 static void wb_miibus_statchg(device_t); 179 180 #ifdef WB_USEIOSPACE 181 #define WB_RES SYS_RES_IOPORT 182 #define WB_RID WB_PCI_LOIO 183 #else 184 #define WB_RES SYS_RES_MEMORY 185 #define WB_RID WB_PCI_LOMEM 186 #endif 187 188 static device_method_t wb_methods[] = { 189 /* Device interface */ 190 DEVMETHOD(device_probe, wb_probe), 191 DEVMETHOD(device_attach, wb_attach), 192 DEVMETHOD(device_detach, wb_detach), 193 DEVMETHOD(device_shutdown, wb_shutdown), 194 195 /* bus interface, for miibus */ 196 DEVMETHOD(bus_print_child, bus_generic_print_child), 197 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 198 199 /* MII interface */ 200 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 201 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 202 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 203 { 0, 0 } 204 }; 205 206 static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc)); 207 static devclass_t wb_devclass; 208 209 DECLARE_DUMMY_MODULE(if_wb); 210 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 211 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 212 213 #define WB_SETBIT(sc, reg, x) \ 214 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 215 216 #define WB_CLRBIT(sc, reg, x) \ 217 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 218 219 #define SIO_SET(x) \ 220 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x)) 221 222 #define SIO_CLR(x) \ 223 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x)) 224 225 /* 226 * Send a read command and address to the EEPROM, check for ACK. 227 */ 228 static void 229 wb_eeprom_putbyte(struct wb_softc *sc, int addr) 230 { 231 int d, i; 232 233 d = addr | WB_EECMD_READ; 234 235 /* 236 * Feed in each bit and stobe the clock. 237 */ 238 for (i = 0x400; i; i >>= 1) { 239 if (d & i) 240 SIO_SET(WB_SIO_EE_DATAIN); 241 else 242 SIO_CLR(WB_SIO_EE_DATAIN); 243 DELAY(100); 244 SIO_SET(WB_SIO_EE_CLK); 245 DELAY(150); 246 SIO_CLR(WB_SIO_EE_CLK); 247 DELAY(100); 248 } 249 } 250 251 /* 252 * Read a word of data stored in the EEPROM at address 'addr.' 253 */ 254 static void 255 wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest) 256 { 257 int i; 258 uint16_t word = 0; 259 260 /* Enter EEPROM access mode. */ 261 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 262 263 /* 264 * Send address of word we want to read. 265 */ 266 wb_eeprom_putbyte(sc, addr); 267 268 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 269 270 /* 271 * Start reading bits from EEPROM. 272 */ 273 for (i = 0x8000; i; i >>= 1) { 274 SIO_SET(WB_SIO_EE_CLK); 275 DELAY(100); 276 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 277 word |= i; 278 SIO_CLR(WB_SIO_EE_CLK); 279 DELAY(100); 280 } 281 282 /* Turn off EEPROM access mode. */ 283 CSR_WRITE_4(sc, WB_SIO, 0); 284 285 *dest = word; 286 } 287 288 /* 289 * Read a sequence of words from the EEPROM. 290 */ 291 static void 292 wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt) 293 { 294 int i; 295 uint16_t word = 0, *ptr; 296 297 for (i = 0; i < cnt; i++) { 298 wb_eeprom_getword(sc, off + i, &word); 299 ptr = (uint16_t *)(dest + (i * 2)); 300 *ptr = word; 301 } 302 } 303 304 /* 305 * Sync the PHYs by setting data bit and strobing the clock 32 times. 306 */ 307 static void 308 wb_mii_sync(struct wb_softc *sc) 309 { 310 int i; 311 312 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN); 313 314 for (i = 0; i < 32; i++) { 315 SIO_SET(WB_SIO_MII_CLK); 316 DELAY(1); 317 SIO_CLR(WB_SIO_MII_CLK); 318 DELAY(1); 319 } 320 } 321 322 /* 323 * Clock a series of bits through the MII. 324 */ 325 static void 326 wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt) 327 { 328 int i; 329 330 SIO_CLR(WB_SIO_MII_CLK); 331 332 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 333 if (bits & i) 334 SIO_SET(WB_SIO_MII_DATAIN); 335 else 336 SIO_CLR(WB_SIO_MII_DATAIN); 337 DELAY(1); 338 SIO_CLR(WB_SIO_MII_CLK); 339 DELAY(1); 340 SIO_SET(WB_SIO_MII_CLK); 341 } 342 } 343 344 /* 345 * Read an PHY register through the MII. 346 */ 347 static int 348 wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame) 349 { 350 int ack, i; 351 352 crit_enter(); 353 354 /* 355 * Set up frame for RX. 356 */ 357 frame->mii_stdelim = WB_MII_STARTDELIM; 358 frame->mii_opcode = WB_MII_READOP; 359 frame->mii_turnaround = 0; 360 frame->mii_data = 0; 361 362 CSR_WRITE_4(sc, WB_SIO, 0); 363 364 /* 365 * Turn on data xmit. 366 */ 367 SIO_SET(WB_SIO_MII_DIR); 368 369 wb_mii_sync(sc); 370 371 /* 372 * Send command/address info. 373 */ 374 wb_mii_send(sc, frame->mii_stdelim, 2); 375 wb_mii_send(sc, frame->mii_opcode, 2); 376 wb_mii_send(sc, frame->mii_phyaddr, 5); 377 wb_mii_send(sc, frame->mii_regaddr, 5); 378 379 /* Idle bit */ 380 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN)); 381 DELAY(1); 382 SIO_SET(WB_SIO_MII_CLK); 383 DELAY(1); 384 385 /* Turn off xmit. */ 386 SIO_CLR(WB_SIO_MII_DIR); 387 /* Check for ack */ 388 SIO_CLR(WB_SIO_MII_CLK); 389 DELAY(1); 390 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 391 SIO_SET(WB_SIO_MII_CLK); 392 DELAY(1); 393 SIO_CLR(WB_SIO_MII_CLK); 394 DELAY(1); 395 SIO_SET(WB_SIO_MII_CLK); 396 DELAY(1); 397 398 /* 399 * Now try reading data bits. If the ack failed, we still 400 * need to clock through 16 cycles to keep the PHY(s) in sync. 401 */ 402 if (ack) { 403 for(i = 0; i < 16; i++) { 404 SIO_CLR(WB_SIO_MII_CLK); 405 DELAY(1); 406 SIO_SET(WB_SIO_MII_CLK); 407 DELAY(1); 408 } 409 goto fail; 410 } 411 412 for (i = 0x8000; i; i >>= 1) { 413 SIO_CLR(WB_SIO_MII_CLK); 414 DELAY(1); 415 if (!ack) { 416 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 417 frame->mii_data |= i; 418 DELAY(1); 419 } 420 SIO_SET(WB_SIO_MII_CLK); 421 DELAY(1); 422 } 423 424 fail: 425 426 SIO_CLR(WB_SIO_MII_CLK); 427 DELAY(1); 428 SIO_SET(WB_SIO_MII_CLK); 429 DELAY(1); 430 431 crit_exit(); 432 433 if (ack) 434 return(1); 435 return(0); 436 } 437 438 /* 439 * Write to a PHY register through the MII. 440 */ 441 static int 442 wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame) 443 { 444 445 crit_enter(); 446 /* 447 * Set up frame for TX. 448 */ 449 450 frame->mii_stdelim = WB_MII_STARTDELIM; 451 frame->mii_opcode = WB_MII_WRITEOP; 452 frame->mii_turnaround = WB_MII_TURNAROUND; 453 454 /* 455 * Turn on data output. 456 */ 457 SIO_SET(WB_SIO_MII_DIR); 458 459 wb_mii_sync(sc); 460 461 wb_mii_send(sc, frame->mii_stdelim, 2); 462 wb_mii_send(sc, frame->mii_opcode, 2); 463 wb_mii_send(sc, frame->mii_phyaddr, 5); 464 wb_mii_send(sc, frame->mii_regaddr, 5); 465 wb_mii_send(sc, frame->mii_turnaround, 2); 466 wb_mii_send(sc, frame->mii_data, 16); 467 468 /* Idle bit. */ 469 SIO_SET(WB_SIO_MII_CLK); 470 DELAY(1); 471 SIO_CLR(WB_SIO_MII_CLK); 472 DELAY(1); 473 474 /* 475 * Turn off xmit. 476 */ 477 SIO_CLR(WB_SIO_MII_DIR); 478 479 crit_exit(); 480 481 return(0); 482 } 483 484 static int 485 wb_miibus_readreg(device_t dev, int phy, int reg) 486 { 487 struct wb_softc *sc = device_get_softc(dev); 488 struct wb_mii_frame frame; 489 490 bzero(&frame, sizeof(frame)); 491 492 frame.mii_phyaddr = phy; 493 frame.mii_regaddr = reg; 494 wb_mii_readreg(sc, &frame); 495 496 return(frame.mii_data); 497 } 498 499 static int 500 wb_miibus_writereg(device_t dev, int phy, int reg, int data) 501 { 502 struct wb_softc *sc = device_get_softc(dev); 503 struct wb_mii_frame frame; 504 505 bzero(&frame, sizeof(frame)); 506 507 frame.mii_phyaddr = phy; 508 frame.mii_regaddr = reg; 509 frame.mii_data = data; 510 511 wb_mii_writereg(sc, &frame); 512 513 return(0); 514 } 515 516 static void 517 wb_miibus_statchg(device_t dev) 518 { 519 struct wb_softc *sc = device_get_softc(dev); 520 struct mii_data *mii; 521 522 mii = device_get_softc(sc->wb_miibus); 523 wb_setcfg(sc, mii->mii_media_active); 524 } 525 526 /* 527 * Program the 64-bit multicast hash filter. 528 */ 529 static void 530 wb_setmulti(struct wb_softc *sc) 531 { 532 struct ifnet *ifp = &sc->arpcom.ac_if; 533 int h = 0, mcnt = 0; 534 uint32_t hashes[2] = { 0, 0 }; 535 struct ifmultiaddr *ifma; 536 uint32_t rxfilt; 537 538 rxfilt = CSR_READ_4(sc, WB_NETCFG); 539 540 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 541 rxfilt |= WB_NETCFG_RX_MULTI; 542 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 543 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 544 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 545 return; 546 } 547 548 /* first, zot all the existing hash bits */ 549 CSR_WRITE_4(sc, WB_MAR0, 0); 550 CSR_WRITE_4(sc, WB_MAR1, 0); 551 552 /* now program new ones */ 553 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 554 if (ifma->ifma_addr->sa_family != AF_LINK) 555 continue; 556 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 557 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 558 if (h < 32) 559 hashes[0] |= (1 << h); 560 else 561 hashes[1] |= (1 << (h - 32)); 562 mcnt++; 563 } 564 565 if (mcnt) 566 rxfilt |= WB_NETCFG_RX_MULTI; 567 else 568 rxfilt &= ~WB_NETCFG_RX_MULTI; 569 570 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 571 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 572 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 573 } 574 575 /* 576 * The Winbond manual states that in order to fiddle with the 577 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 578 * first have to put the transmit and/or receive logic in the idle state. 579 */ 580 static void 581 wb_setcfg(struct wb_softc *sc, uint32_t media) 582 { 583 int i, restart = 0; 584 585 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) { 586 restart = 1; 587 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)); 588 589 for (i = 0; i < WB_TIMEOUT; i++) { 590 DELAY(10); 591 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 592 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 593 break; 594 } 595 596 if (i == WB_TIMEOUT) { 597 if_printf(&sc->arpcom.ac_if, "failed to force tx and " 598 "rx to idle state\n"); 599 } 600 } 601 602 if (IFM_SUBTYPE(media) == IFM_10_T) 603 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 604 else 605 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 606 607 if ((media & IFM_GMASK) == IFM_FDX) 608 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 609 else 610 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 611 612 if (restart) 613 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON); 614 } 615 616 static void 617 wb_reset(struct wb_softc *sc) 618 { 619 int i; 620 struct mii_data *mii; 621 622 CSR_WRITE_4(sc, WB_NETCFG, 0); 623 CSR_WRITE_4(sc, WB_BUSCTL, 0); 624 CSR_WRITE_4(sc, WB_TXADDR, 0); 625 CSR_WRITE_4(sc, WB_RXADDR, 0); 626 627 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 628 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 629 630 for (i = 0; i < WB_TIMEOUT; i++) { 631 DELAY(10); 632 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0) 633 break; 634 } 635 if (i == WB_TIMEOUT) 636 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 637 638 /* Wait a little while for the chip to get its brains in order. */ 639 DELAY(1000); 640 641 if (sc->wb_miibus == NULL) 642 return; 643 644 mii = device_get_softc(sc->wb_miibus); 645 if (mii == NULL) 646 return; 647 648 if (mii->mii_instance) { 649 struct mii_softc *miisc; 650 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 651 mii_phy_reset(miisc); 652 } 653 } 654 655 static void 656 wb_fixmedia(struct wb_softc *sc) 657 { 658 struct mii_data *mii; 659 uint32_t media; 660 661 if (sc->wb_miibus == NULL) 662 return; 663 664 mii = device_get_softc(sc->wb_miibus); 665 666 mii_pollstat(mii); 667 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 668 media = mii->mii_media_active & ~IFM_10_T; 669 media |= IFM_100_TX; 670 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 671 media = mii->mii_media_active & ~IFM_100_TX; 672 media |= IFM_10_T; 673 } else 674 return; 675 676 ifmedia_set(&mii->mii_media, media); 677 } 678 679 /* 680 * Probe for a Winbond chip. Check the PCI vendor and device 681 * IDs against our list and return a device name if we find a match. 682 */ 683 static int 684 wb_probe(device_t dev) 685 { 686 struct wb_type *t; 687 uint16_t vendor, product; 688 689 vendor = pci_get_vendor(dev); 690 product = pci_get_device(dev); 691 692 for (t = wb_devs; t->wb_name != NULL; t++) { 693 if (vendor == t->wb_vid && product == t->wb_did) { 694 device_set_desc(dev, t->wb_name); 695 return(0); 696 } 697 } 698 699 return(ENXIO); 700 } 701 702 /* 703 * Attach the interface. Allocate softc structures, do ifmedia 704 * setup and ethernet/BPF attach. 705 */ 706 static int 707 wb_attach(device_t dev) 708 { 709 u_char eaddr[ETHER_ADDR_LEN]; 710 struct wb_softc *sc; 711 struct ifnet *ifp; 712 int error = 0, rid; 713 714 sc = device_get_softc(dev); 715 callout_init(&sc->wb_stat_timer); 716 717 /* 718 * Handle power management nonsense. 719 */ 720 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 721 uint32_t iobase, membase, irq; 722 723 /* Save important PCI config data. */ 724 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 725 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 726 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 727 728 /* Reset the power state. */ 729 device_printf(dev, "chip is in D%d power mode " 730 "-- setting to D0\n", pci_get_powerstate(dev)); 731 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 732 733 /* Restore PCI config data. */ 734 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 735 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 736 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 737 } 738 739 pci_enable_busmaster(dev); 740 741 rid = WB_RID; 742 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 743 744 if (sc->wb_res == NULL) { 745 device_printf(dev, "couldn't map ports/memory\n"); 746 error = ENXIO; 747 goto fail; 748 } 749 750 sc->wb_btag = rman_get_bustag(sc->wb_res); 751 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 752 753 /* Allocate interrupt */ 754 rid = 0; 755 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 756 RF_SHAREABLE | RF_ACTIVE); 757 758 if (sc->wb_irq == NULL) { 759 device_printf(dev, "couldn't map interrupt\n"); 760 error = ENXIO; 761 goto fail; 762 } 763 764 /* Save the cache line size. */ 765 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 766 767 ifp = &sc->arpcom.ac_if; 768 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 769 770 /* Reset the adapter. */ 771 wb_reset(sc); 772 773 /* 774 * Get station address from the EEPROM. 775 */ 776 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3); 777 778 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 779 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 780 781 if (sc->wb_ldata == NULL) { 782 device_printf(dev, "no memory for list buffers!\n"); 783 error = ENXIO; 784 goto fail; 785 } 786 787 ifp->if_softc = sc; 788 ifp->if_mtu = ETHERMTU; 789 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 790 ifp->if_ioctl = wb_ioctl; 791 ifp->if_start = wb_start; 792 ifp->if_watchdog = wb_watchdog; 793 ifp->if_init = wb_init; 794 ifp->if_baudrate = 10000000; 795 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1); 796 ifq_set_ready(&ifp->if_snd); 797 798 /* 799 * Do MII setup. 800 */ 801 if (mii_phy_probe(dev, &sc->wb_miibus, 802 wb_ifmedia_upd, wb_ifmedia_sts)) { 803 error = ENXIO; 804 goto fail; 805 } 806 807 /* 808 * Call MI attach routine. 809 */ 810 ether_ifattach(ifp, eaddr, NULL); 811 812 error = bus_setup_intr(dev, sc->wb_irq, INTR_NETSAFE, 813 wb_intr, sc, &sc->wb_intrhand, 814 ifp->if_serializer); 815 816 if (error) { 817 device_printf(dev, "couldn't set up irq\n"); 818 ether_ifdetach(ifp); 819 goto fail; 820 } 821 822 return(0); 823 824 fail: 825 wb_detach(dev); 826 return(error); 827 } 828 829 static int 830 wb_detach(device_t dev) 831 { 832 struct wb_softc *sc = device_get_softc(dev); 833 struct ifnet *ifp = &sc->arpcom.ac_if; 834 835 836 if (device_is_attached(dev)) { 837 lwkt_serialize_enter(ifp->if_serializer); 838 wb_stop(sc); 839 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 840 lwkt_serialize_exit(ifp->if_serializer); 841 842 ether_ifdetach(ifp); 843 } 844 845 if (sc->wb_miibus) 846 device_delete_child(dev, sc->wb_miibus); 847 bus_generic_detach(dev); 848 849 if (sc->wb_irq) 850 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 851 if (sc->wb_res) 852 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 853 if (sc->wb_ldata_ptr) { 854 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 855 M_DEVBUF); 856 } 857 858 return(0); 859 } 860 861 /* 862 * Initialize the transmit descriptors. 863 */ 864 static int 865 wb_list_tx_init(struct wb_softc *sc) 866 { 867 struct wb_chain_data *cd; 868 struct wb_list_data *ld; 869 int i, nexti; 870 871 cd = &sc->wb_cdata; 872 ld = sc->wb_ldata; 873 874 for (i = 0; i < WB_TX_LIST_CNT; i++) { 875 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1; 876 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 877 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti]; 878 } 879 880 cd->wb_tx_free = &cd->wb_tx_chain[0]; 881 cd->wb_tx_tail = cd->wb_tx_head = NULL; 882 883 return(0); 884 } 885 886 /* 887 * Initialize the RX descriptors and allocate mbufs for them. Note that 888 * we arrange the descriptors in a closed ring, so that the last descriptor 889 * points back to the first. 890 */ 891 static int 892 wb_list_rx_init(struct wb_softc *sc) 893 { 894 struct wb_chain_data *cd; 895 struct wb_list_data *ld; 896 int i, nexti; 897 898 cd = &sc->wb_cdata; 899 ld = sc->wb_ldata; 900 901 for (i = 0; i < WB_RX_LIST_CNT; i++) { 902 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i]; 903 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i]; 904 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 905 return(ENOBUFS); 906 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1; 907 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti]; 908 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]); 909 } 910 911 cd->wb_rx_head = &cd->wb_rx_chain[0]; 912 913 return(0); 914 } 915 916 static void 917 wb_bfree(void *arg) 918 { 919 } 920 921 /* 922 * Initialize an RX descriptor and attach an MBUF cluster. 923 */ 924 static int 925 wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m) 926 { 927 struct mbuf *m_new = NULL; 928 929 if (m == NULL) { 930 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 931 if (m_new == NULL) 932 return(ENOBUFS); 933 934 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 935 m_new->m_flags |= M_EXT; 936 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 937 m_new->m_len = WB_BUFBYTES; 938 m_new->m_ext.ext_free = wb_bfree; 939 m_new->m_ext.ext_ref = wb_bfree; 940 } else { 941 m_new = m; 942 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 943 m_new->m_data = m_new->m_ext.ext_buf; 944 } 945 946 m_adj(m_new, sizeof(uint64_t)); 947 948 c->wb_mbuf = m_new; 949 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 950 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 951 c->wb_ptr->wb_status = WB_RXSTAT; 952 953 return(0); 954 } 955 956 /* 957 * A frame has been uploaded: pass the resulting mbuf chain up to 958 * the higher level protocols. 959 */ 960 static void 961 wb_rxeof(struct wb_softc *sc) 962 { 963 struct ifnet *ifp = &sc->arpcom.ac_if; 964 struct mbuf *m, *m0; 965 struct wb_chain_onefrag *cur_rx; 966 int total_len = 0; 967 uint32_t rxstat; 968 969 for (;;) { 970 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status; 971 if ((rxstat & WB_RXSTAT_OWN) == 0) 972 break; 973 974 cur_rx = sc->wb_cdata.wb_rx_head; 975 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 976 977 m = cur_rx->wb_mbuf; 978 979 if ((rxstat & WB_RXSTAT_MIIERR) || 980 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 981 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 982 (rxstat & WB_RXSTAT_LASTFRAG) == 0|| 983 (rxstat & WB_RXSTAT_RXCMP) == 0) { 984 ifp->if_ierrors++; 985 wb_newbuf(sc, cur_rx, m); 986 if_printf(ifp, "receiver babbling: possible chip " 987 "bug, forcing reset\n"); 988 wb_fixmedia(sc); 989 wb_reset(sc); 990 wb_init(sc); 991 return; 992 } 993 994 if (rxstat & WB_RXSTAT_RXERR) { 995 ifp->if_ierrors++; 996 wb_newbuf(sc, cur_rx, m); 997 break; 998 } 999 1000 /* No errors; receive the packet. */ 1001 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1002 1003 /* 1004 * XXX The Winbond chip includes the CRC with every 1005 * received frame, and there's no way to turn this 1006 * behavior off (at least, I can't find anything in 1007 * the manual that explains how to do it) so we have 1008 * to trim off the CRC manually. 1009 */ 1010 total_len -= ETHER_CRC_LEN; 1011 1012 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1013 total_len + ETHER_ALIGN, 0, ifp, NULL); 1014 wb_newbuf(sc, cur_rx, m); 1015 if (m0 == NULL) { 1016 ifp->if_ierrors++; 1017 break; 1018 } 1019 m_adj(m0, ETHER_ALIGN); 1020 m = m0; 1021 1022 ifp->if_ipackets++; 1023 ifp->if_input(ifp, m); 1024 } 1025 } 1026 1027 static void 1028 wb_rxeoc(struct wb_softc *sc) 1029 { 1030 wb_rxeof(sc); 1031 1032 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1033 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1034 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1035 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1036 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1037 } 1038 1039 /* 1040 * A frame was downloaded to the chip. It's safe for us to clean up 1041 * the list buffers. 1042 */ 1043 static void 1044 wb_txeof(struct wb_softc *sc) 1045 { 1046 struct ifnet *ifp = &sc->arpcom.ac_if; 1047 struct wb_chain *cur_tx; 1048 1049 /* Clear the timeout timer. */ 1050 ifp->if_timer = 0; 1051 1052 if (sc->wb_cdata.wb_tx_head == NULL) 1053 return; 1054 1055 /* 1056 * Go through our tx list and free mbufs for those 1057 * frames that have been transmitted. 1058 */ 1059 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1060 uint32_t txstat; 1061 1062 cur_tx = sc->wb_cdata.wb_tx_head; 1063 txstat = WB_TXSTATUS(cur_tx); 1064 1065 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1066 break; 1067 1068 if (txstat & WB_TXSTAT_TXERR) { 1069 ifp->if_oerrors++; 1070 if (txstat & WB_TXSTAT_ABORT) 1071 ifp->if_collisions++; 1072 if (txstat & WB_TXSTAT_LATECOLL) 1073 ifp->if_collisions++; 1074 } 1075 1076 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1077 1078 ifp->if_opackets++; 1079 m_freem(cur_tx->wb_mbuf); 1080 cur_tx->wb_mbuf = NULL; 1081 1082 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1083 sc->wb_cdata.wb_tx_head = NULL; 1084 sc->wb_cdata.wb_tx_tail = NULL; 1085 break; 1086 } 1087 1088 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1089 } 1090 } 1091 1092 /* 1093 * TX 'end of channel' interrupt handler. 1094 */ 1095 static void 1096 wb_txeoc(struct wb_softc *sc) 1097 { 1098 struct ifnet *ifp = &sc->arpcom.ac_if; 1099 1100 ifp->if_timer = 0; 1101 1102 if (sc->wb_cdata.wb_tx_head == NULL) { 1103 ifp->if_flags &= ~IFF_OACTIVE; 1104 sc->wb_cdata.wb_tx_tail = NULL; 1105 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1106 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1107 ifp->if_timer = 5; 1108 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1109 } 1110 } 1111 1112 static void 1113 wb_intr(void *arg) 1114 { 1115 struct wb_softc *sc = arg; 1116 struct ifnet *ifp = &sc->arpcom.ac_if; 1117 uint32_t status; 1118 1119 if ((ifp->if_flags & IFF_UP) == 0) 1120 return; 1121 1122 /* Disable interrupts. */ 1123 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1124 1125 for (;;) { 1126 status = CSR_READ_4(sc, WB_ISR); 1127 if (status) 1128 CSR_WRITE_4(sc, WB_ISR, status); 1129 1130 if ((status & WB_INTRS) == 0) 1131 break; 1132 1133 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1134 ifp->if_ierrors++; 1135 wb_reset(sc); 1136 if (status & WB_ISR_RX_ERR) 1137 wb_fixmedia(sc); 1138 wb_init(sc); 1139 continue; 1140 } 1141 1142 if (status & WB_ISR_RX_OK) 1143 wb_rxeof(sc); 1144 1145 if (status & WB_ISR_RX_IDLE) 1146 wb_rxeoc(sc); 1147 1148 if (status & WB_ISR_TX_OK) 1149 wb_txeof(sc); 1150 1151 if (status & WB_ISR_TX_NOBUF) 1152 wb_txeoc(sc); 1153 1154 if (status & WB_ISR_TX_IDLE) { 1155 wb_txeof(sc); 1156 if (sc->wb_cdata.wb_tx_head != NULL) { 1157 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1158 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1159 } 1160 } 1161 1162 if (status & WB_ISR_TX_UNDERRUN) { 1163 ifp->if_oerrors++; 1164 wb_txeof(sc); 1165 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1166 /* Jack up TX threshold */ 1167 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1168 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1169 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1170 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1171 } 1172 1173 if (status & WB_ISR_BUS_ERR) { 1174 wb_reset(sc); 1175 wb_init(sc); 1176 } 1177 } 1178 1179 /* Re-enable interrupts. */ 1180 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1181 1182 if (!ifq_is_empty(&ifp->if_snd)) 1183 wb_start(ifp); 1184 } 1185 1186 static void 1187 wb_tick(void *xsc) 1188 { 1189 struct wb_softc *sc = xsc; 1190 struct ifnet *ifp = &sc->arpcom.ac_if; 1191 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1192 1193 lwkt_serialize_enter(ifp->if_serializer); 1194 mii_tick(mii); 1195 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1196 lwkt_serialize_exit(ifp->if_serializer); 1197 } 1198 1199 /* 1200 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1201 * pointers to the fragment pointers. 1202 */ 1203 static int 1204 wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head) 1205 { 1206 struct wb_desc *f = NULL; 1207 struct mbuf *m; 1208 int frag, total_len; 1209 1210 /* 1211 * Start packing the mbufs in this chain into 1212 * the fragment pointers. Stop when we run out 1213 * of fragments or hit the end of the mbuf chain. 1214 */ 1215 total_len = 0; 1216 1217 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1218 if (m->m_len != 0) { 1219 if (frag == WB_MAXFRAGS) 1220 break; 1221 total_len += m->m_len; 1222 f = &c->wb_ptr->wb_frag[frag]; 1223 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1224 if (frag == 0) { 1225 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1226 f->wb_status = 0; 1227 } else { 1228 f->wb_status = WB_TXSTAT_OWN; 1229 } 1230 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1231 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1232 frag++; 1233 } 1234 } 1235 1236 /* 1237 * Handle special case: we used up all 16 fragments, 1238 * but we have more mbufs left in the chain. Copy the 1239 * data into an mbuf cluster. Note that we don't 1240 * bother clearing the values in the other fragment 1241 * pointers/counters; it wouldn't gain us anything, 1242 * and would waste cycles. 1243 */ 1244 if (m != NULL) { 1245 struct mbuf *m_new = NULL; 1246 1247 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1248 if (m_new == NULL) 1249 return(1); 1250 if (m_head->m_pkthdr.len > MHLEN) { 1251 MCLGET(m_new, MB_DONTWAIT); 1252 if ((m_new->m_flags & M_EXT) == 0) { 1253 m_freem(m_new); 1254 return(1); 1255 } 1256 } 1257 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1258 mtod(m_new, caddr_t)); 1259 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1260 m_freem(m_head); 1261 m_head = m_new; 1262 f = &c->wb_ptr->wb_frag[0]; 1263 f->wb_status = 0; 1264 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1265 f->wb_ctl = total_len = m_new->m_len; 1266 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1267 frag = 1; 1268 } 1269 1270 if (total_len < WB_MIN_FRAMELEN) { 1271 f = &c->wb_ptr->wb_frag[frag]; 1272 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1273 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1274 f->wb_ctl |= WB_TXCTL_TLINK; 1275 f->wb_status = WB_TXSTAT_OWN; 1276 frag++; 1277 } 1278 1279 c->wb_mbuf = m_head; 1280 c->wb_lastdesc = frag - 1; 1281 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1282 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1283 1284 return(0); 1285 } 1286 1287 /* 1288 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1289 * to the mbuf data regions directly in the transmit lists. We also save a 1290 * copy of the pointers since the transmit list fragment pointers are 1291 * physical addresses. 1292 */ 1293 static void 1294 wb_start(struct ifnet *ifp) 1295 { 1296 struct wb_softc *sc = ifp->if_softc; 1297 struct mbuf *m_head = NULL; 1298 struct wb_chain *cur_tx = NULL, *start_tx; 1299 1300 /* 1301 * Check for an available queue slot. If there are none, 1302 * punt. 1303 */ 1304 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1305 ifp->if_flags |= IFF_OACTIVE; 1306 return; 1307 } 1308 1309 start_tx = sc->wb_cdata.wb_tx_free; 1310 1311 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1312 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1313 if (m_head == NULL) 1314 break; 1315 1316 /* Pick a descriptor off the free list. */ 1317 cur_tx = sc->wb_cdata.wb_tx_free; 1318 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1319 1320 /* Pack the data into the descriptor. */ 1321 wb_encap(sc, cur_tx, m_head); 1322 1323 if (cur_tx != start_tx) 1324 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1325 1326 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1327 } 1328 1329 /* 1330 * If there are no packets queued, bail. 1331 */ 1332 if (cur_tx == NULL) 1333 return; 1334 1335 /* 1336 * Place the request for the upload interrupt 1337 * in the last descriptor in the chain. This way, if 1338 * we're chaining several packets at once, we'll only 1339 * get an interupt once for the whole chain rather than 1340 * once for each packet. 1341 */ 1342 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1343 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1344 sc->wb_cdata.wb_tx_tail = cur_tx; 1345 1346 if (sc->wb_cdata.wb_tx_head == NULL) { 1347 sc->wb_cdata.wb_tx_head = start_tx; 1348 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1349 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1350 } else { 1351 /* 1352 * We need to distinguish between the case where 1353 * the own bit is clear because the chip cleared it 1354 * and where the own bit is clear because we haven't 1355 * set it yet. The magic value WB_UNSET is just some 1356 * ramdomly chosen number which doesn't have the own 1357 * bit set. When we actually transmit the frame, the 1358 * status word will have _only_ the own bit set, so 1359 * the txeoc handler will be able to tell if it needs 1360 * to initiate another transmission to flush out pending 1361 * frames. 1362 */ 1363 WB_TXOWN(start_tx) = WB_UNSENT; 1364 } 1365 1366 /* 1367 * Set a timeout in case the chip goes out to lunch. 1368 */ 1369 ifp->if_timer = 5; 1370 } 1371 1372 static void 1373 wb_init(void *xsc) 1374 { 1375 struct wb_softc *sc = xsc; 1376 struct ifnet *ifp = &sc->arpcom.ac_if; 1377 int i; 1378 struct mii_data *mii; 1379 1380 crit_enter(); 1381 1382 mii = device_get_softc(sc->wb_miibus); 1383 1384 /* 1385 * Cancel pending I/O and free all RX/TX buffers. 1386 */ 1387 wb_stop(sc); 1388 wb_reset(sc); 1389 1390 sc->wb_txthresh = WB_TXTHRESH_INIT; 1391 1392 /* 1393 * Set cache alignment and burst length. 1394 */ 1395 #ifdef foo 1396 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1397 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1398 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1399 #endif 1400 1401 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION); 1402 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1403 switch(sc->wb_cachesize) { 1404 case 32: 1405 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1406 break; 1407 case 16: 1408 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1409 break; 1410 case 8: 1411 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1412 break; 1413 case 0: 1414 default: 1415 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1416 break; 1417 } 1418 1419 /* This doesn't tend to work too well at 100Mbps. */ 1420 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1421 1422 /* Init our MAC address */ 1423 for (i = 0; i < ETHER_ADDR_LEN; i++) 1424 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1425 1426 /* Init circular RX list. */ 1427 if (wb_list_rx_init(sc) == ENOBUFS) { 1428 if_printf(ifp, "initialization failed: no " 1429 "memory for rx buffers\n"); 1430 wb_stop(sc); 1431 crit_exit(); 1432 return; 1433 } 1434 1435 /* Init TX descriptors. */ 1436 wb_list_tx_init(sc); 1437 1438 /* If we want promiscuous mode, set the allframes bit. */ 1439 if (ifp->if_flags & IFF_PROMISC) 1440 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1441 else 1442 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1443 1444 /* 1445 * Set capture broadcast bit to capture broadcast frames. 1446 */ 1447 if (ifp->if_flags & IFF_BROADCAST) 1448 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1449 else 1450 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1451 1452 /* 1453 * Program the multicast filter, if necessary. 1454 */ 1455 wb_setmulti(sc); 1456 1457 /* 1458 * Load the address of the RX list. 1459 */ 1460 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1461 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1462 1463 /* 1464 * Enable interrupts. 1465 */ 1466 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1467 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1468 1469 /* Enable receiver and transmitter. */ 1470 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1471 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1472 1473 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1474 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1475 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1476 1477 mii_mediachg(mii); 1478 1479 ifp->if_flags |= IFF_RUNNING; 1480 ifp->if_flags &= ~IFF_OACTIVE; 1481 1482 crit_exit(); 1483 1484 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1485 } 1486 1487 /* 1488 * Set media options. 1489 */ 1490 static int 1491 wb_ifmedia_upd(struct ifnet *ifp) 1492 { 1493 struct wb_softc *sc = ifp->if_softc; 1494 1495 if (ifp->if_flags & IFF_UP) 1496 wb_init(sc); 1497 1498 return(0); 1499 } 1500 1501 /* 1502 * Report current media status. 1503 */ 1504 static void 1505 wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1506 { 1507 struct wb_softc *sc = ifp->if_softc; 1508 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1509 1510 mii_pollstat(mii); 1511 ifmr->ifm_active = mii->mii_media_active; 1512 ifmr->ifm_status = mii->mii_media_status; 1513 } 1514 1515 static int 1516 wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1517 { 1518 struct wb_softc *sc = ifp->if_softc; 1519 struct mii_data *mii; 1520 struct ifreq *ifr = (struct ifreq *) data; 1521 int error = 0; 1522 1523 crit_enter(); 1524 1525 switch(command) { 1526 case SIOCSIFFLAGS: 1527 if (ifp->if_flags & IFF_UP) 1528 wb_init(sc); 1529 else if (ifp->if_flags & IFF_RUNNING) 1530 wb_stop(sc); 1531 error = 0; 1532 break; 1533 case SIOCADDMULTI: 1534 case SIOCDELMULTI: 1535 wb_setmulti(sc); 1536 error = 0; 1537 break; 1538 case SIOCGIFMEDIA: 1539 case SIOCSIFMEDIA: 1540 mii = device_get_softc(sc->wb_miibus); 1541 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1542 break; 1543 default: 1544 error = ether_ioctl(ifp, command, data); 1545 break; 1546 } 1547 1548 crit_exit(); 1549 1550 return(error); 1551 } 1552 1553 static void 1554 wb_watchdog(struct ifnet *ifp) 1555 { 1556 struct wb_softc *sc = ifp->if_softc; 1557 1558 ifp->if_oerrors++; 1559 if_printf(ifp, "watchdog timeout\n"); 1560 #ifdef foo 1561 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0) 1562 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1563 #endif 1564 wb_stop(sc); 1565 wb_reset(sc); 1566 wb_init(sc); 1567 1568 if (!ifq_is_empty(&ifp->if_snd)) 1569 wb_start(ifp); 1570 } 1571 1572 /* 1573 * Stop the adapter and free any mbufs allocated to the 1574 * RX and TX lists. 1575 */ 1576 static void 1577 wb_stop(struct wb_softc *sc) 1578 { 1579 struct ifnet *ifp = &sc->arpcom.ac_if; 1580 int i; 1581 1582 ifp->if_timer = 0; 1583 1584 callout_stop(&sc->wb_stat_timer); 1585 1586 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON)); 1587 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1588 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1589 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1590 1591 /* 1592 * Free data in the RX lists. 1593 */ 1594 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1595 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1596 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1597 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1598 } 1599 } 1600 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list)); 1601 1602 /* 1603 * Free the TX list buffers. 1604 */ 1605 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1606 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1607 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1608 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1609 } 1610 } 1611 1612 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list)); 1613 1614 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1615 } 1616 1617 /* 1618 * Stop all chip I/O so that the kernel's probe routines don't 1619 * get confused by errant DMAs when rebooting. 1620 */ 1621 static void 1622 wb_shutdown(device_t dev) 1623 { 1624 struct wb_softc *sc = device_get_softc(dev); 1625 struct ifnet *ifp = &sc->arpcom.ac_if; 1626 1627 lwkt_serialize_enter(ifp->if_serializer); 1628 wb_stop(sc); 1629 lwkt_serialize_exit(ifp->if_serializer); 1630 } 1631 1632