1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.17 2005/02/21 18:40:37 joerg Exp $ 34 */ 35 36 /* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Winbond W89C840F chip is a bus master; in some ways it resembles 50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 51 * one major difference which is that while the registers do many of 52 * the same things as a tulip adapter, the offsets are different: where 53 * tulip registers are typically spaced 8 bytes apart, the Winbond 54 * registers are spaced 4 bytes apart. The receiver filter is also 55 * programmed differently. 56 * 57 * Like the tulip, the Winbond chip uses small descriptors containing 58 * a status word, a control word and 32-bit areas that can either be used 59 * to point to two external data blocks, or to point to a single block 60 * and another descriptor in a linked list. Descriptors can be grouped 61 * together in blocks to form fixed length rings or can be chained 62 * together in linked lists. A single packet may be spread out over 63 * several descriptors if necessary. 64 * 65 * For the receive ring, this driver uses a linked list of descriptors, 66 * each pointing to a single mbuf cluster buffer, which us large enough 67 * to hold an entire packet. The link list is looped back to created a 68 * closed ring. 69 * 70 * For transmission, the driver creates a linked list of 'super descriptors' 71 * which each contain several individual descriptors linked toghether. 72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 73 * abuse as fragment pointers. This allows us to use a buffer managment 74 * scheme very similar to that used in the ThunderLAN and Etherlink XL 75 * drivers. 76 * 77 * Autonegotiation is performed using the external PHY via the MII bus. 78 * The sample boards I have all use a Davicom PHY. 79 * 80 * Note: the author of the Linux driver for the Winbond chip alludes 81 * to some sort of flaw in the chip's design that seems to mandate some 82 * drastic workaround which signigicantly impairs transmit performance. 83 * I have no idea what he's on about: transmit performance with all 84 * three of my test boards seems fine. 85 */ 86 87 #include "opt_bdg.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 98 #include <net/if.h> 99 #include <net/ifq_var.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/clock.h> /* for DELAY */ 110 #include <machine/bus_memio.h> 111 #include <machine/bus_pio.h> 112 #include <machine/bus.h> 113 #include <machine/resource.h> 114 #include <sys/bus.h> 115 #include <sys/rman.h> 116 117 #include <bus/pci/pcireg.h> 118 #include <bus/pci/pcivar.h> 119 120 #include "../mii_layer/mii.h" 121 #include "../mii_layer/miivar.h" 122 123 /* "controller miibus0" required. See GENERIC if you get errors here. */ 124 #include "miibus_if.h" 125 126 #define WB_USEIOSPACE 127 128 #include "if_wbreg.h" 129 130 /* 131 * Various supported device vendors/types and their names. 132 */ 133 static struct wb_type wb_devs[] = { 134 { WB_VENDORID, WB_DEVICEID_840F, 135 "Winbond W89C840F 10/100BaseTX" }, 136 { CP_VENDORID, CP_DEVICEID_RL100, 137 "Compex RL100-ATX 10/100baseTX" }, 138 { 0, 0, NULL } 139 }; 140 141 static int wb_probe (device_t); 142 static int wb_attach (device_t); 143 static int wb_detach (device_t); 144 145 static void wb_bfree (caddr_t, u_int); 146 static int wb_newbuf (struct wb_softc *, 147 struct wb_chain_onefrag *, 148 struct mbuf *); 149 static int wb_encap (struct wb_softc *, struct wb_chain *, 150 struct mbuf *); 151 152 static void wb_rxeof (struct wb_softc *); 153 static void wb_rxeoc (struct wb_softc *); 154 static void wb_txeof (struct wb_softc *); 155 static void wb_txeoc (struct wb_softc *); 156 static void wb_intr (void *); 157 static void wb_tick (void *); 158 static void wb_start (struct ifnet *); 159 static int wb_ioctl (struct ifnet *, u_long, caddr_t, 160 struct ucred *); 161 static void wb_init (void *); 162 static void wb_stop (struct wb_softc *); 163 static void wb_watchdog (struct ifnet *); 164 static void wb_shutdown (device_t); 165 static int wb_ifmedia_upd (struct ifnet *); 166 static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 167 168 static void wb_eeprom_putbyte (struct wb_softc *, int); 169 static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 170 static void wb_read_eeprom (struct wb_softc *, caddr_t, int, 171 int, int); 172 static void wb_mii_sync (struct wb_softc *); 173 static void wb_mii_send (struct wb_softc *, u_int32_t, int); 174 static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 175 static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 176 177 static void wb_setcfg (struct wb_softc *, u_int32_t); 178 static u_int8_t wb_calchash (caddr_t); 179 static void wb_setmulti (struct wb_softc *); 180 static void wb_reset (struct wb_softc *); 181 static void wb_fixmedia (struct wb_softc *); 182 static int wb_list_rx_init (struct wb_softc *); 183 static int wb_list_tx_init (struct wb_softc *); 184 185 static int wb_miibus_readreg (device_t, int, int); 186 static int wb_miibus_writereg (device_t, int, int, int); 187 static void wb_miibus_statchg (device_t); 188 189 #ifdef WB_USEIOSPACE 190 #define WB_RES SYS_RES_IOPORT 191 #define WB_RID WB_PCI_LOIO 192 #else 193 #define WB_RES SYS_RES_MEMORY 194 #define WB_RID WB_PCI_LOMEM 195 #endif 196 197 static device_method_t wb_methods[] = { 198 /* Device interface */ 199 DEVMETHOD(device_probe, wb_probe), 200 DEVMETHOD(device_attach, wb_attach), 201 DEVMETHOD(device_detach, wb_detach), 202 DEVMETHOD(device_shutdown, wb_shutdown), 203 204 /* bus interface, for miibus */ 205 DEVMETHOD(bus_print_child, bus_generic_print_child), 206 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 207 208 /* MII interface */ 209 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 210 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 211 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 212 { 0, 0 } 213 }; 214 215 static driver_t wb_driver = { 216 "wb", 217 wb_methods, 218 sizeof(struct wb_softc) 219 }; 220 221 static devclass_t wb_devclass; 222 223 DECLARE_DUMMY_MODULE(if_wb); 224 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 225 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 226 227 #define WB_SETBIT(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) | x) 230 231 #define WB_CLRBIT(sc, reg, x) \ 232 CSR_WRITE_4(sc, reg, \ 233 CSR_READ_4(sc, reg) & ~x) 234 235 #define SIO_SET(x) \ 236 CSR_WRITE_4(sc, WB_SIO, \ 237 CSR_READ_4(sc, WB_SIO) | x) 238 239 #define SIO_CLR(x) \ 240 CSR_WRITE_4(sc, WB_SIO, \ 241 CSR_READ_4(sc, WB_SIO) & ~x) 242 243 /* 244 * Send a read command and address to the EEPROM, check for ACK. 245 */ 246 static void wb_eeprom_putbyte(sc, addr) 247 struct wb_softc *sc; 248 int addr; 249 { 250 int d, i; 251 252 d = addr | WB_EECMD_READ; 253 254 /* 255 * Feed in each bit and stobe the clock. 256 */ 257 for (i = 0x400; i; i >>= 1) { 258 if (d & i) { 259 SIO_SET(WB_SIO_EE_DATAIN); 260 } else { 261 SIO_CLR(WB_SIO_EE_DATAIN); 262 } 263 DELAY(100); 264 SIO_SET(WB_SIO_EE_CLK); 265 DELAY(150); 266 SIO_CLR(WB_SIO_EE_CLK); 267 DELAY(100); 268 } 269 270 return; 271 } 272 273 /* 274 * Read a word of data stored in the EEPROM at address 'addr.' 275 */ 276 static void wb_eeprom_getword(sc, addr, dest) 277 struct wb_softc *sc; 278 int addr; 279 u_int16_t *dest; 280 { 281 int i; 282 u_int16_t word = 0; 283 284 /* Enter EEPROM access mode. */ 285 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 286 287 /* 288 * Send address of word we want to read. 289 */ 290 wb_eeprom_putbyte(sc, addr); 291 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Start reading bits from EEPROM. 296 */ 297 for (i = 0x8000; i; i >>= 1) { 298 SIO_SET(WB_SIO_EE_CLK); 299 DELAY(100); 300 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 301 word |= i; 302 SIO_CLR(WB_SIO_EE_CLK); 303 DELAY(100); 304 } 305 306 /* Turn off EEPROM access mode. */ 307 CSR_WRITE_4(sc, WB_SIO, 0); 308 309 *dest = word; 310 311 return; 312 } 313 314 /* 315 * Read a sequence of words from the EEPROM. 316 */ 317 static void wb_read_eeprom(sc, dest, off, cnt, swap) 318 struct wb_softc *sc; 319 caddr_t dest; 320 int off; 321 int cnt; 322 int swap; 323 { 324 int i; 325 u_int16_t word = 0, *ptr; 326 327 for (i = 0; i < cnt; i++) { 328 wb_eeprom_getword(sc, off + i, &word); 329 ptr = (u_int16_t *)(dest + (i * 2)); 330 if (swap) 331 *ptr = ntohs(word); 332 else 333 *ptr = word; 334 } 335 336 return; 337 } 338 339 /* 340 * Sync the PHYs by setting data bit and strobing the clock 32 times. 341 */ 342 static void wb_mii_sync(sc) 343 struct wb_softc *sc; 344 { 345 int i; 346 347 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 348 349 for (i = 0; i < 32; i++) { 350 SIO_SET(WB_SIO_MII_CLK); 351 DELAY(1); 352 SIO_CLR(WB_SIO_MII_CLK); 353 DELAY(1); 354 } 355 356 return; 357 } 358 359 /* 360 * Clock a series of bits through the MII. 361 */ 362 static void wb_mii_send(sc, bits, cnt) 363 struct wb_softc *sc; 364 u_int32_t bits; 365 int cnt; 366 { 367 int i; 368 369 SIO_CLR(WB_SIO_MII_CLK); 370 371 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 372 if (bits & i) { 373 SIO_SET(WB_SIO_MII_DATAIN); 374 } else { 375 SIO_CLR(WB_SIO_MII_DATAIN); 376 } 377 DELAY(1); 378 SIO_CLR(WB_SIO_MII_CLK); 379 DELAY(1); 380 SIO_SET(WB_SIO_MII_CLK); 381 } 382 } 383 384 /* 385 * Read an PHY register through the MII. 386 */ 387 static int wb_mii_readreg(sc, frame) 388 struct wb_softc *sc; 389 struct wb_mii_frame *frame; 390 391 { 392 int i, ack, s; 393 394 s = splimp(); 395 396 /* 397 * Set up frame for RX. 398 */ 399 frame->mii_stdelim = WB_MII_STARTDELIM; 400 frame->mii_opcode = WB_MII_READOP; 401 frame->mii_turnaround = 0; 402 frame->mii_data = 0; 403 404 CSR_WRITE_4(sc, WB_SIO, 0); 405 406 /* 407 * Turn on data xmit. 408 */ 409 SIO_SET(WB_SIO_MII_DIR); 410 411 wb_mii_sync(sc); 412 413 /* 414 * Send command/address info. 415 */ 416 wb_mii_send(sc, frame->mii_stdelim, 2); 417 wb_mii_send(sc, frame->mii_opcode, 2); 418 wb_mii_send(sc, frame->mii_phyaddr, 5); 419 wb_mii_send(sc, frame->mii_regaddr, 5); 420 421 /* Idle bit */ 422 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 423 DELAY(1); 424 SIO_SET(WB_SIO_MII_CLK); 425 DELAY(1); 426 427 /* Turn off xmit. */ 428 SIO_CLR(WB_SIO_MII_DIR); 429 /* Check for ack */ 430 SIO_CLR(WB_SIO_MII_CLK); 431 DELAY(1); 432 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 433 SIO_SET(WB_SIO_MII_CLK); 434 DELAY(1); 435 SIO_CLR(WB_SIO_MII_CLK); 436 DELAY(1); 437 SIO_SET(WB_SIO_MII_CLK); 438 DELAY(1); 439 440 /* 441 * Now try reading data bits. If the ack failed, we still 442 * need to clock through 16 cycles to keep the PHY(s) in sync. 443 */ 444 if (ack) { 445 for(i = 0; i < 16; i++) { 446 SIO_CLR(WB_SIO_MII_CLK); 447 DELAY(1); 448 SIO_SET(WB_SIO_MII_CLK); 449 DELAY(1); 450 } 451 goto fail; 452 } 453 454 for (i = 0x8000; i; i >>= 1) { 455 SIO_CLR(WB_SIO_MII_CLK); 456 DELAY(1); 457 if (!ack) { 458 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 459 frame->mii_data |= i; 460 DELAY(1); 461 } 462 SIO_SET(WB_SIO_MII_CLK); 463 DELAY(1); 464 } 465 466 fail: 467 468 SIO_CLR(WB_SIO_MII_CLK); 469 DELAY(1); 470 SIO_SET(WB_SIO_MII_CLK); 471 DELAY(1); 472 473 splx(s); 474 475 if (ack) 476 return(1); 477 return(0); 478 } 479 480 /* 481 * Write to a PHY register through the MII. 482 */ 483 static int wb_mii_writereg(sc, frame) 484 struct wb_softc *sc; 485 struct wb_mii_frame *frame; 486 487 { 488 int s; 489 490 s = splimp(); 491 /* 492 * Set up frame for TX. 493 */ 494 495 frame->mii_stdelim = WB_MII_STARTDELIM; 496 frame->mii_opcode = WB_MII_WRITEOP; 497 frame->mii_turnaround = WB_MII_TURNAROUND; 498 499 /* 500 * Turn on data output. 501 */ 502 SIO_SET(WB_SIO_MII_DIR); 503 504 wb_mii_sync(sc); 505 506 wb_mii_send(sc, frame->mii_stdelim, 2); 507 wb_mii_send(sc, frame->mii_opcode, 2); 508 wb_mii_send(sc, frame->mii_phyaddr, 5); 509 wb_mii_send(sc, frame->mii_regaddr, 5); 510 wb_mii_send(sc, frame->mii_turnaround, 2); 511 wb_mii_send(sc, frame->mii_data, 16); 512 513 /* Idle bit. */ 514 SIO_SET(WB_SIO_MII_CLK); 515 DELAY(1); 516 SIO_CLR(WB_SIO_MII_CLK); 517 DELAY(1); 518 519 /* 520 * Turn off xmit. 521 */ 522 SIO_CLR(WB_SIO_MII_DIR); 523 524 splx(s); 525 526 return(0); 527 } 528 529 static int wb_miibus_readreg(dev, phy, reg) 530 device_t dev; 531 int phy, reg; 532 { 533 struct wb_softc *sc; 534 struct wb_mii_frame frame; 535 536 sc = device_get_softc(dev); 537 538 bzero((char *)&frame, sizeof(frame)); 539 540 frame.mii_phyaddr = phy; 541 frame.mii_regaddr = reg; 542 wb_mii_readreg(sc, &frame); 543 544 return(frame.mii_data); 545 } 546 547 static int wb_miibus_writereg(dev, phy, reg, data) 548 device_t dev; 549 int phy, reg, data; 550 { 551 struct wb_softc *sc; 552 struct wb_mii_frame frame; 553 554 sc = device_get_softc(dev); 555 556 bzero((char *)&frame, sizeof(frame)); 557 558 frame.mii_phyaddr = phy; 559 frame.mii_regaddr = reg; 560 frame.mii_data = data; 561 562 wb_mii_writereg(sc, &frame); 563 564 return(0); 565 } 566 567 static void wb_miibus_statchg(dev) 568 device_t dev; 569 { 570 struct wb_softc *sc; 571 struct mii_data *mii; 572 573 sc = device_get_softc(dev); 574 mii = device_get_softc(sc->wb_miibus); 575 wb_setcfg(sc, mii->mii_media_active); 576 577 return; 578 } 579 580 static u_int8_t wb_calchash(addr) 581 caddr_t addr; 582 { 583 u_int32_t crc, carry; 584 int i, j; 585 u_int8_t c; 586 587 /* Compute CRC for the address value. */ 588 crc = 0xFFFFFFFF; /* initial value */ 589 590 for (i = 0; i < 6; i++) { 591 c = *(addr + i); 592 for (j = 0; j < 8; j++) { 593 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 594 crc <<= 1; 595 c >>= 1; 596 if (carry) 597 crc = (crc ^ 0x04c11db6) | carry; 598 } 599 } 600 601 /* 602 * return the filter bit position 603 * Note: I arrived at the following nonsense 604 * through experimentation. It's not the usual way to 605 * generate the bit position but it's the only thing 606 * I could come up with that works. 607 */ 608 return(~(crc >> 26) & 0x0000003F); 609 } 610 611 /* 612 * Program the 64-bit multicast hash filter. 613 */ 614 static void wb_setmulti(sc) 615 struct wb_softc *sc; 616 { 617 struct ifnet *ifp; 618 int h = 0; 619 u_int32_t hashes[2] = { 0, 0 }; 620 struct ifmultiaddr *ifma; 621 u_int32_t rxfilt; 622 int mcnt = 0; 623 624 ifp = &sc->arpcom.ac_if; 625 626 rxfilt = CSR_READ_4(sc, WB_NETCFG); 627 628 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 629 rxfilt |= WB_NETCFG_RX_MULTI; 630 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 631 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 632 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 633 return; 634 } 635 636 /* first, zot all the existing hash bits */ 637 CSR_WRITE_4(sc, WB_MAR0, 0); 638 CSR_WRITE_4(sc, WB_MAR1, 0); 639 640 /* now program new ones */ 641 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 642 ifma = ifma->ifma_link.le_next) { 643 if (ifma->ifma_addr->sa_family != AF_LINK) 644 continue; 645 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 646 if (h < 32) 647 hashes[0] |= (1 << h); 648 else 649 hashes[1] |= (1 << (h - 32)); 650 mcnt++; 651 } 652 653 if (mcnt) 654 rxfilt |= WB_NETCFG_RX_MULTI; 655 else 656 rxfilt &= ~WB_NETCFG_RX_MULTI; 657 658 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 659 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 660 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 661 662 return; 663 } 664 665 /* 666 * The Winbond manual states that in order to fiddle with the 667 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 668 * first have to put the transmit and/or receive logic in the idle state. 669 */ 670 static void wb_setcfg(sc, media) 671 struct wb_softc *sc; 672 u_int32_t media; 673 { 674 int i, restart = 0; 675 676 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 677 restart = 1; 678 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 679 680 for (i = 0; i < WB_TIMEOUT; i++) { 681 DELAY(10); 682 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 683 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 684 break; 685 } 686 687 if (i == WB_TIMEOUT) 688 printf("wb%d: failed to force tx and " 689 "rx to idle state\n", sc->wb_unit); 690 } 691 692 if (IFM_SUBTYPE(media) == IFM_10_T) 693 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 694 else 695 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 696 697 if ((media & IFM_GMASK) == IFM_FDX) 698 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 699 else 700 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 701 702 if (restart) 703 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 704 705 return; 706 } 707 708 static void wb_reset(sc) 709 struct wb_softc *sc; 710 { 711 int i; 712 struct mii_data *mii; 713 714 CSR_WRITE_4(sc, WB_NETCFG, 0); 715 CSR_WRITE_4(sc, WB_BUSCTL, 0); 716 CSR_WRITE_4(sc, WB_TXADDR, 0); 717 CSR_WRITE_4(sc, WB_RXADDR, 0); 718 719 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 720 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 721 722 for (i = 0; i < WB_TIMEOUT; i++) { 723 DELAY(10); 724 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 725 break; 726 } 727 if (i == WB_TIMEOUT) 728 printf("wb%d: reset never completed!\n", sc->wb_unit); 729 730 /* Wait a little while for the chip to get its brains in order. */ 731 DELAY(1000); 732 733 if (sc->wb_miibus == NULL) 734 return; 735 736 mii = device_get_softc(sc->wb_miibus); 737 if (mii == NULL) 738 return; 739 740 if (mii->mii_instance) { 741 struct mii_softc *miisc; 742 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 743 miisc = LIST_NEXT(miisc, mii_list)) 744 mii_phy_reset(miisc); 745 } 746 747 return; 748 } 749 750 static void wb_fixmedia(sc) 751 struct wb_softc *sc; 752 { 753 struct mii_data *mii = NULL; 754 struct ifnet *ifp; 755 u_int32_t media; 756 757 if (sc->wb_miibus == NULL) 758 return; 759 760 mii = device_get_softc(sc->wb_miibus); 761 ifp = &sc->arpcom.ac_if; 762 763 mii_pollstat(mii); 764 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 765 media = mii->mii_media_active & ~IFM_10_T; 766 media |= IFM_100_TX; 767 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 768 media = mii->mii_media_active & ~IFM_100_TX; 769 media |= IFM_10_T; 770 } else 771 return; 772 773 ifmedia_set(&mii->mii_media, media); 774 775 return; 776 } 777 778 /* 779 * Probe for a Winbond chip. Check the PCI vendor and device 780 * IDs against our list and return a device name if we find a match. 781 */ 782 static int wb_probe(dev) 783 device_t dev; 784 { 785 struct wb_type *t; 786 787 t = wb_devs; 788 789 while(t->wb_name != NULL) { 790 if ((pci_get_vendor(dev) == t->wb_vid) && 791 (pci_get_device(dev) == t->wb_did)) { 792 device_set_desc(dev, t->wb_name); 793 return(0); 794 } 795 t++; 796 } 797 798 return(ENXIO); 799 } 800 801 /* 802 * Attach the interface. Allocate softc structures, do ifmedia 803 * setup and ethernet/BPF attach. 804 */ 805 static int wb_attach(dev) 806 device_t dev; 807 { 808 int s; 809 u_char eaddr[ETHER_ADDR_LEN]; 810 u_int32_t command; 811 struct wb_softc *sc; 812 struct ifnet *ifp; 813 int unit, error = 0, rid; 814 815 s = splimp(); 816 817 sc = device_get_softc(dev); 818 unit = device_get_unit(dev); 819 callout_init(&sc->wb_stat_timer); 820 821 /* 822 * Handle power management nonsense. 823 */ 824 825 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 826 if (command == 0x01) { 827 828 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 829 if (command & WB_PSTATE_MASK) { 830 u_int32_t iobase, membase, irq; 831 832 /* Save important PCI config data. */ 833 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 834 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 835 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 836 837 /* Reset the power state. */ 838 printf("wb%d: chip is in D%d power mode " 839 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 840 command &= 0xFFFFFFFC; 841 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 842 843 /* Restore PCI config data. */ 844 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 845 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 846 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 847 } 848 } 849 850 /* 851 * Map control/status registers. 852 */ 853 command = pci_read_config(dev, PCIR_COMMAND, 4); 854 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 855 pci_write_config(dev, PCIR_COMMAND, command, 4); 856 command = pci_read_config(dev, PCIR_COMMAND, 4); 857 858 #ifdef WB_USEIOSPACE 859 if (!(command & PCIM_CMD_PORTEN)) { 860 printf("wb%d: failed to enable I/O ports!\n", unit); 861 error = ENXIO; 862 goto fail; 863 } 864 #else 865 if (!(command & PCIM_CMD_MEMEN)) { 866 printf("wb%d: failed to enable memory mapping!\n", unit); 867 error = ENXIO; 868 goto fail; 869 } 870 #endif 871 872 rid = WB_RID; 873 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 874 0, ~0, 1, RF_ACTIVE); 875 876 if (sc->wb_res == NULL) { 877 printf("wb%d: couldn't map ports/memory\n", unit); 878 error = ENXIO; 879 goto fail; 880 } 881 882 sc->wb_btag = rman_get_bustag(sc->wb_res); 883 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 884 885 /* Allocate interrupt */ 886 rid = 0; 887 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 888 RF_SHAREABLE | RF_ACTIVE); 889 890 if (sc->wb_irq == NULL) { 891 printf("wb%d: couldn't map interrupt\n", unit); 892 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 893 error = ENXIO; 894 goto fail; 895 } 896 897 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 898 wb_intr, sc, &sc->wb_intrhand); 899 900 if (error) { 901 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 902 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 903 printf("wb%d: couldn't set up irq\n", unit); 904 goto fail; 905 } 906 907 /* Save the cache line size. */ 908 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 909 910 /* Reset the adapter. */ 911 wb_reset(sc); 912 913 /* 914 * Get station address from the EEPROM. 915 */ 916 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 917 918 sc->wb_unit = unit; 919 920 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 921 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 922 923 if (sc->wb_ldata == NULL) { 924 printf("wb%d: no memory for list buffers!\n", unit); 925 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 926 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 927 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 928 error = ENXIO; 929 goto fail; 930 } 931 932 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 933 934 ifp = &sc->arpcom.ac_if; 935 ifp->if_softc = sc; 936 if_initname(ifp, "wb", unit); 937 ifp->if_mtu = ETHERMTU; 938 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 939 ifp->if_ioctl = wb_ioctl; 940 ifp->if_start = wb_start; 941 ifp->if_watchdog = wb_watchdog; 942 ifp->if_init = wb_init; 943 ifp->if_baudrate = 10000000; 944 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1); 945 ifq_set_ready(&ifp->if_snd); 946 947 /* 948 * Do MII setup. 949 */ 950 if (mii_phy_probe(dev, &sc->wb_miibus, 951 wb_ifmedia_upd, wb_ifmedia_sts)) { 952 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 953 M_DEVBUF); 954 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 955 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 956 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 957 error = ENXIO; 958 goto fail; 959 } 960 961 /* 962 * Call MI attach routine. 963 */ 964 ether_ifattach(ifp, eaddr); 965 966 fail: 967 if (error) 968 device_delete_child(dev, sc->wb_miibus); 969 splx(s); 970 971 return(error); 972 } 973 974 static int wb_detach(dev) 975 device_t dev; 976 { 977 struct wb_softc *sc; 978 struct ifnet *ifp; 979 int s; 980 981 s = splimp(); 982 983 sc = device_get_softc(dev); 984 ifp = &sc->arpcom.ac_if; 985 986 wb_stop(sc); 987 ether_ifdetach(ifp); 988 989 /* Delete any miibus and phy devices attached to this interface */ 990 bus_generic_detach(dev); 991 device_delete_child(dev, sc->wb_miibus); 992 993 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 994 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 995 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 996 997 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 998 M_DEVBUF); 999 1000 splx(s); 1001 1002 return(0); 1003 } 1004 1005 /* 1006 * Initialize the transmit descriptors. 1007 */ 1008 static int wb_list_tx_init(sc) 1009 struct wb_softc *sc; 1010 { 1011 struct wb_chain_data *cd; 1012 struct wb_list_data *ld; 1013 int i; 1014 1015 cd = &sc->wb_cdata; 1016 ld = sc->wb_ldata; 1017 1018 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1019 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1020 if (i == (WB_TX_LIST_CNT - 1)) { 1021 cd->wb_tx_chain[i].wb_nextdesc = 1022 &cd->wb_tx_chain[0]; 1023 } else { 1024 cd->wb_tx_chain[i].wb_nextdesc = 1025 &cd->wb_tx_chain[i + 1]; 1026 } 1027 } 1028 1029 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1030 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1031 1032 return(0); 1033 } 1034 1035 1036 /* 1037 * Initialize the RX descriptors and allocate mbufs for them. Note that 1038 * we arrange the descriptors in a closed ring, so that the last descriptor 1039 * points back to the first. 1040 */ 1041 static int wb_list_rx_init(sc) 1042 struct wb_softc *sc; 1043 { 1044 struct wb_chain_data *cd; 1045 struct wb_list_data *ld; 1046 int i; 1047 1048 cd = &sc->wb_cdata; 1049 ld = sc->wb_ldata; 1050 1051 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1052 cd->wb_rx_chain[i].wb_ptr = 1053 (struct wb_desc *)&ld->wb_rx_list[i]; 1054 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1055 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1056 return(ENOBUFS); 1057 if (i == (WB_RX_LIST_CNT - 1)) { 1058 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1059 ld->wb_rx_list[i].wb_next = 1060 vtophys(&ld->wb_rx_list[0]); 1061 } else { 1062 cd->wb_rx_chain[i].wb_nextdesc = 1063 &cd->wb_rx_chain[i + 1]; 1064 ld->wb_rx_list[i].wb_next = 1065 vtophys(&ld->wb_rx_list[i + 1]); 1066 } 1067 } 1068 1069 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1070 1071 return(0); 1072 } 1073 1074 static void wb_bfree(buf, size) 1075 caddr_t buf; 1076 u_int size; 1077 { 1078 return; 1079 } 1080 1081 /* 1082 * Initialize an RX descriptor and attach an MBUF cluster. 1083 */ 1084 static int wb_newbuf(sc, c, m) 1085 struct wb_softc *sc; 1086 struct wb_chain_onefrag *c; 1087 struct mbuf *m; 1088 { 1089 struct mbuf *m_new = NULL; 1090 1091 if (m == NULL) { 1092 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1093 if (m_new == NULL) 1094 return(ENOBUFS); 1095 1096 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 1097 m_new->m_flags |= M_EXT | M_EXT_OLD; 1098 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1099 m_new->m_len = WB_BUFBYTES; 1100 m_new->m_ext.ext_nfree.old = wb_bfree; 1101 m_new->m_ext.ext_nref.old = wb_bfree; 1102 } else { 1103 m_new = m; 1104 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1105 m_new->m_data = m_new->m_ext.ext_buf; 1106 } 1107 1108 m_adj(m_new, sizeof(u_int64_t)); 1109 1110 c->wb_mbuf = m_new; 1111 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1112 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1113 c->wb_ptr->wb_status = WB_RXSTAT; 1114 1115 return(0); 1116 } 1117 1118 /* 1119 * A frame has been uploaded: pass the resulting mbuf chain up to 1120 * the higher level protocols. 1121 */ 1122 static void wb_rxeof(sc) 1123 struct wb_softc *sc; 1124 { 1125 struct mbuf *m = NULL; 1126 struct ifnet *ifp; 1127 struct wb_chain_onefrag *cur_rx; 1128 int total_len = 0; 1129 u_int32_t rxstat; 1130 1131 ifp = &sc->arpcom.ac_if; 1132 1133 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1134 WB_RXSTAT_OWN)) { 1135 struct mbuf *m0 = NULL; 1136 1137 cur_rx = sc->wb_cdata.wb_rx_head; 1138 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1139 1140 m = cur_rx->wb_mbuf; 1141 1142 if ((rxstat & WB_RXSTAT_MIIERR) || 1143 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1144 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1145 !(rxstat & WB_RXSTAT_LASTFRAG) || 1146 !(rxstat & WB_RXSTAT_RXCMP)) { 1147 ifp->if_ierrors++; 1148 wb_newbuf(sc, cur_rx, m); 1149 printf("wb%x: receiver babbling: possible chip " 1150 "bug, forcing reset\n", sc->wb_unit); 1151 wb_fixmedia(sc); 1152 wb_reset(sc); 1153 wb_init(sc); 1154 return; 1155 } 1156 1157 if (rxstat & WB_RXSTAT_RXERR) { 1158 ifp->if_ierrors++; 1159 wb_newbuf(sc, cur_rx, m); 1160 break; 1161 } 1162 1163 /* No errors; receive the packet. */ 1164 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1165 1166 /* 1167 * XXX The Winbond chip includes the CRC with every 1168 * received frame, and there's no way to turn this 1169 * behavior off (at least, I can't find anything in 1170 * the manual that explains how to do it) so we have 1171 * to trim off the CRC manually. 1172 */ 1173 total_len -= ETHER_CRC_LEN; 1174 1175 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1176 total_len + ETHER_ALIGN, 0, ifp, NULL); 1177 wb_newbuf(sc, cur_rx, m); 1178 if (m0 == NULL) { 1179 ifp->if_ierrors++; 1180 break; 1181 } 1182 m_adj(m0, ETHER_ALIGN); 1183 m = m0; 1184 1185 ifp->if_ipackets++; 1186 (*ifp->if_input)(ifp, m); 1187 } 1188 } 1189 1190 void wb_rxeoc(sc) 1191 struct wb_softc *sc; 1192 { 1193 wb_rxeof(sc); 1194 1195 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1196 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1197 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1198 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1199 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1200 1201 return; 1202 } 1203 1204 /* 1205 * A frame was downloaded to the chip. It's safe for us to clean up 1206 * the list buffers. 1207 */ 1208 static void wb_txeof(sc) 1209 struct wb_softc *sc; 1210 { 1211 struct wb_chain *cur_tx; 1212 struct ifnet *ifp; 1213 1214 ifp = &sc->arpcom.ac_if; 1215 1216 /* Clear the timeout timer. */ 1217 ifp->if_timer = 0; 1218 1219 if (sc->wb_cdata.wb_tx_head == NULL) 1220 return; 1221 1222 /* 1223 * Go through our tx list and free mbufs for those 1224 * frames that have been transmitted. 1225 */ 1226 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1227 u_int32_t txstat; 1228 1229 cur_tx = sc->wb_cdata.wb_tx_head; 1230 txstat = WB_TXSTATUS(cur_tx); 1231 1232 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1233 break; 1234 1235 if (txstat & WB_TXSTAT_TXERR) { 1236 ifp->if_oerrors++; 1237 if (txstat & WB_TXSTAT_ABORT) 1238 ifp->if_collisions++; 1239 if (txstat & WB_TXSTAT_LATECOLL) 1240 ifp->if_collisions++; 1241 } 1242 1243 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1244 1245 ifp->if_opackets++; 1246 m_freem(cur_tx->wb_mbuf); 1247 cur_tx->wb_mbuf = NULL; 1248 1249 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1250 sc->wb_cdata.wb_tx_head = NULL; 1251 sc->wb_cdata.wb_tx_tail = NULL; 1252 break; 1253 } 1254 1255 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1256 } 1257 1258 return; 1259 } 1260 1261 /* 1262 * TX 'end of channel' interrupt handler. 1263 */ 1264 static void wb_txeoc(sc) 1265 struct wb_softc *sc; 1266 { 1267 struct ifnet *ifp; 1268 1269 ifp = &sc->arpcom.ac_if; 1270 1271 ifp->if_timer = 0; 1272 1273 if (sc->wb_cdata.wb_tx_head == NULL) { 1274 ifp->if_flags &= ~IFF_OACTIVE; 1275 sc->wb_cdata.wb_tx_tail = NULL; 1276 } else { 1277 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1278 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1279 ifp->if_timer = 5; 1280 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1281 } 1282 } 1283 1284 return; 1285 } 1286 1287 static void wb_intr(arg) 1288 void *arg; 1289 { 1290 struct wb_softc *sc; 1291 struct ifnet *ifp; 1292 u_int32_t status; 1293 1294 sc = arg; 1295 ifp = &sc->arpcom.ac_if; 1296 1297 if (!(ifp->if_flags & IFF_UP)) 1298 return; 1299 1300 /* Disable interrupts. */ 1301 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1302 1303 for (;;) { 1304 1305 status = CSR_READ_4(sc, WB_ISR); 1306 if (status) 1307 CSR_WRITE_4(sc, WB_ISR, status); 1308 1309 if ((status & WB_INTRS) == 0) 1310 break; 1311 1312 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1313 ifp->if_ierrors++; 1314 wb_reset(sc); 1315 if (status & WB_ISR_RX_ERR) 1316 wb_fixmedia(sc); 1317 wb_init(sc); 1318 continue; 1319 } 1320 1321 if (status & WB_ISR_RX_OK) 1322 wb_rxeof(sc); 1323 1324 if (status & WB_ISR_RX_IDLE) 1325 wb_rxeoc(sc); 1326 1327 if (status & WB_ISR_TX_OK) 1328 wb_txeof(sc); 1329 1330 if (status & WB_ISR_TX_NOBUF) 1331 wb_txeoc(sc); 1332 1333 if (status & WB_ISR_TX_IDLE) { 1334 wb_txeof(sc); 1335 if (sc->wb_cdata.wb_tx_head != NULL) { 1336 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1337 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1338 } 1339 } 1340 1341 if (status & WB_ISR_TX_UNDERRUN) { 1342 ifp->if_oerrors++; 1343 wb_txeof(sc); 1344 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1345 /* Jack up TX threshold */ 1346 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1347 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1348 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1349 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1350 } 1351 1352 if (status & WB_ISR_BUS_ERR) { 1353 wb_reset(sc); 1354 wb_init(sc); 1355 } 1356 1357 } 1358 1359 /* Re-enable interrupts. */ 1360 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1361 1362 if (!ifq_is_empty(&ifp->if_snd)) { 1363 wb_start(ifp); 1364 } 1365 1366 return; 1367 } 1368 1369 static void wb_tick(xsc) 1370 void *xsc; 1371 { 1372 struct wb_softc *sc; 1373 struct mii_data *mii; 1374 int s; 1375 1376 s = splimp(); 1377 1378 sc = xsc; 1379 mii = device_get_softc(sc->wb_miibus); 1380 1381 mii_tick(mii); 1382 1383 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1384 1385 splx(s); 1386 1387 return; 1388 } 1389 1390 /* 1391 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1392 * pointers to the fragment pointers. 1393 */ 1394 static int wb_encap(sc, c, m_head) 1395 struct wb_softc *sc; 1396 struct wb_chain *c; 1397 struct mbuf *m_head; 1398 { 1399 int frag = 0; 1400 struct wb_desc *f = NULL; 1401 int total_len; 1402 struct mbuf *m; 1403 1404 /* 1405 * Start packing the mbufs in this chain into 1406 * the fragment pointers. Stop when we run out 1407 * of fragments or hit the end of the mbuf chain. 1408 */ 1409 m = m_head; 1410 total_len = 0; 1411 1412 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1413 if (m->m_len != 0) { 1414 if (frag == WB_MAXFRAGS) 1415 break; 1416 total_len += m->m_len; 1417 f = &c->wb_ptr->wb_frag[frag]; 1418 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1419 if (frag == 0) { 1420 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1421 f->wb_status = 0; 1422 } else 1423 f->wb_status = WB_TXSTAT_OWN; 1424 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1425 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1426 frag++; 1427 } 1428 } 1429 1430 /* 1431 * Handle special case: we used up all 16 fragments, 1432 * but we have more mbufs left in the chain. Copy the 1433 * data into an mbuf cluster. Note that we don't 1434 * bother clearing the values in the other fragment 1435 * pointers/counters; it wouldn't gain us anything, 1436 * and would waste cycles. 1437 */ 1438 if (m != NULL) { 1439 struct mbuf *m_new = NULL; 1440 1441 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1442 if (m_new == NULL) 1443 return(1); 1444 if (m_head->m_pkthdr.len > MHLEN) { 1445 MCLGET(m_new, MB_DONTWAIT); 1446 if (!(m_new->m_flags & M_EXT)) { 1447 m_freem(m_new); 1448 return(1); 1449 } 1450 } 1451 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1452 mtod(m_new, caddr_t)); 1453 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1454 m_freem(m_head); 1455 m_head = m_new; 1456 f = &c->wb_ptr->wb_frag[0]; 1457 f->wb_status = 0; 1458 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1459 f->wb_ctl = total_len = m_new->m_len; 1460 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1461 frag = 1; 1462 } 1463 1464 if (total_len < WB_MIN_FRAMELEN) { 1465 f = &c->wb_ptr->wb_frag[frag]; 1466 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1467 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1468 f->wb_ctl |= WB_TXCTL_TLINK; 1469 f->wb_status = WB_TXSTAT_OWN; 1470 frag++; 1471 } 1472 1473 c->wb_mbuf = m_head; 1474 c->wb_lastdesc = frag - 1; 1475 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1476 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1477 1478 return(0); 1479 } 1480 1481 /* 1482 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1483 * to the mbuf data regions directly in the transmit lists. We also save a 1484 * copy of the pointers since the transmit list fragment pointers are 1485 * physical addresses. 1486 */ 1487 1488 static void wb_start(ifp) 1489 struct ifnet *ifp; 1490 { 1491 struct wb_softc *sc; 1492 struct mbuf *m_head = NULL; 1493 struct wb_chain *cur_tx = NULL, *start_tx; 1494 1495 sc = ifp->if_softc; 1496 1497 /* 1498 * Check for an available queue slot. If there are none, 1499 * punt. 1500 */ 1501 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1502 ifp->if_flags |= IFF_OACTIVE; 1503 return; 1504 } 1505 1506 start_tx = sc->wb_cdata.wb_tx_free; 1507 1508 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1509 m_head = ifq_dequeue(&ifp->if_snd); 1510 if (m_head == NULL) 1511 break; 1512 1513 /* Pick a descriptor off the free list. */ 1514 cur_tx = sc->wb_cdata.wb_tx_free; 1515 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1516 1517 /* Pack the data into the descriptor. */ 1518 wb_encap(sc, cur_tx, m_head); 1519 1520 if (cur_tx != start_tx) 1521 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1522 1523 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1524 } 1525 1526 /* 1527 * If there are no packets queued, bail. 1528 */ 1529 if (cur_tx == NULL) 1530 return; 1531 1532 /* 1533 * Place the request for the upload interrupt 1534 * in the last descriptor in the chain. This way, if 1535 * we're chaining several packets at once, we'll only 1536 * get an interupt once for the whole chain rather than 1537 * once for each packet. 1538 */ 1539 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1540 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1541 sc->wb_cdata.wb_tx_tail = cur_tx; 1542 1543 if (sc->wb_cdata.wb_tx_head == NULL) { 1544 sc->wb_cdata.wb_tx_head = start_tx; 1545 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1546 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1547 } else { 1548 /* 1549 * We need to distinguish between the case where 1550 * the own bit is clear because the chip cleared it 1551 * and where the own bit is clear because we haven't 1552 * set it yet. The magic value WB_UNSET is just some 1553 * ramdomly chosen number which doesn't have the own 1554 * bit set. When we actually transmit the frame, the 1555 * status word will have _only_ the own bit set, so 1556 * the txeoc handler will be able to tell if it needs 1557 * to initiate another transmission to flush out pending 1558 * frames. 1559 */ 1560 WB_TXOWN(start_tx) = WB_UNSENT; 1561 } 1562 1563 /* 1564 * Set a timeout in case the chip goes out to lunch. 1565 */ 1566 ifp->if_timer = 5; 1567 1568 return; 1569 } 1570 1571 static void wb_init(xsc) 1572 void *xsc; 1573 { 1574 struct wb_softc *sc = xsc; 1575 struct ifnet *ifp = &sc->arpcom.ac_if; 1576 int s, i; 1577 struct mii_data *mii; 1578 1579 s = splimp(); 1580 1581 mii = device_get_softc(sc->wb_miibus); 1582 1583 /* 1584 * Cancel pending I/O and free all RX/TX buffers. 1585 */ 1586 wb_stop(sc); 1587 wb_reset(sc); 1588 1589 sc->wb_txthresh = WB_TXTHRESH_INIT; 1590 1591 /* 1592 * Set cache alignment and burst length. 1593 */ 1594 #ifdef foo 1595 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1596 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1597 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1598 #endif 1599 1600 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1601 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1602 switch(sc->wb_cachesize) { 1603 case 32: 1604 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1605 break; 1606 case 16: 1607 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1608 break; 1609 case 8: 1610 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1611 break; 1612 case 0: 1613 default: 1614 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1615 break; 1616 } 1617 1618 /* This doesn't tend to work too well at 100Mbps. */ 1619 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1620 1621 /* Init our MAC address */ 1622 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1623 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1624 } 1625 1626 /* Init circular RX list. */ 1627 if (wb_list_rx_init(sc) == ENOBUFS) { 1628 printf("wb%d: initialization failed: no " 1629 "memory for rx buffers\n", sc->wb_unit); 1630 wb_stop(sc); 1631 (void)splx(s); 1632 return; 1633 } 1634 1635 /* Init TX descriptors. */ 1636 wb_list_tx_init(sc); 1637 1638 /* If we want promiscuous mode, set the allframes bit. */ 1639 if (ifp->if_flags & IFF_PROMISC) { 1640 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1641 } else { 1642 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1643 } 1644 1645 /* 1646 * Set capture broadcast bit to capture broadcast frames. 1647 */ 1648 if (ifp->if_flags & IFF_BROADCAST) { 1649 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1650 } else { 1651 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1652 } 1653 1654 /* 1655 * Program the multicast filter, if necessary. 1656 */ 1657 wb_setmulti(sc); 1658 1659 /* 1660 * Load the address of the RX list. 1661 */ 1662 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1663 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1664 1665 /* 1666 * Enable interrupts. 1667 */ 1668 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1669 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1670 1671 /* Enable receiver and transmitter. */ 1672 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1673 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1674 1675 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1676 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1677 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1678 1679 mii_mediachg(mii); 1680 1681 ifp->if_flags |= IFF_RUNNING; 1682 ifp->if_flags &= ~IFF_OACTIVE; 1683 1684 (void)splx(s); 1685 1686 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1687 } 1688 1689 /* 1690 * Set media options. 1691 */ 1692 static int wb_ifmedia_upd(ifp) 1693 struct ifnet *ifp; 1694 { 1695 struct wb_softc *sc; 1696 1697 sc = ifp->if_softc; 1698 1699 if (ifp->if_flags & IFF_UP) 1700 wb_init(sc); 1701 1702 return(0); 1703 } 1704 1705 /* 1706 * Report current media status. 1707 */ 1708 static void wb_ifmedia_sts(ifp, ifmr) 1709 struct ifnet *ifp; 1710 struct ifmediareq *ifmr; 1711 { 1712 struct wb_softc *sc; 1713 struct mii_data *mii; 1714 1715 sc = ifp->if_softc; 1716 1717 mii = device_get_softc(sc->wb_miibus); 1718 1719 mii_pollstat(mii); 1720 ifmr->ifm_active = mii->mii_media_active; 1721 ifmr->ifm_status = mii->mii_media_status; 1722 1723 return; 1724 } 1725 1726 static int wb_ioctl(ifp, command, data, cr) 1727 struct ifnet *ifp; 1728 u_long command; 1729 caddr_t data; 1730 struct ucred *cr; 1731 { 1732 struct wb_softc *sc = ifp->if_softc; 1733 struct mii_data *mii; 1734 struct ifreq *ifr = (struct ifreq *) data; 1735 int s, error = 0; 1736 1737 s = splimp(); 1738 1739 switch(command) { 1740 case SIOCSIFADDR: 1741 case SIOCGIFADDR: 1742 case SIOCSIFMTU: 1743 error = ether_ioctl(ifp, command, data); 1744 break; 1745 case SIOCSIFFLAGS: 1746 if (ifp->if_flags & IFF_UP) { 1747 wb_init(sc); 1748 } else { 1749 if (ifp->if_flags & IFF_RUNNING) 1750 wb_stop(sc); 1751 } 1752 error = 0; 1753 break; 1754 case SIOCADDMULTI: 1755 case SIOCDELMULTI: 1756 wb_setmulti(sc); 1757 error = 0; 1758 break; 1759 case SIOCGIFMEDIA: 1760 case SIOCSIFMEDIA: 1761 mii = device_get_softc(sc->wb_miibus); 1762 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1763 break; 1764 default: 1765 error = EINVAL; 1766 break; 1767 } 1768 1769 (void)splx(s); 1770 1771 return(error); 1772 } 1773 1774 static void wb_watchdog(ifp) 1775 struct ifnet *ifp; 1776 { 1777 struct wb_softc *sc; 1778 1779 sc = ifp->if_softc; 1780 1781 ifp->if_oerrors++; 1782 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1783 #ifdef foo 1784 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1785 printf("wb%d: no carrier - transceiver cable problem?\n", 1786 sc->wb_unit); 1787 #endif 1788 wb_stop(sc); 1789 wb_reset(sc); 1790 wb_init(sc); 1791 1792 if (!ifq_is_empty(&ifp->if_snd)) 1793 wb_start(ifp); 1794 1795 return; 1796 } 1797 1798 /* 1799 * Stop the adapter and free any mbufs allocated to the 1800 * RX and TX lists. 1801 */ 1802 static void wb_stop(sc) 1803 struct wb_softc *sc; 1804 { 1805 int i; 1806 struct ifnet *ifp; 1807 1808 ifp = &sc->arpcom.ac_if; 1809 ifp->if_timer = 0; 1810 1811 callout_stop(&sc->wb_stat_timer); 1812 1813 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1814 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1815 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1816 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1817 1818 /* 1819 * Free data in the RX lists. 1820 */ 1821 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1822 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1823 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1824 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1825 } 1826 } 1827 bzero((char *)&sc->wb_ldata->wb_rx_list, 1828 sizeof(sc->wb_ldata->wb_rx_list)); 1829 1830 /* 1831 * Free the TX list buffers. 1832 */ 1833 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1834 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1835 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1836 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1837 } 1838 } 1839 1840 bzero((char *)&sc->wb_ldata->wb_tx_list, 1841 sizeof(sc->wb_ldata->wb_tx_list)); 1842 1843 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1844 1845 return; 1846 } 1847 1848 /* 1849 * Stop all chip I/O so that the kernel's probe routines don't 1850 * get confused by errant DMAs when rebooting. 1851 */ 1852 static void wb_shutdown(dev) 1853 device_t dev; 1854 { 1855 struct wb_softc *sc; 1856 1857 sc = device_get_softc(dev); 1858 wb_stop(sc); 1859 1860 return; 1861 } 1862