1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.25 2005/06/06 23:12:07 okumoto Exp $ 34 */ 35 36 /* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Winbond W89C840F chip is a bus master; in some ways it resembles 50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 51 * one major difference which is that while the registers do many of 52 * the same things as a tulip adapter, the offsets are different: where 53 * tulip registers are typically spaced 8 bytes apart, the Winbond 54 * registers are spaced 4 bytes apart. The receiver filter is also 55 * programmed differently. 56 * 57 * Like the tulip, the Winbond chip uses small descriptors containing 58 * a status word, a control word and 32-bit areas that can either be used 59 * to point to two external data blocks, or to point to a single block 60 * and another descriptor in a linked list. Descriptors can be grouped 61 * together in blocks to form fixed length rings or can be chained 62 * together in linked lists. A single packet may be spread out over 63 * several descriptors if necessary. 64 * 65 * For the receive ring, this driver uses a linked list of descriptors, 66 * each pointing to a single mbuf cluster buffer, which us large enough 67 * to hold an entire packet. The link list is looped back to created a 68 * closed ring. 69 * 70 * For transmission, the driver creates a linked list of 'super descriptors' 71 * which each contain several individual descriptors linked toghether. 72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 73 * abuse as fragment pointers. This allows us to use a buffer managment 74 * scheme very similar to that used in the ThunderLAN and Etherlink XL 75 * drivers. 76 * 77 * Autonegotiation is performed using the external PHY via the MII bus. 78 * The sample boards I have all use a Davicom PHY. 79 * 80 * Note: the author of the Linux driver for the Winbond chip alludes 81 * to some sort of flaw in the chip's design that seems to mandate some 82 * drastic workaround which signigicantly impairs transmit performance. 83 * I have no idea what he's on about: transmit performance with all 84 * three of my test boards seems fine. 85 */ 86 87 #include "opt_bdg.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 #include <sys/thread2.h> 98 99 #include <net/if.h> 100 #include <net/ifq_var.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 106 #include <net/bpf.h> 107 108 #include <vm/vm.h> /* for vtophys */ 109 #include <vm/pmap.h> /* for vtophys */ 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <bus/pci/pcireg.h> 116 #include <bus/pci/pcivar.h> 117 118 #include <dev/netif/mii_layer/mii.h> 119 #include <dev/netif/mii_layer/miivar.h> 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 #define WB_USEIOSPACE 125 126 #include "if_wbreg.h" 127 128 /* 129 * Various supported device vendors/types and their names. 130 */ 131 static struct wb_type wb_devs[] = { 132 { WB_VENDORID, WB_DEVICEID_840F, 133 "Winbond W89C840F 10/100BaseTX" }, 134 { CP_VENDORID, CP_DEVICEID_RL100, 135 "Compex RL100-ATX 10/100baseTX" }, 136 { 0, 0, NULL } 137 }; 138 139 static int wb_probe(device_t); 140 static int wb_attach(device_t); 141 static int wb_detach(device_t); 142 143 static void wb_bfree(void *); 144 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 145 struct mbuf *); 146 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 147 148 static void wb_rxeof(struct wb_softc *); 149 static void wb_rxeoc(struct wb_softc *); 150 static void wb_txeof(struct wb_softc *); 151 static void wb_txeoc(struct wb_softc *); 152 static void wb_intr(void *); 153 static void wb_tick(void *); 154 static void wb_start(struct ifnet *); 155 static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 156 static void wb_init(void *); 157 static void wb_stop(struct wb_softc *); 158 static void wb_watchdog(struct ifnet *); 159 static void wb_shutdown(device_t); 160 static int wb_ifmedia_upd(struct ifnet *); 161 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 162 163 static void wb_eeprom_putbyte(struct wb_softc *, int); 164 static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *); 165 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int); 166 static void wb_mii_sync(struct wb_softc *); 167 static void wb_mii_send(struct wb_softc *, uint32_t, int); 168 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 169 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 170 171 static void wb_setcfg(struct wb_softc *, uint32_t); 172 static void wb_setmulti(struct wb_softc *); 173 static void wb_reset(struct wb_softc *); 174 static void wb_fixmedia(struct wb_softc *); 175 static int wb_list_rx_init(struct wb_softc *); 176 static int wb_list_tx_init(struct wb_softc *); 177 178 static int wb_miibus_readreg(device_t, int, int); 179 static int wb_miibus_writereg(device_t, int, int, int); 180 static void wb_miibus_statchg(device_t); 181 182 #ifdef WB_USEIOSPACE 183 #define WB_RES SYS_RES_IOPORT 184 #define WB_RID WB_PCI_LOIO 185 #else 186 #define WB_RES SYS_RES_MEMORY 187 #define WB_RID WB_PCI_LOMEM 188 #endif 189 190 static device_method_t wb_methods[] = { 191 /* Device interface */ 192 DEVMETHOD(device_probe, wb_probe), 193 DEVMETHOD(device_attach, wb_attach), 194 DEVMETHOD(device_detach, wb_detach), 195 DEVMETHOD(device_shutdown, wb_shutdown), 196 197 /* bus interface, for miibus */ 198 DEVMETHOD(bus_print_child, bus_generic_print_child), 199 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 200 201 /* MII interface */ 202 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 203 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 204 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 205 { 0, 0 } 206 }; 207 208 static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc)); 209 static devclass_t wb_devclass; 210 211 DECLARE_DUMMY_MODULE(if_wb); 212 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 213 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 214 215 #define WB_SETBIT(sc, reg, x) \ 216 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 217 218 #define WB_CLRBIT(sc, reg, x) \ 219 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 220 221 #define SIO_SET(x) \ 222 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x)) 223 224 #define SIO_CLR(x) \ 225 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x)) 226 227 /* 228 * Send a read command and address to the EEPROM, check for ACK. 229 */ 230 static void 231 wb_eeprom_putbyte(struct wb_softc *sc, int addr) 232 { 233 int d, i; 234 235 d = addr | WB_EECMD_READ; 236 237 /* 238 * Feed in each bit and stobe the clock. 239 */ 240 for (i = 0x400; i; i >>= 1) { 241 if (d & i) 242 SIO_SET(WB_SIO_EE_DATAIN); 243 else 244 SIO_CLR(WB_SIO_EE_DATAIN); 245 DELAY(100); 246 SIO_SET(WB_SIO_EE_CLK); 247 DELAY(150); 248 SIO_CLR(WB_SIO_EE_CLK); 249 DELAY(100); 250 } 251 } 252 253 /* 254 * Read a word of data stored in the EEPROM at address 'addr.' 255 */ 256 static void 257 wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest) 258 { 259 int i; 260 uint16_t word = 0; 261 262 /* Enter EEPROM access mode. */ 263 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 264 265 /* 266 * Send address of word we want to read. 267 */ 268 wb_eeprom_putbyte(sc, addr); 269 270 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 271 272 /* 273 * Start reading bits from EEPROM. 274 */ 275 for (i = 0x8000; i; i >>= 1) { 276 SIO_SET(WB_SIO_EE_CLK); 277 DELAY(100); 278 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 279 word |= i; 280 SIO_CLR(WB_SIO_EE_CLK); 281 DELAY(100); 282 } 283 284 /* Turn off EEPROM access mode. */ 285 CSR_WRITE_4(sc, WB_SIO, 0); 286 287 *dest = word; 288 } 289 290 /* 291 * Read a sequence of words from the EEPROM. 292 */ 293 static void 294 wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt) 295 { 296 int i; 297 uint16_t word = 0, *ptr; 298 299 for (i = 0; i < cnt; i++) { 300 wb_eeprom_getword(sc, off + i, &word); 301 ptr = (uint16_t *)(dest + (i * 2)); 302 *ptr = word; 303 } 304 } 305 306 /* 307 * Sync the PHYs by setting data bit and strobing the clock 32 times. 308 */ 309 static void 310 wb_mii_sync(struct wb_softc *sc) 311 { 312 int i; 313 314 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN); 315 316 for (i = 0; i < 32; i++) { 317 SIO_SET(WB_SIO_MII_CLK); 318 DELAY(1); 319 SIO_CLR(WB_SIO_MII_CLK); 320 DELAY(1); 321 } 322 } 323 324 /* 325 * Clock a series of bits through the MII. 326 */ 327 static void 328 wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt) 329 { 330 int i; 331 332 SIO_CLR(WB_SIO_MII_CLK); 333 334 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 335 if (bits & i) 336 SIO_SET(WB_SIO_MII_DATAIN); 337 else 338 SIO_CLR(WB_SIO_MII_DATAIN); 339 DELAY(1); 340 SIO_CLR(WB_SIO_MII_CLK); 341 DELAY(1); 342 SIO_SET(WB_SIO_MII_CLK); 343 } 344 } 345 346 /* 347 * Read an PHY register through the MII. 348 */ 349 static int 350 wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame) 351 { 352 int ack, i; 353 354 crit_enter(); 355 356 /* 357 * Set up frame for RX. 358 */ 359 frame->mii_stdelim = WB_MII_STARTDELIM; 360 frame->mii_opcode = WB_MII_READOP; 361 frame->mii_turnaround = 0; 362 frame->mii_data = 0; 363 364 CSR_WRITE_4(sc, WB_SIO, 0); 365 366 /* 367 * Turn on data xmit. 368 */ 369 SIO_SET(WB_SIO_MII_DIR); 370 371 wb_mii_sync(sc); 372 373 /* 374 * Send command/address info. 375 */ 376 wb_mii_send(sc, frame->mii_stdelim, 2); 377 wb_mii_send(sc, frame->mii_opcode, 2); 378 wb_mii_send(sc, frame->mii_phyaddr, 5); 379 wb_mii_send(sc, frame->mii_regaddr, 5); 380 381 /* Idle bit */ 382 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN)); 383 DELAY(1); 384 SIO_SET(WB_SIO_MII_CLK); 385 DELAY(1); 386 387 /* Turn off xmit. */ 388 SIO_CLR(WB_SIO_MII_DIR); 389 /* Check for ack */ 390 SIO_CLR(WB_SIO_MII_CLK); 391 DELAY(1); 392 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 393 SIO_SET(WB_SIO_MII_CLK); 394 DELAY(1); 395 SIO_CLR(WB_SIO_MII_CLK); 396 DELAY(1); 397 SIO_SET(WB_SIO_MII_CLK); 398 DELAY(1); 399 400 /* 401 * Now try reading data bits. If the ack failed, we still 402 * need to clock through 16 cycles to keep the PHY(s) in sync. 403 */ 404 if (ack) { 405 for(i = 0; i < 16; i++) { 406 SIO_CLR(WB_SIO_MII_CLK); 407 DELAY(1); 408 SIO_SET(WB_SIO_MII_CLK); 409 DELAY(1); 410 } 411 goto fail; 412 } 413 414 for (i = 0x8000; i; i >>= 1) { 415 SIO_CLR(WB_SIO_MII_CLK); 416 DELAY(1); 417 if (!ack) { 418 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 419 frame->mii_data |= i; 420 DELAY(1); 421 } 422 SIO_SET(WB_SIO_MII_CLK); 423 DELAY(1); 424 } 425 426 fail: 427 428 SIO_CLR(WB_SIO_MII_CLK); 429 DELAY(1); 430 SIO_SET(WB_SIO_MII_CLK); 431 DELAY(1); 432 433 crit_exit(); 434 435 if (ack) 436 return(1); 437 return(0); 438 } 439 440 /* 441 * Write to a PHY register through the MII. 442 */ 443 static int 444 wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame) 445 { 446 447 crit_enter(); 448 /* 449 * Set up frame for TX. 450 */ 451 452 frame->mii_stdelim = WB_MII_STARTDELIM; 453 frame->mii_opcode = WB_MII_WRITEOP; 454 frame->mii_turnaround = WB_MII_TURNAROUND; 455 456 /* 457 * Turn on data output. 458 */ 459 SIO_SET(WB_SIO_MII_DIR); 460 461 wb_mii_sync(sc); 462 463 wb_mii_send(sc, frame->mii_stdelim, 2); 464 wb_mii_send(sc, frame->mii_opcode, 2); 465 wb_mii_send(sc, frame->mii_phyaddr, 5); 466 wb_mii_send(sc, frame->mii_regaddr, 5); 467 wb_mii_send(sc, frame->mii_turnaround, 2); 468 wb_mii_send(sc, frame->mii_data, 16); 469 470 /* Idle bit. */ 471 SIO_SET(WB_SIO_MII_CLK); 472 DELAY(1); 473 SIO_CLR(WB_SIO_MII_CLK); 474 DELAY(1); 475 476 /* 477 * Turn off xmit. 478 */ 479 SIO_CLR(WB_SIO_MII_DIR); 480 481 crit_exit(); 482 483 return(0); 484 } 485 486 static int 487 wb_miibus_readreg(device_t dev, int phy, int reg) 488 { 489 struct wb_softc *sc = device_get_softc(dev); 490 struct wb_mii_frame frame; 491 492 bzero(&frame, sizeof(frame)); 493 494 frame.mii_phyaddr = phy; 495 frame.mii_regaddr = reg; 496 wb_mii_readreg(sc, &frame); 497 498 return(frame.mii_data); 499 } 500 501 static int 502 wb_miibus_writereg(device_t dev, int phy, int reg, int data) 503 { 504 struct wb_softc *sc = device_get_softc(dev); 505 struct wb_mii_frame frame; 506 507 bzero(&frame, sizeof(frame)); 508 509 frame.mii_phyaddr = phy; 510 frame.mii_regaddr = reg; 511 frame.mii_data = data; 512 513 wb_mii_writereg(sc, &frame); 514 515 return(0); 516 } 517 518 static void 519 wb_miibus_statchg(device_t dev) 520 { 521 struct wb_softc *sc = device_get_softc(dev); 522 struct mii_data *mii; 523 524 mii = device_get_softc(sc->wb_miibus); 525 wb_setcfg(sc, mii->mii_media_active); 526 } 527 528 /* 529 * Program the 64-bit multicast hash filter. 530 */ 531 static void 532 wb_setmulti(struct wb_softc *sc) 533 { 534 struct ifnet *ifp = &sc->arpcom.ac_if; 535 int h = 0, mcnt = 0; 536 uint32_t hashes[2] = { 0, 0 }; 537 struct ifmultiaddr *ifma; 538 uint32_t rxfilt; 539 540 rxfilt = CSR_READ_4(sc, WB_NETCFG); 541 542 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 543 rxfilt |= WB_NETCFG_RX_MULTI; 544 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 545 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 546 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 547 return; 548 } 549 550 /* first, zot all the existing hash bits */ 551 CSR_WRITE_4(sc, WB_MAR0, 0); 552 CSR_WRITE_4(sc, WB_MAR1, 0); 553 554 /* now program new ones */ 555 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 556 if (ifma->ifma_addr->sa_family != AF_LINK) 557 continue; 558 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 559 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 560 if (h < 32) 561 hashes[0] |= (1 << h); 562 else 563 hashes[1] |= (1 << (h - 32)); 564 mcnt++; 565 } 566 567 if (mcnt) 568 rxfilt |= WB_NETCFG_RX_MULTI; 569 else 570 rxfilt &= ~WB_NETCFG_RX_MULTI; 571 572 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 573 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 574 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 575 } 576 577 /* 578 * The Winbond manual states that in order to fiddle with the 579 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 580 * first have to put the transmit and/or receive logic in the idle state. 581 */ 582 static void 583 wb_setcfg(struct wb_softc *sc, uint32_t media) 584 { 585 int i, restart = 0; 586 587 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) { 588 restart = 1; 589 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)); 590 591 for (i = 0; i < WB_TIMEOUT; i++) { 592 DELAY(10); 593 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 594 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 595 break; 596 } 597 598 if (i == WB_TIMEOUT) 599 printf("wb%d: failed to force tx and " 600 "rx to idle state\n", sc->wb_unit); 601 } 602 603 if (IFM_SUBTYPE(media) == IFM_10_T) 604 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 605 else 606 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 607 608 if ((media & IFM_GMASK) == IFM_FDX) 609 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 610 else 611 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 612 613 if (restart) 614 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON); 615 } 616 617 static void 618 wb_reset(struct wb_softc *sc) 619 { 620 int i; 621 struct mii_data *mii; 622 623 CSR_WRITE_4(sc, WB_NETCFG, 0); 624 CSR_WRITE_4(sc, WB_BUSCTL, 0); 625 CSR_WRITE_4(sc, WB_TXADDR, 0); 626 CSR_WRITE_4(sc, WB_RXADDR, 0); 627 628 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 629 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 630 631 for (i = 0; i < WB_TIMEOUT; i++) { 632 DELAY(10); 633 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0) 634 break; 635 } 636 if (i == WB_TIMEOUT) 637 printf("wb%d: reset never completed!\n", sc->wb_unit); 638 639 /* Wait a little while for the chip to get its brains in order. */ 640 DELAY(1000); 641 642 if (sc->wb_miibus == NULL) 643 return; 644 645 mii = device_get_softc(sc->wb_miibus); 646 if (mii == NULL) 647 return; 648 649 if (mii->mii_instance) { 650 struct mii_softc *miisc; 651 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 652 mii_phy_reset(miisc); 653 } 654 } 655 656 static void 657 wb_fixmedia(struct wb_softc *sc) 658 { 659 struct mii_data *mii; 660 uint32_t media; 661 662 if (sc->wb_miibus == NULL) 663 return; 664 665 mii = device_get_softc(sc->wb_miibus); 666 667 mii_pollstat(mii); 668 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 669 media = mii->mii_media_active & ~IFM_10_T; 670 media |= IFM_100_TX; 671 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 672 media = mii->mii_media_active & ~IFM_100_TX; 673 media |= IFM_10_T; 674 } else 675 return; 676 677 ifmedia_set(&mii->mii_media, media); 678 } 679 680 /* 681 * Probe for a Winbond chip. Check the PCI vendor and device 682 * IDs against our list and return a device name if we find a match. 683 */ 684 static int wb_probe(device_t dev) 685 { 686 struct wb_type *t; 687 uint16_t vendor, product; 688 689 vendor = pci_get_vendor(dev); 690 product = pci_get_device(dev); 691 692 for (t = wb_devs; t->wb_name != NULL; t++) { 693 if (vendor == t->wb_vid && product == t->wb_did) { 694 device_set_desc(dev, t->wb_name); 695 return(0); 696 } 697 } 698 699 return(ENXIO); 700 } 701 702 /* 703 * Attach the interface. Allocate softc structures, do ifmedia 704 * setup and ethernet/BPF attach. 705 */ 706 static int 707 wb_attach(device_t dev) 708 { 709 u_char eaddr[ETHER_ADDR_LEN]; 710 uint32_t command; 711 struct wb_softc *sc; 712 struct ifnet *ifp; 713 int error = 0, rid, unit; 714 715 crit_enter(); 716 717 sc = device_get_softc(dev); 718 unit = device_get_unit(dev); 719 callout_init(&sc->wb_stat_timer); 720 721 /* 722 * Handle power management nonsense. 723 */ 724 725 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 726 if (command == 0x01) { 727 728 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 729 if (command & WB_PSTATE_MASK) { 730 uint32_t iobase, membase, irq; 731 732 /* Save important PCI config data. */ 733 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 734 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 735 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 736 737 /* Reset the power state. */ 738 printf("wb%d: chip is in D%d power mode " 739 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 740 command &= 0xFFFFFFFC; 741 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 742 743 /* Restore PCI config data. */ 744 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 745 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 746 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 747 } 748 } 749 750 /* 751 * Map control/status registers. 752 */ 753 command = pci_read_config(dev, PCIR_COMMAND, 4); 754 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 755 pci_write_config(dev, PCIR_COMMAND, command, 4); 756 command = pci_read_config(dev, PCIR_COMMAND, 4); 757 758 #ifdef WB_USEIOSPACE 759 if ((command & PCIM_CMD_PORTEN) == 0) { 760 printf("wb%d: failed to enable I/O ports!\n", unit); 761 error = ENXIO; 762 goto fail; 763 } 764 #else 765 if ((command & PCIM_CMD_MEMEN) == 0) { 766 printf("wb%d: failed to enable memory mapping!\n", unit); 767 error = ENXIO; 768 goto fail; 769 } 770 #endif 771 772 rid = WB_RID; 773 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 774 775 if (sc->wb_res == NULL) { 776 printf("wb%d: couldn't map ports/memory\n", unit); 777 error = ENXIO; 778 goto fail; 779 } 780 781 sc->wb_btag = rman_get_bustag(sc->wb_res); 782 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 783 784 /* Allocate interrupt */ 785 rid = 0; 786 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 787 RF_SHAREABLE | RF_ACTIVE); 788 789 if (sc->wb_irq == NULL) { 790 printf("wb%d: couldn't map interrupt\n", unit); 791 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 792 error = ENXIO; 793 goto fail; 794 } 795 796 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 797 wb_intr, sc, &sc->wb_intrhand, NULL); 798 799 if (error) { 800 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 801 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 802 printf("wb%d: couldn't set up irq\n", unit); 803 goto fail; 804 } 805 806 /* Save the cache line size. */ 807 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 808 809 /* Reset the adapter. */ 810 wb_reset(sc); 811 812 /* 813 * Get station address from the EEPROM. 814 */ 815 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3); 816 817 sc->wb_unit = unit; 818 819 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 820 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 821 822 if (sc->wb_ldata == NULL) { 823 printf("wb%d: no memory for list buffers!\n", unit); 824 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 825 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 826 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 827 error = ENXIO; 828 goto fail; 829 } 830 831 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 832 833 ifp = &sc->arpcom.ac_if; 834 ifp->if_softc = sc; 835 if_initname(ifp, "wb", unit); 836 ifp->if_mtu = ETHERMTU; 837 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 838 ifp->if_ioctl = wb_ioctl; 839 ifp->if_start = wb_start; 840 ifp->if_watchdog = wb_watchdog; 841 ifp->if_init = wb_init; 842 ifp->if_baudrate = 10000000; 843 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1); 844 ifq_set_ready(&ifp->if_snd); 845 846 /* 847 * Do MII setup. 848 */ 849 if (mii_phy_probe(dev, &sc->wb_miibus, 850 wb_ifmedia_upd, wb_ifmedia_sts)) { 851 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 852 M_DEVBUF); 853 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 854 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 855 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 856 error = ENXIO; 857 goto fail; 858 } 859 860 /* 861 * Call MI attach routine. 862 */ 863 ether_ifattach(ifp, eaddr); 864 865 fail: 866 if (error) 867 device_delete_child(dev, sc->wb_miibus); 868 crit_exit(); 869 870 return(error); 871 } 872 873 static int 874 wb_detach(device_t dev) 875 { 876 struct wb_softc *sc = device_get_softc(dev); 877 struct ifnet *ifp = &sc->arpcom.ac_if; 878 879 crit_enter(); 880 881 wb_stop(sc); 882 ether_ifdetach(ifp); 883 884 /* Delete any miibus and phy devices attached to this interface */ 885 bus_generic_detach(dev); 886 device_delete_child(dev, sc->wb_miibus); 887 888 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 889 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 890 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 891 892 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 893 M_DEVBUF); 894 895 crit_exit(); 896 897 return(0); 898 } 899 900 /* 901 * Initialize the transmit descriptors. 902 */ 903 static int 904 wb_list_tx_init(struct wb_softc *sc) 905 { 906 struct wb_chain_data *cd; 907 struct wb_list_data *ld; 908 int i, nexti; 909 910 cd = &sc->wb_cdata; 911 ld = sc->wb_ldata; 912 913 for (i = 0; i < WB_TX_LIST_CNT; i++) { 914 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1; 915 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 916 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti]; 917 } 918 919 cd->wb_tx_free = &cd->wb_tx_chain[0]; 920 cd->wb_tx_tail = cd->wb_tx_head = NULL; 921 922 return(0); 923 } 924 925 /* 926 * Initialize the RX descriptors and allocate mbufs for them. Note that 927 * we arrange the descriptors in a closed ring, so that the last descriptor 928 * points back to the first. 929 */ 930 static int 931 wb_list_rx_init(struct wb_softc *sc) 932 { 933 struct wb_chain_data *cd; 934 struct wb_list_data *ld; 935 int i, nexti; 936 937 cd = &sc->wb_cdata; 938 ld = sc->wb_ldata; 939 940 for (i = 0; i < WB_RX_LIST_CNT; i++) { 941 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i]; 942 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i]; 943 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 944 return(ENOBUFS); 945 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1; 946 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti]; 947 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]); 948 } 949 950 cd->wb_rx_head = &cd->wb_rx_chain[0]; 951 952 return(0); 953 } 954 955 static void 956 wb_bfree(void *arg) 957 { 958 } 959 960 /* 961 * Initialize an RX descriptor and attach an MBUF cluster. 962 */ 963 static int 964 wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m) 965 { 966 struct mbuf *m_new = NULL; 967 968 if (m == NULL) { 969 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 970 if (m_new == NULL) 971 return(ENOBUFS); 972 973 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 974 m_new->m_flags |= M_EXT; 975 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 976 m_new->m_len = WB_BUFBYTES; 977 m_new->m_ext.ext_free = wb_bfree; 978 m_new->m_ext.ext_ref = wb_bfree; 979 } else { 980 m_new = m; 981 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 982 m_new->m_data = m_new->m_ext.ext_buf; 983 } 984 985 m_adj(m_new, sizeof(uint64_t)); 986 987 c->wb_mbuf = m_new; 988 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 989 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 990 c->wb_ptr->wb_status = WB_RXSTAT; 991 992 return(0); 993 } 994 995 /* 996 * A frame has been uploaded: pass the resulting mbuf chain up to 997 * the higher level protocols. 998 */ 999 static void 1000 wb_rxeof(struct wb_softc *sc) 1001 { 1002 struct ifnet *ifp = &sc->arpcom.ac_if; 1003 struct mbuf *m, *m0; 1004 struct wb_chain_onefrag *cur_rx; 1005 int total_len = 0; 1006 uint32_t rxstat; 1007 1008 for (;;) { 1009 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status; 1010 if ((rxstat & WB_RXSTAT_OWN) == 0) 1011 break; 1012 1013 cur_rx = sc->wb_cdata.wb_rx_head; 1014 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1015 1016 m = cur_rx->wb_mbuf; 1017 1018 if ((rxstat & WB_RXSTAT_MIIERR) || 1019 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1020 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1021 (rxstat & WB_RXSTAT_LASTFRAG) == 0|| 1022 (rxstat & WB_RXSTAT_RXCMP) == 0) { 1023 ifp->if_ierrors++; 1024 wb_newbuf(sc, cur_rx, m); 1025 printf("wb%x: receiver babbling: possible chip " 1026 "bug, forcing reset\n", sc->wb_unit); 1027 wb_fixmedia(sc); 1028 wb_reset(sc); 1029 wb_init(sc); 1030 return; 1031 } 1032 1033 if (rxstat & WB_RXSTAT_RXERR) { 1034 ifp->if_ierrors++; 1035 wb_newbuf(sc, cur_rx, m); 1036 break; 1037 } 1038 1039 /* No errors; receive the packet. */ 1040 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1041 1042 /* 1043 * XXX The Winbond chip includes the CRC with every 1044 * received frame, and there's no way to turn this 1045 * behavior off (at least, I can't find anything in 1046 * the manual that explains how to do it) so we have 1047 * to trim off the CRC manually. 1048 */ 1049 total_len -= ETHER_CRC_LEN; 1050 1051 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1052 total_len + ETHER_ALIGN, 0, ifp, NULL); 1053 wb_newbuf(sc, cur_rx, m); 1054 if (m0 == NULL) { 1055 ifp->if_ierrors++; 1056 break; 1057 } 1058 m_adj(m0, ETHER_ALIGN); 1059 m = m0; 1060 1061 ifp->if_ipackets++; 1062 (*ifp->if_input)(ifp, m); 1063 } 1064 } 1065 1066 static void 1067 wb_rxeoc(struct wb_softc *sc) 1068 { 1069 wb_rxeof(sc); 1070 1071 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1072 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1073 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1074 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1075 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1076 } 1077 1078 /* 1079 * A frame was downloaded to the chip. It's safe for us to clean up 1080 * the list buffers. 1081 */ 1082 static void 1083 wb_txeof(struct wb_softc *sc) 1084 { 1085 struct ifnet *ifp = &sc->arpcom.ac_if; 1086 struct wb_chain *cur_tx; 1087 1088 /* Clear the timeout timer. */ 1089 ifp->if_timer = 0; 1090 1091 if (sc->wb_cdata.wb_tx_head == NULL) 1092 return; 1093 1094 /* 1095 * Go through our tx list and free mbufs for those 1096 * frames that have been transmitted. 1097 */ 1098 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1099 uint32_t txstat; 1100 1101 cur_tx = sc->wb_cdata.wb_tx_head; 1102 txstat = WB_TXSTATUS(cur_tx); 1103 1104 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1105 break; 1106 1107 if (txstat & WB_TXSTAT_TXERR) { 1108 ifp->if_oerrors++; 1109 if (txstat & WB_TXSTAT_ABORT) 1110 ifp->if_collisions++; 1111 if (txstat & WB_TXSTAT_LATECOLL) 1112 ifp->if_collisions++; 1113 } 1114 1115 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1116 1117 ifp->if_opackets++; 1118 m_freem(cur_tx->wb_mbuf); 1119 cur_tx->wb_mbuf = NULL; 1120 1121 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1122 sc->wb_cdata.wb_tx_head = NULL; 1123 sc->wb_cdata.wb_tx_tail = NULL; 1124 break; 1125 } 1126 1127 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1128 } 1129 } 1130 1131 /* 1132 * TX 'end of channel' interrupt handler. 1133 */ 1134 static void 1135 wb_txeoc(struct wb_softc *sc) 1136 { 1137 struct ifnet *ifp = &sc->arpcom.ac_if; 1138 1139 ifp->if_timer = 0; 1140 1141 if (sc->wb_cdata.wb_tx_head == NULL) { 1142 ifp->if_flags &= ~IFF_OACTIVE; 1143 sc->wb_cdata.wb_tx_tail = NULL; 1144 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1145 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1146 ifp->if_timer = 5; 1147 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1148 } 1149 } 1150 1151 static void 1152 wb_intr(void *arg) 1153 { 1154 struct wb_softc *sc = arg; 1155 struct ifnet *ifp = &sc->arpcom.ac_if; 1156 uint32_t status; 1157 1158 if ((ifp->if_flags & IFF_UP) == 0) 1159 return; 1160 1161 /* Disable interrupts. */ 1162 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1163 1164 for (;;) { 1165 status = CSR_READ_4(sc, WB_ISR); 1166 if (status) 1167 CSR_WRITE_4(sc, WB_ISR, status); 1168 1169 if ((status & WB_INTRS) == 0) 1170 break; 1171 1172 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1173 ifp->if_ierrors++; 1174 wb_reset(sc); 1175 if (status & WB_ISR_RX_ERR) 1176 wb_fixmedia(sc); 1177 wb_init(sc); 1178 continue; 1179 } 1180 1181 if (status & WB_ISR_RX_OK) 1182 wb_rxeof(sc); 1183 1184 if (status & WB_ISR_RX_IDLE) 1185 wb_rxeoc(sc); 1186 1187 if (status & WB_ISR_TX_OK) 1188 wb_txeof(sc); 1189 1190 if (status & WB_ISR_TX_NOBUF) 1191 wb_txeoc(sc); 1192 1193 if (status & WB_ISR_TX_IDLE) { 1194 wb_txeof(sc); 1195 if (sc->wb_cdata.wb_tx_head != NULL) { 1196 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1197 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1198 } 1199 } 1200 1201 if (status & WB_ISR_TX_UNDERRUN) { 1202 ifp->if_oerrors++; 1203 wb_txeof(sc); 1204 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1205 /* Jack up TX threshold */ 1206 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1207 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1208 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1209 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1210 } 1211 1212 if (status & WB_ISR_BUS_ERR) { 1213 wb_reset(sc); 1214 wb_init(sc); 1215 } 1216 } 1217 1218 /* Re-enable interrupts. */ 1219 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1220 1221 if (!ifq_is_empty(&ifp->if_snd)) 1222 wb_start(ifp); 1223 } 1224 1225 static void 1226 wb_tick(void *xsc) 1227 { 1228 struct wb_softc *sc = xsc; 1229 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1230 1231 crit_enter(); 1232 1233 mii_tick(mii); 1234 1235 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1236 1237 crit_exit(); 1238 } 1239 1240 /* 1241 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1242 * pointers to the fragment pointers. 1243 */ 1244 static int 1245 wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head) 1246 { 1247 struct wb_desc *f = NULL; 1248 struct mbuf *m; 1249 int frag, total_len; 1250 1251 /* 1252 * Start packing the mbufs in this chain into 1253 * the fragment pointers. Stop when we run out 1254 * of fragments or hit the end of the mbuf chain. 1255 */ 1256 total_len = 0; 1257 1258 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1259 if (m->m_len != 0) { 1260 if (frag == WB_MAXFRAGS) 1261 break; 1262 total_len += m->m_len; 1263 f = &c->wb_ptr->wb_frag[frag]; 1264 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1265 if (frag == 0) { 1266 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1267 f->wb_status = 0; 1268 } else { 1269 f->wb_status = WB_TXSTAT_OWN; 1270 } 1271 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1272 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1273 frag++; 1274 } 1275 } 1276 1277 /* 1278 * Handle special case: we used up all 16 fragments, 1279 * but we have more mbufs left in the chain. Copy the 1280 * data into an mbuf cluster. Note that we don't 1281 * bother clearing the values in the other fragment 1282 * pointers/counters; it wouldn't gain us anything, 1283 * and would waste cycles. 1284 */ 1285 if (m != NULL) { 1286 struct mbuf *m_new = NULL; 1287 1288 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1289 if (m_new == NULL) 1290 return(1); 1291 if (m_head->m_pkthdr.len > MHLEN) { 1292 MCLGET(m_new, MB_DONTWAIT); 1293 if ((m_new->m_flags & M_EXT) == 0) { 1294 m_freem(m_new); 1295 return(1); 1296 } 1297 } 1298 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1299 mtod(m_new, caddr_t)); 1300 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1301 m_freem(m_head); 1302 m_head = m_new; 1303 f = &c->wb_ptr->wb_frag[0]; 1304 f->wb_status = 0; 1305 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1306 f->wb_ctl = total_len = m_new->m_len; 1307 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1308 frag = 1; 1309 } 1310 1311 if (total_len < WB_MIN_FRAMELEN) { 1312 f = &c->wb_ptr->wb_frag[frag]; 1313 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1314 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1315 f->wb_ctl |= WB_TXCTL_TLINK; 1316 f->wb_status = WB_TXSTAT_OWN; 1317 frag++; 1318 } 1319 1320 c->wb_mbuf = m_head; 1321 c->wb_lastdesc = frag - 1; 1322 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1323 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1324 1325 return(0); 1326 } 1327 1328 /* 1329 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1330 * to the mbuf data regions directly in the transmit lists. We also save a 1331 * copy of the pointers since the transmit list fragment pointers are 1332 * physical addresses. 1333 */ 1334 static void 1335 wb_start(struct ifnet *ifp) 1336 { 1337 struct wb_softc *sc = ifp->if_softc; 1338 struct mbuf *m_head = NULL; 1339 struct wb_chain *cur_tx = NULL, *start_tx; 1340 1341 /* 1342 * Check for an available queue slot. If there are none, 1343 * punt. 1344 */ 1345 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1346 ifp->if_flags |= IFF_OACTIVE; 1347 return; 1348 } 1349 1350 start_tx = sc->wb_cdata.wb_tx_free; 1351 1352 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1353 m_head = ifq_dequeue(&ifp->if_snd); 1354 if (m_head == NULL) 1355 break; 1356 1357 /* Pick a descriptor off the free list. */ 1358 cur_tx = sc->wb_cdata.wb_tx_free; 1359 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1360 1361 /* Pack the data into the descriptor. */ 1362 wb_encap(sc, cur_tx, m_head); 1363 1364 if (cur_tx != start_tx) 1365 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1366 1367 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1368 } 1369 1370 /* 1371 * If there are no packets queued, bail. 1372 */ 1373 if (cur_tx == NULL) 1374 return; 1375 1376 /* 1377 * Place the request for the upload interrupt 1378 * in the last descriptor in the chain. This way, if 1379 * we're chaining several packets at once, we'll only 1380 * get an interupt once for the whole chain rather than 1381 * once for each packet. 1382 */ 1383 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1384 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1385 sc->wb_cdata.wb_tx_tail = cur_tx; 1386 1387 if (sc->wb_cdata.wb_tx_head == NULL) { 1388 sc->wb_cdata.wb_tx_head = start_tx; 1389 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1390 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1391 } else { 1392 /* 1393 * We need to distinguish between the case where 1394 * the own bit is clear because the chip cleared it 1395 * and where the own bit is clear because we haven't 1396 * set it yet. The magic value WB_UNSET is just some 1397 * ramdomly chosen number which doesn't have the own 1398 * bit set. When we actually transmit the frame, the 1399 * status word will have _only_ the own bit set, so 1400 * the txeoc handler will be able to tell if it needs 1401 * to initiate another transmission to flush out pending 1402 * frames. 1403 */ 1404 WB_TXOWN(start_tx) = WB_UNSENT; 1405 } 1406 1407 /* 1408 * Set a timeout in case the chip goes out to lunch. 1409 */ 1410 ifp->if_timer = 5; 1411 } 1412 1413 static void 1414 wb_init(void *xsc) 1415 { 1416 struct wb_softc *sc = xsc; 1417 struct ifnet *ifp = &sc->arpcom.ac_if; 1418 int i; 1419 struct mii_data *mii; 1420 1421 crit_enter(); 1422 1423 mii = device_get_softc(sc->wb_miibus); 1424 1425 /* 1426 * Cancel pending I/O and free all RX/TX buffers. 1427 */ 1428 wb_stop(sc); 1429 wb_reset(sc); 1430 1431 sc->wb_txthresh = WB_TXTHRESH_INIT; 1432 1433 /* 1434 * Set cache alignment and burst length. 1435 */ 1436 #ifdef foo 1437 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1438 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1439 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1440 #endif 1441 1442 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION); 1443 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1444 switch(sc->wb_cachesize) { 1445 case 32: 1446 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1447 break; 1448 case 16: 1449 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1450 break; 1451 case 8: 1452 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1453 break; 1454 case 0: 1455 default: 1456 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1457 break; 1458 } 1459 1460 /* This doesn't tend to work too well at 100Mbps. */ 1461 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1462 1463 /* Init our MAC address */ 1464 for (i = 0; i < ETHER_ADDR_LEN; i++) 1465 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1466 1467 /* Init circular RX list. */ 1468 if (wb_list_rx_init(sc) == ENOBUFS) { 1469 printf("wb%d: initialization failed: no " 1470 "memory for rx buffers\n", sc->wb_unit); 1471 wb_stop(sc); 1472 crit_exit(); 1473 return; 1474 } 1475 1476 /* Init TX descriptors. */ 1477 wb_list_tx_init(sc); 1478 1479 /* If we want promiscuous mode, set the allframes bit. */ 1480 if (ifp->if_flags & IFF_PROMISC) 1481 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1482 else 1483 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1484 1485 /* 1486 * Set capture broadcast bit to capture broadcast frames. 1487 */ 1488 if (ifp->if_flags & IFF_BROADCAST) 1489 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1490 else 1491 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1492 1493 /* 1494 * Program the multicast filter, if necessary. 1495 */ 1496 wb_setmulti(sc); 1497 1498 /* 1499 * Load the address of the RX list. 1500 */ 1501 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1502 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1503 1504 /* 1505 * Enable interrupts. 1506 */ 1507 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1508 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1509 1510 /* Enable receiver and transmitter. */ 1511 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1512 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1513 1514 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1515 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1516 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1517 1518 mii_mediachg(mii); 1519 1520 ifp->if_flags |= IFF_RUNNING; 1521 ifp->if_flags &= ~IFF_OACTIVE; 1522 1523 crit_exit(); 1524 1525 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1526 } 1527 1528 /* 1529 * Set media options. 1530 */ 1531 static int 1532 wb_ifmedia_upd(struct ifnet *ifp) 1533 { 1534 struct wb_softc *sc = ifp->if_softc; 1535 1536 if (ifp->if_flags & IFF_UP) 1537 wb_init(sc); 1538 1539 return(0); 1540 } 1541 1542 /* 1543 * Report current media status. 1544 */ 1545 static void 1546 wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1547 { 1548 struct wb_softc *sc = ifp->if_softc; 1549 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1550 1551 mii_pollstat(mii); 1552 ifmr->ifm_active = mii->mii_media_active; 1553 ifmr->ifm_status = mii->mii_media_status; 1554 } 1555 1556 static int 1557 wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1558 { 1559 struct wb_softc *sc = ifp->if_softc; 1560 struct mii_data *mii; 1561 struct ifreq *ifr = (struct ifreq *) data; 1562 int error = 0; 1563 1564 crit_enter(); 1565 1566 switch(command) { 1567 case SIOCSIFFLAGS: 1568 if (ifp->if_flags & IFF_UP) 1569 wb_init(sc); 1570 else if (ifp->if_flags & IFF_RUNNING) 1571 wb_stop(sc); 1572 error = 0; 1573 break; 1574 case SIOCADDMULTI: 1575 case SIOCDELMULTI: 1576 wb_setmulti(sc); 1577 error = 0; 1578 break; 1579 case SIOCGIFMEDIA: 1580 case SIOCSIFMEDIA: 1581 mii = device_get_softc(sc->wb_miibus); 1582 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1583 break; 1584 default: 1585 error = ether_ioctl(ifp, command, data); 1586 break; 1587 } 1588 1589 crit_exit(); 1590 1591 return(error); 1592 } 1593 1594 static void 1595 wb_watchdog(struct ifnet *ifp) 1596 { 1597 struct wb_softc *sc = ifp->if_softc; 1598 1599 ifp->if_oerrors++; 1600 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1601 #ifdef foo 1602 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0) 1603 printf("wb%d: no carrier - transceiver cable problem?\n", 1604 sc->wb_unit); 1605 #endif 1606 wb_stop(sc); 1607 wb_reset(sc); 1608 wb_init(sc); 1609 1610 if (!ifq_is_empty(&ifp->if_snd)) 1611 wb_start(ifp); 1612 } 1613 1614 /* 1615 * Stop the adapter and free any mbufs allocated to the 1616 * RX and TX lists. 1617 */ 1618 static void 1619 wb_stop(struct wb_softc *sc) 1620 { 1621 struct ifnet *ifp = &sc->arpcom.ac_if; 1622 int i; 1623 1624 ifp->if_timer = 0; 1625 1626 callout_stop(&sc->wb_stat_timer); 1627 1628 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON)); 1629 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1630 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1631 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1632 1633 /* 1634 * Free data in the RX lists. 1635 */ 1636 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1637 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1638 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1639 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1640 } 1641 } 1642 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list)); 1643 1644 /* 1645 * Free the TX list buffers. 1646 */ 1647 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1648 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1649 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1650 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1651 } 1652 } 1653 1654 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list)); 1655 1656 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1657 } 1658 1659 /* 1660 * Stop all chip I/O so that the kernel's probe routines don't 1661 * get confused by errant DMAs when rebooting. 1662 */ 1663 static void 1664 wb_shutdown(device_t dev) 1665 { 1666 struct wb_softc *sc = device_get_softc(dev); 1667 1668 wb_stop(sc); 1669 } 1670