1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.29 2005/06/10 16:05:34 joerg Exp $ 34 */ 35 36 /* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Winbond W89C840F chip is a bus master; in some ways it resembles 50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 51 * one major difference which is that while the registers do many of 52 * the same things as a tulip adapter, the offsets are different: where 53 * tulip registers are typically spaced 8 bytes apart, the Winbond 54 * registers are spaced 4 bytes apart. The receiver filter is also 55 * programmed differently. 56 * 57 * Like the tulip, the Winbond chip uses small descriptors containing 58 * a status word, a control word and 32-bit areas that can either be used 59 * to point to two external data blocks, or to point to a single block 60 * and another descriptor in a linked list. Descriptors can be grouped 61 * together in blocks to form fixed length rings or can be chained 62 * together in linked lists. A single packet may be spread out over 63 * several descriptors if necessary. 64 * 65 * For the receive ring, this driver uses a linked list of descriptors, 66 * each pointing to a single mbuf cluster buffer, which us large enough 67 * to hold an entire packet. The link list is looped back to created a 68 * closed ring. 69 * 70 * For transmission, the driver creates a linked list of 'super descriptors' 71 * which each contain several individual descriptors linked toghether. 72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 73 * abuse as fragment pointers. This allows us to use a buffer managment 74 * scheme very similar to that used in the ThunderLAN and Etherlink XL 75 * drivers. 76 * 77 * Autonegotiation is performed using the external PHY via the MII bus. 78 * The sample boards I have all use a Davicom PHY. 79 * 80 * Note: the author of the Linux driver for the Winbond chip alludes 81 * to some sort of flaw in the chip's design that seems to mandate some 82 * drastic workaround which signigicantly impairs transmit performance. 83 * I have no idea what he's on about: transmit performance with all 84 * three of my test boards seems fine. 85 */ 86 87 #include "opt_bdg.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 #include <sys/thread2.h> 98 99 #include <net/if.h> 100 #include <net/ifq_var.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 106 #include <net/bpf.h> 107 108 #include <vm/vm.h> /* for vtophys */ 109 #include <vm/pmap.h> /* for vtophys */ 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <bus/pci/pcireg.h> 116 #include <bus/pci/pcivar.h> 117 118 #include <dev/netif/mii_layer/mii.h> 119 #include <dev/netif/mii_layer/miivar.h> 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 #define WB_USEIOSPACE 125 126 #include "if_wbreg.h" 127 128 /* 129 * Various supported device vendors/types and their names. 130 */ 131 static struct wb_type wb_devs[] = { 132 { WB_VENDORID, WB_DEVICEID_840F, 133 "Winbond W89C840F 10/100BaseTX" }, 134 { CP_VENDORID, CP_DEVICEID_RL100, 135 "Compex RL100-ATX 10/100baseTX" }, 136 { 0, 0, NULL } 137 }; 138 139 static int wb_probe(device_t); 140 static int wb_attach(device_t); 141 static int wb_detach(device_t); 142 143 static void wb_bfree(void *); 144 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 145 struct mbuf *); 146 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 147 148 static void wb_rxeof(struct wb_softc *); 149 static void wb_rxeoc(struct wb_softc *); 150 static void wb_txeof(struct wb_softc *); 151 static void wb_txeoc(struct wb_softc *); 152 static void wb_intr(void *); 153 static void wb_tick(void *); 154 static void wb_start(struct ifnet *); 155 static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 156 static void wb_init(void *); 157 static void wb_stop(struct wb_softc *); 158 static void wb_watchdog(struct ifnet *); 159 static void wb_shutdown(device_t); 160 static int wb_ifmedia_upd(struct ifnet *); 161 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 162 163 static void wb_eeprom_putbyte(struct wb_softc *, int); 164 static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *); 165 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int); 166 static void wb_mii_sync(struct wb_softc *); 167 static void wb_mii_send(struct wb_softc *, uint32_t, int); 168 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 169 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 170 171 static void wb_setcfg(struct wb_softc *, uint32_t); 172 static void wb_setmulti(struct wb_softc *); 173 static void wb_reset(struct wb_softc *); 174 static void wb_fixmedia(struct wb_softc *); 175 static int wb_list_rx_init(struct wb_softc *); 176 static int wb_list_tx_init(struct wb_softc *); 177 178 static int wb_miibus_readreg(device_t, int, int); 179 static int wb_miibus_writereg(device_t, int, int, int); 180 static void wb_miibus_statchg(device_t); 181 182 #ifdef WB_USEIOSPACE 183 #define WB_RES SYS_RES_IOPORT 184 #define WB_RID WB_PCI_LOIO 185 #else 186 #define WB_RES SYS_RES_MEMORY 187 #define WB_RID WB_PCI_LOMEM 188 #endif 189 190 static device_method_t wb_methods[] = { 191 /* Device interface */ 192 DEVMETHOD(device_probe, wb_probe), 193 DEVMETHOD(device_attach, wb_attach), 194 DEVMETHOD(device_detach, wb_detach), 195 DEVMETHOD(device_shutdown, wb_shutdown), 196 197 /* bus interface, for miibus */ 198 DEVMETHOD(bus_print_child, bus_generic_print_child), 199 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 200 201 /* MII interface */ 202 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 203 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 204 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 205 { 0, 0 } 206 }; 207 208 static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc)); 209 static devclass_t wb_devclass; 210 211 DECLARE_DUMMY_MODULE(if_wb); 212 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 213 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 214 215 #define WB_SETBIT(sc, reg, x) \ 216 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 217 218 #define WB_CLRBIT(sc, reg, x) \ 219 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 220 221 #define SIO_SET(x) \ 222 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x)) 223 224 #define SIO_CLR(x) \ 225 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x)) 226 227 /* 228 * Send a read command and address to the EEPROM, check for ACK. 229 */ 230 static void 231 wb_eeprom_putbyte(struct wb_softc *sc, int addr) 232 { 233 int d, i; 234 235 d = addr | WB_EECMD_READ; 236 237 /* 238 * Feed in each bit and stobe the clock. 239 */ 240 for (i = 0x400; i; i >>= 1) { 241 if (d & i) 242 SIO_SET(WB_SIO_EE_DATAIN); 243 else 244 SIO_CLR(WB_SIO_EE_DATAIN); 245 DELAY(100); 246 SIO_SET(WB_SIO_EE_CLK); 247 DELAY(150); 248 SIO_CLR(WB_SIO_EE_CLK); 249 DELAY(100); 250 } 251 } 252 253 /* 254 * Read a word of data stored in the EEPROM at address 'addr.' 255 */ 256 static void 257 wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest) 258 { 259 int i; 260 uint16_t word = 0; 261 262 /* Enter EEPROM access mode. */ 263 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 264 265 /* 266 * Send address of word we want to read. 267 */ 268 wb_eeprom_putbyte(sc, addr); 269 270 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 271 272 /* 273 * Start reading bits from EEPROM. 274 */ 275 for (i = 0x8000; i; i >>= 1) { 276 SIO_SET(WB_SIO_EE_CLK); 277 DELAY(100); 278 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 279 word |= i; 280 SIO_CLR(WB_SIO_EE_CLK); 281 DELAY(100); 282 } 283 284 /* Turn off EEPROM access mode. */ 285 CSR_WRITE_4(sc, WB_SIO, 0); 286 287 *dest = word; 288 } 289 290 /* 291 * Read a sequence of words from the EEPROM. 292 */ 293 static void 294 wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt) 295 { 296 int i; 297 uint16_t word = 0, *ptr; 298 299 for (i = 0; i < cnt; i++) { 300 wb_eeprom_getword(sc, off + i, &word); 301 ptr = (uint16_t *)(dest + (i * 2)); 302 *ptr = word; 303 } 304 } 305 306 /* 307 * Sync the PHYs by setting data bit and strobing the clock 32 times. 308 */ 309 static void 310 wb_mii_sync(struct wb_softc *sc) 311 { 312 int i; 313 314 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN); 315 316 for (i = 0; i < 32; i++) { 317 SIO_SET(WB_SIO_MII_CLK); 318 DELAY(1); 319 SIO_CLR(WB_SIO_MII_CLK); 320 DELAY(1); 321 } 322 } 323 324 /* 325 * Clock a series of bits through the MII. 326 */ 327 static void 328 wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt) 329 { 330 int i; 331 332 SIO_CLR(WB_SIO_MII_CLK); 333 334 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 335 if (bits & i) 336 SIO_SET(WB_SIO_MII_DATAIN); 337 else 338 SIO_CLR(WB_SIO_MII_DATAIN); 339 DELAY(1); 340 SIO_CLR(WB_SIO_MII_CLK); 341 DELAY(1); 342 SIO_SET(WB_SIO_MII_CLK); 343 } 344 } 345 346 /* 347 * Read an PHY register through the MII. 348 */ 349 static int 350 wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame) 351 { 352 int ack, i; 353 354 crit_enter(); 355 356 /* 357 * Set up frame for RX. 358 */ 359 frame->mii_stdelim = WB_MII_STARTDELIM; 360 frame->mii_opcode = WB_MII_READOP; 361 frame->mii_turnaround = 0; 362 frame->mii_data = 0; 363 364 CSR_WRITE_4(sc, WB_SIO, 0); 365 366 /* 367 * Turn on data xmit. 368 */ 369 SIO_SET(WB_SIO_MII_DIR); 370 371 wb_mii_sync(sc); 372 373 /* 374 * Send command/address info. 375 */ 376 wb_mii_send(sc, frame->mii_stdelim, 2); 377 wb_mii_send(sc, frame->mii_opcode, 2); 378 wb_mii_send(sc, frame->mii_phyaddr, 5); 379 wb_mii_send(sc, frame->mii_regaddr, 5); 380 381 /* Idle bit */ 382 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN)); 383 DELAY(1); 384 SIO_SET(WB_SIO_MII_CLK); 385 DELAY(1); 386 387 /* Turn off xmit. */ 388 SIO_CLR(WB_SIO_MII_DIR); 389 /* Check for ack */ 390 SIO_CLR(WB_SIO_MII_CLK); 391 DELAY(1); 392 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 393 SIO_SET(WB_SIO_MII_CLK); 394 DELAY(1); 395 SIO_CLR(WB_SIO_MII_CLK); 396 DELAY(1); 397 SIO_SET(WB_SIO_MII_CLK); 398 DELAY(1); 399 400 /* 401 * Now try reading data bits. If the ack failed, we still 402 * need to clock through 16 cycles to keep the PHY(s) in sync. 403 */ 404 if (ack) { 405 for(i = 0; i < 16; i++) { 406 SIO_CLR(WB_SIO_MII_CLK); 407 DELAY(1); 408 SIO_SET(WB_SIO_MII_CLK); 409 DELAY(1); 410 } 411 goto fail; 412 } 413 414 for (i = 0x8000; i; i >>= 1) { 415 SIO_CLR(WB_SIO_MII_CLK); 416 DELAY(1); 417 if (!ack) { 418 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 419 frame->mii_data |= i; 420 DELAY(1); 421 } 422 SIO_SET(WB_SIO_MII_CLK); 423 DELAY(1); 424 } 425 426 fail: 427 428 SIO_CLR(WB_SIO_MII_CLK); 429 DELAY(1); 430 SIO_SET(WB_SIO_MII_CLK); 431 DELAY(1); 432 433 crit_exit(); 434 435 if (ack) 436 return(1); 437 return(0); 438 } 439 440 /* 441 * Write to a PHY register through the MII. 442 */ 443 static int 444 wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame) 445 { 446 447 crit_enter(); 448 /* 449 * Set up frame for TX. 450 */ 451 452 frame->mii_stdelim = WB_MII_STARTDELIM; 453 frame->mii_opcode = WB_MII_WRITEOP; 454 frame->mii_turnaround = WB_MII_TURNAROUND; 455 456 /* 457 * Turn on data output. 458 */ 459 SIO_SET(WB_SIO_MII_DIR); 460 461 wb_mii_sync(sc); 462 463 wb_mii_send(sc, frame->mii_stdelim, 2); 464 wb_mii_send(sc, frame->mii_opcode, 2); 465 wb_mii_send(sc, frame->mii_phyaddr, 5); 466 wb_mii_send(sc, frame->mii_regaddr, 5); 467 wb_mii_send(sc, frame->mii_turnaround, 2); 468 wb_mii_send(sc, frame->mii_data, 16); 469 470 /* Idle bit. */ 471 SIO_SET(WB_SIO_MII_CLK); 472 DELAY(1); 473 SIO_CLR(WB_SIO_MII_CLK); 474 DELAY(1); 475 476 /* 477 * Turn off xmit. 478 */ 479 SIO_CLR(WB_SIO_MII_DIR); 480 481 crit_exit(); 482 483 return(0); 484 } 485 486 static int 487 wb_miibus_readreg(device_t dev, int phy, int reg) 488 { 489 struct wb_softc *sc = device_get_softc(dev); 490 struct wb_mii_frame frame; 491 492 bzero(&frame, sizeof(frame)); 493 494 frame.mii_phyaddr = phy; 495 frame.mii_regaddr = reg; 496 wb_mii_readreg(sc, &frame); 497 498 return(frame.mii_data); 499 } 500 501 static int 502 wb_miibus_writereg(device_t dev, int phy, int reg, int data) 503 { 504 struct wb_softc *sc = device_get_softc(dev); 505 struct wb_mii_frame frame; 506 507 bzero(&frame, sizeof(frame)); 508 509 frame.mii_phyaddr = phy; 510 frame.mii_regaddr = reg; 511 frame.mii_data = data; 512 513 wb_mii_writereg(sc, &frame); 514 515 return(0); 516 } 517 518 static void 519 wb_miibus_statchg(device_t dev) 520 { 521 struct wb_softc *sc = device_get_softc(dev); 522 struct mii_data *mii; 523 524 mii = device_get_softc(sc->wb_miibus); 525 wb_setcfg(sc, mii->mii_media_active); 526 } 527 528 /* 529 * Program the 64-bit multicast hash filter. 530 */ 531 static void 532 wb_setmulti(struct wb_softc *sc) 533 { 534 struct ifnet *ifp = &sc->arpcom.ac_if; 535 int h = 0, mcnt = 0; 536 uint32_t hashes[2] = { 0, 0 }; 537 struct ifmultiaddr *ifma; 538 uint32_t rxfilt; 539 540 rxfilt = CSR_READ_4(sc, WB_NETCFG); 541 542 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 543 rxfilt |= WB_NETCFG_RX_MULTI; 544 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 545 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 546 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 547 return; 548 } 549 550 /* first, zot all the existing hash bits */ 551 CSR_WRITE_4(sc, WB_MAR0, 0); 552 CSR_WRITE_4(sc, WB_MAR1, 0); 553 554 /* now program new ones */ 555 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 556 if (ifma->ifma_addr->sa_family != AF_LINK) 557 continue; 558 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 559 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 560 if (h < 32) 561 hashes[0] |= (1 << h); 562 else 563 hashes[1] |= (1 << (h - 32)); 564 mcnt++; 565 } 566 567 if (mcnt) 568 rxfilt |= WB_NETCFG_RX_MULTI; 569 else 570 rxfilt &= ~WB_NETCFG_RX_MULTI; 571 572 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 573 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 574 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 575 } 576 577 /* 578 * The Winbond manual states that in order to fiddle with the 579 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 580 * first have to put the transmit and/or receive logic in the idle state. 581 */ 582 static void 583 wb_setcfg(struct wb_softc *sc, uint32_t media) 584 { 585 int i, restart = 0; 586 587 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) { 588 restart = 1; 589 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)); 590 591 for (i = 0; i < WB_TIMEOUT; i++) { 592 DELAY(10); 593 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 594 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 595 break; 596 } 597 598 if (i == WB_TIMEOUT) { 599 if_printf(&sc->arpcom.ac_if, "failed to force tx and " 600 "rx to idle state\n"); 601 } 602 } 603 604 if (IFM_SUBTYPE(media) == IFM_10_T) 605 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 606 else 607 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 608 609 if ((media & IFM_GMASK) == IFM_FDX) 610 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 611 else 612 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 613 614 if (restart) 615 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON); 616 } 617 618 static void 619 wb_reset(struct wb_softc *sc) 620 { 621 int i; 622 struct mii_data *mii; 623 624 CSR_WRITE_4(sc, WB_NETCFG, 0); 625 CSR_WRITE_4(sc, WB_BUSCTL, 0); 626 CSR_WRITE_4(sc, WB_TXADDR, 0); 627 CSR_WRITE_4(sc, WB_RXADDR, 0); 628 629 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 630 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 631 632 for (i = 0; i < WB_TIMEOUT; i++) { 633 DELAY(10); 634 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0) 635 break; 636 } 637 if (i == WB_TIMEOUT) 638 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 639 640 /* Wait a little while for the chip to get its brains in order. */ 641 DELAY(1000); 642 643 if (sc->wb_miibus == NULL) 644 return; 645 646 mii = device_get_softc(sc->wb_miibus); 647 if (mii == NULL) 648 return; 649 650 if (mii->mii_instance) { 651 struct mii_softc *miisc; 652 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 653 mii_phy_reset(miisc); 654 } 655 } 656 657 static void 658 wb_fixmedia(struct wb_softc *sc) 659 { 660 struct mii_data *mii; 661 uint32_t media; 662 663 if (sc->wb_miibus == NULL) 664 return; 665 666 mii = device_get_softc(sc->wb_miibus); 667 668 mii_pollstat(mii); 669 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 670 media = mii->mii_media_active & ~IFM_10_T; 671 media |= IFM_100_TX; 672 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 673 media = mii->mii_media_active & ~IFM_100_TX; 674 media |= IFM_10_T; 675 } else 676 return; 677 678 ifmedia_set(&mii->mii_media, media); 679 } 680 681 /* 682 * Probe for a Winbond chip. Check the PCI vendor and device 683 * IDs against our list and return a device name if we find a match. 684 */ 685 static int wb_probe(device_t dev) 686 { 687 struct wb_type *t; 688 uint16_t vendor, product; 689 690 vendor = pci_get_vendor(dev); 691 product = pci_get_device(dev); 692 693 for (t = wb_devs; t->wb_name != NULL; t++) { 694 if (vendor == t->wb_vid && product == t->wb_did) { 695 device_set_desc(dev, t->wb_name); 696 return(0); 697 } 698 } 699 700 return(ENXIO); 701 } 702 703 /* 704 * Attach the interface. Allocate softc structures, do ifmedia 705 * setup and ethernet/BPF attach. 706 */ 707 static int 708 wb_attach(device_t dev) 709 { 710 u_char eaddr[ETHER_ADDR_LEN]; 711 uint32_t command; 712 struct wb_softc *sc; 713 struct ifnet *ifp; 714 int error = 0, rid; 715 716 sc = device_get_softc(dev); 717 callout_init(&sc->wb_stat_timer); 718 719 /* 720 * Handle power management nonsense. 721 */ 722 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 723 uint32_t iobase, membase, irq; 724 725 /* Save important PCI config data. */ 726 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 727 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 728 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 729 730 /* Reset the power state. */ 731 device_printf(dev, "chip is in D%d power mode " 732 "-- setting to D0\n", pci_get_powerstate(dev)); 733 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 734 735 /* Restore PCI config data. */ 736 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 737 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 738 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 739 } 740 741 /* 742 * Map control/status registers. 743 */ 744 pci_enable_busmaster(dev); 745 pci_enable_io(dev, SYS_RES_IOPORT); 746 pci_enable_io(dev, SYS_RES_MEMORY); 747 command = pci_read_config(dev, PCIR_COMMAND, 4); 748 749 #ifdef WB_USEIOSPACE 750 if ((command & PCIM_CMD_PORTEN) == 0) { 751 device_printf(dev, "failed to enable I/O ports!\n"); 752 error = ENXIO; 753 goto fail; 754 } 755 #else 756 if ((command & PCIM_CMD_MEMEN) == 0) { 757 device_printf(dev, "failed to enable memory mapping!\n"); 758 error = ENXIO; 759 goto fail; 760 } 761 #endif 762 763 rid = WB_RID; 764 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 765 766 if (sc->wb_res == NULL) { 767 device_printf(dev, "couldn't map ports/memory\n"); 768 error = ENXIO; 769 goto fail; 770 } 771 772 sc->wb_btag = rman_get_bustag(sc->wb_res); 773 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 774 775 /* Allocate interrupt */ 776 rid = 0; 777 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 778 RF_SHAREABLE | RF_ACTIVE); 779 780 if (sc->wb_irq == NULL) { 781 device_printf(dev, "couldn't map interrupt\n"); 782 error = ENXIO; 783 goto fail; 784 } 785 786 /* Save the cache line size. */ 787 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 788 789 ifp = &sc->arpcom.ac_if; 790 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 791 792 /* Reset the adapter. */ 793 wb_reset(sc); 794 795 /* 796 * Get station address from the EEPROM. 797 */ 798 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3); 799 800 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 801 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 802 803 if (sc->wb_ldata == NULL) { 804 device_printf(dev, "no memory for list buffers!\n"); 805 error = ENXIO; 806 goto fail; 807 } 808 809 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 810 811 ifp->if_softc = sc; 812 ifp->if_mtu = ETHERMTU; 813 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 814 ifp->if_ioctl = wb_ioctl; 815 ifp->if_start = wb_start; 816 ifp->if_watchdog = wb_watchdog; 817 ifp->if_init = wb_init; 818 ifp->if_baudrate = 10000000; 819 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1); 820 ifq_set_ready(&ifp->if_snd); 821 822 /* 823 * Do MII setup. 824 */ 825 if (mii_phy_probe(dev, &sc->wb_miibus, 826 wb_ifmedia_upd, wb_ifmedia_sts)) { 827 error = ENXIO; 828 goto fail; 829 } 830 831 /* 832 * Call MI attach routine. 833 */ 834 ether_ifattach(ifp, eaddr); 835 836 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 837 wb_intr, sc, &sc->wb_intrhand, NULL); 838 839 if (error) { 840 device_printf(dev, "couldn't set up irq\n"); 841 ether_ifdetach(ifp); 842 goto fail; 843 } 844 845 return(0); 846 847 fail: 848 wb_detach(dev); 849 return(error); 850 } 851 852 static int 853 wb_detach(device_t dev) 854 { 855 struct wb_softc *sc = device_get_softc(dev); 856 struct ifnet *ifp = &sc->arpcom.ac_if; 857 858 crit_enter(); 859 860 if (device_is_attached(dev)) { 861 if (bus_child_present(dev)) 862 wb_stop(sc); 863 ether_ifdetach(ifp); 864 } 865 866 if (sc->wb_miibus) 867 device_delete_child(dev, sc->wb_miibus); 868 bus_generic_detach(dev); 869 870 if (sc->wb_intrhand) 871 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 872 crit_exit(); 873 if (sc->wb_irq); 874 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 875 if (sc->wb_res) 876 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 877 if (sc->wb_ldata_ptr) { 878 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 879 M_DEVBUF); 880 } 881 882 return(0); 883 } 884 885 /* 886 * Initialize the transmit descriptors. 887 */ 888 static int 889 wb_list_tx_init(struct wb_softc *sc) 890 { 891 struct wb_chain_data *cd; 892 struct wb_list_data *ld; 893 int i, nexti; 894 895 cd = &sc->wb_cdata; 896 ld = sc->wb_ldata; 897 898 for (i = 0; i < WB_TX_LIST_CNT; i++) { 899 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1; 900 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 901 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti]; 902 } 903 904 cd->wb_tx_free = &cd->wb_tx_chain[0]; 905 cd->wb_tx_tail = cd->wb_tx_head = NULL; 906 907 return(0); 908 } 909 910 /* 911 * Initialize the RX descriptors and allocate mbufs for them. Note that 912 * we arrange the descriptors in a closed ring, so that the last descriptor 913 * points back to the first. 914 */ 915 static int 916 wb_list_rx_init(struct wb_softc *sc) 917 { 918 struct wb_chain_data *cd; 919 struct wb_list_data *ld; 920 int i, nexti; 921 922 cd = &sc->wb_cdata; 923 ld = sc->wb_ldata; 924 925 for (i = 0; i < WB_RX_LIST_CNT; i++) { 926 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i]; 927 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i]; 928 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 929 return(ENOBUFS); 930 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1; 931 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti]; 932 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]); 933 } 934 935 cd->wb_rx_head = &cd->wb_rx_chain[0]; 936 937 return(0); 938 } 939 940 static void 941 wb_bfree(void *arg) 942 { 943 } 944 945 /* 946 * Initialize an RX descriptor and attach an MBUF cluster. 947 */ 948 static int 949 wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m) 950 { 951 struct mbuf *m_new = NULL; 952 953 if (m == NULL) { 954 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 955 if (m_new == NULL) 956 return(ENOBUFS); 957 958 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 959 m_new->m_flags |= M_EXT; 960 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 961 m_new->m_len = WB_BUFBYTES; 962 m_new->m_ext.ext_free = wb_bfree; 963 m_new->m_ext.ext_ref = wb_bfree; 964 } else { 965 m_new = m; 966 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 967 m_new->m_data = m_new->m_ext.ext_buf; 968 } 969 970 m_adj(m_new, sizeof(uint64_t)); 971 972 c->wb_mbuf = m_new; 973 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 974 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 975 c->wb_ptr->wb_status = WB_RXSTAT; 976 977 return(0); 978 } 979 980 /* 981 * A frame has been uploaded: pass the resulting mbuf chain up to 982 * the higher level protocols. 983 */ 984 static void 985 wb_rxeof(struct wb_softc *sc) 986 { 987 struct ifnet *ifp = &sc->arpcom.ac_if; 988 struct mbuf *m, *m0; 989 struct wb_chain_onefrag *cur_rx; 990 int total_len = 0; 991 uint32_t rxstat; 992 993 for (;;) { 994 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status; 995 if ((rxstat & WB_RXSTAT_OWN) == 0) 996 break; 997 998 cur_rx = sc->wb_cdata.wb_rx_head; 999 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1000 1001 m = cur_rx->wb_mbuf; 1002 1003 if ((rxstat & WB_RXSTAT_MIIERR) || 1004 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1005 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1006 (rxstat & WB_RXSTAT_LASTFRAG) == 0|| 1007 (rxstat & WB_RXSTAT_RXCMP) == 0) { 1008 ifp->if_ierrors++; 1009 wb_newbuf(sc, cur_rx, m); 1010 if_printf(ifp, "receiver babbling: possible chip " 1011 "bug, forcing reset\n"); 1012 wb_fixmedia(sc); 1013 wb_reset(sc); 1014 wb_init(sc); 1015 return; 1016 } 1017 1018 if (rxstat & WB_RXSTAT_RXERR) { 1019 ifp->if_ierrors++; 1020 wb_newbuf(sc, cur_rx, m); 1021 break; 1022 } 1023 1024 /* No errors; receive the packet. */ 1025 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1026 1027 /* 1028 * XXX The Winbond chip includes the CRC with every 1029 * received frame, and there's no way to turn this 1030 * behavior off (at least, I can't find anything in 1031 * the manual that explains how to do it) so we have 1032 * to trim off the CRC manually. 1033 */ 1034 total_len -= ETHER_CRC_LEN; 1035 1036 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1037 total_len + ETHER_ALIGN, 0, ifp, NULL); 1038 wb_newbuf(sc, cur_rx, m); 1039 if (m0 == NULL) { 1040 ifp->if_ierrors++; 1041 break; 1042 } 1043 m_adj(m0, ETHER_ALIGN); 1044 m = m0; 1045 1046 ifp->if_ipackets++; 1047 (*ifp->if_input)(ifp, m); 1048 } 1049 } 1050 1051 static void 1052 wb_rxeoc(struct wb_softc *sc) 1053 { 1054 wb_rxeof(sc); 1055 1056 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1057 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1058 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1059 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1060 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1061 } 1062 1063 /* 1064 * A frame was downloaded to the chip. It's safe for us to clean up 1065 * the list buffers. 1066 */ 1067 static void 1068 wb_txeof(struct wb_softc *sc) 1069 { 1070 struct ifnet *ifp = &sc->arpcom.ac_if; 1071 struct wb_chain *cur_tx; 1072 1073 /* Clear the timeout timer. */ 1074 ifp->if_timer = 0; 1075 1076 if (sc->wb_cdata.wb_tx_head == NULL) 1077 return; 1078 1079 /* 1080 * Go through our tx list and free mbufs for those 1081 * frames that have been transmitted. 1082 */ 1083 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1084 uint32_t txstat; 1085 1086 cur_tx = sc->wb_cdata.wb_tx_head; 1087 txstat = WB_TXSTATUS(cur_tx); 1088 1089 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1090 break; 1091 1092 if (txstat & WB_TXSTAT_TXERR) { 1093 ifp->if_oerrors++; 1094 if (txstat & WB_TXSTAT_ABORT) 1095 ifp->if_collisions++; 1096 if (txstat & WB_TXSTAT_LATECOLL) 1097 ifp->if_collisions++; 1098 } 1099 1100 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1101 1102 ifp->if_opackets++; 1103 m_freem(cur_tx->wb_mbuf); 1104 cur_tx->wb_mbuf = NULL; 1105 1106 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1107 sc->wb_cdata.wb_tx_head = NULL; 1108 sc->wb_cdata.wb_tx_tail = NULL; 1109 break; 1110 } 1111 1112 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1113 } 1114 } 1115 1116 /* 1117 * TX 'end of channel' interrupt handler. 1118 */ 1119 static void 1120 wb_txeoc(struct wb_softc *sc) 1121 { 1122 struct ifnet *ifp = &sc->arpcom.ac_if; 1123 1124 ifp->if_timer = 0; 1125 1126 if (sc->wb_cdata.wb_tx_head == NULL) { 1127 ifp->if_flags &= ~IFF_OACTIVE; 1128 sc->wb_cdata.wb_tx_tail = NULL; 1129 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1130 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1131 ifp->if_timer = 5; 1132 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1133 } 1134 } 1135 1136 static void 1137 wb_intr(void *arg) 1138 { 1139 struct wb_softc *sc = arg; 1140 struct ifnet *ifp = &sc->arpcom.ac_if; 1141 uint32_t status; 1142 1143 if ((ifp->if_flags & IFF_UP) == 0) 1144 return; 1145 1146 /* Disable interrupts. */ 1147 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1148 1149 for (;;) { 1150 status = CSR_READ_4(sc, WB_ISR); 1151 if (status) 1152 CSR_WRITE_4(sc, WB_ISR, status); 1153 1154 if ((status & WB_INTRS) == 0) 1155 break; 1156 1157 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1158 ifp->if_ierrors++; 1159 wb_reset(sc); 1160 if (status & WB_ISR_RX_ERR) 1161 wb_fixmedia(sc); 1162 wb_init(sc); 1163 continue; 1164 } 1165 1166 if (status & WB_ISR_RX_OK) 1167 wb_rxeof(sc); 1168 1169 if (status & WB_ISR_RX_IDLE) 1170 wb_rxeoc(sc); 1171 1172 if (status & WB_ISR_TX_OK) 1173 wb_txeof(sc); 1174 1175 if (status & WB_ISR_TX_NOBUF) 1176 wb_txeoc(sc); 1177 1178 if (status & WB_ISR_TX_IDLE) { 1179 wb_txeof(sc); 1180 if (sc->wb_cdata.wb_tx_head != NULL) { 1181 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1182 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1183 } 1184 } 1185 1186 if (status & WB_ISR_TX_UNDERRUN) { 1187 ifp->if_oerrors++; 1188 wb_txeof(sc); 1189 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1190 /* Jack up TX threshold */ 1191 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1192 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1193 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1194 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1195 } 1196 1197 if (status & WB_ISR_BUS_ERR) { 1198 wb_reset(sc); 1199 wb_init(sc); 1200 } 1201 } 1202 1203 /* Re-enable interrupts. */ 1204 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1205 1206 if (!ifq_is_empty(&ifp->if_snd)) 1207 wb_start(ifp); 1208 } 1209 1210 static void 1211 wb_tick(void *xsc) 1212 { 1213 struct wb_softc *sc = xsc; 1214 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1215 1216 crit_enter(); 1217 1218 mii_tick(mii); 1219 1220 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1221 1222 crit_exit(); 1223 } 1224 1225 /* 1226 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1227 * pointers to the fragment pointers. 1228 */ 1229 static int 1230 wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head) 1231 { 1232 struct wb_desc *f = NULL; 1233 struct mbuf *m; 1234 int frag, total_len; 1235 1236 /* 1237 * Start packing the mbufs in this chain into 1238 * the fragment pointers. Stop when we run out 1239 * of fragments or hit the end of the mbuf chain. 1240 */ 1241 total_len = 0; 1242 1243 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1244 if (m->m_len != 0) { 1245 if (frag == WB_MAXFRAGS) 1246 break; 1247 total_len += m->m_len; 1248 f = &c->wb_ptr->wb_frag[frag]; 1249 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1250 if (frag == 0) { 1251 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1252 f->wb_status = 0; 1253 } else { 1254 f->wb_status = WB_TXSTAT_OWN; 1255 } 1256 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1257 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1258 frag++; 1259 } 1260 } 1261 1262 /* 1263 * Handle special case: we used up all 16 fragments, 1264 * but we have more mbufs left in the chain. Copy the 1265 * data into an mbuf cluster. Note that we don't 1266 * bother clearing the values in the other fragment 1267 * pointers/counters; it wouldn't gain us anything, 1268 * and would waste cycles. 1269 */ 1270 if (m != NULL) { 1271 struct mbuf *m_new = NULL; 1272 1273 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1274 if (m_new == NULL) 1275 return(1); 1276 if (m_head->m_pkthdr.len > MHLEN) { 1277 MCLGET(m_new, MB_DONTWAIT); 1278 if ((m_new->m_flags & M_EXT) == 0) { 1279 m_freem(m_new); 1280 return(1); 1281 } 1282 } 1283 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1284 mtod(m_new, caddr_t)); 1285 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1286 m_freem(m_head); 1287 m_head = m_new; 1288 f = &c->wb_ptr->wb_frag[0]; 1289 f->wb_status = 0; 1290 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1291 f->wb_ctl = total_len = m_new->m_len; 1292 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1293 frag = 1; 1294 } 1295 1296 if (total_len < WB_MIN_FRAMELEN) { 1297 f = &c->wb_ptr->wb_frag[frag]; 1298 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1299 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1300 f->wb_ctl |= WB_TXCTL_TLINK; 1301 f->wb_status = WB_TXSTAT_OWN; 1302 frag++; 1303 } 1304 1305 c->wb_mbuf = m_head; 1306 c->wb_lastdesc = frag - 1; 1307 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1308 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1309 1310 return(0); 1311 } 1312 1313 /* 1314 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1315 * to the mbuf data regions directly in the transmit lists. We also save a 1316 * copy of the pointers since the transmit list fragment pointers are 1317 * physical addresses. 1318 */ 1319 static void 1320 wb_start(struct ifnet *ifp) 1321 { 1322 struct wb_softc *sc = ifp->if_softc; 1323 struct mbuf *m_head = NULL; 1324 struct wb_chain *cur_tx = NULL, *start_tx; 1325 1326 /* 1327 * Check for an available queue slot. If there are none, 1328 * punt. 1329 */ 1330 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1331 ifp->if_flags |= IFF_OACTIVE; 1332 return; 1333 } 1334 1335 start_tx = sc->wb_cdata.wb_tx_free; 1336 1337 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1338 m_head = ifq_dequeue(&ifp->if_snd); 1339 if (m_head == NULL) 1340 break; 1341 1342 /* Pick a descriptor off the free list. */ 1343 cur_tx = sc->wb_cdata.wb_tx_free; 1344 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1345 1346 /* Pack the data into the descriptor. */ 1347 wb_encap(sc, cur_tx, m_head); 1348 1349 if (cur_tx != start_tx) 1350 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1351 1352 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1353 } 1354 1355 /* 1356 * If there are no packets queued, bail. 1357 */ 1358 if (cur_tx == NULL) 1359 return; 1360 1361 /* 1362 * Place the request for the upload interrupt 1363 * in the last descriptor in the chain. This way, if 1364 * we're chaining several packets at once, we'll only 1365 * get an interupt once for the whole chain rather than 1366 * once for each packet. 1367 */ 1368 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1369 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1370 sc->wb_cdata.wb_tx_tail = cur_tx; 1371 1372 if (sc->wb_cdata.wb_tx_head == NULL) { 1373 sc->wb_cdata.wb_tx_head = start_tx; 1374 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1375 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1376 } else { 1377 /* 1378 * We need to distinguish between the case where 1379 * the own bit is clear because the chip cleared it 1380 * and where the own bit is clear because we haven't 1381 * set it yet. The magic value WB_UNSET is just some 1382 * ramdomly chosen number which doesn't have the own 1383 * bit set. When we actually transmit the frame, the 1384 * status word will have _only_ the own bit set, so 1385 * the txeoc handler will be able to tell if it needs 1386 * to initiate another transmission to flush out pending 1387 * frames. 1388 */ 1389 WB_TXOWN(start_tx) = WB_UNSENT; 1390 } 1391 1392 /* 1393 * Set a timeout in case the chip goes out to lunch. 1394 */ 1395 ifp->if_timer = 5; 1396 } 1397 1398 static void 1399 wb_init(void *xsc) 1400 { 1401 struct wb_softc *sc = xsc; 1402 struct ifnet *ifp = &sc->arpcom.ac_if; 1403 int i; 1404 struct mii_data *mii; 1405 1406 crit_enter(); 1407 1408 mii = device_get_softc(sc->wb_miibus); 1409 1410 /* 1411 * Cancel pending I/O and free all RX/TX buffers. 1412 */ 1413 wb_stop(sc); 1414 wb_reset(sc); 1415 1416 sc->wb_txthresh = WB_TXTHRESH_INIT; 1417 1418 /* 1419 * Set cache alignment and burst length. 1420 */ 1421 #ifdef foo 1422 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1423 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1424 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1425 #endif 1426 1427 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION); 1428 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1429 switch(sc->wb_cachesize) { 1430 case 32: 1431 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1432 break; 1433 case 16: 1434 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1435 break; 1436 case 8: 1437 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1438 break; 1439 case 0: 1440 default: 1441 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1442 break; 1443 } 1444 1445 /* This doesn't tend to work too well at 100Mbps. */ 1446 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1447 1448 /* Init our MAC address */ 1449 for (i = 0; i < ETHER_ADDR_LEN; i++) 1450 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1451 1452 /* Init circular RX list. */ 1453 if (wb_list_rx_init(sc) == ENOBUFS) { 1454 if_printf(ifp, "initialization failed: no " 1455 "memory for rx buffers\n"); 1456 wb_stop(sc); 1457 crit_exit(); 1458 return; 1459 } 1460 1461 /* Init TX descriptors. */ 1462 wb_list_tx_init(sc); 1463 1464 /* If we want promiscuous mode, set the allframes bit. */ 1465 if (ifp->if_flags & IFF_PROMISC) 1466 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1467 else 1468 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1469 1470 /* 1471 * Set capture broadcast bit to capture broadcast frames. 1472 */ 1473 if (ifp->if_flags & IFF_BROADCAST) 1474 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1475 else 1476 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1477 1478 /* 1479 * Program the multicast filter, if necessary. 1480 */ 1481 wb_setmulti(sc); 1482 1483 /* 1484 * Load the address of the RX list. 1485 */ 1486 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1487 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1488 1489 /* 1490 * Enable interrupts. 1491 */ 1492 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1493 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1494 1495 /* Enable receiver and transmitter. */ 1496 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1497 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1498 1499 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1500 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1501 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1502 1503 mii_mediachg(mii); 1504 1505 ifp->if_flags |= IFF_RUNNING; 1506 ifp->if_flags &= ~IFF_OACTIVE; 1507 1508 crit_exit(); 1509 1510 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1511 } 1512 1513 /* 1514 * Set media options. 1515 */ 1516 static int 1517 wb_ifmedia_upd(struct ifnet *ifp) 1518 { 1519 struct wb_softc *sc = ifp->if_softc; 1520 1521 if (ifp->if_flags & IFF_UP) 1522 wb_init(sc); 1523 1524 return(0); 1525 } 1526 1527 /* 1528 * Report current media status. 1529 */ 1530 static void 1531 wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1532 { 1533 struct wb_softc *sc = ifp->if_softc; 1534 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1535 1536 mii_pollstat(mii); 1537 ifmr->ifm_active = mii->mii_media_active; 1538 ifmr->ifm_status = mii->mii_media_status; 1539 } 1540 1541 static int 1542 wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1543 { 1544 struct wb_softc *sc = ifp->if_softc; 1545 struct mii_data *mii; 1546 struct ifreq *ifr = (struct ifreq *) data; 1547 int error = 0; 1548 1549 crit_enter(); 1550 1551 switch(command) { 1552 case SIOCSIFFLAGS: 1553 if (ifp->if_flags & IFF_UP) 1554 wb_init(sc); 1555 else if (ifp->if_flags & IFF_RUNNING) 1556 wb_stop(sc); 1557 error = 0; 1558 break; 1559 case SIOCADDMULTI: 1560 case SIOCDELMULTI: 1561 wb_setmulti(sc); 1562 error = 0; 1563 break; 1564 case SIOCGIFMEDIA: 1565 case SIOCSIFMEDIA: 1566 mii = device_get_softc(sc->wb_miibus); 1567 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1568 break; 1569 default: 1570 error = ether_ioctl(ifp, command, data); 1571 break; 1572 } 1573 1574 crit_exit(); 1575 1576 return(error); 1577 } 1578 1579 static void 1580 wb_watchdog(struct ifnet *ifp) 1581 { 1582 struct wb_softc *sc = ifp->if_softc; 1583 1584 ifp->if_oerrors++; 1585 if_printf(ifp, "watchdog timeout\n"); 1586 #ifdef foo 1587 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0) 1588 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1589 #endif 1590 wb_stop(sc); 1591 wb_reset(sc); 1592 wb_init(sc); 1593 1594 if (!ifq_is_empty(&ifp->if_snd)) 1595 wb_start(ifp); 1596 } 1597 1598 /* 1599 * Stop the adapter and free any mbufs allocated to the 1600 * RX and TX lists. 1601 */ 1602 static void 1603 wb_stop(struct wb_softc *sc) 1604 { 1605 struct ifnet *ifp = &sc->arpcom.ac_if; 1606 int i; 1607 1608 ifp->if_timer = 0; 1609 1610 callout_stop(&sc->wb_stat_timer); 1611 1612 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON)); 1613 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1614 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1615 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1616 1617 /* 1618 * Free data in the RX lists. 1619 */ 1620 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1621 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1622 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1623 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1624 } 1625 } 1626 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list)); 1627 1628 /* 1629 * Free the TX list buffers. 1630 */ 1631 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1632 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1633 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1634 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1635 } 1636 } 1637 1638 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list)); 1639 1640 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1641 } 1642 1643 /* 1644 * Stop all chip I/O so that the kernel's probe routines don't 1645 * get confused by errant DMAs when rebooting. 1646 */ 1647 static void 1648 wb_shutdown(device_t dev) 1649 { 1650 struct wb_softc *sc = device_get_softc(dev); 1651 1652 wb_stop(sc); 1653 } 1654