1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.24 2005/05/31 14:11:43 joerg Exp $ 34 */ 35 36 /* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Winbond W89C840F chip is a bus master; in some ways it resembles 50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 51 * one major difference which is that while the registers do many of 52 * the same things as a tulip adapter, the offsets are different: where 53 * tulip registers are typically spaced 8 bytes apart, the Winbond 54 * registers are spaced 4 bytes apart. The receiver filter is also 55 * programmed differently. 56 * 57 * Like the tulip, the Winbond chip uses small descriptors containing 58 * a status word, a control word and 32-bit areas that can either be used 59 * to point to two external data blocks, or to point to a single block 60 * and another descriptor in a linked list. Descriptors can be grouped 61 * together in blocks to form fixed length rings or can be chained 62 * together in linked lists. A single packet may be spread out over 63 * several descriptors if necessary. 64 * 65 * For the receive ring, this driver uses a linked list of descriptors, 66 * each pointing to a single mbuf cluster buffer, which us large enough 67 * to hold an entire packet. The link list is looped back to created a 68 * closed ring. 69 * 70 * For transmission, the driver creates a linked list of 'super descriptors' 71 * which each contain several individual descriptors linked toghether. 72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 73 * abuse as fragment pointers. This allows us to use a buffer managment 74 * scheme very similar to that used in the ThunderLAN and Etherlink XL 75 * drivers. 76 * 77 * Autonegotiation is performed using the external PHY via the MII bus. 78 * The sample boards I have all use a Davicom PHY. 79 * 80 * Note: the author of the Linux driver for the Winbond chip alludes 81 * to some sort of flaw in the chip's design that seems to mandate some 82 * drastic workaround which signigicantly impairs transmit performance. 83 * I have no idea what he's on about: transmit performance with all 84 * three of my test boards seems fine. 85 */ 86 87 #include "opt_bdg.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 98 #include <net/if.h> 99 #include <net/ifq_var.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/bus.h> 110 #include <machine/resource.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 114 #include <bus/pci/pcireg.h> 115 #include <bus/pci/pcivar.h> 116 117 #include <dev/netif/mii_layer/mii.h> 118 #include <dev/netif/mii_layer/miivar.h> 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 #define WB_USEIOSPACE 124 125 #include "if_wbreg.h" 126 127 /* 128 * Various supported device vendors/types and their names. 129 */ 130 static struct wb_type wb_devs[] = { 131 { WB_VENDORID, WB_DEVICEID_840F, 132 "Winbond W89C840F 10/100BaseTX" }, 133 { CP_VENDORID, CP_DEVICEID_RL100, 134 "Compex RL100-ATX 10/100baseTX" }, 135 { 0, 0, NULL } 136 }; 137 138 static int wb_probe(device_t); 139 static int wb_attach(device_t); 140 static int wb_detach(device_t); 141 142 static void wb_bfree(void *); 143 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 144 struct mbuf *); 145 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 146 147 static void wb_rxeof(struct wb_softc *); 148 static void wb_rxeoc(struct wb_softc *); 149 static void wb_txeof(struct wb_softc *); 150 static void wb_txeoc(struct wb_softc *); 151 static void wb_intr(void *); 152 static void wb_tick(void *); 153 static void wb_start(struct ifnet *); 154 static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 155 static void wb_init(void *); 156 static void wb_stop(struct wb_softc *); 157 static void wb_watchdog(struct ifnet *); 158 static void wb_shutdown(device_t); 159 static int wb_ifmedia_upd(struct ifnet *); 160 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 161 162 static void wb_eeprom_putbyte(struct wb_softc *, int); 163 static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *); 164 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int); 165 static void wb_mii_sync(struct wb_softc *); 166 static void wb_mii_send(struct wb_softc *, uint32_t, int); 167 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 168 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 169 170 static void wb_setcfg(struct wb_softc *, uint32_t); 171 static void wb_setmulti(struct wb_softc *); 172 static void wb_reset(struct wb_softc *); 173 static void wb_fixmedia(struct wb_softc *); 174 static int wb_list_rx_init(struct wb_softc *); 175 static int wb_list_tx_init(struct wb_softc *); 176 177 static int wb_miibus_readreg(device_t, int, int); 178 static int wb_miibus_writereg(device_t, int, int, int); 179 static void wb_miibus_statchg(device_t); 180 181 #ifdef WB_USEIOSPACE 182 #define WB_RES SYS_RES_IOPORT 183 #define WB_RID WB_PCI_LOIO 184 #else 185 #define WB_RES SYS_RES_MEMORY 186 #define WB_RID WB_PCI_LOMEM 187 #endif 188 189 static device_method_t wb_methods[] = { 190 /* Device interface */ 191 DEVMETHOD(device_probe, wb_probe), 192 DEVMETHOD(device_attach, wb_attach), 193 DEVMETHOD(device_detach, wb_detach), 194 DEVMETHOD(device_shutdown, wb_shutdown), 195 196 /* bus interface, for miibus */ 197 DEVMETHOD(bus_print_child, bus_generic_print_child), 198 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 199 200 /* MII interface */ 201 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 202 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 203 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 204 { 0, 0 } 205 }; 206 207 static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc)); 208 static devclass_t wb_devclass; 209 210 DECLARE_DUMMY_MODULE(if_wb); 211 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 212 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 213 214 #define WB_SETBIT(sc, reg, x) \ 215 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 216 217 #define WB_CLRBIT(sc, reg, x) \ 218 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 219 220 #define SIO_SET(x) \ 221 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x)) 222 223 #define SIO_CLR(x) \ 224 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x)) 225 226 /* 227 * Send a read command and address to the EEPROM, check for ACK. 228 */ 229 static void 230 wb_eeprom_putbyte(struct wb_softc *sc, int addr) 231 { 232 int d, i; 233 234 d = addr | WB_EECMD_READ; 235 236 /* 237 * Feed in each bit and stobe the clock. 238 */ 239 for (i = 0x400; i; i >>= 1) { 240 if (d & i) 241 SIO_SET(WB_SIO_EE_DATAIN); 242 else 243 SIO_CLR(WB_SIO_EE_DATAIN); 244 DELAY(100); 245 SIO_SET(WB_SIO_EE_CLK); 246 DELAY(150); 247 SIO_CLR(WB_SIO_EE_CLK); 248 DELAY(100); 249 } 250 } 251 252 /* 253 * Read a word of data stored in the EEPROM at address 'addr.' 254 */ 255 static void 256 wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest) 257 { 258 int i; 259 uint16_t word = 0; 260 261 /* Enter EEPROM access mode. */ 262 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 263 264 /* 265 * Send address of word we want to read. 266 */ 267 wb_eeprom_putbyte(sc, addr); 268 269 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 270 271 /* 272 * Start reading bits from EEPROM. 273 */ 274 for (i = 0x8000; i; i >>= 1) { 275 SIO_SET(WB_SIO_EE_CLK); 276 DELAY(100); 277 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 278 word |= i; 279 SIO_CLR(WB_SIO_EE_CLK); 280 DELAY(100); 281 } 282 283 /* Turn off EEPROM access mode. */ 284 CSR_WRITE_4(sc, WB_SIO, 0); 285 286 *dest = word; 287 } 288 289 /* 290 * Read a sequence of words from the EEPROM. 291 */ 292 static void 293 wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt) 294 { 295 int i; 296 uint16_t word = 0, *ptr; 297 298 for (i = 0; i < cnt; i++) { 299 wb_eeprom_getword(sc, off + i, &word); 300 ptr = (uint16_t *)(dest + (i * 2)); 301 *ptr = word; 302 } 303 } 304 305 /* 306 * Sync the PHYs by setting data bit and strobing the clock 32 times. 307 */ 308 static void 309 wb_mii_sync(struct wb_softc *sc) 310 { 311 int i; 312 313 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN); 314 315 for (i = 0; i < 32; i++) { 316 SIO_SET(WB_SIO_MII_CLK); 317 DELAY(1); 318 SIO_CLR(WB_SIO_MII_CLK); 319 DELAY(1); 320 } 321 } 322 323 /* 324 * Clock a series of bits through the MII. 325 */ 326 static void 327 wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt) 328 { 329 int i; 330 331 SIO_CLR(WB_SIO_MII_CLK); 332 333 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 334 if (bits & i) 335 SIO_SET(WB_SIO_MII_DATAIN); 336 else 337 SIO_CLR(WB_SIO_MII_DATAIN); 338 DELAY(1); 339 SIO_CLR(WB_SIO_MII_CLK); 340 DELAY(1); 341 SIO_SET(WB_SIO_MII_CLK); 342 } 343 } 344 345 /* 346 * Read an PHY register through the MII. 347 */ 348 static int 349 wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame) 350 { 351 int ack, i, s; 352 353 s = splimp(); 354 355 /* 356 * Set up frame for RX. 357 */ 358 frame->mii_stdelim = WB_MII_STARTDELIM; 359 frame->mii_opcode = WB_MII_READOP; 360 frame->mii_turnaround = 0; 361 frame->mii_data = 0; 362 363 CSR_WRITE_4(sc, WB_SIO, 0); 364 365 /* 366 * Turn on data xmit. 367 */ 368 SIO_SET(WB_SIO_MII_DIR); 369 370 wb_mii_sync(sc); 371 372 /* 373 * Send command/address info. 374 */ 375 wb_mii_send(sc, frame->mii_stdelim, 2); 376 wb_mii_send(sc, frame->mii_opcode, 2); 377 wb_mii_send(sc, frame->mii_phyaddr, 5); 378 wb_mii_send(sc, frame->mii_regaddr, 5); 379 380 /* Idle bit */ 381 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN)); 382 DELAY(1); 383 SIO_SET(WB_SIO_MII_CLK); 384 DELAY(1); 385 386 /* Turn off xmit. */ 387 SIO_CLR(WB_SIO_MII_DIR); 388 /* Check for ack */ 389 SIO_CLR(WB_SIO_MII_CLK); 390 DELAY(1); 391 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 392 SIO_SET(WB_SIO_MII_CLK); 393 DELAY(1); 394 SIO_CLR(WB_SIO_MII_CLK); 395 DELAY(1); 396 SIO_SET(WB_SIO_MII_CLK); 397 DELAY(1); 398 399 /* 400 * Now try reading data bits. If the ack failed, we still 401 * need to clock through 16 cycles to keep the PHY(s) in sync. 402 */ 403 if (ack) { 404 for(i = 0; i < 16; i++) { 405 SIO_CLR(WB_SIO_MII_CLK); 406 DELAY(1); 407 SIO_SET(WB_SIO_MII_CLK); 408 DELAY(1); 409 } 410 goto fail; 411 } 412 413 for (i = 0x8000; i; i >>= 1) { 414 SIO_CLR(WB_SIO_MII_CLK); 415 DELAY(1); 416 if (!ack) { 417 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 418 frame->mii_data |= i; 419 DELAY(1); 420 } 421 SIO_SET(WB_SIO_MII_CLK); 422 DELAY(1); 423 } 424 425 fail: 426 427 SIO_CLR(WB_SIO_MII_CLK); 428 DELAY(1); 429 SIO_SET(WB_SIO_MII_CLK); 430 DELAY(1); 431 432 splx(s); 433 434 if (ack) 435 return(1); 436 return(0); 437 } 438 439 /* 440 * Write to a PHY register through the MII. 441 */ 442 static int 443 wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame) 444 { 445 int s; 446 447 s = splimp(); 448 /* 449 * Set up frame for TX. 450 */ 451 452 frame->mii_stdelim = WB_MII_STARTDELIM; 453 frame->mii_opcode = WB_MII_WRITEOP; 454 frame->mii_turnaround = WB_MII_TURNAROUND; 455 456 /* 457 * Turn on data output. 458 */ 459 SIO_SET(WB_SIO_MII_DIR); 460 461 wb_mii_sync(sc); 462 463 wb_mii_send(sc, frame->mii_stdelim, 2); 464 wb_mii_send(sc, frame->mii_opcode, 2); 465 wb_mii_send(sc, frame->mii_phyaddr, 5); 466 wb_mii_send(sc, frame->mii_regaddr, 5); 467 wb_mii_send(sc, frame->mii_turnaround, 2); 468 wb_mii_send(sc, frame->mii_data, 16); 469 470 /* Idle bit. */ 471 SIO_SET(WB_SIO_MII_CLK); 472 DELAY(1); 473 SIO_CLR(WB_SIO_MII_CLK); 474 DELAY(1); 475 476 /* 477 * Turn off xmit. 478 */ 479 SIO_CLR(WB_SIO_MII_DIR); 480 481 splx(s); 482 483 return(0); 484 } 485 486 static int 487 wb_miibus_readreg(device_t dev, int phy, int reg) 488 { 489 struct wb_softc *sc = device_get_softc(dev); 490 struct wb_mii_frame frame; 491 492 bzero(&frame, sizeof(frame)); 493 494 frame.mii_phyaddr = phy; 495 frame.mii_regaddr = reg; 496 wb_mii_readreg(sc, &frame); 497 498 return(frame.mii_data); 499 } 500 501 static int 502 wb_miibus_writereg(device_t dev, int phy, int reg, int data) 503 { 504 struct wb_softc *sc = device_get_softc(dev); 505 struct wb_mii_frame frame; 506 507 bzero(&frame, sizeof(frame)); 508 509 frame.mii_phyaddr = phy; 510 frame.mii_regaddr = reg; 511 frame.mii_data = data; 512 513 wb_mii_writereg(sc, &frame); 514 515 return(0); 516 } 517 518 static void 519 wb_miibus_statchg(device_t dev) 520 { 521 struct wb_softc *sc = device_get_softc(dev); 522 struct mii_data *mii; 523 524 mii = device_get_softc(sc->wb_miibus); 525 wb_setcfg(sc, mii->mii_media_active); 526 } 527 528 /* 529 * Program the 64-bit multicast hash filter. 530 */ 531 static void 532 wb_setmulti(struct wb_softc *sc) 533 { 534 struct ifnet *ifp = &sc->arpcom.ac_if; 535 int h = 0, mcnt = 0; 536 uint32_t hashes[2] = { 0, 0 }; 537 struct ifmultiaddr *ifma; 538 uint32_t rxfilt; 539 540 rxfilt = CSR_READ_4(sc, WB_NETCFG); 541 542 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 543 rxfilt |= WB_NETCFG_RX_MULTI; 544 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 545 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 546 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 547 return; 548 } 549 550 /* first, zot all the existing hash bits */ 551 CSR_WRITE_4(sc, WB_MAR0, 0); 552 CSR_WRITE_4(sc, WB_MAR1, 0); 553 554 /* now program new ones */ 555 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 556 if (ifma->ifma_addr->sa_family != AF_LINK) 557 continue; 558 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 559 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 560 if (h < 32) 561 hashes[0] |= (1 << h); 562 else 563 hashes[1] |= (1 << (h - 32)); 564 mcnt++; 565 } 566 567 if (mcnt) 568 rxfilt |= WB_NETCFG_RX_MULTI; 569 else 570 rxfilt &= ~WB_NETCFG_RX_MULTI; 571 572 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 573 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 574 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 575 } 576 577 /* 578 * The Winbond manual states that in order to fiddle with the 579 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 580 * first have to put the transmit and/or receive logic in the idle state. 581 */ 582 static void 583 wb_setcfg(struct wb_softc *sc, uint32_t media) 584 { 585 int i, restart = 0; 586 587 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) { 588 restart = 1; 589 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)); 590 591 for (i = 0; i < WB_TIMEOUT; i++) { 592 DELAY(10); 593 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 594 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 595 break; 596 } 597 598 if (i == WB_TIMEOUT) 599 printf("wb%d: failed to force tx and " 600 "rx to idle state\n", sc->wb_unit); 601 } 602 603 if (IFM_SUBTYPE(media) == IFM_10_T) 604 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 605 else 606 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 607 608 if ((media & IFM_GMASK) == IFM_FDX) 609 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 610 else 611 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 612 613 if (restart) 614 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON); 615 } 616 617 static void 618 wb_reset(struct wb_softc *sc) 619 { 620 int i; 621 struct mii_data *mii; 622 623 CSR_WRITE_4(sc, WB_NETCFG, 0); 624 CSR_WRITE_4(sc, WB_BUSCTL, 0); 625 CSR_WRITE_4(sc, WB_TXADDR, 0); 626 CSR_WRITE_4(sc, WB_RXADDR, 0); 627 628 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 629 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 630 631 for (i = 0; i < WB_TIMEOUT; i++) { 632 DELAY(10); 633 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0) 634 break; 635 } 636 if (i == WB_TIMEOUT) 637 printf("wb%d: reset never completed!\n", sc->wb_unit); 638 639 /* Wait a little while for the chip to get its brains in order. */ 640 DELAY(1000); 641 642 if (sc->wb_miibus == NULL) 643 return; 644 645 mii = device_get_softc(sc->wb_miibus); 646 if (mii == NULL) 647 return; 648 649 if (mii->mii_instance) { 650 struct mii_softc *miisc; 651 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 652 mii_phy_reset(miisc); 653 } 654 } 655 656 static void 657 wb_fixmedia(struct wb_softc *sc) 658 { 659 struct mii_data *mii; 660 uint32_t media; 661 662 if (sc->wb_miibus == NULL) 663 return; 664 665 mii = device_get_softc(sc->wb_miibus); 666 667 mii_pollstat(mii); 668 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 669 media = mii->mii_media_active & ~IFM_10_T; 670 media |= IFM_100_TX; 671 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 672 media = mii->mii_media_active & ~IFM_100_TX; 673 media |= IFM_10_T; 674 } else 675 return; 676 677 ifmedia_set(&mii->mii_media, media); 678 } 679 680 /* 681 * Probe for a Winbond chip. Check the PCI vendor and device 682 * IDs against our list and return a device name if we find a match. 683 */ 684 static int wb_probe(device_t dev) 685 { 686 struct wb_type *t; 687 uint16_t vendor, product; 688 689 vendor = pci_get_vendor(dev); 690 product = pci_get_device(dev); 691 692 for (t = wb_devs; t->wb_name != NULL; t++) { 693 if (vendor == t->wb_vid && product == t->wb_did) { 694 device_set_desc(dev, t->wb_name); 695 return(0); 696 } 697 } 698 699 return(ENXIO); 700 } 701 702 /* 703 * Attach the interface. Allocate softc structures, do ifmedia 704 * setup and ethernet/BPF attach. 705 */ 706 static int 707 wb_attach(device_t dev) 708 { 709 u_char eaddr[ETHER_ADDR_LEN]; 710 uint32_t command; 711 struct wb_softc *sc; 712 struct ifnet *ifp; 713 int error = 0, rid, s, unit; 714 715 s = splimp(); 716 717 sc = device_get_softc(dev); 718 unit = device_get_unit(dev); 719 callout_init(&sc->wb_stat_timer); 720 721 /* 722 * Handle power management nonsense. 723 */ 724 725 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 726 if (command == 0x01) { 727 728 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 729 if (command & WB_PSTATE_MASK) { 730 uint32_t iobase, membase, irq; 731 732 /* Save important PCI config data. */ 733 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 734 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 735 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 736 737 /* Reset the power state. */ 738 printf("wb%d: chip is in D%d power mode " 739 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 740 command &= 0xFFFFFFFC; 741 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 742 743 /* Restore PCI config data. */ 744 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 745 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 746 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 747 } 748 } 749 750 /* 751 * Map control/status registers. 752 */ 753 command = pci_read_config(dev, PCIR_COMMAND, 4); 754 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 755 pci_write_config(dev, PCIR_COMMAND, command, 4); 756 command = pci_read_config(dev, PCIR_COMMAND, 4); 757 758 #ifdef WB_USEIOSPACE 759 if ((command & PCIM_CMD_PORTEN) == 0) { 760 printf("wb%d: failed to enable I/O ports!\n", unit); 761 error = ENXIO; 762 goto fail; 763 } 764 #else 765 if ((command & PCIM_CMD_MEMEN) == 0) { 766 printf("wb%d: failed to enable memory mapping!\n", unit); 767 error = ENXIO; 768 goto fail; 769 } 770 #endif 771 772 rid = WB_RID; 773 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 774 775 if (sc->wb_res == NULL) { 776 printf("wb%d: couldn't map ports/memory\n", unit); 777 error = ENXIO; 778 goto fail; 779 } 780 781 sc->wb_btag = rman_get_bustag(sc->wb_res); 782 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 783 784 /* Allocate interrupt */ 785 rid = 0; 786 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 787 RF_SHAREABLE | RF_ACTIVE); 788 789 if (sc->wb_irq == NULL) { 790 printf("wb%d: couldn't map interrupt\n", unit); 791 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 792 error = ENXIO; 793 goto fail; 794 } 795 796 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 797 wb_intr, sc, &sc->wb_intrhand, NULL); 798 799 if (error) { 800 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 801 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 802 printf("wb%d: couldn't set up irq\n", unit); 803 goto fail; 804 } 805 806 /* Save the cache line size. */ 807 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 808 809 /* Reset the adapter. */ 810 wb_reset(sc); 811 812 /* 813 * Get station address from the EEPROM. 814 */ 815 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3); 816 817 sc->wb_unit = unit; 818 819 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 820 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 821 822 if (sc->wb_ldata == NULL) { 823 printf("wb%d: no memory for list buffers!\n", unit); 824 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 825 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 826 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 827 error = ENXIO; 828 goto fail; 829 } 830 831 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 832 833 ifp = &sc->arpcom.ac_if; 834 ifp->if_softc = sc; 835 if_initname(ifp, "wb", unit); 836 ifp->if_mtu = ETHERMTU; 837 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 838 ifp->if_ioctl = wb_ioctl; 839 ifp->if_start = wb_start; 840 ifp->if_watchdog = wb_watchdog; 841 ifp->if_init = wb_init; 842 ifp->if_baudrate = 10000000; 843 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1); 844 ifq_set_ready(&ifp->if_snd); 845 846 /* 847 * Do MII setup. 848 */ 849 if (mii_phy_probe(dev, &sc->wb_miibus, 850 wb_ifmedia_upd, wb_ifmedia_sts)) { 851 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 852 M_DEVBUF); 853 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 854 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 855 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 856 error = ENXIO; 857 goto fail; 858 } 859 860 /* 861 * Call MI attach routine. 862 */ 863 ether_ifattach(ifp, eaddr); 864 865 fail: 866 if (error) 867 device_delete_child(dev, sc->wb_miibus); 868 splx(s); 869 870 return(error); 871 } 872 873 static int 874 wb_detach(device_t dev) 875 { 876 struct wb_softc *sc = device_get_softc(dev); 877 struct ifnet *ifp = &sc->arpcom.ac_if; 878 int s; 879 880 s = splimp(); 881 882 wb_stop(sc); 883 ether_ifdetach(ifp); 884 885 /* Delete any miibus and phy devices attached to this interface */ 886 bus_generic_detach(dev); 887 device_delete_child(dev, sc->wb_miibus); 888 889 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 890 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 891 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 892 893 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 894 M_DEVBUF); 895 896 splx(s); 897 898 return(0); 899 } 900 901 /* 902 * Initialize the transmit descriptors. 903 */ 904 static int 905 wb_list_tx_init(struct wb_softc *sc) 906 { 907 struct wb_chain_data *cd; 908 struct wb_list_data *ld; 909 int i, nexti; 910 911 cd = &sc->wb_cdata; 912 ld = sc->wb_ldata; 913 914 for (i = 0; i < WB_TX_LIST_CNT; i++) { 915 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1; 916 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 917 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti]; 918 } 919 920 cd->wb_tx_free = &cd->wb_tx_chain[0]; 921 cd->wb_tx_tail = cd->wb_tx_head = NULL; 922 923 return(0); 924 } 925 926 /* 927 * Initialize the RX descriptors and allocate mbufs for them. Note that 928 * we arrange the descriptors in a closed ring, so that the last descriptor 929 * points back to the first. 930 */ 931 static int 932 wb_list_rx_init(struct wb_softc *sc) 933 { 934 struct wb_chain_data *cd; 935 struct wb_list_data *ld; 936 int i, nexti; 937 938 cd = &sc->wb_cdata; 939 ld = sc->wb_ldata; 940 941 for (i = 0; i < WB_RX_LIST_CNT; i++) { 942 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i]; 943 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i]; 944 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 945 return(ENOBUFS); 946 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1; 947 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti]; 948 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]); 949 } 950 951 cd->wb_rx_head = &cd->wb_rx_chain[0]; 952 953 return(0); 954 } 955 956 static void 957 wb_bfree(void *arg) 958 { 959 } 960 961 /* 962 * Initialize an RX descriptor and attach an MBUF cluster. 963 */ 964 static int 965 wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m) 966 { 967 struct mbuf *m_new = NULL; 968 969 if (m == NULL) { 970 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 971 if (m_new == NULL) 972 return(ENOBUFS); 973 974 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 975 m_new->m_flags |= M_EXT; 976 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 977 m_new->m_len = WB_BUFBYTES; 978 m_new->m_ext.ext_free = wb_bfree; 979 m_new->m_ext.ext_ref = wb_bfree; 980 } else { 981 m_new = m; 982 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 983 m_new->m_data = m_new->m_ext.ext_buf; 984 } 985 986 m_adj(m_new, sizeof(uint64_t)); 987 988 c->wb_mbuf = m_new; 989 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 990 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 991 c->wb_ptr->wb_status = WB_RXSTAT; 992 993 return(0); 994 } 995 996 /* 997 * A frame has been uploaded: pass the resulting mbuf chain up to 998 * the higher level protocols. 999 */ 1000 static void 1001 wb_rxeof(struct wb_softc *sc) 1002 { 1003 struct ifnet *ifp = &sc->arpcom.ac_if; 1004 struct mbuf *m, *m0; 1005 struct wb_chain_onefrag *cur_rx; 1006 int total_len = 0; 1007 uint32_t rxstat; 1008 1009 for (;;) { 1010 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status; 1011 if ((rxstat & WB_RXSTAT_OWN) == 0) 1012 break; 1013 1014 cur_rx = sc->wb_cdata.wb_rx_head; 1015 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1016 1017 m = cur_rx->wb_mbuf; 1018 1019 if ((rxstat & WB_RXSTAT_MIIERR) || 1020 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1021 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1022 (rxstat & WB_RXSTAT_LASTFRAG) == 0|| 1023 (rxstat & WB_RXSTAT_RXCMP) == 0) { 1024 ifp->if_ierrors++; 1025 wb_newbuf(sc, cur_rx, m); 1026 printf("wb%x: receiver babbling: possible chip " 1027 "bug, forcing reset\n", sc->wb_unit); 1028 wb_fixmedia(sc); 1029 wb_reset(sc); 1030 wb_init(sc); 1031 return; 1032 } 1033 1034 if (rxstat & WB_RXSTAT_RXERR) { 1035 ifp->if_ierrors++; 1036 wb_newbuf(sc, cur_rx, m); 1037 break; 1038 } 1039 1040 /* No errors; receive the packet. */ 1041 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1042 1043 /* 1044 * XXX The Winbond chip includes the CRC with every 1045 * received frame, and there's no way to turn this 1046 * behavior off (at least, I can't find anything in 1047 * the manual that explains how to do it) so we have 1048 * to trim off the CRC manually. 1049 */ 1050 total_len -= ETHER_CRC_LEN; 1051 1052 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1053 total_len + ETHER_ALIGN, 0, ifp, NULL); 1054 wb_newbuf(sc, cur_rx, m); 1055 if (m0 == NULL) { 1056 ifp->if_ierrors++; 1057 break; 1058 } 1059 m_adj(m0, ETHER_ALIGN); 1060 m = m0; 1061 1062 ifp->if_ipackets++; 1063 (*ifp->if_input)(ifp, m); 1064 } 1065 } 1066 1067 static void 1068 wb_rxeoc(struct wb_softc *sc) 1069 { 1070 wb_rxeof(sc); 1071 1072 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1073 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1074 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1075 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1076 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1077 } 1078 1079 /* 1080 * A frame was downloaded to the chip. It's safe for us to clean up 1081 * the list buffers. 1082 */ 1083 static void 1084 wb_txeof(struct wb_softc *sc) 1085 { 1086 struct ifnet *ifp = &sc->arpcom.ac_if; 1087 struct wb_chain *cur_tx; 1088 1089 /* Clear the timeout timer. */ 1090 ifp->if_timer = 0; 1091 1092 if (sc->wb_cdata.wb_tx_head == NULL) 1093 return; 1094 1095 /* 1096 * Go through our tx list and free mbufs for those 1097 * frames that have been transmitted. 1098 */ 1099 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1100 uint32_t txstat; 1101 1102 cur_tx = sc->wb_cdata.wb_tx_head; 1103 txstat = WB_TXSTATUS(cur_tx); 1104 1105 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1106 break; 1107 1108 if (txstat & WB_TXSTAT_TXERR) { 1109 ifp->if_oerrors++; 1110 if (txstat & WB_TXSTAT_ABORT) 1111 ifp->if_collisions++; 1112 if (txstat & WB_TXSTAT_LATECOLL) 1113 ifp->if_collisions++; 1114 } 1115 1116 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1117 1118 ifp->if_opackets++; 1119 m_freem(cur_tx->wb_mbuf); 1120 cur_tx->wb_mbuf = NULL; 1121 1122 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1123 sc->wb_cdata.wb_tx_head = NULL; 1124 sc->wb_cdata.wb_tx_tail = NULL; 1125 break; 1126 } 1127 1128 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1129 } 1130 } 1131 1132 /* 1133 * TX 'end of channel' interrupt handler. 1134 */ 1135 static void 1136 wb_txeoc(struct wb_softc *sc) 1137 { 1138 struct ifnet *ifp = &sc->arpcom.ac_if; 1139 1140 ifp->if_timer = 0; 1141 1142 if (sc->wb_cdata.wb_tx_head == NULL) { 1143 ifp->if_flags &= ~IFF_OACTIVE; 1144 sc->wb_cdata.wb_tx_tail = NULL; 1145 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1146 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1147 ifp->if_timer = 5; 1148 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1149 } 1150 } 1151 1152 static void 1153 wb_intr(void *arg) 1154 { 1155 struct wb_softc *sc = arg; 1156 struct ifnet *ifp = &sc->arpcom.ac_if; 1157 uint32_t status; 1158 1159 if ((ifp->if_flags & IFF_UP) == 0) 1160 return; 1161 1162 /* Disable interrupts. */ 1163 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1164 1165 for (;;) { 1166 status = CSR_READ_4(sc, WB_ISR); 1167 if (status) 1168 CSR_WRITE_4(sc, WB_ISR, status); 1169 1170 if ((status & WB_INTRS) == 0) 1171 break; 1172 1173 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1174 ifp->if_ierrors++; 1175 wb_reset(sc); 1176 if (status & WB_ISR_RX_ERR) 1177 wb_fixmedia(sc); 1178 wb_init(sc); 1179 continue; 1180 } 1181 1182 if (status & WB_ISR_RX_OK) 1183 wb_rxeof(sc); 1184 1185 if (status & WB_ISR_RX_IDLE) 1186 wb_rxeoc(sc); 1187 1188 if (status & WB_ISR_TX_OK) 1189 wb_txeof(sc); 1190 1191 if (status & WB_ISR_TX_NOBUF) 1192 wb_txeoc(sc); 1193 1194 if (status & WB_ISR_TX_IDLE) { 1195 wb_txeof(sc); 1196 if (sc->wb_cdata.wb_tx_head != NULL) { 1197 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1198 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1199 } 1200 } 1201 1202 if (status & WB_ISR_TX_UNDERRUN) { 1203 ifp->if_oerrors++; 1204 wb_txeof(sc); 1205 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1206 /* Jack up TX threshold */ 1207 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1208 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1209 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1210 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1211 } 1212 1213 if (status & WB_ISR_BUS_ERR) { 1214 wb_reset(sc); 1215 wb_init(sc); 1216 } 1217 } 1218 1219 /* Re-enable interrupts. */ 1220 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1221 1222 if (!ifq_is_empty(&ifp->if_snd)) 1223 wb_start(ifp); 1224 } 1225 1226 static void 1227 wb_tick(void *xsc) 1228 { 1229 struct wb_softc *sc = xsc; 1230 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1231 int s; 1232 1233 s = splimp(); 1234 1235 mii_tick(mii); 1236 1237 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1238 1239 splx(s); 1240 } 1241 1242 /* 1243 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1244 * pointers to the fragment pointers. 1245 */ 1246 static int 1247 wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head) 1248 { 1249 struct wb_desc *f = NULL; 1250 struct mbuf *m; 1251 int frag, total_len; 1252 1253 /* 1254 * Start packing the mbufs in this chain into 1255 * the fragment pointers. Stop when we run out 1256 * of fragments or hit the end of the mbuf chain. 1257 */ 1258 total_len = 0; 1259 1260 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1261 if (m->m_len != 0) { 1262 if (frag == WB_MAXFRAGS) 1263 break; 1264 total_len += m->m_len; 1265 f = &c->wb_ptr->wb_frag[frag]; 1266 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1267 if (frag == 0) { 1268 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1269 f->wb_status = 0; 1270 } else { 1271 f->wb_status = WB_TXSTAT_OWN; 1272 } 1273 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1274 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1275 frag++; 1276 } 1277 } 1278 1279 /* 1280 * Handle special case: we used up all 16 fragments, 1281 * but we have more mbufs left in the chain. Copy the 1282 * data into an mbuf cluster. Note that we don't 1283 * bother clearing the values in the other fragment 1284 * pointers/counters; it wouldn't gain us anything, 1285 * and would waste cycles. 1286 */ 1287 if (m != NULL) { 1288 struct mbuf *m_new = NULL; 1289 1290 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1291 if (m_new == NULL) 1292 return(1); 1293 if (m_head->m_pkthdr.len > MHLEN) { 1294 MCLGET(m_new, MB_DONTWAIT); 1295 if ((m_new->m_flags & M_EXT) == 0) { 1296 m_freem(m_new); 1297 return(1); 1298 } 1299 } 1300 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1301 mtod(m_new, caddr_t)); 1302 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1303 m_freem(m_head); 1304 m_head = m_new; 1305 f = &c->wb_ptr->wb_frag[0]; 1306 f->wb_status = 0; 1307 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1308 f->wb_ctl = total_len = m_new->m_len; 1309 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1310 frag = 1; 1311 } 1312 1313 if (total_len < WB_MIN_FRAMELEN) { 1314 f = &c->wb_ptr->wb_frag[frag]; 1315 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1316 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1317 f->wb_ctl |= WB_TXCTL_TLINK; 1318 f->wb_status = WB_TXSTAT_OWN; 1319 frag++; 1320 } 1321 1322 c->wb_mbuf = m_head; 1323 c->wb_lastdesc = frag - 1; 1324 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1325 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1326 1327 return(0); 1328 } 1329 1330 /* 1331 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1332 * to the mbuf data regions directly in the transmit lists. We also save a 1333 * copy of the pointers since the transmit list fragment pointers are 1334 * physical addresses. 1335 */ 1336 static void 1337 wb_start(struct ifnet *ifp) 1338 { 1339 struct wb_softc *sc = ifp->if_softc; 1340 struct mbuf *m_head = NULL; 1341 struct wb_chain *cur_tx = NULL, *start_tx; 1342 1343 /* 1344 * Check for an available queue slot. If there are none, 1345 * punt. 1346 */ 1347 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1348 ifp->if_flags |= IFF_OACTIVE; 1349 return; 1350 } 1351 1352 start_tx = sc->wb_cdata.wb_tx_free; 1353 1354 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1355 m_head = ifq_dequeue(&ifp->if_snd); 1356 if (m_head == NULL) 1357 break; 1358 1359 /* Pick a descriptor off the free list. */ 1360 cur_tx = sc->wb_cdata.wb_tx_free; 1361 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1362 1363 /* Pack the data into the descriptor. */ 1364 wb_encap(sc, cur_tx, m_head); 1365 1366 if (cur_tx != start_tx) 1367 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1368 1369 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1370 } 1371 1372 /* 1373 * If there are no packets queued, bail. 1374 */ 1375 if (cur_tx == NULL) 1376 return; 1377 1378 /* 1379 * Place the request for the upload interrupt 1380 * in the last descriptor in the chain. This way, if 1381 * we're chaining several packets at once, we'll only 1382 * get an interupt once for the whole chain rather than 1383 * once for each packet. 1384 */ 1385 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1386 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1387 sc->wb_cdata.wb_tx_tail = cur_tx; 1388 1389 if (sc->wb_cdata.wb_tx_head == NULL) { 1390 sc->wb_cdata.wb_tx_head = start_tx; 1391 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1392 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1393 } else { 1394 /* 1395 * We need to distinguish between the case where 1396 * the own bit is clear because the chip cleared it 1397 * and where the own bit is clear because we haven't 1398 * set it yet. The magic value WB_UNSET is just some 1399 * ramdomly chosen number which doesn't have the own 1400 * bit set. When we actually transmit the frame, the 1401 * status word will have _only_ the own bit set, so 1402 * the txeoc handler will be able to tell if it needs 1403 * to initiate another transmission to flush out pending 1404 * frames. 1405 */ 1406 WB_TXOWN(start_tx) = WB_UNSENT; 1407 } 1408 1409 /* 1410 * Set a timeout in case the chip goes out to lunch. 1411 */ 1412 ifp->if_timer = 5; 1413 } 1414 1415 static void 1416 wb_init(void *xsc) 1417 { 1418 struct wb_softc *sc = xsc; 1419 struct ifnet *ifp = &sc->arpcom.ac_if; 1420 int s, i; 1421 struct mii_data *mii; 1422 1423 s = splimp(); 1424 1425 mii = device_get_softc(sc->wb_miibus); 1426 1427 /* 1428 * Cancel pending I/O and free all RX/TX buffers. 1429 */ 1430 wb_stop(sc); 1431 wb_reset(sc); 1432 1433 sc->wb_txthresh = WB_TXTHRESH_INIT; 1434 1435 /* 1436 * Set cache alignment and burst length. 1437 */ 1438 #ifdef foo 1439 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1440 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1441 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1442 #endif 1443 1444 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION); 1445 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1446 switch(sc->wb_cachesize) { 1447 case 32: 1448 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1449 break; 1450 case 16: 1451 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1452 break; 1453 case 8: 1454 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1455 break; 1456 case 0: 1457 default: 1458 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1459 break; 1460 } 1461 1462 /* This doesn't tend to work too well at 100Mbps. */ 1463 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1464 1465 /* Init our MAC address */ 1466 for (i = 0; i < ETHER_ADDR_LEN; i++) 1467 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1468 1469 /* Init circular RX list. */ 1470 if (wb_list_rx_init(sc) == ENOBUFS) { 1471 printf("wb%d: initialization failed: no " 1472 "memory for rx buffers\n", sc->wb_unit); 1473 wb_stop(sc); 1474 splx(s); 1475 return; 1476 } 1477 1478 /* Init TX descriptors. */ 1479 wb_list_tx_init(sc); 1480 1481 /* If we want promiscuous mode, set the allframes bit. */ 1482 if (ifp->if_flags & IFF_PROMISC) 1483 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1484 else 1485 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1486 1487 /* 1488 * Set capture broadcast bit to capture broadcast frames. 1489 */ 1490 if (ifp->if_flags & IFF_BROADCAST) 1491 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1492 else 1493 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1494 1495 /* 1496 * Program the multicast filter, if necessary. 1497 */ 1498 wb_setmulti(sc); 1499 1500 /* 1501 * Load the address of the RX list. 1502 */ 1503 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1504 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1505 1506 /* 1507 * Enable interrupts. 1508 */ 1509 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1510 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1511 1512 /* Enable receiver and transmitter. */ 1513 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1514 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1515 1516 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1517 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1518 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1519 1520 mii_mediachg(mii); 1521 1522 ifp->if_flags |= IFF_RUNNING; 1523 ifp->if_flags &= ~IFF_OACTIVE; 1524 1525 splx(s); 1526 1527 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1528 } 1529 1530 /* 1531 * Set media options. 1532 */ 1533 static int 1534 wb_ifmedia_upd(struct ifnet *ifp) 1535 { 1536 struct wb_softc *sc = ifp->if_softc; 1537 1538 if (ifp->if_flags & IFF_UP) 1539 wb_init(sc); 1540 1541 return(0); 1542 } 1543 1544 /* 1545 * Report current media status. 1546 */ 1547 static void 1548 wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1549 { 1550 struct wb_softc *sc = ifp->if_softc; 1551 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1552 1553 mii_pollstat(mii); 1554 ifmr->ifm_active = mii->mii_media_active; 1555 ifmr->ifm_status = mii->mii_media_status; 1556 } 1557 1558 static int 1559 wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1560 { 1561 struct wb_softc *sc = ifp->if_softc; 1562 struct mii_data *mii; 1563 struct ifreq *ifr = (struct ifreq *) data; 1564 int error = 0, s; 1565 1566 s = splimp(); 1567 1568 switch(command) { 1569 case SIOCSIFFLAGS: 1570 if (ifp->if_flags & IFF_UP) 1571 wb_init(sc); 1572 else if (ifp->if_flags & IFF_RUNNING) 1573 wb_stop(sc); 1574 error = 0; 1575 break; 1576 case SIOCADDMULTI: 1577 case SIOCDELMULTI: 1578 wb_setmulti(sc); 1579 error = 0; 1580 break; 1581 case SIOCGIFMEDIA: 1582 case SIOCSIFMEDIA: 1583 mii = device_get_softc(sc->wb_miibus); 1584 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1585 break; 1586 default: 1587 error = ether_ioctl(ifp, command, data); 1588 break; 1589 } 1590 1591 splx(s); 1592 1593 return(error); 1594 } 1595 1596 static void 1597 wb_watchdog(struct ifnet *ifp) 1598 { 1599 struct wb_softc *sc = ifp->if_softc; 1600 1601 ifp->if_oerrors++; 1602 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1603 #ifdef foo 1604 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0) 1605 printf("wb%d: no carrier - transceiver cable problem?\n", 1606 sc->wb_unit); 1607 #endif 1608 wb_stop(sc); 1609 wb_reset(sc); 1610 wb_init(sc); 1611 1612 if (!ifq_is_empty(&ifp->if_snd)) 1613 wb_start(ifp); 1614 } 1615 1616 /* 1617 * Stop the adapter and free any mbufs allocated to the 1618 * RX and TX lists. 1619 */ 1620 static void 1621 wb_stop(struct wb_softc *sc) 1622 { 1623 struct ifnet *ifp = &sc->arpcom.ac_if; 1624 int i; 1625 1626 ifp->if_timer = 0; 1627 1628 callout_stop(&sc->wb_stat_timer); 1629 1630 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON)); 1631 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1632 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1633 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1634 1635 /* 1636 * Free data in the RX lists. 1637 */ 1638 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1639 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1640 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1641 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1642 } 1643 } 1644 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list)); 1645 1646 /* 1647 * Free the TX list buffers. 1648 */ 1649 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1650 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1651 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1652 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1653 } 1654 } 1655 1656 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list)); 1657 1658 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1659 } 1660 1661 /* 1662 * Stop all chip I/O so that the kernel's probe routines don't 1663 * get confused by errant DMAs when rebooting. 1664 */ 1665 static void 1666 wb_shutdown(device_t dev) 1667 { 1668 struct wb_softc *sc = device_get_softc(dev); 1669 1670 wb_stop(sc); 1671 } 1672