1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.20 2005/03/07 17:16:01 joerg Exp $ 34 */ 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 71 #include <net/if.h> 72 #include <net/ifq_var.h> 73 #include <net/if_arp.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 78 #include <net/bpf.h> 79 80 #include <vm/vm.h> /* for vtophys */ 81 #include <vm/pmap.h> /* for vtophys */ 82 #include <machine/bus_pio.h> 83 #include <machine/bus_memio.h> 84 #include <machine/bus.h> 85 #include <machine/resource.h> 86 #include <sys/bus.h> 87 #include <sys/rman.h> 88 89 #include <dev/netif/mii_layer/mii.h> 90 #include <dev/netif/mii_layer/miivar.h> 91 92 #include <bus/pci/pcireg.h> 93 #include <bus/pci/pcivar.h> 94 95 #define VR_USEIOSPACE 96 97 #include <dev/netif/vr/if_vrreg.h> 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 #undef VR_USESWSHIFT 103 104 /* 105 * Various supported device vendors/types and their names. 106 */ 107 static struct vr_type vr_devs[] = { 108 { VIA_VENDORID, VIA_DEVICEID_RHINE, 109 "VIA VT3043 Rhine I 10/100BaseTX" }, 110 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 111 "VIA VT86C100A Rhine II 10/100BaseTX" }, 112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 113 "VIA VT6102 Rhine II 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 115 "VIA VT6105 Rhine III 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 117 "VIA VT6105M Rhine III 10/100BaseTX" }, 118 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 119 "Delta Electronics Rhine II 10/100BaseTX" }, 120 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 121 "Addtron Technology Rhine II 10/100BaseTX" }, 122 { 0, 0, NULL } 123 }; 124 125 static int vr_probe(device_t); 126 static int vr_attach(device_t); 127 static int vr_detach(device_t); 128 129 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 130 struct mbuf *); 131 static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * ); 132 133 static void vr_rxeof(struct vr_softc *); 134 static void vr_rxeoc(struct vr_softc *); 135 static void vr_txeof(struct vr_softc *); 136 static void vr_txeoc(struct vr_softc *); 137 static void vr_tick(void *); 138 static void vr_intr(void *); 139 static void vr_start(struct ifnet *); 140 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 141 static void vr_init(void *); 142 static void vr_stop(struct vr_softc *); 143 static void vr_watchdog(struct ifnet *); 144 static void vr_shutdown(device_t); 145 static int vr_ifmedia_upd(struct ifnet *); 146 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 147 148 #ifdef VR_USESWSHIFT 149 static void vr_mii_sync(struct vr_softc *); 150 static void vr_mii_send(struct vr_softc *, uint32_t, int); 151 #endif 152 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 153 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 154 static int vr_miibus_readreg(device_t, int, int); 155 static int vr_miibus_writereg(device_t, int, int, int); 156 static void vr_miibus_statchg(device_t); 157 158 static void vr_setcfg(struct vr_softc *, int); 159 static uint8_t vr_calchash(uint8_t *); 160 static void vr_setmulti(struct vr_softc *); 161 static void vr_reset(struct vr_softc *); 162 static int vr_list_rx_init(struct vr_softc *); 163 static int vr_list_tx_init(struct vr_softc *); 164 165 #ifdef VR_USEIOSPACE 166 #define VR_RES SYS_RES_IOPORT 167 #define VR_RID VR_PCI_LOIO 168 #else 169 #define VR_RES SYS_RES_MEMORY 170 #define VR_RID VR_PCI_LOMEM 171 #endif 172 173 static device_method_t vr_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, vr_probe), 176 DEVMETHOD(device_attach, vr_attach), 177 DEVMETHOD(device_detach, vr_detach), 178 DEVMETHOD(device_shutdown, vr_shutdown), 179 180 /* bus interface */ 181 DEVMETHOD(bus_print_child, bus_generic_print_child), 182 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 186 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 187 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 188 189 { 0, 0 } 190 }; 191 192 static driver_t vr_driver = { 193 "vr", 194 vr_methods, 195 sizeof(struct vr_softc) 196 }; 197 198 static devclass_t vr_devclass; 199 200 DECLARE_DUMMY_MODULE(if_vr); 201 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 202 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 203 204 #define VR_SETBIT(sc, reg, x) \ 205 CSR_WRITE_1(sc, reg, \ 206 CSR_READ_1(sc, reg) | (x)) 207 208 #define VR_CLRBIT(sc, reg, x) \ 209 CSR_WRITE_1(sc, reg, \ 210 CSR_READ_1(sc, reg) & ~(x)) 211 212 #define VR_SETBIT16(sc, reg, x) \ 213 CSR_WRITE_2(sc, reg, \ 214 CSR_READ_2(sc, reg) | (x)) 215 216 #define VR_CLRBIT16(sc, reg, x) \ 217 CSR_WRITE_2(sc, reg, \ 218 CSR_READ_2(sc, reg) & ~(x)) 219 220 #define VR_SETBIT32(sc, reg, x) \ 221 CSR_WRITE_4(sc, reg, \ 222 CSR_READ_4(sc, reg) | (x)) 223 224 #define VR_CLRBIT32(sc, reg, x) \ 225 CSR_WRITE_4(sc, reg, \ 226 CSR_READ_4(sc, reg) & ~(x)) 227 228 #define SIO_SET(x) \ 229 CSR_WRITE_1(sc, VR_MIICMD, \ 230 CSR_READ_1(sc, VR_MIICMD) | (x)) 231 232 #define SIO_CLR(x) \ 233 CSR_WRITE_1(sc, VR_MIICMD, \ 234 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 235 236 #ifdef VR_USESWSHIFT 237 /* 238 * Sync the PHYs by setting data bit and strobing the clock 32 times. 239 */ 240 static void 241 vr_mii_sync(struct vr_softc *sc) 242 { 243 int i; 244 245 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 246 247 for (i = 0; i < 32; i++) { 248 SIO_SET(VR_MIICMD_CLK); 249 DELAY(1); 250 SIO_CLR(VR_MIICMD_CLK); 251 DELAY(1); 252 } 253 } 254 255 /* 256 * Clock a series of bits through the MII. 257 */ 258 static void 259 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 260 { 261 int i; 262 263 SIO_CLR(VR_MIICMD_CLK); 264 265 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 266 if (bits & i) 267 SIO_SET(VR_MIICMD_DATAIN); 268 else 269 SIO_CLR(VR_MIICMD_DATAIN); 270 DELAY(1); 271 SIO_CLR(VR_MIICMD_CLK); 272 DELAY(1); 273 SIO_SET(VR_MIICMD_CLK); 274 } 275 } 276 #endif 277 278 /* 279 * Read an PHY register through the MII. 280 */ 281 static int 282 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 283 #ifdef VR_USESWSHIFT 284 { 285 int i, ack, s; 286 287 s = splimp(); 288 289 /* Set up frame for RX. */ 290 frame->mii_stdelim = VR_MII_STARTDELIM; 291 frame->mii_opcode = VR_MII_READOP; 292 frame->mii_turnaround = 0; 293 frame->mii_data = 0; 294 295 CSR_WRITE_1(sc, VR_MIICMD, 0); 296 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 297 298 /* Turn on data xmit. */ 299 SIO_SET(VR_MIICMD_DIR); 300 301 vr_mii_sync(sc); 302 303 /* Send command/address info. */ 304 vr_mii_send(sc, frame->mii_stdelim, 2); 305 vr_mii_send(sc, frame->mii_opcode, 2); 306 vr_mii_send(sc, frame->mii_phyaddr, 5); 307 vr_mii_send(sc, frame->mii_regaddr, 5); 308 309 /* Idle bit. */ 310 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 311 DELAY(1); 312 SIO_SET(VR_MIICMD_CLK); 313 DELAY(1); 314 315 /* Turn off xmit. */ 316 SIO_CLR(VR_MIICMD_DIR); 317 318 /* Check for ack */ 319 SIO_CLR(VR_MIICMD_CLK); 320 DELAY(1); 321 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 322 SIO_SET(VR_MIICMD_CLK); 323 DELAY(1); 324 325 /* 326 * Now try reading data bits. If the ack failed, we still 327 * need to clock through 16 cycles to keep the PHY(s) in sync. 328 */ 329 if (ack) { 330 for(i = 0; i < 16; i++) { 331 SIO_CLR(VR_MIICMD_CLK); 332 DELAY(1); 333 SIO_SET(VR_MIICMD_CLK); 334 DELAY(1); 335 } 336 goto fail; 337 } 338 339 for (i = 0x8000; i; i >>= 1) { 340 SIO_CLR(VR_MIICMD_CLK); 341 DELAY(1); 342 if (!ack) { 343 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 344 frame->mii_data |= i; 345 DELAY(1); 346 } 347 SIO_SET(VR_MIICMD_CLK); 348 DELAY(1); 349 } 350 351 fail: 352 SIO_CLR(VR_MIICMD_CLK); 353 DELAY(1); 354 SIO_SET(VR_MIICMD_CLK); 355 DELAY(1); 356 357 splx(s); 358 359 if (ack) 360 return(1); 361 return(0); 362 } 363 #else 364 { 365 int s, i; 366 367 s = splimp(); 368 369 /* Set the PHY address. */ 370 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 371 frame->mii_phyaddr); 372 373 /* Set the register address. */ 374 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 375 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 376 377 for (i = 0; i < 10000; i++) { 378 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 379 break; 380 DELAY(1); 381 } 382 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 383 384 splx(s); 385 386 return(0); 387 } 388 #endif 389 390 391 /* 392 * Write to a PHY register through the MII. 393 */ 394 static int 395 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 396 #ifdef VR_USESWSHIFT 397 { 398 int s; 399 400 s = splimp(); 401 402 CSR_WRITE_1(sc, VR_MIICMD, 0); 403 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 404 405 /* Set up frame for TX. */ 406 frame->mii_stdelim = VR_MII_STARTDELIM; 407 frame->mii_opcode = VR_MII_WRITEOP; 408 frame->mii_turnaround = VR_MII_TURNAROUND; 409 410 /* Turn on data output. */ 411 SIO_SET(VR_MIICMD_DIR); 412 413 vr_mii_sync(sc); 414 415 vr_mii_send(sc, frame->mii_stdelim, 2); 416 vr_mii_send(sc, frame->mii_opcode, 2); 417 vr_mii_send(sc, frame->mii_phyaddr, 5); 418 vr_mii_send(sc, frame->mii_regaddr, 5); 419 vr_mii_send(sc, frame->mii_turnaround, 2); 420 vr_mii_send(sc, frame->mii_data, 16); 421 422 /* Idle bit. */ 423 SIO_SET(VR_MIICMD_CLK); 424 DELAY(1); 425 SIO_CLR(VR_MIICMD_CLK); 426 DELAY(1); 427 428 /* Turn off xmit. */ 429 SIO_CLR(VR_MIICMD_DIR); 430 431 splx(s); 432 433 return(0); 434 } 435 #else 436 { 437 int s, i; 438 439 s = splimp(); 440 441 /* Set the PHY-adress */ 442 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 443 frame->mii_phyaddr); 444 445 /* Set the register address and data to write. */ 446 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 447 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 448 449 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 450 451 for (i = 0; i < 10000; i++) { 452 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 453 break; 454 DELAY(1); 455 } 456 457 splx(s); 458 459 return(0); 460 } 461 #endif 462 463 static int 464 vr_miibus_readreg(device_t dev, int phy, int reg) 465 { 466 struct vr_mii_frame frame; 467 struct vr_softc *sc; 468 469 sc = device_get_softc(dev); 470 471 switch (sc->vr_revid) { 472 case REV_ID_VT6102_APOLLO: 473 if (phy != 1) 474 return(0); 475 break; 476 default: 477 break; 478 } 479 480 bzero(&frame, sizeof(frame)); 481 482 frame.mii_phyaddr = phy; 483 frame.mii_regaddr = reg; 484 vr_mii_readreg(sc, &frame); 485 486 return(frame.mii_data); 487 } 488 489 static int 490 vr_miibus_writereg(device_t dev, int phy, int reg, int data) 491 { 492 struct vr_mii_frame frame; 493 struct vr_softc *sc; 494 495 sc = device_get_softc(dev); 496 497 switch (sc->vr_revid) { 498 case REV_ID_VT6102_APOLLO: 499 if (phy != 1) 500 return 0; 501 break; 502 default: 503 break; 504 } 505 506 bzero(&frame, sizeof(frame)); 507 508 frame.mii_phyaddr = phy; 509 frame.mii_regaddr = reg; 510 frame.mii_data = data; 511 512 vr_mii_writereg(sc, &frame); 513 514 return(0); 515 } 516 517 static void 518 vr_miibus_statchg(device_t dev) 519 { 520 struct mii_data *mii; 521 struct vr_softc *sc; 522 523 sc = device_get_softc(dev); 524 mii = device_get_softc(sc->vr_miibus); 525 vr_setcfg(sc, mii->mii_media_active); 526 } 527 528 /* 529 * Calculate CRC of a multicast group address, return the lower 6 bits. 530 */ 531 static uint8_t 532 vr_calchash(uint8_t *addr) 533 { 534 uint32_t crc, carry; 535 int i, j; 536 uint8_t c; 537 538 /* Compute CRC for the address value. */ 539 crc = 0xFFFFFFFF; /* initial value */ 540 541 for (i = 0; i < 6; i++) { 542 c = *(addr + i); 543 for (j = 0; j < 8; j++) { 544 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 545 crc <<= 1; 546 c >>= 1; 547 if (carry) 548 crc = (crc ^ 0x04c11db6) | carry; 549 } 550 } 551 552 /* return the filter bit position */ 553 return((crc >> 26) & 0x0000003F); 554 } 555 556 /* 557 * Program the 64-bit multicast hash filter. 558 */ 559 static void 560 vr_setmulti(struct vr_softc *sc) 561 { 562 struct ifnet *ifp; 563 int h = 0; 564 uint32_t hashes[2] = { 0, 0 }; 565 struct ifmultiaddr *ifma; 566 uint8_t rxfilt; 567 int mcnt = 0; 568 569 ifp = &sc->arpcom.ac_if; 570 571 rxfilt = CSR_READ_1(sc, VR_RXCFG); 572 573 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 574 rxfilt |= VR_RXCFG_RX_MULTI; 575 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 576 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 577 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 578 return; 579 } 580 581 /* First, zero out all the existing hash bits. */ 582 CSR_WRITE_4(sc, VR_MAR0, 0); 583 CSR_WRITE_4(sc, VR_MAR1, 0); 584 585 /* Now program new ones. */ 586 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 587 ifma = ifma->ifma_link.le_next) { 588 if (ifma->ifma_addr->sa_family != AF_LINK) 589 continue; 590 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 591 if (h < 32) 592 hashes[0] |= (1 << h); 593 else 594 hashes[1] |= (1 << (h - 32)); 595 mcnt++; 596 } 597 598 if (mcnt) 599 rxfilt |= VR_RXCFG_RX_MULTI; 600 else 601 rxfilt &= ~VR_RXCFG_RX_MULTI; 602 603 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 604 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 605 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 606 } 607 608 /* 609 * In order to fiddle with the 610 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 611 * first have to put the transmit and/or receive logic in the idle state. 612 */ 613 static void 614 vr_setcfg(struct vr_softc *sc, int media) 615 { 616 int restart = 0; 617 618 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 619 restart = 1; 620 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 621 } 622 623 if ((media & IFM_GMASK) == IFM_FDX) 624 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 625 else 626 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 627 628 if (restart) 629 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 630 } 631 632 static void 633 vr_reset(struct vr_softc *sc) 634 { 635 int i; 636 637 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 638 639 for (i = 0; i < VR_TIMEOUT; i++) { 640 DELAY(10); 641 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 642 break; 643 } 644 if (i == VR_TIMEOUT) { 645 struct ifnet *ifp = &sc->arpcom.ac_if; 646 647 if (sc->vr_revid < REV_ID_VT3065_A) { 648 if_printf(ifp, "reset never completed!\n"); 649 } else { 650 /* Use newer force reset command */ 651 if_printf(ifp, "Using force reset command.\n"); 652 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 653 } 654 } 655 656 /* Wait a little while for the chip to get its brains in order. */ 657 DELAY(1000); 658 } 659 660 /* 661 * Probe for a VIA Rhine chip. Check the PCI vendor and device 662 * IDs against our list and return a device name if we find a match. 663 */ 664 static int 665 vr_probe(device_t dev) 666 { 667 struct vr_type *t; 668 669 t = vr_devs; 670 671 while(t->vr_name != NULL) { 672 if ((pci_get_vendor(dev) == t->vr_vid) && 673 (pci_get_device(dev) == t->vr_did)) { 674 device_set_desc(dev, t->vr_name); 675 return(0); 676 } 677 t++; 678 } 679 680 return(ENXIO); 681 } 682 683 /* 684 * Attach the interface. Allocate softc structures, do ifmedia 685 * setup and ethernet/BPF attach. 686 */ 687 static int 688 vr_attach(device_t dev) 689 { 690 int i, s; 691 uint8_t eaddr[ETHER_ADDR_LEN]; 692 uint32_t command; 693 struct vr_softc *sc; 694 struct ifnet *ifp; 695 int unit, error = 0, rid; 696 697 s = splimp(); 698 699 sc = device_get_softc(dev); 700 unit = device_get_unit(dev); 701 callout_init(&sc->vr_stat_timer); 702 703 /* 704 * Handle power management nonsense. 705 */ 706 707 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 708 if (command == 0x01) { 709 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 710 if (command & VR_PSTATE_MASK) { 711 uint32_t iobase, membase, irq; 712 713 /* Save important PCI config data. */ 714 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 715 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 716 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 717 718 /* Reset the power state. */ 719 device_printf(dev, "chip is in D%d power mode " 720 "-- setting to D0\n", command & VR_PSTATE_MASK); 721 command &= 0xFFFFFFFC; 722 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 723 724 /* Restore PCI config data. */ 725 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 726 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 727 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 728 } 729 } 730 731 /* 732 * Map control/status registers. 733 */ 734 command = pci_read_config(dev, PCIR_COMMAND, 4); 735 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 736 pci_write_config(dev, PCIR_COMMAND, command, 4); 737 command = pci_read_config(dev, PCIR_COMMAND, 4); 738 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 739 740 #ifdef VR_USEIOSPACE 741 if (!(command & PCIM_CMD_PORTEN)) { 742 device_printf(dev, "failed to enable I/O ports!\n"); 743 free(sc, M_DEVBUF); 744 goto fail; 745 } 746 #else 747 if (!(command & PCIM_CMD_MEMEN)) { 748 device_printf(dev, "failed to enable memory mapping!\n"); 749 goto fail; 750 } 751 #endif 752 753 rid = VR_RID; 754 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 755 756 if (sc->vr_res == NULL) { 757 device_printf(dev, "couldn't map ports/memory\n"); 758 error = ENXIO; 759 goto fail; 760 } 761 762 sc->vr_btag = rman_get_bustag(sc->vr_res); 763 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 764 765 /* Allocate interrupt */ 766 rid = 0; 767 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 768 RF_SHAREABLE | RF_ACTIVE); 769 770 if (sc->vr_irq == NULL) { 771 device_printf(dev, "couldn't map interrupt\n"); 772 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 773 error = ENXIO; 774 goto fail; 775 } 776 777 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 778 vr_intr, sc, &sc->vr_intrhand); 779 780 if (error) { 781 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 782 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 783 device_printf(dev, "couldn't set up irq\n"); 784 goto fail; 785 } 786 787 /* 788 * Windows may put the chip in suspend mode when it 789 * shuts down. Be sure to kick it in the head to wake it 790 * up again. 791 */ 792 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 793 794 /* Reset the adapter. */ 795 vr_reset(sc); 796 797 /* 798 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 799 * initialization and disable AUTOPOLL. 800 */ 801 pci_write_config(dev, VR_PCI_MODE, 802 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 803 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 804 805 /* 806 * Get station address. The way the Rhine chips work, 807 * you're not allowed to directly access the EEPROM once 808 * they've been programmed a special way. Consequently, 809 * we need to read the node address from the PAR0 and PAR1 810 * registers. 811 */ 812 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 813 DELAY(200); 814 for (i = 0; i < ETHER_ADDR_LEN; i++) 815 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 816 817 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 818 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 819 820 if (sc->vr_ldata == NULL) { 821 device_printf(dev, "no memory for list buffers!\n"); 822 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 823 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 824 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 825 error = ENXIO; 826 goto fail; 827 } 828 829 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 830 831 ifp = &sc->arpcom.ac_if; 832 ifp->if_softc = sc; 833 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 834 ifp->if_mtu = ETHERMTU; 835 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 836 ifp->if_ioctl = vr_ioctl; 837 ifp->if_start = vr_start; 838 ifp->if_watchdog = vr_watchdog; 839 ifp->if_init = vr_init; 840 ifp->if_baudrate = 10000000; 841 ifq_set_maxlen(&ifp->if_snd, VR_TX_LIST_CNT - 1); 842 ifq_set_ready(&ifp->if_snd); 843 844 /* 845 * Do MII setup. 846 */ 847 if (mii_phy_probe(dev, &sc->vr_miibus, 848 vr_ifmedia_upd, vr_ifmedia_sts)) { 849 if_printf(ifp, "MII without any phy!\n"); 850 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 851 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 852 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 853 contigfree(sc->vr_ldata, 854 sizeof(struct vr_list_data), M_DEVBUF); 855 error = ENXIO; 856 goto fail; 857 } 858 859 /* Call MI attach routine. */ 860 ether_ifattach(ifp, eaddr); 861 862 fail: 863 splx(s); 864 return(error); 865 } 866 867 static int 868 vr_detach(device_t dev) 869 { 870 struct vr_softc *sc; 871 struct ifnet *ifp; 872 int s; 873 874 s = splimp(); 875 876 sc = device_get_softc(dev); 877 ifp = &sc->arpcom.ac_if; 878 879 vr_stop(sc); 880 ether_ifdetach(ifp); 881 882 bus_generic_detach(dev); 883 device_delete_child(dev, sc->vr_miibus); 884 885 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 886 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 887 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 888 889 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 890 891 splx(s); 892 893 return(0); 894 } 895 896 /* 897 * Initialize the transmit descriptors. 898 */ 899 static int 900 vr_list_tx_init(struct vr_softc *sc) 901 { 902 struct vr_chain_data *cd; 903 struct vr_list_data *ld; 904 int i, nexti; 905 906 cd = &sc->vr_cdata; 907 ld = sc->vr_ldata; 908 for (i = 0; i < VR_TX_LIST_CNT; i++) { 909 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 910 if (i == (VR_TX_LIST_CNT - 1)) 911 nexti = 0; 912 else 913 nexti = i + 1; 914 cd->vr_tx_chain[i].vr_nextdesc = &cd->vr_tx_chain[nexti]; 915 } 916 917 cd->vr_tx_free = &cd->vr_tx_chain[0]; 918 cd->vr_tx_tail = cd->vr_tx_head = NULL; 919 920 return(0); 921 } 922 923 924 /* 925 * Initialize the RX descriptors and allocate mbufs for them. Note that 926 * we arrange the descriptors in a closed ring, so that the last descriptor 927 * points back to the first. 928 */ 929 static int 930 vr_list_rx_init(struct vr_softc *sc) 931 { 932 struct vr_chain_data *cd; 933 struct vr_list_data *ld; 934 int i, nexti; 935 936 cd = &sc->vr_cdata; 937 ld = sc->vr_ldata; 938 939 for (i = 0; i < VR_RX_LIST_CNT; i++) { 940 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i]; 941 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 942 return(ENOBUFS); 943 if (i == (VR_RX_LIST_CNT - 1)) 944 nexti = 0; 945 else 946 nexti = i + 1; 947 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti]; 948 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]); 949 } 950 951 cd->vr_rx_head = &cd->vr_rx_chain[0]; 952 953 return(0); 954 } 955 956 /* 957 * Initialize an RX descriptor and attach an MBUF cluster. 958 * Note: the length fields are only 11 bits wide, which means the 959 * largest size we can specify is 2047. This is important because 960 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 961 * overflow the field and make a mess. 962 */ 963 static int 964 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 965 { 966 struct mbuf *m_new = NULL; 967 968 if (m == NULL) { 969 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 970 if (m_new == NULL) 971 return(ENOBUFS); 972 973 MCLGET(m_new, MB_DONTWAIT); 974 if (!(m_new->m_flags & M_EXT)) { 975 m_freem(m_new); 976 return(ENOBUFS); 977 } 978 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 979 } else { 980 m_new = m; 981 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 982 m_new->m_data = m_new->m_ext.ext_buf; 983 } 984 985 m_adj(m_new, sizeof(uint64_t)); 986 987 c->vr_mbuf = m_new; 988 c->vr_ptr->vr_status = VR_RXSTAT; 989 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 990 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 991 992 return(0); 993 } 994 995 /* 996 * A frame has been uploaded: pass the resulting mbuf chain up to 997 * the higher level protocols. 998 */ 999 static void 1000 vr_rxeof(struct vr_softc *sc) 1001 { 1002 struct mbuf *m; 1003 struct ifnet *ifp; 1004 struct vr_chain_onefrag *cur_rx; 1005 int total_len = 0; 1006 uint32_t rxstat; 1007 1008 ifp = &sc->arpcom.ac_if; 1009 1010 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1011 VR_RXSTAT_OWN)) { 1012 struct mbuf *m0 = NULL; 1013 1014 cur_rx = sc->vr_cdata.vr_rx_head; 1015 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1016 m = cur_rx->vr_mbuf; 1017 1018 /* 1019 * If an error occurs, update stats, clear the 1020 * status word and leave the mbuf cluster in place: 1021 * it should simply get re-used next time this descriptor 1022 * comes up in the ring. 1023 */ 1024 if (rxstat & VR_RXSTAT_RXERR) { 1025 ifp->if_ierrors++; 1026 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff); 1027 if (rxstat & VR_RXSTAT_CRCERR) 1028 printf(" crc error"); 1029 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1030 printf(" frame alignment error\n"); 1031 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1032 printf(" FIFO overflow"); 1033 if (rxstat & VR_RXSTAT_GIANT) 1034 printf(" received giant packet"); 1035 if (rxstat & VR_RXSTAT_RUNT) 1036 printf(" received runt packet"); 1037 if (rxstat & VR_RXSTAT_BUSERR) 1038 printf(" system bus error"); 1039 if (rxstat & VR_RXSTAT_BUFFERR) 1040 printf("rx buffer error"); 1041 printf("\n"); 1042 vr_newbuf(sc, cur_rx, m); 1043 continue; 1044 } 1045 1046 /* No errors; receive the packet. */ 1047 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1048 1049 /* 1050 * XXX The VIA Rhine chip includes the CRC with every 1051 * received frame, and there's no way to turn this 1052 * behavior off (at least, I can't find anything in 1053 * the manual that explains how to do it) so we have 1054 * to trim off the CRC manually. 1055 */ 1056 total_len -= ETHER_CRC_LEN; 1057 1058 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1059 total_len + ETHER_ALIGN, 0, ifp, NULL); 1060 vr_newbuf(sc, cur_rx, m); 1061 if (m0 == NULL) { 1062 ifp->if_ierrors++; 1063 continue; 1064 } 1065 m_adj(m0, ETHER_ALIGN); 1066 m = m0; 1067 1068 ifp->if_ipackets++; 1069 (*ifp->if_input)(ifp, m); 1070 } 1071 } 1072 1073 static void 1074 vr_rxeoc(struct vr_softc *sc) 1075 { 1076 struct ifnet *ifp; 1077 int i; 1078 1079 ifp = &sc->arpcom.ac_if; 1080 1081 ifp->if_ierrors++; 1082 1083 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1084 DELAY(10000); 1085 1086 /* Wait for receiver to stop */ 1087 for (i = 0x400; 1088 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1089 i--) 1090 ; /* Wait for receiver to stop */ 1091 1092 if (i == 0) { 1093 if_printf(ifp, "rx shutdown error!\n"); 1094 sc->vr_flags |= VR_F_RESTART; 1095 return; 1096 } 1097 1098 vr_rxeof(sc); 1099 1100 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1101 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1102 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1103 } 1104 1105 /* 1106 * A frame was downloaded to the chip. It's safe for us to clean up 1107 * the list buffers. 1108 */ 1109 static void 1110 vr_txeof(struct vr_softc *sc) 1111 { 1112 struct vr_chain *cur_tx; 1113 struct ifnet *ifp; 1114 1115 ifp = &sc->arpcom.ac_if; 1116 1117 /* Reset the timeout timer; if_txeoc will clear it. */ 1118 ifp->if_timer = 5; 1119 1120 /* Sanity check. */ 1121 if (sc->vr_cdata.vr_tx_head == NULL) 1122 return; 1123 1124 /* 1125 * Go through our tx list and free mbufs for those 1126 * frames that have been transmitted. 1127 */ 1128 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1129 uint32_t txstat; 1130 int i; 1131 1132 cur_tx = sc->vr_cdata.vr_tx_head; 1133 txstat = cur_tx->vr_ptr->vr_status; 1134 1135 if ((txstat & VR_TXSTAT_ABRT) || 1136 (txstat & VR_TXSTAT_UDF)) { 1137 for (i = 0x400; 1138 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1139 i--) 1140 ; /* Wait for chip to shutdown */ 1141 if (i == 0) { 1142 if_printf(ifp, "tx shutdown timeout\n"); 1143 sc->vr_flags |= VR_F_RESTART; 1144 break; 1145 } 1146 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1147 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1148 break; 1149 } 1150 1151 if (txstat & VR_TXSTAT_OWN) 1152 break; 1153 1154 if (txstat & VR_TXSTAT_ERRSUM) { 1155 ifp->if_oerrors++; 1156 if (txstat & VR_TXSTAT_DEFER) 1157 ifp->if_collisions++; 1158 if (txstat & VR_TXSTAT_LATECOLL) 1159 ifp->if_collisions++; 1160 } 1161 1162 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1163 1164 ifp->if_opackets++; 1165 if (cur_tx->vr_mbuf != NULL) { 1166 m_freem(cur_tx->vr_mbuf); 1167 cur_tx->vr_mbuf = NULL; 1168 } 1169 1170 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1171 sc->vr_cdata.vr_tx_head = NULL; 1172 sc->vr_cdata.vr_tx_tail = NULL; 1173 break; 1174 } 1175 1176 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1177 } 1178 } 1179 1180 /* 1181 * TX 'end of channel' interrupt handler. 1182 */ 1183 static void 1184 vr_txeoc(struct vr_softc *sc) 1185 { 1186 struct ifnet *ifp; 1187 1188 ifp = &sc->arpcom.ac_if; 1189 1190 if (sc->vr_cdata.vr_tx_head == NULL) { 1191 ifp->if_flags &= ~IFF_OACTIVE; 1192 sc->vr_cdata.vr_tx_tail = NULL; 1193 ifp->if_timer = 0; 1194 } 1195 } 1196 1197 static void 1198 vr_tick(void *xsc) 1199 { 1200 struct vr_softc *sc; 1201 struct mii_data *mii; 1202 int s; 1203 1204 s = splimp(); 1205 1206 sc = xsc; 1207 if (sc->vr_flags & VR_F_RESTART) { 1208 if_printf(&sc->arpcom.ac_if, "restarting\n"); 1209 vr_stop(sc); 1210 vr_reset(sc); 1211 vr_init(sc); 1212 sc->vr_flags &= ~VR_F_RESTART; 1213 } 1214 1215 mii = device_get_softc(sc->vr_miibus); 1216 mii_tick(mii); 1217 1218 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1219 1220 splx(s); 1221 } 1222 1223 static void 1224 vr_intr(void *arg) 1225 { 1226 struct vr_softc *sc; 1227 struct ifnet *ifp; 1228 uint16_t status; 1229 1230 sc = arg; 1231 ifp = &sc->arpcom.ac_if; 1232 1233 /* Supress unwanted interrupts. */ 1234 if (!(ifp->if_flags & IFF_UP)) { 1235 vr_stop(sc); 1236 return; 1237 } 1238 1239 /* Disable interrupts. */ 1240 if ((ifp->if_flags & IFF_POLLING) == 0) 1241 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1242 1243 for (;;) { 1244 status = CSR_READ_2(sc, VR_ISR); 1245 if (status) 1246 CSR_WRITE_2(sc, VR_ISR, status); 1247 1248 if ((status & VR_INTRS) == 0) 1249 break; 1250 1251 if (status & VR_ISR_RX_OK) 1252 vr_rxeof(sc); 1253 1254 if (status & VR_ISR_RX_DROPPED) { 1255 if_printf(ifp, "rx packet lost\n"); 1256 ifp->if_ierrors++; 1257 } 1258 1259 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1260 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1261 if_printf(ifp, "receive error (%04x)", status); 1262 if (status & VR_ISR_RX_NOBUF) 1263 printf(" no buffers"); 1264 if (status & VR_ISR_RX_OFLOW) 1265 printf(" overflow"); 1266 if (status & VR_ISR_RX_DROPPED) 1267 printf(" packet lost"); 1268 printf("\n"); 1269 vr_rxeoc(sc); 1270 } 1271 1272 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1273 vr_reset(sc); 1274 vr_init(sc); 1275 break; 1276 } 1277 1278 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1279 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1280 vr_txeof(sc); 1281 if ((status & VR_ISR_UDFI) || 1282 (status & VR_ISR_TX_ABRT2) || 1283 (status & VR_ISR_TX_ABRT)) { 1284 ifp->if_oerrors++; 1285 if (sc->vr_cdata.vr_tx_head != NULL) { 1286 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1287 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1288 } 1289 } else { 1290 vr_txeoc(sc); 1291 } 1292 } 1293 1294 } 1295 1296 /* Re-enable interrupts. */ 1297 if ((ifp->if_flags & IFF_POLLING) == 0) 1298 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1299 1300 if (!ifq_is_empty(&ifp->if_snd)) 1301 vr_start(ifp); 1302 } 1303 1304 /* 1305 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1306 * pointers to the fragment pointers. 1307 */ 1308 static int 1309 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1310 { 1311 int frag = 0; 1312 struct vr_desc *f = NULL; 1313 int total_len; 1314 struct mbuf *m_new; 1315 1316 total_len = 0; 1317 1318 /* 1319 * The VIA Rhine wants packet buffers to be longword 1320 * aligned, but very often our mbufs aren't. Rather than 1321 * waste time trying to decide when to copy and when not 1322 * to copy, just do it all the time. 1323 */ 1324 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1325 if (m_new == NULL) { 1326 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n"); 1327 return(1); 1328 } 1329 if (m_head->m_pkthdr.len > MHLEN) { 1330 MCLGET(m_new, MB_DONTWAIT); 1331 if (!(m_new->m_flags & M_EXT)) { 1332 m_freem(m_new); 1333 if_printf(&sc->arpcom.ac_if, 1334 "no memory for tx list\n"); 1335 return(1); 1336 } 1337 } 1338 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1339 mtod(m_new, caddr_t)); 1340 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1341 /* 1342 * The Rhine chip doesn't auto-pad, so we have to make 1343 * sure to pad short frames out to the minimum frame length 1344 * ourselves. 1345 */ 1346 if (m_new->m_len < VR_MIN_FRAMELEN) { 1347 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1348 m_new->m_len = m_new->m_pkthdr.len; 1349 } 1350 f = c->vr_ptr; 1351 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1352 f->vr_ctl = total_len = m_new->m_len; 1353 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1354 f->vr_status = 0; 1355 frag = 1; 1356 1357 c->vr_mbuf = m_new; 1358 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1359 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1360 1361 return(0); 1362 } 1363 1364 /* 1365 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1366 * to the mbuf data regions directly in the transmit lists. We also save a 1367 * copy of the pointers since the transmit list fragment pointers are 1368 * physical addresses. 1369 */ 1370 static void 1371 vr_start(struct ifnet *ifp) 1372 { 1373 struct vr_softc *sc; 1374 struct mbuf *m_head = NULL; 1375 struct vr_chain *cur_tx = NULL, *start_tx; 1376 1377 sc = ifp->if_softc; 1378 1379 if (ifp->if_flags & IFF_OACTIVE) 1380 return; 1381 1382 /* Check for an available queue slot. If there are none, punt. */ 1383 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1384 ifp->if_flags |= IFF_OACTIVE; 1385 return; 1386 } 1387 1388 start_tx = sc->vr_cdata.vr_tx_free; 1389 1390 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1391 m_head = ifq_poll(&ifp->if_snd); 1392 if (m_head == NULL) 1393 break; 1394 1395 /* Pick a descriptor off the free list. */ 1396 cur_tx = sc->vr_cdata.vr_tx_free; 1397 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1398 1399 /* Pack the data into the descriptor. */ 1400 if (vr_encap(sc, cur_tx, m_head)) { 1401 ifp->if_flags |= IFF_OACTIVE; 1402 cur_tx = NULL; 1403 break; 1404 } 1405 1406 m_head = ifq_dequeue(&ifp->if_snd); 1407 if (cur_tx != start_tx) 1408 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1409 1410 BPF_MTAP(ifp, m_head); 1411 m_freem(m_head); 1412 1413 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1414 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1415 } 1416 1417 /* If there are no frames queued, bail. */ 1418 if (cur_tx == NULL) 1419 return; 1420 1421 sc->vr_cdata.vr_tx_tail = cur_tx; 1422 1423 if (sc->vr_cdata.vr_tx_head == NULL) 1424 sc->vr_cdata.vr_tx_head = start_tx; 1425 1426 /* 1427 * Set a timeout in case the chip goes out to lunch. 1428 */ 1429 ifp->if_timer = 5; 1430 } 1431 1432 static void 1433 vr_init(void *xsc) 1434 { 1435 struct vr_softc *sc = xsc; 1436 struct ifnet *ifp = &sc->arpcom.ac_if; 1437 struct mii_data *mii; 1438 int s, i; 1439 1440 s = splimp(); 1441 1442 mii = device_get_softc(sc->vr_miibus); 1443 1444 /* Cancel pending I/O and free all RX/TX buffers. */ 1445 vr_stop(sc); 1446 vr_reset(sc); 1447 1448 /* Set our station address. */ 1449 for (i = 0; i < ETHER_ADDR_LEN; i++) 1450 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1451 1452 /* Set DMA size. */ 1453 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1454 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1455 1456 /* 1457 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1458 * so we must set both. 1459 */ 1460 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1461 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1462 1463 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1464 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1465 1466 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1467 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1468 1469 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1470 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1471 1472 /* Init circular RX list. */ 1473 if (vr_list_rx_init(sc) == ENOBUFS) { 1474 if_printf(ifp, "initialization failed: no memory for rx buffers\n"); 1475 vr_stop(sc); 1476 splx(s); 1477 return; 1478 } 1479 1480 /* Init tx descriptors. */ 1481 vr_list_tx_init(sc); 1482 1483 /* If we want promiscuous mode, set the allframes bit. */ 1484 if (ifp->if_flags & IFF_PROMISC) 1485 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1486 else 1487 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1488 1489 /* Set capture broadcast bit to capture broadcast frames. */ 1490 if (ifp->if_flags & IFF_BROADCAST) 1491 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1492 else 1493 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1494 1495 /* 1496 * Program the multicast filter, if necessary. 1497 */ 1498 vr_setmulti(sc); 1499 1500 /* 1501 * Load the address of the RX list. 1502 */ 1503 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1504 1505 /* Enable receiver and transmitter. */ 1506 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1507 VR_CMD_TX_ON|VR_CMD_RX_ON| 1508 VR_CMD_RX_GO); 1509 1510 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1511 1512 /* 1513 * Enable interrupts, unless we are polling. 1514 */ 1515 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1516 if ((ifp->if_flags & IFF_POLLING) == 0) 1517 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1518 1519 mii_mediachg(mii); 1520 1521 ifp->if_flags |= IFF_RUNNING; 1522 ifp->if_flags &= ~IFF_OACTIVE; 1523 1524 splx(s); 1525 1526 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1527 } 1528 1529 /* 1530 * Set media options. 1531 */ 1532 static int 1533 vr_ifmedia_upd(struct ifnet *ifp) 1534 { 1535 struct vr_softc *sc; 1536 1537 sc = ifp->if_softc; 1538 1539 if (ifp->if_flags & IFF_UP) 1540 vr_init(sc); 1541 1542 return(0); 1543 } 1544 1545 /* 1546 * Report current media status. 1547 */ 1548 static void 1549 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1550 { 1551 struct vr_softc *sc; 1552 struct mii_data *mii; 1553 1554 sc = ifp->if_softc; 1555 mii = device_get_softc(sc->vr_miibus); 1556 mii_pollstat(mii); 1557 ifmr->ifm_active = mii->mii_media_active; 1558 ifmr->ifm_status = mii->mii_media_status; 1559 } 1560 1561 static int 1562 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1563 { 1564 struct vr_softc *sc = ifp->if_softc; 1565 struct ifreq *ifr = (struct ifreq *) data; 1566 struct mii_data *mii; 1567 int s, error = 0; 1568 1569 s = splimp(); 1570 1571 switch(command) { 1572 case SIOCSIFADDR: 1573 case SIOCGIFADDR: 1574 case SIOCSIFMTU: 1575 error = ether_ioctl(ifp, command, data); 1576 break; 1577 case SIOCSIFFLAGS: 1578 if (ifp->if_flags & IFF_UP) { 1579 vr_init(sc); 1580 } else { 1581 if (ifp->if_flags & IFF_RUNNING) 1582 vr_stop(sc); 1583 } 1584 error = 0; 1585 break; 1586 case SIOCADDMULTI: 1587 case SIOCDELMULTI: 1588 vr_setmulti(sc); 1589 error = 0; 1590 break; 1591 case SIOCGIFMEDIA: 1592 case SIOCSIFMEDIA: 1593 mii = device_get_softc(sc->vr_miibus); 1594 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1595 break; 1596 default: 1597 error = EINVAL; 1598 break; 1599 } 1600 1601 splx(s); 1602 1603 return(error); 1604 } 1605 1606 #ifdef DEVICE_POLLING 1607 static void 1608 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1609 { 1610 struct vr_softc *sc = ifp->if_softc; 1611 1612 if (cmd == POLL_DEREGISTER) 1613 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1614 else 1615 vr_intr(sc); 1616 } 1617 #endif 1618 1619 static void 1620 vr_watchdog(struct ifnet *ifp) 1621 { 1622 struct vr_softc *sc; 1623 1624 sc = ifp->if_softc; 1625 1626 ifp->if_oerrors++; 1627 if_printf(ifp, "watchdog timeout\n"); 1628 1629 #ifdef DEVICE_POLLING 1630 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) { 1631 if_printf(ifp, "ints don't seem to be working, " 1632 "emergency switch to polling\n"); 1633 emergency_poll_enable("if_vr"); 1634 if (ether_poll_register(vr_poll, ifp)) 1635 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1636 } else 1637 #endif 1638 { 1639 vr_stop(sc); 1640 vr_reset(sc); 1641 vr_init(sc); 1642 } 1643 1644 if (!ifq_is_empty(&ifp->if_snd)) 1645 vr_start(ifp); 1646 } 1647 1648 /* 1649 * Stop the adapter and free any mbufs allocated to the 1650 * RX and TX lists. 1651 */ 1652 static void 1653 vr_stop(struct vr_softc *sc) 1654 { 1655 int i; 1656 struct ifnet *ifp; 1657 1658 ifp = &sc->arpcom.ac_if; 1659 ifp->if_timer = 0; 1660 1661 callout_stop(&sc->vr_stat_timer); 1662 1663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1664 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1665 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1666 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1667 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1668 1669 /* 1670 * Free data in the RX lists. 1671 */ 1672 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1673 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1674 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1675 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1676 } 1677 } 1678 bzero((char *)&sc->vr_ldata->vr_rx_list, 1679 sizeof(sc->vr_ldata->vr_rx_list)); 1680 1681 /* 1682 * Free the TX list buffers. 1683 */ 1684 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1685 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1686 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1687 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1688 } 1689 } 1690 1691 bzero((char *)&sc->vr_ldata->vr_tx_list, 1692 sizeof(sc->vr_ldata->vr_tx_list)); 1693 1694 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1695 } 1696 1697 /* 1698 * Stop all chip I/O so that the kernel's probe routines don't 1699 * get confused by errant DMAs when rebooting. 1700 */ 1701 static void 1702 vr_shutdown(device_t dev) 1703 { 1704 struct vr_softc *sc; 1705 1706 sc = device_get_softc(dev); 1707 1708 vr_stop(sc); 1709 } 1710