1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.17 2005/02/12 02:23:24 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 36 */ 37 38 /* 39 * VIA Rhine fast ethernet PCI NIC driver 40 * 41 * Supports various network adapters based on the VIA Rhine 42 * and Rhine II PCI controllers, including the D-Link DFE530TX. 43 * Datasheets are available at http://www.via.com.tw. 44 * 45 * Written by Bill Paul <wpaul@ctr.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The VIA Rhine controllers are similar in some respects to the 52 * the DEC tulip chips, except less complicated. The controller 53 * uses an MII bus and an external physical layer interface. The 54 * receiver has a one entry perfect filter and a 64-bit hash table 55 * multicast filter. Transmit and receive descriptors are similar 56 * to the tulip. 57 * 58 * The Rhine has a serious flaw in its transmit DMA mechanism: 59 * transmit buffers must be longword aligned. Unfortunately, 60 * FreeBSD doesn't guarantee that mbufs will be filled in starting 61 * at longword boundaries, so we have to do a buffer copy before 62 * transmission. 63 */ 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/sockio.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/kernel.h> 71 #include <sys/socket.h> 72 73 #include <net/if.h> 74 #include <net/if_arp.h> 75 #include <net/ethernet.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 79 #include <net/bpf.h> 80 81 #include <vm/vm.h> /* for vtophys */ 82 #include <vm/pmap.h> /* for vtophys */ 83 #include <machine/bus_pio.h> 84 #include <machine/bus_memio.h> 85 #include <machine/bus.h> 86 #include <machine/resource.h> 87 #include <sys/bus.h> 88 #include <sys/rman.h> 89 90 #include <dev/netif/mii_layer/mii.h> 91 #include <dev/netif/mii_layer/miivar.h> 92 93 #include <bus/pci/pcireg.h> 94 #include <bus/pci/pcivar.h> 95 96 #define VR_USEIOSPACE 97 98 #include <dev/netif/vr/if_vrreg.h> 99 100 /* "controller miibus0" required. See GENERIC if you get errors here. */ 101 #include "miibus_if.h" 102 103 #undef VR_USESWSHIFT 104 105 /* 106 * Various supported device vendors/types and their names. 107 */ 108 static struct vr_type vr_devs[] = { 109 { VIA_VENDORID, VIA_DEVICEID_RHINE, 110 "VIA VT3043 Rhine I 10/100BaseTX" }, 111 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 112 "VIA VT86C100A Rhine II 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 114 "VIA VT6102 Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 116 "VIA VT6105 Rhine III 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 118 "VIA VT6105M Rhine III 10/100BaseTX" }, 119 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 120 "Delta Electronics Rhine II 10/100BaseTX" }, 121 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 122 "Addtron Technology Rhine II 10/100BaseTX" }, 123 { 0, 0, NULL } 124 }; 125 126 static int vr_probe(device_t); 127 static int vr_attach(device_t); 128 static int vr_detach(device_t); 129 130 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 131 struct mbuf *); 132 static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * ); 133 134 static void vr_rxeof(struct vr_softc *); 135 static void vr_rxeoc(struct vr_softc *); 136 static void vr_txeof(struct vr_softc *); 137 static void vr_txeoc(struct vr_softc *); 138 static void vr_tick(void *); 139 static void vr_intr(void *); 140 static void vr_start(struct ifnet *); 141 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 142 static void vr_init(void *); 143 static void vr_stop(struct vr_softc *); 144 static void vr_watchdog(struct ifnet *); 145 static void vr_shutdown(device_t); 146 static int vr_ifmedia_upd(struct ifnet *); 147 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148 149 #ifdef VR_USESWSHIFT 150 static void vr_mii_sync(struct vr_softc *); 151 static void vr_mii_send(struct vr_softc *, uint32_t, int); 152 #endif 153 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 154 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 155 static int vr_miibus_readreg(device_t, int, int); 156 static int vr_miibus_writereg(device_t, int, int, int); 157 static void vr_miibus_statchg(device_t); 158 159 static void vr_setcfg(struct vr_softc *, int); 160 static uint8_t vr_calchash(uint8_t *); 161 static void vr_setmulti(struct vr_softc *); 162 static void vr_reset(struct vr_softc *); 163 static int vr_list_rx_init(struct vr_softc *); 164 static int vr_list_tx_init(struct vr_softc *); 165 166 #ifdef VR_USEIOSPACE 167 #define VR_RES SYS_RES_IOPORT 168 #define VR_RID VR_PCI_LOIO 169 #else 170 #define VR_RES SYS_RES_MEMORY 171 #define VR_RID VR_PCI_LOMEM 172 #endif 173 174 static device_method_t vr_methods[] = { 175 /* Device interface */ 176 DEVMETHOD(device_probe, vr_probe), 177 DEVMETHOD(device_attach, vr_attach), 178 DEVMETHOD(device_detach, vr_detach), 179 DEVMETHOD(device_shutdown, vr_shutdown), 180 181 /* bus interface */ 182 DEVMETHOD(bus_print_child, bus_generic_print_child), 183 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 184 185 /* MII interface */ 186 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 187 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 188 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 189 190 { 0, 0 } 191 }; 192 193 static driver_t vr_driver = { 194 "vr", 195 vr_methods, 196 sizeof(struct vr_softc) 197 }; 198 199 static devclass_t vr_devclass; 200 201 DECLARE_DUMMY_MODULE(if_vr); 202 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 203 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 204 205 #define VR_SETBIT(sc, reg, x) \ 206 CSR_WRITE_1(sc, reg, \ 207 CSR_READ_1(sc, reg) | (x)) 208 209 #define VR_CLRBIT(sc, reg, x) \ 210 CSR_WRITE_1(sc, reg, \ 211 CSR_READ_1(sc, reg) & ~(x)) 212 213 #define VR_SETBIT16(sc, reg, x) \ 214 CSR_WRITE_2(sc, reg, \ 215 CSR_READ_2(sc, reg) | (x)) 216 217 #define VR_CLRBIT16(sc, reg, x) \ 218 CSR_WRITE_2(sc, reg, \ 219 CSR_READ_2(sc, reg) & ~(x)) 220 221 #define VR_SETBIT32(sc, reg, x) \ 222 CSR_WRITE_4(sc, reg, \ 223 CSR_READ_4(sc, reg) | (x)) 224 225 #define VR_CLRBIT32(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) & ~(x)) 228 229 #define SIO_SET(x) \ 230 CSR_WRITE_1(sc, VR_MIICMD, \ 231 CSR_READ_1(sc, VR_MIICMD) | (x)) 232 233 #define SIO_CLR(x) \ 234 CSR_WRITE_1(sc, VR_MIICMD, \ 235 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 236 237 #ifdef VR_USESWSHIFT 238 /* 239 * Sync the PHYs by setting data bit and strobing the clock 32 times. 240 */ 241 static void 242 vr_mii_sync(struct vr_softc *sc) 243 { 244 int i; 245 246 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 247 248 for (i = 0; i < 32; i++) { 249 SIO_SET(VR_MIICMD_CLK); 250 DELAY(1); 251 SIO_CLR(VR_MIICMD_CLK); 252 DELAY(1); 253 } 254 } 255 256 /* 257 * Clock a series of bits through the MII. 258 */ 259 static void 260 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 261 { 262 int i; 263 264 SIO_CLR(VR_MIICMD_CLK); 265 266 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 267 if (bits & i) 268 SIO_SET(VR_MIICMD_DATAIN); 269 else 270 SIO_CLR(VR_MIICMD_DATAIN); 271 DELAY(1); 272 SIO_CLR(VR_MIICMD_CLK); 273 DELAY(1); 274 SIO_SET(VR_MIICMD_CLK); 275 } 276 } 277 #endif 278 279 /* 280 * Read an PHY register through the MII. 281 */ 282 static int 283 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 284 #ifdef VR_USESWSHIFT 285 { 286 int i, ack, s; 287 288 s = splimp(); 289 290 /* Set up frame for RX. */ 291 frame->mii_stdelim = VR_MII_STARTDELIM; 292 frame->mii_opcode = VR_MII_READOP; 293 frame->mii_turnaround = 0; 294 frame->mii_data = 0; 295 296 CSR_WRITE_1(sc, VR_MIICMD, 0); 297 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 298 299 /* Turn on data xmit. */ 300 SIO_SET(VR_MIICMD_DIR); 301 302 vr_mii_sync(sc); 303 304 /* Send command/address info. */ 305 vr_mii_send(sc, frame->mii_stdelim, 2); 306 vr_mii_send(sc, frame->mii_opcode, 2); 307 vr_mii_send(sc, frame->mii_phyaddr, 5); 308 vr_mii_send(sc, frame->mii_regaddr, 5); 309 310 /* Idle bit. */ 311 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 312 DELAY(1); 313 SIO_SET(VR_MIICMD_CLK); 314 DELAY(1); 315 316 /* Turn off xmit. */ 317 SIO_CLR(VR_MIICMD_DIR); 318 319 /* Check for ack */ 320 SIO_CLR(VR_MIICMD_CLK); 321 DELAY(1); 322 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 323 SIO_SET(VR_MIICMD_CLK); 324 DELAY(1); 325 326 /* 327 * Now try reading data bits. If the ack failed, we still 328 * need to clock through 16 cycles to keep the PHY(s) in sync. 329 */ 330 if (ack) { 331 for(i = 0; i < 16; i++) { 332 SIO_CLR(VR_MIICMD_CLK); 333 DELAY(1); 334 SIO_SET(VR_MIICMD_CLK); 335 DELAY(1); 336 } 337 goto fail; 338 } 339 340 for (i = 0x8000; i; i >>= 1) { 341 SIO_CLR(VR_MIICMD_CLK); 342 DELAY(1); 343 if (!ack) { 344 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 345 frame->mii_data |= i; 346 DELAY(1); 347 } 348 SIO_SET(VR_MIICMD_CLK); 349 DELAY(1); 350 } 351 352 fail: 353 SIO_CLR(VR_MIICMD_CLK); 354 DELAY(1); 355 SIO_SET(VR_MIICMD_CLK); 356 DELAY(1); 357 358 splx(s); 359 360 if (ack) 361 return(1); 362 return(0); 363 } 364 #else 365 { 366 int s, i; 367 368 s = splimp(); 369 370 /* Set the PHY address. */ 371 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 372 frame->mii_phyaddr); 373 374 /* Set the register address. */ 375 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 376 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 377 378 for (i = 0; i < 10000; i++) { 379 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 380 break; 381 DELAY(1); 382 } 383 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 384 385 splx(s); 386 387 return(0); 388 } 389 #endif 390 391 392 /* 393 * Write to a PHY register through the MII. 394 */ 395 static int 396 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 397 #ifdef VR_USESWSHIFT 398 { 399 int s; 400 401 s = splimp(); 402 403 CSR_WRITE_1(sc, VR_MIICMD, 0); 404 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 405 406 /* Set up frame for TX. */ 407 frame->mii_stdelim = VR_MII_STARTDELIM; 408 frame->mii_opcode = VR_MII_WRITEOP; 409 frame->mii_turnaround = VR_MII_TURNAROUND; 410 411 /* Turn on data output. */ 412 SIO_SET(VR_MIICMD_DIR); 413 414 vr_mii_sync(sc); 415 416 vr_mii_send(sc, frame->mii_stdelim, 2); 417 vr_mii_send(sc, frame->mii_opcode, 2); 418 vr_mii_send(sc, frame->mii_phyaddr, 5); 419 vr_mii_send(sc, frame->mii_regaddr, 5); 420 vr_mii_send(sc, frame->mii_turnaround, 2); 421 vr_mii_send(sc, frame->mii_data, 16); 422 423 /* Idle bit. */ 424 SIO_SET(VR_MIICMD_CLK); 425 DELAY(1); 426 SIO_CLR(VR_MIICMD_CLK); 427 DELAY(1); 428 429 /* Turn off xmit. */ 430 SIO_CLR(VR_MIICMD_DIR); 431 432 splx(s); 433 434 return(0); 435 } 436 #else 437 { 438 int s, i; 439 440 s = splimp(); 441 442 /* Set the PHY-adress */ 443 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 444 frame->mii_phyaddr); 445 446 /* Set the register address and data to write. */ 447 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 448 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 449 450 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 451 452 for (i = 0; i < 10000; i++) { 453 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 454 break; 455 DELAY(1); 456 } 457 458 splx(s); 459 460 return(0); 461 } 462 #endif 463 464 static int 465 vr_miibus_readreg(device_t dev, int phy, int reg) 466 { 467 struct vr_mii_frame frame; 468 struct vr_softc *sc; 469 470 sc = device_get_softc(dev); 471 472 switch (sc->vr_revid) { 473 case REV_ID_VT6102_APOLLO: 474 if (phy != 1) 475 return(0); 476 break; 477 default: 478 break; 479 } 480 481 bzero(&frame, sizeof(frame)); 482 483 frame.mii_phyaddr = phy; 484 frame.mii_regaddr = reg; 485 vr_mii_readreg(sc, &frame); 486 487 return(frame.mii_data); 488 } 489 490 static int 491 vr_miibus_writereg(device_t dev, int phy, int reg, int data) 492 { 493 struct vr_mii_frame frame; 494 struct vr_softc *sc; 495 496 sc = device_get_softc(dev); 497 498 switch (sc->vr_revid) { 499 case REV_ID_VT6102_APOLLO: 500 if (phy != 1) 501 return 0; 502 break; 503 default: 504 break; 505 } 506 507 bzero(&frame, sizeof(frame)); 508 509 frame.mii_phyaddr = phy; 510 frame.mii_regaddr = reg; 511 frame.mii_data = data; 512 513 vr_mii_writereg(sc, &frame); 514 515 return(0); 516 } 517 518 static void 519 vr_miibus_statchg(device_t dev) 520 { 521 struct mii_data *mii; 522 struct vr_softc *sc; 523 524 sc = device_get_softc(dev); 525 mii = device_get_softc(sc->vr_miibus); 526 vr_setcfg(sc, mii->mii_media_active); 527 } 528 529 /* 530 * Calculate CRC of a multicast group address, return the lower 6 bits. 531 */ 532 static uint8_t 533 vr_calchash(uint8_t *addr) 534 { 535 uint32_t crc, carry; 536 int i, j; 537 uint8_t c; 538 539 /* Compute CRC for the address value. */ 540 crc = 0xFFFFFFFF; /* initial value */ 541 542 for (i = 0; i < 6; i++) { 543 c = *(addr + i); 544 for (j = 0; j < 8; j++) { 545 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 546 crc <<= 1; 547 c >>= 1; 548 if (carry) 549 crc = (crc ^ 0x04c11db6) | carry; 550 } 551 } 552 553 /* return the filter bit position */ 554 return((crc >> 26) & 0x0000003F); 555 } 556 557 /* 558 * Program the 64-bit multicast hash filter. 559 */ 560 static void 561 vr_setmulti(struct vr_softc *sc) 562 { 563 struct ifnet *ifp; 564 int h = 0; 565 uint32_t hashes[2] = { 0, 0 }; 566 struct ifmultiaddr *ifma; 567 uint8_t rxfilt; 568 int mcnt = 0; 569 570 ifp = &sc->arpcom.ac_if; 571 572 rxfilt = CSR_READ_1(sc, VR_RXCFG); 573 574 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 575 rxfilt |= VR_RXCFG_RX_MULTI; 576 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 577 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 578 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 579 return; 580 } 581 582 /* First, zero out all the existing hash bits. */ 583 CSR_WRITE_4(sc, VR_MAR0, 0); 584 CSR_WRITE_4(sc, VR_MAR1, 0); 585 586 /* Now program new ones. */ 587 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 588 ifma = ifma->ifma_link.le_next) { 589 if (ifma->ifma_addr->sa_family != AF_LINK) 590 continue; 591 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 592 if (h < 32) 593 hashes[0] |= (1 << h); 594 else 595 hashes[1] |= (1 << (h - 32)); 596 mcnt++; 597 } 598 599 if (mcnt) 600 rxfilt |= VR_RXCFG_RX_MULTI; 601 else 602 rxfilt &= ~VR_RXCFG_RX_MULTI; 603 604 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 605 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 606 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 607 } 608 609 /* 610 * In order to fiddle with the 611 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 612 * first have to put the transmit and/or receive logic in the idle state. 613 */ 614 static void 615 vr_setcfg(struct vr_softc *sc, int media) 616 { 617 int restart = 0; 618 619 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 620 restart = 1; 621 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 622 } 623 624 if ((media & IFM_GMASK) == IFM_FDX) 625 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 626 else 627 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 628 629 if (restart) 630 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 631 } 632 633 static void 634 vr_reset(struct vr_softc *sc) 635 { 636 int i; 637 638 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 639 640 for (i = 0; i < VR_TIMEOUT; i++) { 641 DELAY(10); 642 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 643 break; 644 } 645 if (i == VR_TIMEOUT) { 646 struct ifnet *ifp = &sc->arpcom.ac_if; 647 648 if (sc->vr_revid < REV_ID_VT3065_A) { 649 if_printf(ifp, "reset never completed!\n"); 650 } else { 651 /* Use newer force reset command */ 652 if_printf(ifp, "Using force reset command.\n"); 653 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 654 } 655 } 656 657 /* Wait a little while for the chip to get its brains in order. */ 658 DELAY(1000); 659 } 660 661 /* 662 * Probe for a VIA Rhine chip. Check the PCI vendor and device 663 * IDs against our list and return a device name if we find a match. 664 */ 665 static int 666 vr_probe(device_t dev) 667 { 668 struct vr_type *t; 669 670 t = vr_devs; 671 672 while(t->vr_name != NULL) { 673 if ((pci_get_vendor(dev) == t->vr_vid) && 674 (pci_get_device(dev) == t->vr_did)) { 675 device_set_desc(dev, t->vr_name); 676 return(0); 677 } 678 t++; 679 } 680 681 return(ENXIO); 682 } 683 684 /* 685 * Attach the interface. Allocate softc structures, do ifmedia 686 * setup and ethernet/BPF attach. 687 */ 688 static int 689 vr_attach(device_t dev) 690 { 691 int i, s; 692 uint8_t eaddr[ETHER_ADDR_LEN]; 693 uint32_t command; 694 struct vr_softc *sc; 695 struct ifnet *ifp; 696 int unit, error = 0, rid; 697 698 s = splimp(); 699 700 sc = device_get_softc(dev); 701 unit = device_get_unit(dev); 702 callout_init(&sc->vr_stat_timer); 703 704 /* 705 * Handle power management nonsense. 706 */ 707 708 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 709 if (command == 0x01) { 710 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 711 if (command & VR_PSTATE_MASK) { 712 uint32_t iobase, membase, irq; 713 714 /* Save important PCI config data. */ 715 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 716 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 717 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 718 719 /* Reset the power state. */ 720 device_printf(dev, "chip is in D%d power mode " 721 "-- setting to D0\n", command & VR_PSTATE_MASK); 722 command &= 0xFFFFFFFC; 723 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 724 725 /* Restore PCI config data. */ 726 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 727 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 728 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 729 } 730 } 731 732 /* 733 * Map control/status registers. 734 */ 735 command = pci_read_config(dev, PCIR_COMMAND, 4); 736 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 737 pci_write_config(dev, PCIR_COMMAND, command, 4); 738 command = pci_read_config(dev, PCIR_COMMAND, 4); 739 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 740 741 #ifdef VR_USEIOSPACE 742 if (!(command & PCIM_CMD_PORTEN)) { 743 device_printf(dev, "failed to enable I/O ports!\n"); 744 free(sc, M_DEVBUF); 745 goto fail; 746 } 747 #else 748 if (!(command & PCIM_CMD_MEMEN)) { 749 device_printf(dev, "failed to enable memory mapping!\n"); 750 goto fail; 751 } 752 #endif 753 754 rid = VR_RID; 755 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 756 757 if (sc->vr_res == NULL) { 758 device_printf(dev, "couldn't map ports/memory\n"); 759 error = ENXIO; 760 goto fail; 761 } 762 763 sc->vr_btag = rman_get_bustag(sc->vr_res); 764 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 765 766 /* Allocate interrupt */ 767 rid = 0; 768 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 769 RF_SHAREABLE | RF_ACTIVE); 770 771 if (sc->vr_irq == NULL) { 772 device_printf(dev, "couldn't map interrupt\n"); 773 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 774 error = ENXIO; 775 goto fail; 776 } 777 778 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 779 vr_intr, sc, &sc->vr_intrhand); 780 781 if (error) { 782 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 783 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 784 device_printf(dev, "couldn't set up irq\n"); 785 goto fail; 786 } 787 788 /* 789 * Windows may put the chip in suspend mode when it 790 * shuts down. Be sure to kick it in the head to wake it 791 * up again. 792 */ 793 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 794 795 /* Reset the adapter. */ 796 vr_reset(sc); 797 798 /* 799 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 800 * initialization and disable AUTOPOLL. 801 */ 802 pci_write_config(dev, VR_PCI_MODE, 803 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 804 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 805 806 /* 807 * Get station address. The way the Rhine chips work, 808 * you're not allowed to directly access the EEPROM once 809 * they've been programmed a special way. Consequently, 810 * we need to read the node address from the PAR0 and PAR1 811 * registers. 812 */ 813 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 814 DELAY(200); 815 for (i = 0; i < ETHER_ADDR_LEN; i++) 816 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 817 818 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 819 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 820 821 if (sc->vr_ldata == NULL) { 822 device_printf(dev, "no memory for list buffers!\n"); 823 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 824 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 825 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 826 error = ENXIO; 827 goto fail; 828 } 829 830 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 831 832 ifp = &sc->arpcom.ac_if; 833 ifp->if_softc = sc; 834 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 835 ifp->if_mtu = ETHERMTU; 836 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 837 ifp->if_ioctl = vr_ioctl; 838 ifp->if_start = vr_start; 839 ifp->if_watchdog = vr_watchdog; 840 ifp->if_init = vr_init; 841 ifp->if_baudrate = 10000000; 842 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 843 844 /* 845 * Do MII setup. 846 */ 847 if (mii_phy_probe(dev, &sc->vr_miibus, 848 vr_ifmedia_upd, vr_ifmedia_sts)) { 849 if_printf(ifp, "MII without any phy!\n"); 850 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 851 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 852 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 853 contigfree(sc->vr_ldata, 854 sizeof(struct vr_list_data), M_DEVBUF); 855 error = ENXIO; 856 goto fail; 857 } 858 859 /* Call MI attach routine. */ 860 ether_ifattach(ifp, eaddr); 861 862 fail: 863 splx(s); 864 return(error); 865 } 866 867 static int 868 vr_detach(device_t dev) 869 { 870 struct vr_softc *sc; 871 struct ifnet *ifp; 872 int s; 873 874 s = splimp(); 875 876 sc = device_get_softc(dev); 877 ifp = &sc->arpcom.ac_if; 878 879 vr_stop(sc); 880 ether_ifdetach(ifp); 881 882 bus_generic_detach(dev); 883 device_delete_child(dev, sc->vr_miibus); 884 885 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 886 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 887 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 888 889 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 890 891 splx(s); 892 893 return(0); 894 } 895 896 /* 897 * Initialize the transmit descriptors. 898 */ 899 static int 900 vr_list_tx_init(struct vr_softc *sc) 901 { 902 struct vr_chain_data *cd; 903 struct vr_list_data *ld; 904 int i, nexti; 905 906 cd = &sc->vr_cdata; 907 ld = sc->vr_ldata; 908 for (i = 0; i < VR_TX_LIST_CNT; i++) { 909 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 910 if (i == (VR_TX_LIST_CNT - 1)) 911 nexti = 0; 912 else 913 nexti = i + 1; 914 cd->vr_tx_chain[i].vr_nextdesc = &cd->vr_tx_chain[nexti]; 915 } 916 917 cd->vr_tx_free = &cd->vr_tx_chain[0]; 918 cd->vr_tx_tail = cd->vr_tx_head = NULL; 919 920 return(0); 921 } 922 923 924 /* 925 * Initialize the RX descriptors and allocate mbufs for them. Note that 926 * we arrange the descriptors in a closed ring, so that the last descriptor 927 * points back to the first. 928 */ 929 static int 930 vr_list_rx_init(struct vr_softc *sc) 931 { 932 struct vr_chain_data *cd; 933 struct vr_list_data *ld; 934 int i, nexti; 935 936 cd = &sc->vr_cdata; 937 ld = sc->vr_ldata; 938 939 for (i = 0; i < VR_RX_LIST_CNT; i++) { 940 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i]; 941 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 942 return(ENOBUFS); 943 if (i == (VR_RX_LIST_CNT - 1)) 944 nexti = 0; 945 else 946 nexti = i + 1; 947 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti]; 948 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]); 949 } 950 951 cd->vr_rx_head = &cd->vr_rx_chain[0]; 952 953 return(0); 954 } 955 956 /* 957 * Initialize an RX descriptor and attach an MBUF cluster. 958 * Note: the length fields are only 11 bits wide, which means the 959 * largest size we can specify is 2047. This is important because 960 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 961 * overflow the field and make a mess. 962 */ 963 static int 964 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 965 { 966 struct mbuf *m_new = NULL; 967 968 if (m == NULL) { 969 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 970 if (m_new == NULL) 971 return(ENOBUFS); 972 973 MCLGET(m_new, MB_DONTWAIT); 974 if (!(m_new->m_flags & M_EXT)) { 975 m_freem(m_new); 976 return(ENOBUFS); 977 } 978 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 979 } else { 980 m_new = m; 981 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 982 m_new->m_data = m_new->m_ext.ext_buf; 983 } 984 985 m_adj(m_new, sizeof(uint64_t)); 986 987 c->vr_mbuf = m_new; 988 c->vr_ptr->vr_status = VR_RXSTAT; 989 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 990 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 991 992 return(0); 993 } 994 995 /* 996 * A frame has been uploaded: pass the resulting mbuf chain up to 997 * the higher level protocols. 998 */ 999 static void 1000 vr_rxeof(struct vr_softc *sc) 1001 { 1002 struct mbuf *m; 1003 struct ifnet *ifp; 1004 struct vr_chain_onefrag *cur_rx; 1005 int total_len = 0; 1006 uint32_t rxstat; 1007 1008 ifp = &sc->arpcom.ac_if; 1009 1010 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1011 VR_RXSTAT_OWN)) { 1012 struct mbuf *m0 = NULL; 1013 1014 cur_rx = sc->vr_cdata.vr_rx_head; 1015 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1016 m = cur_rx->vr_mbuf; 1017 1018 /* 1019 * If an error occurs, update stats, clear the 1020 * status word and leave the mbuf cluster in place: 1021 * it should simply get re-used next time this descriptor 1022 * comes up in the ring. 1023 */ 1024 if (rxstat & VR_RXSTAT_RXERR) { 1025 ifp->if_ierrors++; 1026 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff); 1027 if (rxstat & VR_RXSTAT_CRCERR) 1028 printf(" crc error"); 1029 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1030 printf(" frame alignment error\n"); 1031 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1032 printf(" FIFO overflow"); 1033 if (rxstat & VR_RXSTAT_GIANT) 1034 printf(" received giant packet"); 1035 if (rxstat & VR_RXSTAT_RUNT) 1036 printf(" received runt packet"); 1037 if (rxstat & VR_RXSTAT_BUSERR) 1038 printf(" system bus error"); 1039 if (rxstat & VR_RXSTAT_BUFFERR) 1040 printf("rx buffer error"); 1041 printf("\n"); 1042 vr_newbuf(sc, cur_rx, m); 1043 continue; 1044 } 1045 1046 /* No errors; receive the packet. */ 1047 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1048 1049 /* 1050 * XXX The VIA Rhine chip includes the CRC with every 1051 * received frame, and there's no way to turn this 1052 * behavior off (at least, I can't find anything in 1053 * the manual that explains how to do it) so we have 1054 * to trim off the CRC manually. 1055 */ 1056 total_len -= ETHER_CRC_LEN; 1057 1058 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1059 total_len + ETHER_ALIGN, 0, ifp, NULL); 1060 vr_newbuf(sc, cur_rx, m); 1061 if (m0 == NULL) { 1062 ifp->if_ierrors++; 1063 continue; 1064 } 1065 m_adj(m0, ETHER_ALIGN); 1066 m = m0; 1067 1068 ifp->if_ipackets++; 1069 (*ifp->if_input)(ifp, m); 1070 } 1071 } 1072 1073 static void 1074 vr_rxeoc(struct vr_softc *sc) 1075 { 1076 struct ifnet *ifp; 1077 int i; 1078 1079 ifp = &sc->arpcom.ac_if; 1080 1081 ifp->if_ierrors++; 1082 1083 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1084 DELAY(10000); 1085 1086 /* Wait for receiver to stop */ 1087 for (i = 0x400; 1088 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1089 i--) 1090 ; /* Wait for receiver to stop */ 1091 1092 if (i == 0) { 1093 if_printf(ifp, "rx shutdown error!\n"); 1094 sc->vr_flags |= VR_F_RESTART; 1095 return; 1096 } 1097 1098 vr_rxeof(sc); 1099 1100 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1101 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1102 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1103 } 1104 1105 /* 1106 * A frame was downloaded to the chip. It's safe for us to clean up 1107 * the list buffers. 1108 */ 1109 static void 1110 vr_txeof(struct vr_softc *sc) 1111 { 1112 struct vr_chain *cur_tx; 1113 struct ifnet *ifp; 1114 1115 ifp = &sc->arpcom.ac_if; 1116 1117 /* Reset the timeout timer; if_txeoc will clear it. */ 1118 ifp->if_timer = 5; 1119 1120 /* Sanity check. */ 1121 if (sc->vr_cdata.vr_tx_head == NULL) 1122 return; 1123 1124 /* 1125 * Go through our tx list and free mbufs for those 1126 * frames that have been transmitted. 1127 */ 1128 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1129 uint32_t txstat; 1130 int i; 1131 1132 cur_tx = sc->vr_cdata.vr_tx_head; 1133 txstat = cur_tx->vr_ptr->vr_status; 1134 1135 if ((txstat & VR_TXSTAT_ABRT) || 1136 (txstat & VR_TXSTAT_UDF)) { 1137 for (i = 0x400; 1138 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1139 i--) 1140 ; /* Wait for chip to shutdown */ 1141 if (i == 0) { 1142 if_printf(ifp, "tx shutdown timeout\n"); 1143 sc->vr_flags |= VR_F_RESTART; 1144 break; 1145 } 1146 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1147 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1148 break; 1149 } 1150 1151 if (txstat & VR_TXSTAT_OWN) 1152 break; 1153 1154 if (txstat & VR_TXSTAT_ERRSUM) { 1155 ifp->if_oerrors++; 1156 if (txstat & VR_TXSTAT_DEFER) 1157 ifp->if_collisions++; 1158 if (txstat & VR_TXSTAT_LATECOLL) 1159 ifp->if_collisions++; 1160 } 1161 1162 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1163 1164 ifp->if_opackets++; 1165 if (cur_tx->vr_mbuf != NULL) { 1166 m_freem(cur_tx->vr_mbuf); 1167 cur_tx->vr_mbuf = NULL; 1168 } 1169 1170 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1171 sc->vr_cdata.vr_tx_head = NULL; 1172 sc->vr_cdata.vr_tx_tail = NULL; 1173 break; 1174 } 1175 1176 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1177 } 1178 } 1179 1180 /* 1181 * TX 'end of channel' interrupt handler. 1182 */ 1183 static void 1184 vr_txeoc(struct vr_softc *sc) 1185 { 1186 struct ifnet *ifp; 1187 1188 ifp = &sc->arpcom.ac_if; 1189 1190 if (sc->vr_cdata.vr_tx_head == NULL) { 1191 ifp->if_flags &= ~IFF_OACTIVE; 1192 sc->vr_cdata.vr_tx_tail = NULL; 1193 ifp->if_timer = 0; 1194 } 1195 } 1196 1197 static void 1198 vr_tick(void *xsc) 1199 { 1200 struct vr_softc *sc; 1201 struct mii_data *mii; 1202 int s; 1203 1204 s = splimp(); 1205 1206 sc = xsc; 1207 if (sc->vr_flags & VR_F_RESTART) { 1208 if_printf(&sc->arpcom.ac_if, "restarting\n"); 1209 vr_stop(sc); 1210 vr_reset(sc); 1211 vr_init(sc); 1212 sc->vr_flags &= ~VR_F_RESTART; 1213 } 1214 1215 mii = device_get_softc(sc->vr_miibus); 1216 mii_tick(mii); 1217 1218 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1219 1220 splx(s); 1221 } 1222 1223 static void 1224 vr_intr(void *arg) 1225 { 1226 struct vr_softc *sc; 1227 struct ifnet *ifp; 1228 uint16_t status; 1229 1230 sc = arg; 1231 ifp = &sc->arpcom.ac_if; 1232 1233 /* Supress unwanted interrupts. */ 1234 if (!(ifp->if_flags & IFF_UP)) { 1235 vr_stop(sc); 1236 return; 1237 } 1238 1239 /* Disable interrupts. */ 1240 if ((ifp->if_flags & IFF_POLLING) == 0) 1241 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1242 1243 for (;;) { 1244 status = CSR_READ_2(sc, VR_ISR); 1245 if (status) 1246 CSR_WRITE_2(sc, VR_ISR, status); 1247 1248 if ((status & VR_INTRS) == 0) 1249 break; 1250 1251 if (status & VR_ISR_RX_OK) 1252 vr_rxeof(sc); 1253 1254 if (status & VR_ISR_RX_DROPPED) { 1255 if_printf(ifp, "rx packet lost\n"); 1256 ifp->if_ierrors++; 1257 } 1258 1259 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1260 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1261 if_printf(ifp, "receive error (%04x)", status); 1262 if (status & VR_ISR_RX_NOBUF) 1263 printf(" no buffers"); 1264 if (status & VR_ISR_RX_OFLOW) 1265 printf(" overflow"); 1266 if (status & VR_ISR_RX_DROPPED) 1267 printf(" packet lost"); 1268 printf("\n"); 1269 vr_rxeoc(sc); 1270 } 1271 1272 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1273 vr_reset(sc); 1274 vr_init(sc); 1275 break; 1276 } 1277 1278 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1279 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1280 vr_txeof(sc); 1281 if ((status & VR_ISR_UDFI) || 1282 (status & VR_ISR_TX_ABRT2) || 1283 (status & VR_ISR_TX_ABRT)) { 1284 ifp->if_oerrors++; 1285 if (sc->vr_cdata.vr_tx_head != NULL) { 1286 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1287 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1288 } 1289 } else { 1290 vr_txeoc(sc); 1291 } 1292 } 1293 1294 } 1295 1296 /* Re-enable interrupts. */ 1297 if ((ifp->if_flags & IFF_POLLING) == 0) 1298 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1299 1300 if (ifp->if_snd.ifq_head != NULL) 1301 vr_start(ifp); 1302 } 1303 1304 /* 1305 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1306 * pointers to the fragment pointers. 1307 */ 1308 static int 1309 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1310 { 1311 int frag = 0; 1312 struct vr_desc *f = NULL; 1313 int total_len; 1314 struct mbuf *m; 1315 1316 m = m_head; 1317 total_len = 0; 1318 1319 /* 1320 * The VIA Rhine wants packet buffers to be longword 1321 * aligned, but very often our mbufs aren't. Rather than 1322 * waste time trying to decide when to copy and when not 1323 * to copy, just do it all the time. 1324 */ 1325 if (m != NULL) { 1326 struct mbuf *m_new = NULL; 1327 1328 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1329 if (m_new == NULL) { 1330 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n"); 1331 return(1); 1332 } 1333 if (m_head->m_pkthdr.len > MHLEN) { 1334 MCLGET(m_new, MB_DONTWAIT); 1335 if (!(m_new->m_flags & M_EXT)) { 1336 m_freem(m_new); 1337 if_printf(&sc->arpcom.ac_if, 1338 "no memory for tx list\n"); 1339 return(1); 1340 } 1341 } 1342 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1343 mtod(m_new, caddr_t)); 1344 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1345 m_freem(m_head); 1346 m_head = m_new; 1347 /* 1348 * The Rhine chip doesn't auto-pad, so we have to make 1349 * sure to pad short frames out to the minimum frame length 1350 * ourselves. 1351 */ 1352 if (m_head->m_len < VR_MIN_FRAMELEN) { 1353 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1354 m_new->m_len = m_new->m_pkthdr.len; 1355 } 1356 f = c->vr_ptr; 1357 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1358 f->vr_ctl = total_len = m_new->m_len; 1359 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1360 f->vr_status = 0; 1361 frag = 1; 1362 } 1363 1364 c->vr_mbuf = m_head; 1365 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1366 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1367 1368 return(0); 1369 } 1370 1371 /* 1372 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1373 * to the mbuf data regions directly in the transmit lists. We also save a 1374 * copy of the pointers since the transmit list fragment pointers are 1375 * physical addresses. 1376 */ 1377 static void 1378 vr_start(struct ifnet *ifp) 1379 { 1380 struct vr_softc *sc; 1381 struct mbuf *m_head = NULL; 1382 struct vr_chain *cur_tx = NULL, *start_tx; 1383 1384 sc = ifp->if_softc; 1385 1386 if (ifp->if_flags & IFF_OACTIVE) 1387 return; 1388 1389 /* Check for an available queue slot. If there are none, punt. */ 1390 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1391 ifp->if_flags |= IFF_OACTIVE; 1392 return; 1393 } 1394 1395 start_tx = sc->vr_cdata.vr_tx_free; 1396 1397 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1398 IF_DEQUEUE(&ifp->if_snd, m_head); 1399 if (m_head == NULL) 1400 break; 1401 1402 /* Pick a descriptor off the free list. */ 1403 cur_tx = sc->vr_cdata.vr_tx_free; 1404 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1405 1406 /* Pack the data into the descriptor. */ 1407 if (vr_encap(sc, cur_tx, m_head)) { 1408 IF_PREPEND(&ifp->if_snd, m_head); 1409 ifp->if_flags |= IFF_OACTIVE; 1410 cur_tx = NULL; 1411 break; 1412 } 1413 1414 if (cur_tx != start_tx) 1415 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1416 1417 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1418 1419 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1420 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1421 } 1422 1423 /* If there are no frames queued, bail. */ 1424 if (cur_tx == NULL) 1425 return; 1426 1427 sc->vr_cdata.vr_tx_tail = cur_tx; 1428 1429 if (sc->vr_cdata.vr_tx_head == NULL) 1430 sc->vr_cdata.vr_tx_head = start_tx; 1431 1432 /* 1433 * Set a timeout in case the chip goes out to lunch. 1434 */ 1435 ifp->if_timer = 5; 1436 } 1437 1438 static void 1439 vr_init(void *xsc) 1440 { 1441 struct vr_softc *sc = xsc; 1442 struct ifnet *ifp = &sc->arpcom.ac_if; 1443 struct mii_data *mii; 1444 int s, i; 1445 1446 s = splimp(); 1447 1448 mii = device_get_softc(sc->vr_miibus); 1449 1450 /* Cancel pending I/O and free all RX/TX buffers. */ 1451 vr_stop(sc); 1452 vr_reset(sc); 1453 1454 /* Set our station address. */ 1455 for (i = 0; i < ETHER_ADDR_LEN; i++) 1456 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1457 1458 /* Set DMA size. */ 1459 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1460 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1461 1462 /* 1463 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1464 * so we must set both. 1465 */ 1466 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1467 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1468 1469 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1470 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1471 1472 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1473 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1474 1475 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1476 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1477 1478 /* Init circular RX list. */ 1479 if (vr_list_rx_init(sc) == ENOBUFS) { 1480 if_printf(ifp, "initialization failed: no memory for rx buffers\n"); 1481 vr_stop(sc); 1482 splx(s); 1483 return; 1484 } 1485 1486 /* Init tx descriptors. */ 1487 vr_list_tx_init(sc); 1488 1489 /* If we want promiscuous mode, set the allframes bit. */ 1490 if (ifp->if_flags & IFF_PROMISC) 1491 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1492 else 1493 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1494 1495 /* Set capture broadcast bit to capture broadcast frames. */ 1496 if (ifp->if_flags & IFF_BROADCAST) 1497 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1498 else 1499 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1500 1501 /* 1502 * Program the multicast filter, if necessary. 1503 */ 1504 vr_setmulti(sc); 1505 1506 /* 1507 * Load the address of the RX list. 1508 */ 1509 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1510 1511 /* Enable receiver and transmitter. */ 1512 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1513 VR_CMD_TX_ON|VR_CMD_RX_ON| 1514 VR_CMD_RX_GO); 1515 1516 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1517 1518 /* 1519 * Enable interrupts, unless we are polling. 1520 */ 1521 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1522 if ((ifp->if_flags & IFF_POLLING) == 0) 1523 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1524 1525 mii_mediachg(mii); 1526 1527 ifp->if_flags |= IFF_RUNNING; 1528 ifp->if_flags &= ~IFF_OACTIVE; 1529 1530 splx(s); 1531 1532 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1533 } 1534 1535 /* 1536 * Set media options. 1537 */ 1538 static int 1539 vr_ifmedia_upd(struct ifnet *ifp) 1540 { 1541 struct vr_softc *sc; 1542 1543 sc = ifp->if_softc; 1544 1545 if (ifp->if_flags & IFF_UP) 1546 vr_init(sc); 1547 1548 return(0); 1549 } 1550 1551 /* 1552 * Report current media status. 1553 */ 1554 static void 1555 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1556 { 1557 struct vr_softc *sc; 1558 struct mii_data *mii; 1559 1560 sc = ifp->if_softc; 1561 mii = device_get_softc(sc->vr_miibus); 1562 mii_pollstat(mii); 1563 ifmr->ifm_active = mii->mii_media_active; 1564 ifmr->ifm_status = mii->mii_media_status; 1565 } 1566 1567 static int 1568 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1569 { 1570 struct vr_softc *sc = ifp->if_softc; 1571 struct ifreq *ifr = (struct ifreq *) data; 1572 struct mii_data *mii; 1573 int s, error = 0; 1574 1575 s = splimp(); 1576 1577 switch(command) { 1578 case SIOCSIFADDR: 1579 case SIOCGIFADDR: 1580 case SIOCSIFMTU: 1581 error = ether_ioctl(ifp, command, data); 1582 break; 1583 case SIOCSIFFLAGS: 1584 if (ifp->if_flags & IFF_UP) { 1585 vr_init(sc); 1586 } else { 1587 if (ifp->if_flags & IFF_RUNNING) 1588 vr_stop(sc); 1589 } 1590 error = 0; 1591 break; 1592 case SIOCADDMULTI: 1593 case SIOCDELMULTI: 1594 vr_setmulti(sc); 1595 error = 0; 1596 break; 1597 case SIOCGIFMEDIA: 1598 case SIOCSIFMEDIA: 1599 mii = device_get_softc(sc->vr_miibus); 1600 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1601 break; 1602 default: 1603 error = EINVAL; 1604 break; 1605 } 1606 1607 splx(s); 1608 1609 return(error); 1610 } 1611 1612 #ifdef DEVICE_POLLING 1613 static void 1614 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1615 { 1616 struct vr_softc *sc = ifp->if_softc; 1617 1618 if (cmd == POLL_DEREGISTER) 1619 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1620 else 1621 vr_intr(sc); 1622 } 1623 #endif 1624 1625 static void 1626 vr_watchdog(struct ifnet *ifp) 1627 { 1628 struct vr_softc *sc; 1629 1630 sc = ifp->if_softc; 1631 1632 ifp->if_oerrors++; 1633 if_printf(ifp, "watchdog timeout\n"); 1634 1635 #ifdef DEVICE_POLLING 1636 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) { 1637 if_printf(ifp, "ints don't seem to be working, " 1638 "emergency switch to polling\n"); 1639 emergency_poll_enable("if_vr"); 1640 if (ether_poll_register(vr_poll, ifp)) 1641 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1642 } else 1643 #endif 1644 { 1645 vr_stop(sc); 1646 vr_reset(sc); 1647 vr_init(sc); 1648 } 1649 1650 if (ifp->if_snd.ifq_head != NULL) 1651 vr_start(ifp); 1652 } 1653 1654 /* 1655 * Stop the adapter and free any mbufs allocated to the 1656 * RX and TX lists. 1657 */ 1658 static void 1659 vr_stop(struct vr_softc *sc) 1660 { 1661 int i; 1662 struct ifnet *ifp; 1663 1664 ifp = &sc->arpcom.ac_if; 1665 ifp->if_timer = 0; 1666 1667 callout_stop(&sc->vr_stat_timer); 1668 1669 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1670 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1671 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1672 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1673 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1674 1675 /* 1676 * Free data in the RX lists. 1677 */ 1678 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1679 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1680 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1681 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1682 } 1683 } 1684 bzero((char *)&sc->vr_ldata->vr_rx_list, 1685 sizeof(sc->vr_ldata->vr_rx_list)); 1686 1687 /* 1688 * Free the TX list buffers. 1689 */ 1690 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1691 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1692 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1693 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1694 } 1695 } 1696 1697 bzero((char *)&sc->vr_ldata->vr_tx_list, 1698 sizeof(sc->vr_ldata->vr_tx_list)); 1699 1700 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1701 } 1702 1703 /* 1704 * Stop all chip I/O so that the kernel's probe routines don't 1705 * get confused by errant DMAs when rebooting. 1706 */ 1707 static void 1708 vr_shutdown(device_t dev) 1709 { 1710 struct vr_softc *sc; 1711 1712 sc = device_get_softc(dev); 1713 1714 vr_stop(sc); 1715 } 1716