1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.26 2005/06/10 15:13:37 joerg Exp $ 34 */ 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/thread2.h> 71 72 #include <net/if.h> 73 #include <net/ifq_var.h> 74 #include <net/if_arp.h> 75 #include <net/ethernet.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 79 #include <net/bpf.h> 80 81 #include <vm/vm.h> /* for vtophys */ 82 #include <vm/pmap.h> /* for vtophys */ 83 #include <machine/bus_pio.h> 84 #include <machine/bus_memio.h> 85 #include <machine/bus.h> 86 #include <machine/resource.h> 87 #include <sys/bus.h> 88 #include <sys/rman.h> 89 90 #include <dev/netif/mii_layer/mii.h> 91 #include <dev/netif/mii_layer/miivar.h> 92 93 #include <bus/pci/pcireg.h> 94 #include <bus/pci/pcivar.h> 95 96 #define VR_USEIOSPACE 97 98 #include <dev/netif/vr/if_vrreg.h> 99 100 /* "controller miibus0" required. See GENERIC if you get errors here. */ 101 #include "miibus_if.h" 102 103 #undef VR_USESWSHIFT 104 105 /* 106 * Various supported device vendors/types and their names. 107 */ 108 static struct vr_type vr_devs[] = { 109 { VIA_VENDORID, VIA_DEVICEID_RHINE, 110 "VIA VT3043 Rhine I 10/100BaseTX" }, 111 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 112 "VIA VT86C100A Rhine II 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 114 "VIA VT6102 Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 116 "VIA VT6105 Rhine III 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 118 "VIA VT6105M Rhine III 10/100BaseTX" }, 119 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 120 "Delta Electronics Rhine II 10/100BaseTX" }, 121 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 122 "Addtron Technology Rhine II 10/100BaseTX" }, 123 { 0, 0, NULL } 124 }; 125 126 static int vr_probe(device_t); 127 static int vr_attach(device_t); 128 static int vr_detach(device_t); 129 130 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 131 struct mbuf *); 132 static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * ); 133 134 static void vr_rxeof(struct vr_softc *); 135 static void vr_rxeoc(struct vr_softc *); 136 static void vr_txeof(struct vr_softc *); 137 static void vr_txeoc(struct vr_softc *); 138 static void vr_tick(void *); 139 static void vr_intr(void *); 140 static void vr_start(struct ifnet *); 141 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 142 static void vr_init(void *); 143 static void vr_stop(struct vr_softc *); 144 static void vr_watchdog(struct ifnet *); 145 static void vr_shutdown(device_t); 146 static int vr_ifmedia_upd(struct ifnet *); 147 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148 149 #ifdef VR_USESWSHIFT 150 static void vr_mii_sync(struct vr_softc *); 151 static void vr_mii_send(struct vr_softc *, uint32_t, int); 152 #endif 153 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 154 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 155 static int vr_miibus_readreg(device_t, int, int); 156 static int vr_miibus_writereg(device_t, int, int, int); 157 static void vr_miibus_statchg(device_t); 158 159 static void vr_setcfg(struct vr_softc *, int); 160 static uint8_t vr_calchash(uint8_t *); 161 static void vr_setmulti(struct vr_softc *); 162 static void vr_reset(struct vr_softc *); 163 static int vr_list_rx_init(struct vr_softc *); 164 static int vr_list_tx_init(struct vr_softc *); 165 #ifdef DEVICE_POLLING 166 static void vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 167 #endif 168 169 #ifdef VR_USEIOSPACE 170 #define VR_RES SYS_RES_IOPORT 171 #define VR_RID VR_PCI_LOIO 172 #else 173 #define VR_RES SYS_RES_MEMORY 174 #define VR_RID VR_PCI_LOMEM 175 #endif 176 177 static device_method_t vr_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, vr_probe), 180 DEVMETHOD(device_attach, vr_attach), 181 DEVMETHOD(device_detach, vr_detach), 182 DEVMETHOD(device_shutdown, vr_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 190 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 191 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 192 193 { 0, 0 } 194 }; 195 196 static driver_t vr_driver = { 197 "vr", 198 vr_methods, 199 sizeof(struct vr_softc) 200 }; 201 202 static devclass_t vr_devclass; 203 204 DECLARE_DUMMY_MODULE(if_vr); 205 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 206 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 207 208 #define VR_SETBIT(sc, reg, x) \ 209 CSR_WRITE_1(sc, reg, \ 210 CSR_READ_1(sc, reg) | (x)) 211 212 #define VR_CLRBIT(sc, reg, x) \ 213 CSR_WRITE_1(sc, reg, \ 214 CSR_READ_1(sc, reg) & ~(x)) 215 216 #define VR_SETBIT16(sc, reg, x) \ 217 CSR_WRITE_2(sc, reg, \ 218 CSR_READ_2(sc, reg) | (x)) 219 220 #define VR_CLRBIT16(sc, reg, x) \ 221 CSR_WRITE_2(sc, reg, \ 222 CSR_READ_2(sc, reg) & ~(x)) 223 224 #define VR_SETBIT32(sc, reg, x) \ 225 CSR_WRITE_4(sc, reg, \ 226 CSR_READ_4(sc, reg) | (x)) 227 228 #define VR_CLRBIT32(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, \ 230 CSR_READ_4(sc, reg) & ~(x)) 231 232 #define SIO_SET(x) \ 233 CSR_WRITE_1(sc, VR_MIICMD, \ 234 CSR_READ_1(sc, VR_MIICMD) | (x)) 235 236 #define SIO_CLR(x) \ 237 CSR_WRITE_1(sc, VR_MIICMD, \ 238 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 239 240 #ifdef VR_USESWSHIFT 241 /* 242 * Sync the PHYs by setting data bit and strobing the clock 32 times. 243 */ 244 static void 245 vr_mii_sync(struct vr_softc *sc) 246 { 247 int i; 248 249 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 250 251 for (i = 0; i < 32; i++) { 252 SIO_SET(VR_MIICMD_CLK); 253 DELAY(1); 254 SIO_CLR(VR_MIICMD_CLK); 255 DELAY(1); 256 } 257 } 258 259 /* 260 * Clock a series of bits through the MII. 261 */ 262 static void 263 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 264 { 265 int i; 266 267 SIO_CLR(VR_MIICMD_CLK); 268 269 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 270 if (bits & i) 271 SIO_SET(VR_MIICMD_DATAIN); 272 else 273 SIO_CLR(VR_MIICMD_DATAIN); 274 DELAY(1); 275 SIO_CLR(VR_MIICMD_CLK); 276 DELAY(1); 277 SIO_SET(VR_MIICMD_CLK); 278 } 279 } 280 #endif 281 282 /* 283 * Read an PHY register through the MII. 284 */ 285 static int 286 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 287 #ifdef VR_USESWSHIFT 288 { 289 int i, ack; 290 291 crit_enter(); 292 293 /* Set up frame for RX. */ 294 frame->mii_stdelim = VR_MII_STARTDELIM; 295 frame->mii_opcode = VR_MII_READOP; 296 frame->mii_turnaround = 0; 297 frame->mii_data = 0; 298 299 CSR_WRITE_1(sc, VR_MIICMD, 0); 300 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 301 302 /* Turn on data xmit. */ 303 SIO_SET(VR_MIICMD_DIR); 304 305 vr_mii_sync(sc); 306 307 /* Send command/address info. */ 308 vr_mii_send(sc, frame->mii_stdelim, 2); 309 vr_mii_send(sc, frame->mii_opcode, 2); 310 vr_mii_send(sc, frame->mii_phyaddr, 5); 311 vr_mii_send(sc, frame->mii_regaddr, 5); 312 313 /* Idle bit. */ 314 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 315 DELAY(1); 316 SIO_SET(VR_MIICMD_CLK); 317 DELAY(1); 318 319 /* Turn off xmit. */ 320 SIO_CLR(VR_MIICMD_DIR); 321 322 /* Check for ack */ 323 SIO_CLR(VR_MIICMD_CLK); 324 DELAY(1); 325 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 326 SIO_SET(VR_MIICMD_CLK); 327 DELAY(1); 328 329 /* 330 * Now try reading data bits. If the ack failed, we still 331 * need to clock through 16 cycles to keep the PHY(s) in sync. 332 */ 333 if (ack) { 334 for(i = 0; i < 16; i++) { 335 SIO_CLR(VR_MIICMD_CLK); 336 DELAY(1); 337 SIO_SET(VR_MIICMD_CLK); 338 DELAY(1); 339 } 340 goto fail; 341 } 342 343 for (i = 0x8000; i; i >>= 1) { 344 SIO_CLR(VR_MIICMD_CLK); 345 DELAY(1); 346 if (!ack) { 347 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 348 frame->mii_data |= i; 349 DELAY(1); 350 } 351 SIO_SET(VR_MIICMD_CLK); 352 DELAY(1); 353 } 354 355 fail: 356 SIO_CLR(VR_MIICMD_CLK); 357 DELAY(1); 358 SIO_SET(VR_MIICMD_CLK); 359 DELAY(1); 360 361 crit_exit(); 362 363 if (ack) 364 return(1); 365 return(0); 366 } 367 #else 368 { 369 int i; 370 371 crit_enter(); 372 373 /* Set the PHY address. */ 374 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 375 frame->mii_phyaddr); 376 377 /* Set the register address. */ 378 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 379 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 380 381 for (i = 0; i < 10000; i++) { 382 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 383 break; 384 DELAY(1); 385 } 386 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 387 388 crit_exit(); 389 390 return(0); 391 } 392 #endif 393 394 395 /* 396 * Write to a PHY register through the MII. 397 */ 398 static int 399 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 400 #ifdef VR_USESWSHIFT 401 { 402 403 crit_enter(); 404 405 CSR_WRITE_1(sc, VR_MIICMD, 0); 406 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 407 408 /* Set up frame for TX. */ 409 frame->mii_stdelim = VR_MII_STARTDELIM; 410 frame->mii_opcode = VR_MII_WRITEOP; 411 frame->mii_turnaround = VR_MII_TURNAROUND; 412 413 /* Turn on data output. */ 414 SIO_SET(VR_MIICMD_DIR); 415 416 vr_mii_sync(sc); 417 418 vr_mii_send(sc, frame->mii_stdelim, 2); 419 vr_mii_send(sc, frame->mii_opcode, 2); 420 vr_mii_send(sc, frame->mii_phyaddr, 5); 421 vr_mii_send(sc, frame->mii_regaddr, 5); 422 vr_mii_send(sc, frame->mii_turnaround, 2); 423 vr_mii_send(sc, frame->mii_data, 16); 424 425 /* Idle bit. */ 426 SIO_SET(VR_MIICMD_CLK); 427 DELAY(1); 428 SIO_CLR(VR_MIICMD_CLK); 429 DELAY(1); 430 431 /* Turn off xmit. */ 432 SIO_CLR(VR_MIICMD_DIR); 433 434 crit_exit(); 435 436 return(0); 437 } 438 #else 439 { 440 int i; 441 442 crit_enter(); 443 444 /* Set the PHY-adress */ 445 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 446 frame->mii_phyaddr); 447 448 /* Set the register address and data to write. */ 449 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 450 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 451 452 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 453 454 for (i = 0; i < 10000; i++) { 455 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 456 break; 457 DELAY(1); 458 } 459 460 crit_exit(); 461 462 return(0); 463 } 464 #endif 465 466 static int 467 vr_miibus_readreg(device_t dev, int phy, int reg) 468 { 469 struct vr_mii_frame frame; 470 struct vr_softc *sc; 471 472 sc = device_get_softc(dev); 473 474 switch (sc->vr_revid) { 475 case REV_ID_VT6102_APOLLO: 476 if (phy != 1) 477 return(0); 478 break; 479 default: 480 break; 481 } 482 483 bzero(&frame, sizeof(frame)); 484 485 frame.mii_phyaddr = phy; 486 frame.mii_regaddr = reg; 487 vr_mii_readreg(sc, &frame); 488 489 return(frame.mii_data); 490 } 491 492 static int 493 vr_miibus_writereg(device_t dev, int phy, int reg, int data) 494 { 495 struct vr_mii_frame frame; 496 struct vr_softc *sc; 497 498 sc = device_get_softc(dev); 499 500 switch (sc->vr_revid) { 501 case REV_ID_VT6102_APOLLO: 502 if (phy != 1) 503 return 0; 504 break; 505 default: 506 break; 507 } 508 509 bzero(&frame, sizeof(frame)); 510 511 frame.mii_phyaddr = phy; 512 frame.mii_regaddr = reg; 513 frame.mii_data = data; 514 515 vr_mii_writereg(sc, &frame); 516 517 return(0); 518 } 519 520 static void 521 vr_miibus_statchg(device_t dev) 522 { 523 struct mii_data *mii; 524 struct vr_softc *sc; 525 526 sc = device_get_softc(dev); 527 mii = device_get_softc(sc->vr_miibus); 528 vr_setcfg(sc, mii->mii_media_active); 529 } 530 531 /* 532 * Calculate CRC of a multicast group address, return the lower 6 bits. 533 */ 534 static uint8_t 535 vr_calchash(uint8_t *addr) 536 { 537 uint32_t crc, carry; 538 int i, j; 539 uint8_t c; 540 541 /* Compute CRC for the address value. */ 542 crc = 0xFFFFFFFF; /* initial value */ 543 544 for (i = 0; i < 6; i++) { 545 c = *(addr + i); 546 for (j = 0; j < 8; j++) { 547 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 548 crc <<= 1; 549 c >>= 1; 550 if (carry) 551 crc = (crc ^ 0x04c11db6) | carry; 552 } 553 } 554 555 /* return the filter bit position */ 556 return((crc >> 26) & 0x0000003F); 557 } 558 559 /* 560 * Program the 64-bit multicast hash filter. 561 */ 562 static void 563 vr_setmulti(struct vr_softc *sc) 564 { 565 struct ifnet *ifp; 566 int h = 0; 567 uint32_t hashes[2] = { 0, 0 }; 568 struct ifmultiaddr *ifma; 569 uint8_t rxfilt; 570 int mcnt = 0; 571 572 ifp = &sc->arpcom.ac_if; 573 574 rxfilt = CSR_READ_1(sc, VR_RXCFG); 575 576 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 577 rxfilt |= VR_RXCFG_RX_MULTI; 578 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 579 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 580 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 581 return; 582 } 583 584 /* First, zero out all the existing hash bits. */ 585 CSR_WRITE_4(sc, VR_MAR0, 0); 586 CSR_WRITE_4(sc, VR_MAR1, 0); 587 588 /* Now program new ones. */ 589 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 590 ifma = ifma->ifma_link.le_next) { 591 if (ifma->ifma_addr->sa_family != AF_LINK) 592 continue; 593 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 594 if (h < 32) 595 hashes[0] |= (1 << h); 596 else 597 hashes[1] |= (1 << (h - 32)); 598 mcnt++; 599 } 600 601 if (mcnt) 602 rxfilt |= VR_RXCFG_RX_MULTI; 603 else 604 rxfilt &= ~VR_RXCFG_RX_MULTI; 605 606 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 607 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 608 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 609 } 610 611 /* 612 * In order to fiddle with the 613 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 614 * first have to put the transmit and/or receive logic in the idle state. 615 */ 616 static void 617 vr_setcfg(struct vr_softc *sc, int media) 618 { 619 int restart = 0; 620 621 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 622 restart = 1; 623 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 624 } 625 626 if ((media & IFM_GMASK) == IFM_FDX) 627 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 628 else 629 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 630 631 if (restart) 632 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 633 } 634 635 static void 636 vr_reset(struct vr_softc *sc) 637 { 638 int i; 639 640 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 641 642 for (i = 0; i < VR_TIMEOUT; i++) { 643 DELAY(10); 644 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 645 break; 646 } 647 if (i == VR_TIMEOUT) { 648 struct ifnet *ifp = &sc->arpcom.ac_if; 649 650 if (sc->vr_revid < REV_ID_VT3065_A) { 651 if_printf(ifp, "reset never completed!\n"); 652 } else { 653 /* Use newer force reset command */ 654 if_printf(ifp, "Using force reset command.\n"); 655 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 656 } 657 } 658 659 /* Wait a little while for the chip to get its brains in order. */ 660 DELAY(1000); 661 } 662 663 /* 664 * Probe for a VIA Rhine chip. Check the PCI vendor and device 665 * IDs against our list and return a device name if we find a match. 666 */ 667 static int 668 vr_probe(device_t dev) 669 { 670 struct vr_type *t; 671 672 t = vr_devs; 673 674 while(t->vr_name != NULL) { 675 if ((pci_get_vendor(dev) == t->vr_vid) && 676 (pci_get_device(dev) == t->vr_did)) { 677 device_set_desc(dev, t->vr_name); 678 return(0); 679 } 680 t++; 681 } 682 683 return(ENXIO); 684 } 685 686 /* 687 * Attach the interface. Allocate softc structures, do ifmedia 688 * setup and ethernet/BPF attach. 689 */ 690 static int 691 vr_attach(device_t dev) 692 { 693 int i; 694 uint8_t eaddr[ETHER_ADDR_LEN]; 695 uint32_t command; 696 struct vr_softc *sc; 697 struct ifnet *ifp; 698 int error = 0, rid; 699 700 crit_enter(); 701 702 sc = device_get_softc(dev); 703 callout_init(&sc->vr_stat_timer); 704 705 /* 706 * Handle power management nonsense. 707 */ 708 709 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 710 if (command == 0x01) { 711 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 712 if (command & VR_PSTATE_MASK) { 713 uint32_t iobase, membase, irq; 714 715 /* Save important PCI config data. */ 716 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 717 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 718 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 719 720 /* Reset the power state. */ 721 device_printf(dev, "chip is in D%d power mode " 722 "-- setting to D0\n", command & VR_PSTATE_MASK); 723 command &= 0xFFFFFFFC; 724 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 725 726 /* Restore PCI config data. */ 727 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 728 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 729 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 730 } 731 } 732 733 /* 734 * Map control/status registers. 735 */ 736 command = pci_read_config(dev, PCIR_COMMAND, 4); 737 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 738 pci_write_config(dev, PCIR_COMMAND, command, 4); 739 command = pci_read_config(dev, PCIR_COMMAND, 4); 740 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 741 742 #ifdef VR_USEIOSPACE 743 if (!(command & PCIM_CMD_PORTEN)) { 744 device_printf(dev, "failed to enable I/O ports!\n"); 745 free(sc, M_DEVBUF); 746 goto fail; 747 } 748 #else 749 if (!(command & PCIM_CMD_MEMEN)) { 750 device_printf(dev, "failed to enable memory mapping!\n"); 751 goto fail; 752 } 753 #endif 754 755 rid = VR_RID; 756 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 757 758 if (sc->vr_res == NULL) { 759 device_printf(dev, "couldn't map ports/memory\n"); 760 error = ENXIO; 761 goto fail; 762 } 763 764 sc->vr_btag = rman_get_bustag(sc->vr_res); 765 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 766 767 /* Allocate interrupt */ 768 rid = 0; 769 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 770 RF_SHAREABLE | RF_ACTIVE); 771 772 if (sc->vr_irq == NULL) { 773 device_printf(dev, "couldn't map interrupt\n"); 774 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 775 error = ENXIO; 776 goto fail; 777 } 778 779 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 780 vr_intr, sc, &sc->vr_intrhand, NULL); 781 782 if (error) { 783 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 784 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 785 device_printf(dev, "couldn't set up irq\n"); 786 goto fail; 787 } 788 789 /* 790 * Windows may put the chip in suspend mode when it 791 * shuts down. Be sure to kick it in the head to wake it 792 * up again. 793 */ 794 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 795 796 /* Reset the adapter. */ 797 vr_reset(sc); 798 799 /* 800 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 801 * initialization and disable AUTOPOLL. 802 */ 803 pci_write_config(dev, VR_PCI_MODE, 804 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 805 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 806 807 ifp = &sc->arpcom.ac_if; 808 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 809 810 /* 811 * Get station address. The way the Rhine chips work, 812 * you're not allowed to directly access the EEPROM once 813 * they've been programmed a special way. Consequently, 814 * we need to read the node address from the PAR0 and PAR1 815 * registers. 816 */ 817 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 818 DELAY(200); 819 for (i = 0; i < ETHER_ADDR_LEN; i++) 820 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 821 822 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 823 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 824 825 if (sc->vr_ldata == NULL) { 826 device_printf(dev, "no memory for list buffers!\n"); 827 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 828 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 829 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 830 error = ENXIO; 831 goto fail; 832 } 833 834 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 835 836 ifp->if_softc = sc; 837 ifp->if_mtu = ETHERMTU; 838 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 839 ifp->if_ioctl = vr_ioctl; 840 ifp->if_start = vr_start; 841 #ifdef DEVICE_POLLING 842 ifp->if_poll = vr_poll; 843 #endif 844 ifp->if_watchdog = vr_watchdog; 845 ifp->if_init = vr_init; 846 ifp->if_baudrate = 10000000; 847 ifq_set_maxlen(&ifp->if_snd, VR_TX_LIST_CNT - 1); 848 ifq_set_ready(&ifp->if_snd); 849 850 /* 851 * Do MII setup. 852 */ 853 if (mii_phy_probe(dev, &sc->vr_miibus, 854 vr_ifmedia_upd, vr_ifmedia_sts)) { 855 if_printf(ifp, "MII without any phy!\n"); 856 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 857 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 858 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 859 contigfree(sc->vr_ldata, 860 sizeof(struct vr_list_data), M_DEVBUF); 861 error = ENXIO; 862 goto fail; 863 } 864 865 /* Call MI attach routine. */ 866 ether_ifattach(ifp, eaddr); 867 868 fail: 869 crit_exit(); 870 return(error); 871 } 872 873 static int 874 vr_detach(device_t dev) 875 { 876 struct vr_softc *sc = device_get_softc(dev); 877 struct ifnet *ifp = &sc->arpcom.ac_if; 878 879 crit_enter(); 880 881 vr_stop(sc); 882 ether_ifdetach(ifp); 883 884 bus_generic_detach(dev); 885 device_delete_child(dev, sc->vr_miibus); 886 887 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 888 889 crit_exit(); 890 891 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 892 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 893 894 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 895 896 return(0); 897 } 898 899 /* 900 * Initialize the transmit descriptors. 901 */ 902 static int 903 vr_list_tx_init(struct vr_softc *sc) 904 { 905 struct vr_chain_data *cd; 906 struct vr_list_data *ld; 907 int i, nexti; 908 909 cd = &sc->vr_cdata; 910 ld = sc->vr_ldata; 911 for (i = 0; i < VR_TX_LIST_CNT; i++) { 912 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 913 if (i == (VR_TX_LIST_CNT - 1)) 914 nexti = 0; 915 else 916 nexti = i + 1; 917 cd->vr_tx_chain[i].vr_nextdesc = &cd->vr_tx_chain[nexti]; 918 } 919 920 cd->vr_tx_free = &cd->vr_tx_chain[0]; 921 cd->vr_tx_tail = cd->vr_tx_head = NULL; 922 923 return(0); 924 } 925 926 927 /* 928 * Initialize the RX descriptors and allocate mbufs for them. Note that 929 * we arrange the descriptors in a closed ring, so that the last descriptor 930 * points back to the first. 931 */ 932 static int 933 vr_list_rx_init(struct vr_softc *sc) 934 { 935 struct vr_chain_data *cd; 936 struct vr_list_data *ld; 937 int i, nexti; 938 939 cd = &sc->vr_cdata; 940 ld = sc->vr_ldata; 941 942 for (i = 0; i < VR_RX_LIST_CNT; i++) { 943 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i]; 944 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 945 return(ENOBUFS); 946 if (i == (VR_RX_LIST_CNT - 1)) 947 nexti = 0; 948 else 949 nexti = i + 1; 950 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti]; 951 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]); 952 } 953 954 cd->vr_rx_head = &cd->vr_rx_chain[0]; 955 956 return(0); 957 } 958 959 /* 960 * Initialize an RX descriptor and attach an MBUF cluster. 961 * Note: the length fields are only 11 bits wide, which means the 962 * largest size we can specify is 2047. This is important because 963 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 964 * overflow the field and make a mess. 965 */ 966 static int 967 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 968 { 969 struct mbuf *m_new = NULL; 970 971 if (m == NULL) { 972 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 973 if (m_new == NULL) 974 return(ENOBUFS); 975 976 MCLGET(m_new, MB_DONTWAIT); 977 if (!(m_new->m_flags & M_EXT)) { 978 m_freem(m_new); 979 return(ENOBUFS); 980 } 981 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 982 } else { 983 m_new = m; 984 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 985 m_new->m_data = m_new->m_ext.ext_buf; 986 } 987 988 m_adj(m_new, sizeof(uint64_t)); 989 990 c->vr_mbuf = m_new; 991 c->vr_ptr->vr_status = VR_RXSTAT; 992 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 993 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 994 995 return(0); 996 } 997 998 /* 999 * A frame has been uploaded: pass the resulting mbuf chain up to 1000 * the higher level protocols. 1001 */ 1002 static void 1003 vr_rxeof(struct vr_softc *sc) 1004 { 1005 struct mbuf *m; 1006 struct ifnet *ifp; 1007 struct vr_chain_onefrag *cur_rx; 1008 int total_len = 0; 1009 uint32_t rxstat; 1010 1011 ifp = &sc->arpcom.ac_if; 1012 1013 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1014 VR_RXSTAT_OWN)) { 1015 struct mbuf *m0 = NULL; 1016 1017 cur_rx = sc->vr_cdata.vr_rx_head; 1018 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1019 m = cur_rx->vr_mbuf; 1020 1021 /* 1022 * If an error occurs, update stats, clear the 1023 * status word and leave the mbuf cluster in place: 1024 * it should simply get re-used next time this descriptor 1025 * comes up in the ring. 1026 */ 1027 if (rxstat & VR_RXSTAT_RXERR) { 1028 ifp->if_ierrors++; 1029 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff); 1030 if (rxstat & VR_RXSTAT_CRCERR) 1031 printf(" crc error"); 1032 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1033 printf(" frame alignment error\n"); 1034 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1035 printf(" FIFO overflow"); 1036 if (rxstat & VR_RXSTAT_GIANT) 1037 printf(" received giant packet"); 1038 if (rxstat & VR_RXSTAT_RUNT) 1039 printf(" received runt packet"); 1040 if (rxstat & VR_RXSTAT_BUSERR) 1041 printf(" system bus error"); 1042 if (rxstat & VR_RXSTAT_BUFFERR) 1043 printf("rx buffer error"); 1044 printf("\n"); 1045 vr_newbuf(sc, cur_rx, m); 1046 continue; 1047 } 1048 1049 /* No errors; receive the packet. */ 1050 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1051 1052 /* 1053 * XXX The VIA Rhine chip includes the CRC with every 1054 * received frame, and there's no way to turn this 1055 * behavior off (at least, I can't find anything in 1056 * the manual that explains how to do it) so we have 1057 * to trim off the CRC manually. 1058 */ 1059 total_len -= ETHER_CRC_LEN; 1060 1061 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1062 total_len + ETHER_ALIGN, 0, ifp, NULL); 1063 vr_newbuf(sc, cur_rx, m); 1064 if (m0 == NULL) { 1065 ifp->if_ierrors++; 1066 continue; 1067 } 1068 m_adj(m0, ETHER_ALIGN); 1069 m = m0; 1070 1071 ifp->if_ipackets++; 1072 (*ifp->if_input)(ifp, m); 1073 } 1074 } 1075 1076 static void 1077 vr_rxeoc(struct vr_softc *sc) 1078 { 1079 struct ifnet *ifp; 1080 int i; 1081 1082 ifp = &sc->arpcom.ac_if; 1083 1084 ifp->if_ierrors++; 1085 1086 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1087 DELAY(10000); 1088 1089 /* Wait for receiver to stop */ 1090 for (i = 0x400; 1091 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1092 i--) 1093 ; /* Wait for receiver to stop */ 1094 1095 if (i == 0) { 1096 if_printf(ifp, "rx shutdown error!\n"); 1097 sc->vr_flags |= VR_F_RESTART; 1098 return; 1099 } 1100 1101 vr_rxeof(sc); 1102 1103 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1104 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1105 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1106 } 1107 1108 /* 1109 * A frame was downloaded to the chip. It's safe for us to clean up 1110 * the list buffers. 1111 */ 1112 static void 1113 vr_txeof(struct vr_softc *sc) 1114 { 1115 struct vr_chain *cur_tx; 1116 struct ifnet *ifp; 1117 1118 ifp = &sc->arpcom.ac_if; 1119 1120 /* Reset the timeout timer; if_txeoc will clear it. */ 1121 ifp->if_timer = 5; 1122 1123 /* Sanity check. */ 1124 if (sc->vr_cdata.vr_tx_head == NULL) 1125 return; 1126 1127 /* 1128 * Go through our tx list and free mbufs for those 1129 * frames that have been transmitted. 1130 */ 1131 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1132 uint32_t txstat; 1133 int i; 1134 1135 cur_tx = sc->vr_cdata.vr_tx_head; 1136 txstat = cur_tx->vr_ptr->vr_status; 1137 1138 if ((txstat & VR_TXSTAT_ABRT) || 1139 (txstat & VR_TXSTAT_UDF)) { 1140 for (i = 0x400; 1141 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1142 i--) 1143 ; /* Wait for chip to shutdown */ 1144 if (i == 0) { 1145 if_printf(ifp, "tx shutdown timeout\n"); 1146 sc->vr_flags |= VR_F_RESTART; 1147 break; 1148 } 1149 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1150 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1151 break; 1152 } 1153 1154 if (txstat & VR_TXSTAT_OWN) 1155 break; 1156 1157 if (txstat & VR_TXSTAT_ERRSUM) { 1158 ifp->if_oerrors++; 1159 if (txstat & VR_TXSTAT_DEFER) 1160 ifp->if_collisions++; 1161 if (txstat & VR_TXSTAT_LATECOLL) 1162 ifp->if_collisions++; 1163 } 1164 1165 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1166 1167 ifp->if_opackets++; 1168 if (cur_tx->vr_mbuf != NULL) { 1169 m_freem(cur_tx->vr_mbuf); 1170 cur_tx->vr_mbuf = NULL; 1171 } 1172 1173 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1174 sc->vr_cdata.vr_tx_head = NULL; 1175 sc->vr_cdata.vr_tx_tail = NULL; 1176 break; 1177 } 1178 1179 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1180 } 1181 } 1182 1183 /* 1184 * TX 'end of channel' interrupt handler. 1185 */ 1186 static void 1187 vr_txeoc(struct vr_softc *sc) 1188 { 1189 struct ifnet *ifp; 1190 1191 ifp = &sc->arpcom.ac_if; 1192 1193 if (sc->vr_cdata.vr_tx_head == NULL) { 1194 ifp->if_flags &= ~IFF_OACTIVE; 1195 sc->vr_cdata.vr_tx_tail = NULL; 1196 ifp->if_timer = 0; 1197 } 1198 } 1199 1200 static void 1201 vr_tick(void *xsc) 1202 { 1203 struct vr_softc *sc = xsc; 1204 struct mii_data *mii; 1205 1206 crit_enter(); 1207 1208 if (sc->vr_flags & VR_F_RESTART) { 1209 if_printf(&sc->arpcom.ac_if, "restarting\n"); 1210 vr_stop(sc); 1211 vr_reset(sc); 1212 vr_init(sc); 1213 sc->vr_flags &= ~VR_F_RESTART; 1214 } 1215 1216 mii = device_get_softc(sc->vr_miibus); 1217 mii_tick(mii); 1218 1219 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1220 1221 crit_exit(); 1222 } 1223 1224 static void 1225 vr_intr(void *arg) 1226 { 1227 struct vr_softc *sc; 1228 struct ifnet *ifp; 1229 uint16_t status; 1230 1231 sc = arg; 1232 ifp = &sc->arpcom.ac_if; 1233 1234 /* Supress unwanted interrupts. */ 1235 if (!(ifp->if_flags & IFF_UP)) { 1236 vr_stop(sc); 1237 return; 1238 } 1239 1240 /* Disable interrupts. */ 1241 if ((ifp->if_flags & IFF_POLLING) == 0) 1242 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1243 1244 for (;;) { 1245 status = CSR_READ_2(sc, VR_ISR); 1246 if (status) 1247 CSR_WRITE_2(sc, VR_ISR, status); 1248 1249 if ((status & VR_INTRS) == 0) 1250 break; 1251 1252 if (status & VR_ISR_RX_OK) 1253 vr_rxeof(sc); 1254 1255 if (status & VR_ISR_RX_DROPPED) { 1256 if_printf(ifp, "rx packet lost\n"); 1257 ifp->if_ierrors++; 1258 } 1259 1260 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1261 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1262 if_printf(ifp, "receive error (%04x)", status); 1263 if (status & VR_ISR_RX_NOBUF) 1264 printf(" no buffers"); 1265 if (status & VR_ISR_RX_OFLOW) 1266 printf(" overflow"); 1267 if (status & VR_ISR_RX_DROPPED) 1268 printf(" packet lost"); 1269 printf("\n"); 1270 vr_rxeoc(sc); 1271 } 1272 1273 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1274 vr_reset(sc); 1275 vr_init(sc); 1276 break; 1277 } 1278 1279 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1280 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1281 vr_txeof(sc); 1282 if ((status & VR_ISR_UDFI) || 1283 (status & VR_ISR_TX_ABRT2) || 1284 (status & VR_ISR_TX_ABRT)) { 1285 ifp->if_oerrors++; 1286 if (sc->vr_cdata.vr_tx_head != NULL) { 1287 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1288 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1289 } 1290 } else { 1291 vr_txeoc(sc); 1292 } 1293 } 1294 1295 } 1296 1297 /* Re-enable interrupts. */ 1298 if ((ifp->if_flags & IFF_POLLING) == 0) 1299 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1300 1301 if (!ifq_is_empty(&ifp->if_snd)) 1302 vr_start(ifp); 1303 } 1304 1305 /* 1306 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1307 * pointers to the fragment pointers. 1308 */ 1309 static int 1310 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1311 { 1312 int frag = 0; 1313 struct vr_desc *f = NULL; 1314 int total_len; 1315 struct mbuf *m_new; 1316 1317 total_len = 0; 1318 1319 /* 1320 * The VIA Rhine wants packet buffers to be longword 1321 * aligned, but very often our mbufs aren't. Rather than 1322 * waste time trying to decide when to copy and when not 1323 * to copy, just do it all the time. 1324 */ 1325 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1326 if (m_new == NULL) { 1327 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n"); 1328 return(1); 1329 } 1330 if (m_head->m_pkthdr.len > MHLEN) { 1331 MCLGET(m_new, MB_DONTWAIT); 1332 if (!(m_new->m_flags & M_EXT)) { 1333 m_freem(m_new); 1334 if_printf(&sc->arpcom.ac_if, 1335 "no memory for tx list\n"); 1336 return(1); 1337 } 1338 } 1339 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1340 mtod(m_new, caddr_t)); 1341 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1342 /* 1343 * The Rhine chip doesn't auto-pad, so we have to make 1344 * sure to pad short frames out to the minimum frame length 1345 * ourselves. 1346 */ 1347 if (m_new->m_len < VR_MIN_FRAMELEN) { 1348 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1349 m_new->m_len = m_new->m_pkthdr.len; 1350 } 1351 f = c->vr_ptr; 1352 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1353 f->vr_ctl = total_len = m_new->m_len; 1354 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1355 f->vr_status = 0; 1356 frag = 1; 1357 1358 c->vr_mbuf = m_new; 1359 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1360 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1361 1362 return(0); 1363 } 1364 1365 /* 1366 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1367 * to the mbuf data regions directly in the transmit lists. We also save a 1368 * copy of the pointers since the transmit list fragment pointers are 1369 * physical addresses. 1370 */ 1371 static void 1372 vr_start(struct ifnet *ifp) 1373 { 1374 struct vr_softc *sc; 1375 struct mbuf *m_head = NULL; 1376 struct vr_chain *cur_tx = NULL, *start_tx; 1377 1378 sc = ifp->if_softc; 1379 1380 if (ifp->if_flags & IFF_OACTIVE) 1381 return; 1382 1383 /* Check for an available queue slot. If there are none, punt. */ 1384 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1385 ifp->if_flags |= IFF_OACTIVE; 1386 return; 1387 } 1388 1389 start_tx = sc->vr_cdata.vr_tx_free; 1390 1391 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1392 m_head = ifq_poll(&ifp->if_snd); 1393 if (m_head == NULL) 1394 break; 1395 1396 /* Pick a descriptor off the free list. */ 1397 cur_tx = sc->vr_cdata.vr_tx_free; 1398 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1399 1400 /* Pack the data into the descriptor. */ 1401 if (vr_encap(sc, cur_tx, m_head)) { 1402 ifp->if_flags |= IFF_OACTIVE; 1403 cur_tx = NULL; 1404 break; 1405 } 1406 1407 m_head = ifq_dequeue(&ifp->if_snd); 1408 if (cur_tx != start_tx) 1409 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1410 1411 BPF_MTAP(ifp, m_head); 1412 m_freem(m_head); 1413 1414 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1415 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1416 } 1417 1418 /* If there are no frames queued, bail. */ 1419 if (cur_tx == NULL) 1420 return; 1421 1422 sc->vr_cdata.vr_tx_tail = cur_tx; 1423 1424 if (sc->vr_cdata.vr_tx_head == NULL) 1425 sc->vr_cdata.vr_tx_head = start_tx; 1426 1427 /* 1428 * Set a timeout in case the chip goes out to lunch. 1429 */ 1430 ifp->if_timer = 5; 1431 } 1432 1433 static void 1434 vr_init(void *xsc) 1435 { 1436 struct vr_softc *sc = xsc; 1437 struct ifnet *ifp = &sc->arpcom.ac_if; 1438 struct mii_data *mii; 1439 int i; 1440 1441 mii = device_get_softc(sc->vr_miibus); 1442 1443 crit_enter(); 1444 1445 /* Cancel pending I/O and free all RX/TX buffers. */ 1446 vr_stop(sc); 1447 vr_reset(sc); 1448 1449 /* Set our station address. */ 1450 for (i = 0; i < ETHER_ADDR_LEN; i++) 1451 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1452 1453 /* Set DMA size. */ 1454 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1455 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1456 1457 /* 1458 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1459 * so we must set both. 1460 */ 1461 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1462 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1463 1464 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1465 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1466 1467 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1468 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1469 1470 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1471 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1472 1473 /* Init circular RX list. */ 1474 if (vr_list_rx_init(sc) == ENOBUFS) { 1475 vr_stop(sc); 1476 crit_exit(); 1477 if_printf(ifp, "initialization failed: no memory for rx buffers\n"); 1478 return; 1479 } 1480 1481 /* Init tx descriptors. */ 1482 vr_list_tx_init(sc); 1483 1484 /* If we want promiscuous mode, set the allframes bit. */ 1485 if (ifp->if_flags & IFF_PROMISC) 1486 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1487 else 1488 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1489 1490 /* Set capture broadcast bit to capture broadcast frames. */ 1491 if (ifp->if_flags & IFF_BROADCAST) 1492 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1493 else 1494 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1495 1496 /* 1497 * Program the multicast filter, if necessary. 1498 */ 1499 vr_setmulti(sc); 1500 1501 /* 1502 * Load the address of the RX list. 1503 */ 1504 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1505 1506 /* Enable receiver and transmitter. */ 1507 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1508 VR_CMD_TX_ON|VR_CMD_RX_ON| 1509 VR_CMD_RX_GO); 1510 1511 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1512 1513 /* 1514 * Enable interrupts, unless we are polling. 1515 */ 1516 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1517 if ((ifp->if_flags & IFF_POLLING) == 0) 1518 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1519 1520 mii_mediachg(mii); 1521 1522 ifp->if_flags |= IFF_RUNNING; 1523 ifp->if_flags &= ~IFF_OACTIVE; 1524 1525 crit_exit(); 1526 1527 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1528 } 1529 1530 /* 1531 * Set media options. 1532 */ 1533 static int 1534 vr_ifmedia_upd(struct ifnet *ifp) 1535 { 1536 struct vr_softc *sc; 1537 1538 sc = ifp->if_softc; 1539 1540 if (ifp->if_flags & IFF_UP) 1541 vr_init(sc); 1542 1543 return(0); 1544 } 1545 1546 /* 1547 * Report current media status. 1548 */ 1549 static void 1550 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1551 { 1552 struct vr_softc *sc; 1553 struct mii_data *mii; 1554 1555 sc = ifp->if_softc; 1556 mii = device_get_softc(sc->vr_miibus); 1557 mii_pollstat(mii); 1558 ifmr->ifm_active = mii->mii_media_active; 1559 ifmr->ifm_status = mii->mii_media_status; 1560 } 1561 1562 static int 1563 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1564 { 1565 struct vr_softc *sc = ifp->if_softc; 1566 struct ifreq *ifr = (struct ifreq *) data; 1567 struct mii_data *mii; 1568 int error = 0; 1569 1570 crit_enter(); 1571 1572 switch(command) { 1573 case SIOCSIFFLAGS: 1574 if (ifp->if_flags & IFF_UP) { 1575 vr_init(sc); 1576 } else { 1577 if (ifp->if_flags & IFF_RUNNING) 1578 vr_stop(sc); 1579 } 1580 error = 0; 1581 break; 1582 case SIOCADDMULTI: 1583 case SIOCDELMULTI: 1584 vr_setmulti(sc); 1585 error = 0; 1586 break; 1587 case SIOCGIFMEDIA: 1588 case SIOCSIFMEDIA: 1589 mii = device_get_softc(sc->vr_miibus); 1590 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1591 break; 1592 default: 1593 error = ether_ioctl(ifp, command, data); 1594 break; 1595 } 1596 1597 crit_exit(); 1598 1599 return(error); 1600 } 1601 1602 #ifdef DEVICE_POLLING 1603 1604 static void 1605 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1606 { 1607 struct vr_softc *sc = ifp->if_softc; 1608 1609 switch(cmd) { 1610 case POLL_REGISTER: 1611 /* disable interrupts */ 1612 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1613 break; 1614 case POLL_DEREGISTER: 1615 /* enable interrupts */ 1616 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1617 break; 1618 default: 1619 vr_intr(sc); 1620 break; 1621 } 1622 } 1623 #endif 1624 1625 static void 1626 vr_watchdog(struct ifnet *ifp) 1627 { 1628 struct vr_softc *sc; 1629 1630 sc = ifp->if_softc; 1631 1632 ifp->if_oerrors++; 1633 if_printf(ifp, "watchdog timeout\n"); 1634 1635 #ifdef DEVICE_POLLING 1636 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) { 1637 if_printf(ifp, "ints don't seem to be working, " 1638 "emergency switch to polling\n"); 1639 emergency_poll_enable("if_vr"); 1640 ether_poll_register(ifp); /* XXX illegal */ 1641 } else 1642 #endif 1643 { 1644 vr_stop(sc); 1645 vr_reset(sc); 1646 vr_init(sc); 1647 } 1648 1649 if (!ifq_is_empty(&ifp->if_snd)) 1650 vr_start(ifp); 1651 } 1652 1653 /* 1654 * Stop the adapter and free any mbufs allocated to the 1655 * RX and TX lists. 1656 */ 1657 static void 1658 vr_stop(struct vr_softc *sc) 1659 { 1660 int i; 1661 struct ifnet *ifp; 1662 1663 ifp = &sc->arpcom.ac_if; 1664 ifp->if_timer = 0; 1665 1666 callout_stop(&sc->vr_stat_timer); 1667 1668 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1669 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1670 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1671 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1672 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1673 1674 /* 1675 * Free data in the RX lists. 1676 */ 1677 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1678 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1679 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1680 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1681 } 1682 } 1683 bzero((char *)&sc->vr_ldata->vr_rx_list, 1684 sizeof(sc->vr_ldata->vr_rx_list)); 1685 1686 /* 1687 * Free the TX list buffers. 1688 */ 1689 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1690 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1691 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1692 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1693 } 1694 } 1695 1696 bzero((char *)&sc->vr_ldata->vr_tx_list, 1697 sizeof(sc->vr_ldata->vr_tx_list)); 1698 1699 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1700 } 1701 1702 /* 1703 * Stop all chip I/O so that the kernel's probe routines don't 1704 * get confused by errant DMAs when rebooting. 1705 */ 1706 static void 1707 vr_shutdown(device_t dev) 1708 { 1709 struct vr_softc *sc; 1710 1711 sc = device_get_softc(dev); 1712 1713 vr_stop(sc); 1714 } 1715