1 /* 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/vge/if_vge.c,v 1.24 2006/02/14 12:44:56 glebius Exp $ 33 * $DragonFly: src/sys/dev/netif/vge/if_vge.c,v 1.7 2008/03/10 12:59:52 sephe Exp $ 34 */ 35 36 /* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83 #include "opt_polling.h" 84 85 #include <sys/param.h> 86 #include <sys/endian.h> 87 #include <sys/systm.h> 88 #include <sys/sockio.h> 89 #include <sys/mbuf.h> 90 #include <sys/malloc.h> 91 #include <sys/module.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/serialize.h> 95 #include <sys/proc.h> 96 #include <sys/bus.h> 97 #include <sys/rman.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/ifq_var.h> 105 #include <net/if_types.h> 106 #include <net/vlan/if_vlan_var.h> 107 #include <net/vlan/if_vlan_ether.h> 108 109 #include <net/bpf.h> 110 111 #include <dev/netif/mii_layer/mii.h> 112 #include <dev/netif/mii_layer/miivar.h> 113 114 #include <bus/pci/pcireg.h> 115 #include <bus/pci/pcivar.h> 116 #include <bus/pci/pcidevs.h> 117 118 #include "miibus_if.h" 119 120 #include <dev/netif/vge/if_vgereg.h> 121 #include <dev/netif/vge/if_vgevar.h> 122 123 #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 124 125 /* 126 * Various supported device vendors/types and their names. 127 */ 128 static const struct vge_type vge_devs[] = { 129 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612X, 130 "VIA Networking Gigabit Ethernet" }, 131 { 0, 0, NULL } 132 }; 133 134 static int vge_probe (device_t); 135 static int vge_attach (device_t); 136 static int vge_detach (device_t); 137 138 static int vge_encap (struct vge_softc *, struct mbuf *, int); 139 140 static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 141 static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 142 bus_size_t, int); 143 static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 144 bus_size_t, int); 145 static int vge_dma_alloc (device_t); 146 static void vge_dma_free (struct vge_softc *); 147 static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 148 static int vge_rx_list_init (struct vge_softc *); 149 static int vge_tx_list_init (struct vge_softc *); 150 #ifdef VGE_FIXUP_RX 151 static __inline void vge_fixup_rx 152 (struct mbuf *); 153 #endif 154 static void vge_rxeof (struct vge_softc *, int); 155 static void vge_txeof (struct vge_softc *); 156 static void vge_intr (void *); 157 static void vge_tick (struct vge_softc *); 158 static void vge_start (struct ifnet *); 159 static int vge_ioctl (struct ifnet *, u_long, caddr_t, 160 struct ucred *); 161 static void vge_init (void *); 162 static void vge_stop (struct vge_softc *); 163 static void vge_watchdog (struct ifnet *); 164 static int vge_suspend (device_t); 165 static int vge_resume (device_t); 166 static void vge_shutdown (device_t); 167 static int vge_ifmedia_upd (struct ifnet *); 168 static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 169 170 #ifdef VGE_EEPROM 171 static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 172 #endif 173 static void vge_read_eeprom (struct vge_softc *, uint8_t *, int, int, int); 174 175 static void vge_miipoll_start (struct vge_softc *); 176 static void vge_miipoll_stop (struct vge_softc *); 177 static int vge_miibus_readreg (device_t, int, int); 178 static int vge_miibus_writereg (device_t, int, int, int); 179 static void vge_miibus_statchg (device_t); 180 181 static void vge_cam_clear (struct vge_softc *); 182 static int vge_cam_set (struct vge_softc *, uint8_t *); 183 static void vge_setmulti (struct vge_softc *); 184 static void vge_reset (struct vge_softc *); 185 186 #ifdef DEVICE_POLLING 187 static void vge_poll(struct ifnet *, enum poll_cmd, int); 188 static void vge_disable_intr(struct vge_softc *); 189 #endif 190 static void vge_enable_intr(struct vge_softc *, uint32_t); 191 192 #define VGE_PCI_LOIO 0x10 193 #define VGE_PCI_LOMEM 0x14 194 195 static device_method_t vge_methods[] = { 196 /* Device interface */ 197 DEVMETHOD(device_probe, vge_probe), 198 DEVMETHOD(device_attach, vge_attach), 199 DEVMETHOD(device_detach, vge_detach), 200 DEVMETHOD(device_suspend, vge_suspend), 201 DEVMETHOD(device_resume, vge_resume), 202 DEVMETHOD(device_shutdown, vge_shutdown), 203 204 /* bus interface */ 205 DEVMETHOD(bus_print_child, bus_generic_print_child), 206 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 207 208 /* MII interface */ 209 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 210 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 211 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 212 213 { 0, 0 } 214 }; 215 216 static driver_t vge_driver = { 217 "vge", 218 vge_methods, 219 sizeof(struct vge_softc) 220 }; 221 222 static devclass_t vge_devclass; 223 224 DECLARE_DUMMY_MODULE(if_vge); 225 MODULE_DEPEND(if_vge, miibus, 1, 1, 1); 226 DRIVER_MODULE(if_vge, pci, vge_driver, vge_devclass, 0, 0); 227 DRIVER_MODULE(if_vge, cardbus, vge_driver, vge_devclass, 0, 0); 228 DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 229 230 #ifdef VGE_EEPROM 231 /* 232 * Read a word of data stored in the EEPROM at address 'addr.' 233 */ 234 static void 235 vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t dest) 236 { 237 uint16_t word = 0; 238 int i; 239 240 /* 241 * Enter EEPROM embedded programming mode. In order to 242 * access the EEPROM at all, we first have to set the 243 * EELOAD bit in the CHIPCFG2 register. 244 */ 245 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 246 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 247 248 /* Select the address of the word we want to read */ 249 CSR_WRITE_1(sc, VGE_EEADDR, addr); 250 251 /* Issue read command */ 252 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 253 254 /* Wait for the done bit to be set. */ 255 for (i = 0; i < VGE_TIMEOUT; i++) { 256 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 257 break; 258 } 259 if (i == VGE_TIMEOUT) { 260 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261 *dest = 0; 262 return; 263 } 264 265 /* Read the result */ 266 word = CSR_READ_2(sc, VGE_EERDDAT); 267 268 /* Turn off EEPROM access mode. */ 269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271 272 *dest = word; 273 } 274 #endif 275 276 /* 277 * Read a sequence of words from the EEPROM. 278 */ 279 static void 280 vge_read_eeprom(struct vge_softc *sc, uint8_t *dest, int off, int cnt, int swap) 281 { 282 int i; 283 #ifdef VGE_EEPROM 284 uint16_t word = 0, *ptr; 285 286 for (i = 0; i < cnt; i++) { 287 vge_eeprom_getword(sc, off + i, &word); 288 ptr = (uint16_t *)(dest + (i * 2)); 289 if (swap) 290 *ptr = ntohs(word); 291 else 292 *ptr = word; 293 } 294 #else 295 for (i = 0; i < ETHER_ADDR_LEN; i++) 296 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 297 #endif 298 } 299 300 static void 301 vge_miipoll_stop(struct vge_softc *sc) 302 { 303 int i; 304 305 CSR_WRITE_1(sc, VGE_MIICMD, 0); 306 307 for (i = 0; i < VGE_TIMEOUT; i++) { 308 DELAY(1); 309 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 310 break; 311 } 312 if (i == VGE_TIMEOUT) 313 if_printf(&sc->arpcom.ac_if, "failed to idle MII autopoll\n"); 314 } 315 316 static void 317 vge_miipoll_start(struct vge_softc *sc) 318 { 319 int i; 320 321 /* First, make sure we're idle. */ 322 CSR_WRITE_1(sc, VGE_MIICMD, 0); 323 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 324 325 for (i = 0; i < VGE_TIMEOUT; i++) { 326 DELAY(1); 327 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 328 break; 329 } 330 if (i == VGE_TIMEOUT) { 331 if_printf(&sc->arpcom.ac_if, "failed to idle MII autopoll\n"); 332 return; 333 } 334 335 /* Now enable auto poll mode. */ 336 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 337 338 /* And make sure it started. */ 339 for (i = 0; i < VGE_TIMEOUT; i++) { 340 DELAY(1); 341 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 342 break; 343 } 344 if (i == VGE_TIMEOUT) 345 if_printf(&sc->arpcom.ac_if, "failed to start MII autopoll\n"); 346 } 347 348 static int 349 vge_miibus_readreg(device_t dev, int phy, int reg) 350 { 351 struct vge_softc *sc; 352 int i; 353 uint16_t rval = 0; 354 355 sc = device_get_softc(dev); 356 357 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 358 return(0); 359 360 vge_miipoll_stop(sc); 361 362 /* Specify the register we want to read. */ 363 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 364 365 /* Issue read command. */ 366 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 367 368 /* Wait for the read command bit to self-clear. */ 369 for (i = 0; i < VGE_TIMEOUT; i++) { 370 DELAY(1); 371 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 372 break; 373 } 374 if (i == VGE_TIMEOUT) 375 if_printf(&sc->arpcom.ac_if, "MII read timed out\n"); 376 else 377 rval = CSR_READ_2(sc, VGE_MIIDATA); 378 379 vge_miipoll_start(sc); 380 381 return (rval); 382 } 383 384 static int 385 vge_miibus_writereg(device_t dev, int phy, int reg, int data) 386 { 387 struct vge_softc *sc; 388 int i, rval = 0; 389 390 sc = device_get_softc(dev); 391 392 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 393 return(0); 394 395 vge_miipoll_stop(sc); 396 397 /* Specify the register we want to write. */ 398 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 399 400 /* Specify the data we want to write. */ 401 CSR_WRITE_2(sc, VGE_MIIDATA, data); 402 403 /* Issue write command. */ 404 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 405 406 /* Wait for the write command bit to self-clear. */ 407 for (i = 0; i < VGE_TIMEOUT; i++) { 408 DELAY(1); 409 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 410 break; 411 } 412 if (i == VGE_TIMEOUT) { 413 if_printf(&sc->arpcom.ac_if, "MII write timed out\n"); 414 rval = EIO; 415 } 416 417 vge_miipoll_start(sc); 418 419 return (rval); 420 } 421 422 static void 423 vge_cam_clear(struct vge_softc *sc) 424 { 425 int i; 426 427 /* 428 * Turn off all the mask bits. This tells the chip 429 * that none of the entries in the CAM filter are valid. 430 * desired entries will be enabled as we fill the filter in. 431 */ 432 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 433 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 434 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 435 for (i = 0; i < 8; i++) 436 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 437 438 /* Clear the VLAN filter too. */ 439 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 440 for (i = 0; i < 8; i++) 441 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 442 443 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 444 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 445 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 446 447 sc->vge_camidx = 0; 448 } 449 450 static int 451 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 452 { 453 int i, error = 0; 454 455 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 456 return(ENOSPC); 457 458 /* Select the CAM data page. */ 459 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 460 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 461 462 /* Set the filter entry we want to update and enable writing. */ 463 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 464 465 /* Write the address to the CAM registers */ 466 for (i = 0; i < ETHER_ADDR_LEN; i++) 467 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 468 469 /* Issue a write command. */ 470 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 471 472 /* Wake for it to clear. */ 473 for (i = 0; i < VGE_TIMEOUT; i++) { 474 DELAY(1); 475 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 476 break; 477 } 478 if (i == VGE_TIMEOUT) { 479 if_printf(&sc->arpcom.ac_if, "setting CAM filter failed\n"); 480 error = EIO; 481 goto fail; 482 } 483 484 /* Select the CAM mask page. */ 485 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 486 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 487 488 /* Set the mask bit that enables this filter. */ 489 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 490 1<<(sc->vge_camidx & 7)); 491 492 sc->vge_camidx++; 493 494 fail: 495 /* Turn off access to CAM. */ 496 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 497 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 498 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 499 500 return (error); 501 } 502 503 /* 504 * Program the multicast filter. We use the 64-entry CAM filter 505 * for perfect filtering. If there's more than 64 multicast addresses, 506 * we use the hash filter insted. 507 */ 508 static void 509 vge_setmulti(struct vge_softc *sc) 510 { 511 struct ifnet *ifp = &sc->arpcom.ac_if; 512 int error = 0; 513 struct ifmultiaddr *ifma; 514 uint32_t h, hashes[2] = { 0, 0 }; 515 516 /* First, zot all the multicast entries. */ 517 vge_cam_clear(sc); 518 CSR_WRITE_4(sc, VGE_MAR0, 0); 519 CSR_WRITE_4(sc, VGE_MAR1, 0); 520 521 /* 522 * If the user wants allmulti or promisc mode, enable reception 523 * of all multicast frames. 524 */ 525 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 526 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 527 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 528 return; 529 } 530 531 /* Now program new ones */ 532 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 533 if (ifma->ifma_addr->sa_family != AF_LINK) 534 continue; 535 error = vge_cam_set(sc, 536 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 537 if (error) 538 break; 539 } 540 541 /* If there were too many addresses, use the hash filter. */ 542 if (error) { 543 vge_cam_clear(sc); 544 545 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 546 if (ifma->ifma_addr->sa_family != AF_LINK) 547 continue; 548 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 549 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 550 if (h < 32) 551 hashes[0] |= (1 << h); 552 else 553 hashes[1] |= (1 << (h - 32)); 554 } 555 556 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 557 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 558 } 559 } 560 561 static void 562 vge_reset(struct vge_softc *sc) 563 { 564 int i; 565 566 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 567 568 for (i = 0; i < VGE_TIMEOUT; i++) { 569 DELAY(5); 570 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 571 break; 572 } 573 574 if (i == VGE_TIMEOUT) { 575 if_printf(&sc->arpcom.ac_if, "soft reset timed out"); 576 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 577 DELAY(2000); 578 } 579 580 DELAY(5000); 581 582 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 583 584 for (i = 0; i < VGE_TIMEOUT; i++) { 585 DELAY(5); 586 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 587 break; 588 } 589 if (i == VGE_TIMEOUT) { 590 if_printf(&sc->arpcom.ac_if, "EEPROM reload timed out\n"); 591 return; 592 } 593 594 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 595 } 596 597 /* 598 * Probe for a VIA gigabit chip. Check the PCI vendor and device 599 * IDs against our list and return a device name if we find a match. 600 */ 601 static int 602 vge_probe(device_t dev) 603 { 604 const struct vge_type *t; 605 uint16_t did, vid; 606 607 did = pci_get_device(dev); 608 vid = pci_get_vendor(dev); 609 for (t = vge_devs; t->vge_name != NULL; ++t) { 610 if (vid == t->vge_vid && did == t->vge_did) { 611 device_set_desc(dev, t->vge_name); 612 return 0; 613 } 614 } 615 return (ENXIO); 616 } 617 618 static void 619 vge_dma_map_rx_desc(void *arg, bus_dma_segment_t *segs, int nseg, 620 bus_size_t mapsize, int error) 621 { 622 623 struct vge_dmaload_arg *ctx; 624 struct vge_rx_desc *d = NULL; 625 626 if (error) 627 return; 628 629 ctx = arg; 630 631 /* Signal error to caller if there's too many segments */ 632 if (nseg > ctx->vge_maxsegs) { 633 ctx->vge_maxsegs = 0; 634 return; 635 } 636 637 /* 638 * Map the segment array into descriptors. 639 */ 640 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 641 642 /* If this descriptor is still owned by the chip, bail. */ 643 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 644 if_printf(&ctx->sc->arpcom.ac_if, 645 "tried to map busy descriptor\n"); 646 ctx->vge_maxsegs = 0; 647 return; 648 } 649 650 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 651 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 652 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 653 d->vge_sts = 0; 654 d->vge_ctl = 0; 655 656 ctx->vge_maxsegs = 1; 657 } 658 659 static void 660 vge_dma_map_tx_desc(void *arg, bus_dma_segment_t *segs, int nseg, 661 bus_size_t mapsize, int error) 662 { 663 struct vge_dmaload_arg *ctx; 664 struct vge_tx_desc *d = NULL; 665 struct vge_tx_frag *f; 666 int i = 0; 667 668 if (error) 669 return; 670 671 ctx = arg; 672 673 /* Signal error to caller if there's too many segments */ 674 if (nseg > ctx->vge_maxsegs) { 675 ctx->vge_maxsegs = 0; 676 return; 677 } 678 679 /* Map the segment array into descriptors. */ 680 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 681 682 /* If this descriptor is still owned by the chip, bail. */ 683 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 684 ctx->vge_maxsegs = 0; 685 return; 686 } 687 688 for (i = 0; i < nseg; i++) { 689 f = &d->vge_frag[i]; 690 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 691 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 692 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 693 } 694 695 /* Argh. This chip does not autopad short frames */ 696 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 697 f = &d->vge_frag[i]; 698 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 699 ctx->vge_m0->m_pkthdr.len)); 700 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 701 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 702 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 703 i++; 704 } 705 706 /* 707 * When telling the chip how many segments there are, we 708 * must use nsegs + 1 instead of just nsegs. Darned if I 709 * know why. 710 */ 711 i++; 712 713 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 714 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 715 716 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 717 d->vge_ctl |= VGE_TDCTL_JUMBO; 718 719 ctx->vge_maxsegs = nseg; 720 } 721 722 /* 723 * Map a single buffer address. 724 */ 725 726 static void 727 vge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 728 { 729 if (error) 730 return; 731 732 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 733 *((bus_addr_t *)arg) = segs->ds_addr; 734 } 735 736 static int 737 vge_dma_alloc(device_t dev) 738 { 739 struct vge_softc *sc = device_get_softc(dev); 740 int error, nseg, i, tx_pos = 0, rx_pos = 0; 741 742 /* 743 * Allocate the parent bus DMA tag appropriate for PCI. 744 */ 745 #define VGE_NSEG_NEW 32 746 error = bus_dma_tag_create(NULL, /* parent */ 747 1, 0, /* alignment, boundary */ 748 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 749 BUS_SPACE_MAXADDR, /* highaddr */ 750 NULL, NULL, /* filter, filterarg */ 751 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 752 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 753 BUS_DMA_ALLOCNOW, /* flags */ 754 &sc->vge_parent_tag); 755 if (error) { 756 device_printf(dev, "can't create parent dma tag\n"); 757 return error; 758 } 759 760 /* 761 * Allocate map for RX mbufs. 762 */ 763 nseg = 32; 764 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 765 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 766 NULL, NULL, 767 MCLBYTES * nseg, nseg, MCLBYTES, 768 BUS_DMA_ALLOCNOW, &sc->vge_ldata.vge_mtag); 769 if (error) { 770 device_printf(dev, "could not allocate mbuf dma tag\n"); 771 return error; 772 } 773 774 /* 775 * Allocate map for TX descriptor list. 776 */ 777 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 0, 778 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 779 NULL, NULL, 780 VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, 781 BUS_DMA_ALLOCNOW, 782 &sc->vge_ldata.vge_tx_list_tag); 783 if (error) { 784 device_printf(dev, "could not allocate tx list dma tag\n"); 785 return error; 786 } 787 788 /* Allocate DMA'able memory for the TX ring */ 789 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 790 (void **)&sc->vge_ldata.vge_tx_list, 791 BUS_DMA_WAITOK | BUS_DMA_ZERO, 792 &sc->vge_ldata.vge_tx_list_map); 793 if (error) { 794 device_printf(dev, "could not allocate tx list dma memory\n"); 795 return error; 796 } 797 798 /* Load the map for the TX ring. */ 799 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 800 sc->vge_ldata.vge_tx_list_map, 801 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, 802 vge_dma_map_addr, 803 &sc->vge_ldata.vge_tx_list_addr, 804 BUS_DMA_WAITOK); 805 if (error) { 806 device_printf(dev, "could not load tx list\n"); 807 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 808 sc->vge_ldata.vge_tx_list, 809 sc->vge_ldata.vge_tx_list_map); 810 sc->vge_ldata.vge_tx_list = NULL; 811 return error; 812 } 813 814 /* Create DMA maps for TX buffers */ 815 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 816 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 817 &sc->vge_ldata.vge_tx_dmamap[i]); 818 if (error) { 819 device_printf(dev, "can't create DMA map for TX\n"); 820 tx_pos = i; 821 goto map_fail; 822 } 823 } 824 tx_pos = VGE_TX_DESC_CNT; 825 826 /* 827 * Allocate map for RX descriptor list. 828 */ 829 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 0, 830 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 831 NULL, NULL, 832 VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, 833 BUS_DMA_ALLOCNOW, 834 &sc->vge_ldata.vge_rx_list_tag); 835 if (error) { 836 device_printf(dev, "could not allocate rx list dma tag\n"); 837 return error; 838 } 839 840 /* Allocate DMA'able memory for the RX ring */ 841 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 842 (void **)&sc->vge_ldata.vge_rx_list, 843 BUS_DMA_WAITOK | BUS_DMA_ZERO, 844 &sc->vge_ldata.vge_rx_list_map); 845 if (error) { 846 device_printf(dev, "could not allocate rx list dma memory\n"); 847 return error; 848 } 849 850 /* Load the map for the RX ring. */ 851 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 852 sc->vge_ldata.vge_rx_list_map, 853 sc->vge_ldata.vge_rx_list, VGE_TX_LIST_SZ, 854 vge_dma_map_addr, 855 &sc->vge_ldata.vge_rx_list_addr, 856 BUS_DMA_WAITOK); 857 if (error) { 858 device_printf(dev, "could not load rx list\n"); 859 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 860 sc->vge_ldata.vge_rx_list, 861 sc->vge_ldata.vge_rx_list_map); 862 sc->vge_ldata.vge_rx_list = NULL; 863 return error; 864 } 865 866 /* Create DMA maps for RX buffers */ 867 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 868 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 869 &sc->vge_ldata.vge_rx_dmamap[i]); 870 if (error) { 871 device_printf(dev, "can't create DMA map for RX\n"); 872 rx_pos = i; 873 goto map_fail; 874 } 875 } 876 return (0); 877 878 map_fail: 879 for (i = 0; i < tx_pos; ++i) { 880 error = bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 881 sc->vge_ldata.vge_tx_dmamap[i]); 882 } 883 for (i = 0; i < rx_pos; ++i) { 884 error = bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 885 sc->vge_ldata.vge_rx_dmamap[i]); 886 } 887 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 888 sc->vge_ldata.vge_mtag = NULL; 889 890 return error; 891 } 892 893 static void 894 vge_dma_free(struct vge_softc *sc) 895 { 896 /* Unload and free the RX DMA ring memory and map */ 897 if (sc->vge_ldata.vge_rx_list_tag) { 898 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 899 sc->vge_ldata.vge_rx_list_map); 900 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 901 sc->vge_ldata.vge_rx_list, 902 sc->vge_ldata.vge_rx_list_map); 903 } 904 905 if (sc->vge_ldata.vge_rx_list_tag) 906 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 907 908 /* Unload and free the TX DMA ring memory and map */ 909 if (sc->vge_ldata.vge_tx_list_tag) { 910 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 911 sc->vge_ldata.vge_tx_list_map); 912 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 913 sc->vge_ldata.vge_tx_list, 914 sc->vge_ldata.vge_tx_list_map); 915 } 916 917 if (sc->vge_ldata.vge_tx_list_tag) 918 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 919 920 /* Destroy all the RX and TX buffer maps */ 921 if (sc->vge_ldata.vge_mtag) { 922 int i; 923 924 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 925 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 926 sc->vge_ldata.vge_tx_dmamap[i]); 927 } 928 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 929 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 930 sc->vge_ldata.vge_rx_dmamap[i]); 931 } 932 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 933 } 934 935 if (sc->vge_parent_tag) 936 bus_dma_tag_destroy(sc->vge_parent_tag); 937 } 938 939 /* 940 * Attach the interface. Allocate softc structures, do ifmedia 941 * setup and ethernet/BPF attach. 942 */ 943 static int 944 vge_attach(device_t dev) 945 { 946 uint8_t eaddr[ETHER_ADDR_LEN]; 947 struct vge_softc *sc; 948 struct ifnet *ifp; 949 int error = 0; 950 951 sc = device_get_softc(dev); 952 ifp = &sc->arpcom.ac_if; 953 954 /* Initialize if_xname early, so if_printf() can be used */ 955 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 956 957 /* 958 * Map control/status registers. 959 */ 960 pci_enable_busmaster(dev); 961 962 sc->vge_res_rid = VGE_PCI_LOMEM; 963 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 964 &sc->vge_res_rid, RF_ACTIVE); 965 if (sc->vge_res == NULL) { 966 device_printf(dev, "couldn't map ports/memory\n"); 967 return ENXIO; 968 } 969 970 sc->vge_btag = rman_get_bustag(sc->vge_res); 971 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 972 973 /* Allocate interrupt */ 974 sc->vge_irq_rid = 0; 975 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->vge_irq_rid, 976 RF_SHAREABLE | RF_ACTIVE); 977 if (sc->vge_irq == NULL) { 978 device_printf(dev, "couldn't map interrupt\n"); 979 error = ENXIO; 980 goto fail; 981 } 982 983 /* Reset the adapter. */ 984 vge_reset(sc); 985 986 /* 987 * Get station address from the EEPROM. 988 */ 989 vge_read_eeprom(sc, eaddr, VGE_EE_EADDR, 3, 0); 990 991 /* Allocate DMA related stuffs */ 992 error = vge_dma_alloc(dev); 993 if (error) 994 goto fail; 995 996 /* Do MII setup */ 997 error = mii_phy_probe(dev, &sc->vge_miibus, vge_ifmedia_upd, 998 vge_ifmedia_sts); 999 if (error) { 1000 device_printf(dev, "MII without any phy!\n"); 1001 goto fail; 1002 } 1003 1004 ifp->if_softc = sc; 1005 ifp->if_mtu = ETHERMTU; 1006 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1007 ifp->if_init = vge_init; 1008 ifp->if_start = vge_start; 1009 ifp->if_watchdog = vge_watchdog; 1010 ifp->if_ioctl = vge_ioctl; 1011 #ifdef DEVICE_POLLING 1012 ifp->if_poll = vge_poll; 1013 #endif 1014 ifp->if_hwassist = VGE_CSUM_FEATURES; 1015 ifp->if_capabilities = IFCAP_VLAN_MTU | 1016 IFCAP_HWCSUM | 1017 IFCAP_VLAN_HWTAGGING; 1018 ifp->if_capenable = ifp->if_capabilities; 1019 ifq_set_maxlen(&ifp->if_snd, VGE_IFQ_MAXLEN); 1020 ifq_set_ready(&ifp->if_snd); 1021 1022 /* 1023 * Call MI attach routine. 1024 */ 1025 ether_ifattach(ifp, eaddr, NULL); 1026 1027 /* Hook interrupt last to avoid having to lock softc */ 1028 error = bus_setup_intr(dev, sc->vge_irq, INTR_MPSAFE, vge_intr, sc, 1029 &sc->vge_intrhand, ifp->if_serializer); 1030 if (error) { 1031 device_printf(dev, "couldn't set up irq\n"); 1032 ether_ifdetach(ifp); 1033 goto fail; 1034 } 1035 1036 return 0; 1037 fail: 1038 vge_detach(dev); 1039 return error; 1040 } 1041 1042 /* 1043 * Shutdown hardware and free up resources. This can be called any 1044 * time after the mutex has been initialized. It is called in both 1045 * the error case in attach and the normal detach case so it needs 1046 * to be careful about only freeing resources that have actually been 1047 * allocated. 1048 */ 1049 static int 1050 vge_detach(device_t dev) 1051 { 1052 struct vge_softc *sc = device_get_softc(dev); 1053 struct ifnet *ifp = &sc->arpcom.ac_if; 1054 1055 /* These should only be active if attach succeeded */ 1056 if (device_is_attached(dev)) { 1057 lwkt_serialize_enter(ifp->if_serializer); 1058 1059 vge_stop(sc); 1060 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1061 /* 1062 * Force off the IFF_UP flag here, in case someone 1063 * still had a BPF descriptor attached to this 1064 * interface. If they do, ether_ifattach() will cause 1065 * the BPF code to try and clear the promisc mode 1066 * flag, which will bubble down to vge_ioctl(), 1067 * which will try to call vge_init() again. This will 1068 * turn the NIC back on and restart the MII ticker, 1069 * which will panic the system when the kernel tries 1070 * to invoke the vge_tick() function that isn't there 1071 * anymore. 1072 */ 1073 ifp->if_flags &= ~IFF_UP; 1074 1075 lwkt_serialize_exit(ifp->if_serializer); 1076 1077 ether_ifdetach(ifp); 1078 } 1079 1080 if (sc->vge_miibus) 1081 device_delete_child(dev, sc->vge_miibus); 1082 bus_generic_detach(dev); 1083 1084 if (sc->vge_irq) { 1085 bus_release_resource(dev, SYS_RES_IRQ, sc->vge_irq_rid, 1086 sc->vge_irq); 1087 } 1088 1089 if (sc->vge_res) { 1090 bus_release_resource(dev, SYS_RES_MEMORY, sc->vge_res_rid, 1091 sc->vge_res); 1092 } 1093 1094 vge_dma_free(sc); 1095 return (0); 1096 } 1097 1098 static int 1099 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 1100 { 1101 struct vge_dmaload_arg arg; 1102 struct mbuf *n = NULL; 1103 int i, error; 1104 1105 if (m == NULL) { 1106 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1107 if (n == NULL) 1108 return (ENOBUFS); 1109 m = n; 1110 } else { 1111 m->m_data = m->m_ext.ext_buf; 1112 } 1113 1114 1115 #ifdef VGE_FIXUP_RX 1116 /* 1117 * This is part of an evil trick to deal with non-x86 platforms. 1118 * The VIA chip requires RX buffers to be aligned on 32-bit 1119 * boundaries, but that will hose non-x86 machines. To get around 1120 * this, we leave some empty space at the start of each buffer 1121 * and for non-x86 hosts, we copy the buffer back two bytes 1122 * to achieve word alignment. This is slightly more efficient 1123 * than allocating a new buffer, copying the contents, and 1124 * discarding the old buffer. 1125 */ 1126 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1127 m_adj(m, VGE_ETHER_ALIGN); 1128 #else 1129 m->m_len = m->m_pkthdr.len = MCLBYTES; 1130 #endif 1131 1132 arg.sc = sc; 1133 arg.vge_idx = idx; 1134 arg.vge_maxsegs = 1; 1135 arg.vge_flags = 0; 1136 1137 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1138 sc->vge_ldata.vge_rx_dmamap[idx], m, 1139 vge_dma_map_rx_desc, &arg, BUS_DMA_NOWAIT); 1140 if (error || arg.vge_maxsegs != 1) { 1141 if (n != NULL) 1142 m_freem(n); 1143 return (ENOMEM); 1144 } 1145 1146 /* 1147 * Note: the manual fails to document the fact that for 1148 * proper opration, the driver needs to replentish the RX 1149 * DMA ring 4 descriptors at a time (rather than one at a 1150 * time, like most chips). We can allocate the new buffers 1151 * but we should not set the OWN bits until we're ready 1152 * to hand back 4 of them in one shot. 1153 */ 1154 1155 #define VGE_RXCHUNK 4 1156 sc->vge_rx_consumed++; 1157 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1158 for (i = idx; i != idx - sc->vge_rx_consumed; i--) { 1159 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1160 htole32(VGE_RDSTS_OWN); 1161 } 1162 sc->vge_rx_consumed = 0; 1163 } 1164 1165 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1166 1167 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1168 sc->vge_ldata.vge_rx_dmamap[idx], BUS_DMASYNC_PREREAD); 1169 1170 return (0); 1171 } 1172 1173 static int 1174 vge_tx_list_init(struct vge_softc *sc) 1175 { 1176 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1177 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1178 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1179 1180 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1181 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1182 sc->vge_ldata.vge_tx_prodidx = 0; 1183 sc->vge_ldata.vge_tx_considx = 0; 1184 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1185 1186 return (0); 1187 } 1188 1189 static int 1190 vge_rx_list_init(struct vge_softc *sc) 1191 { 1192 int i; 1193 1194 bzero(sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1195 bzero(&sc->vge_ldata.vge_rx_mbuf, 1196 VGE_RX_DESC_CNT * sizeof(struct mbuf *)); 1197 1198 sc->vge_rx_consumed = 0; 1199 1200 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1201 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1202 return (ENOBUFS); 1203 } 1204 1205 /* Flush the RX descriptors */ 1206 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1207 sc->vge_ldata.vge_rx_list_map, 1208 BUS_DMASYNC_PREWRITE); 1209 1210 sc->vge_ldata.vge_rx_prodidx = 0; 1211 sc->vge_rx_consumed = 0; 1212 sc->vge_head = sc->vge_tail = NULL; 1213 return (0); 1214 } 1215 1216 #ifdef VGE_FIXUP_RX 1217 static __inline void 1218 vge_fixup_rx(struct mbuf *m) 1219 { 1220 uint16_t *src, *dst; 1221 int i; 1222 1223 src = mtod(m, uint16_t *); 1224 dst = src - 1; 1225 1226 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1227 *dst++ = *src++; 1228 1229 m->m_data -= ETHER_ALIGN; 1230 } 1231 #endif 1232 1233 /* 1234 * RX handler. We support the reception of jumbo frames that have 1235 * been fragmented across multiple 2K mbuf cluster buffers. 1236 */ 1237 static void 1238 vge_rxeof(struct vge_softc *sc, int count) 1239 { 1240 struct ifnet *ifp = &sc->arpcom.ac_if; 1241 struct mbuf *m; 1242 int i, total_len, lim = 0; 1243 struct vge_rx_desc *cur_rx; 1244 uint32_t rxstat, rxctl; 1245 1246 ASSERT_SERIALIZED(ifp->if_serializer); 1247 1248 i = sc->vge_ldata.vge_rx_prodidx; 1249 1250 /* Invalidate the descriptor memory */ 1251 1252 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1253 sc->vge_ldata.vge_rx_list_map, BUS_DMASYNC_POSTREAD); 1254 1255 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1256 #ifdef DEVICE_POLLING 1257 if (count >= 0 && count-- == 0) 1258 break; 1259 #endif 1260 1261 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1262 m = sc->vge_ldata.vge_rx_mbuf[i]; 1263 total_len = VGE_RXBYTES(cur_rx); 1264 rxstat = le32toh(cur_rx->vge_sts); 1265 rxctl = le32toh(cur_rx->vge_ctl); 1266 1267 /* Invalidate the RX mbuf and unload its map */ 1268 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1269 sc->vge_ldata.vge_rx_dmamap[i], 1270 BUS_DMASYNC_POSTWRITE); 1271 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1272 sc->vge_ldata.vge_rx_dmamap[i]); 1273 1274 /* 1275 * If the 'start of frame' bit is set, this indicates 1276 * either the first fragment in a multi-fragment receive, 1277 * or an intermediate fragment. Either way, we want to 1278 * accumulate the buffers. 1279 */ 1280 if (rxstat & VGE_RXPKT_SOF) { 1281 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1282 if (sc->vge_head == NULL) { 1283 sc->vge_head = sc->vge_tail = m; 1284 } else { 1285 m->m_flags &= ~M_PKTHDR; 1286 sc->vge_tail->m_next = m; 1287 sc->vge_tail = m; 1288 } 1289 vge_newbuf(sc, i, NULL); 1290 VGE_RX_DESC_INC(i); 1291 continue; 1292 } 1293 1294 /* 1295 * Bad/error frames will have the RXOK bit cleared. 1296 * However, there's one error case we want to allow: 1297 * if a VLAN tagged frame arrives and the chip can't 1298 * match it against the CAM filter, it considers this 1299 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1300 * We don't want to drop the frame though: our VLAN 1301 * filtering is done in software. 1302 */ 1303 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) && 1304 !(rxstat & VGE_RDSTS_CSUMERR)) { 1305 ifp->if_ierrors++; 1306 /* 1307 * If this is part of a multi-fragment packet, 1308 * discard all the pieces. 1309 */ 1310 if (sc->vge_head != NULL) { 1311 m_freem(sc->vge_head); 1312 sc->vge_head = sc->vge_tail = NULL; 1313 } 1314 vge_newbuf(sc, i, m); 1315 VGE_RX_DESC_INC(i); 1316 continue; 1317 } 1318 1319 /* 1320 * If allocating a replacement mbuf fails, 1321 * reload the current one. 1322 */ 1323 if (vge_newbuf(sc, i, NULL)) { 1324 ifp->if_ierrors++; 1325 if (sc->vge_head != NULL) { 1326 m_freem(sc->vge_head); 1327 sc->vge_head = sc->vge_tail = NULL; 1328 } 1329 vge_newbuf(sc, i, m); 1330 VGE_RX_DESC_INC(i); 1331 continue; 1332 } 1333 1334 VGE_RX_DESC_INC(i); 1335 1336 if (sc->vge_head != NULL) { 1337 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1338 /* 1339 * Special case: if there's 4 bytes or less 1340 * in this buffer, the mbuf can be discarded: 1341 * the last 4 bytes is the CRC, which we don't 1342 * care about anyway. 1343 */ 1344 if (m->m_len <= ETHER_CRC_LEN) { 1345 sc->vge_tail->m_len -= 1346 (ETHER_CRC_LEN - m->m_len); 1347 m_freem(m); 1348 } else { 1349 m->m_len -= ETHER_CRC_LEN; 1350 m->m_flags &= ~M_PKTHDR; 1351 sc->vge_tail->m_next = m; 1352 } 1353 m = sc->vge_head; 1354 sc->vge_head = sc->vge_tail = NULL; 1355 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1356 } else { 1357 m->m_pkthdr.len = m->m_len = 1358 (total_len - ETHER_CRC_LEN); 1359 } 1360 1361 #ifdef VGE_FIXUP_RX 1362 vge_fixup_rx(m); 1363 #endif 1364 ifp->if_ipackets++; 1365 m->m_pkthdr.rcvif = ifp; 1366 1367 /* Do RX checksumming if enabled */ 1368 if (ifp->if_capenable & IFCAP_RXCSUM) { 1369 /* Check IP header checksum */ 1370 if (rxctl & VGE_RDCTL_IPPKT) 1371 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1372 if (rxctl & VGE_RDCTL_IPCSUMOK) 1373 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1374 1375 /* Check TCP/UDP checksum */ 1376 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1377 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1378 m->m_pkthdr.csum_flags |= 1379 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 1380 CSUM_FRAG_NOT_CHECKED; 1381 m->m_pkthdr.csum_data = 0xffff; 1382 } 1383 } 1384 1385 if (rxstat & VGE_RDSTS_VTAG) 1386 VLAN_INPUT_TAG(m, ntohs((rxctl & VGE_RDCTL_VLANID))); 1387 else 1388 ifp->if_input(ifp, m); 1389 1390 lim++; 1391 if (lim == VGE_RX_DESC_CNT) 1392 break; 1393 } 1394 1395 /* Flush the RX DMA ring */ 1396 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1397 sc->vge_ldata.vge_rx_list_map, 1398 BUS_DMASYNC_PREWRITE); 1399 1400 sc->vge_ldata.vge_rx_prodidx = i; 1401 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1402 } 1403 1404 static void 1405 vge_txeof(struct vge_softc *sc) 1406 { 1407 struct ifnet *ifp = &sc->arpcom.ac_if; 1408 uint32_t txstat; 1409 int idx; 1410 1411 idx = sc->vge_ldata.vge_tx_considx; 1412 1413 /* Invalidate the TX descriptor list */ 1414 1415 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1416 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_POSTREAD); 1417 1418 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1419 1420 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1421 if (txstat & VGE_TDSTS_OWN) 1422 break; 1423 1424 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1425 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1426 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1427 sc->vge_ldata.vge_tx_dmamap[idx]); 1428 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1429 ifp->if_collisions++; 1430 if (txstat & VGE_TDSTS_TXERR) 1431 ifp->if_oerrors++; 1432 else 1433 ifp->if_opackets++; 1434 1435 sc->vge_ldata.vge_tx_free++; 1436 VGE_TX_DESC_INC(idx); 1437 } 1438 1439 /* No changes made to the TX ring, so no flush needed */ 1440 if (idx != sc->vge_ldata.vge_tx_considx) { 1441 sc->vge_ldata.vge_tx_considx = idx; 1442 ifp->if_flags &= ~IFF_OACTIVE; 1443 ifp->if_timer = 0; 1444 } 1445 1446 /* 1447 * If not all descriptors have been released reaped yet, 1448 * reload the timer so that we will eventually get another 1449 * interrupt that will cause us to re-enter this routine. 1450 * This is done in case the transmitter has gone idle. 1451 */ 1452 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1453 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1454 } 1455 1456 static void 1457 vge_tick(struct vge_softc *sc) 1458 { 1459 struct ifnet *ifp = &sc->arpcom.ac_if; 1460 struct mii_data *mii; 1461 1462 mii = device_get_softc(sc->vge_miibus); 1463 1464 mii_tick(mii); 1465 if (sc->vge_link) { 1466 if (!(mii->mii_media_status & IFM_ACTIVE)) 1467 sc->vge_link = 0; 1468 } else { 1469 if (mii->mii_media_status & IFM_ACTIVE && 1470 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1471 sc->vge_link = 1; 1472 if (!ifq_is_empty(&ifp->if_snd)) 1473 ifp->if_start(ifp); 1474 } 1475 } 1476 } 1477 1478 #ifdef DEVICE_POLLING 1479 static void 1480 vge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1481 { 1482 struct vge_softc *sc = ifp->if_softc; 1483 1484 sc->rxcycles = count; 1485 1486 switch (cmd) { 1487 case POLL_REGISTER: 1488 vge_disable_intr(sc); 1489 break; 1490 case POLL_DEREGISTER: 1491 vge_enable_intr(sc, 0xffffffff); 1492 break; 1493 case POLL_ONLY: 1494 case POLL_AND_CHECK_STATUS: 1495 vge_rxeof(sc, count); 1496 vge_txeof(sc); 1497 1498 if (!ifq_is_empty(&ifp->if_snd)) 1499 ifp->if_start(ifp); 1500 1501 /* XXX copy & paste from vge_intr */ 1502 if (cmd == POLL_AND_CHECK_STATUS) { 1503 uint32_t status = 0; 1504 1505 status = CSR_READ_4(sc, VGE_ISR); 1506 if (status == 0xffffffff) 1507 break; 1508 1509 if (status) 1510 CSR_WRITE_4(sc, VGE_ISR, status); 1511 1512 if (status & (VGE_ISR_TXDMA_STALL | 1513 VGE_ISR_RXDMA_STALL)) 1514 vge_init(sc); 1515 1516 if (status & (VGE_ISR_RXOFLOW | VGE_ISR_RXNODESC)) { 1517 ifp->if_ierrors++; 1518 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1519 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1520 } 1521 } 1522 break; 1523 } 1524 1525 } 1526 #endif /* DEVICE_POLLING */ 1527 1528 static void 1529 vge_intr(void *arg) 1530 { 1531 struct vge_softc *sc = arg; 1532 struct ifnet *ifp = &sc->arpcom.ac_if; 1533 uint32_t status; 1534 1535 if (sc->suspended || !(ifp->if_flags & IFF_UP)) 1536 return; 1537 1538 /* Disable interrupts */ 1539 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1540 1541 for (;;) { 1542 status = CSR_READ_4(sc, VGE_ISR); 1543 /* If the card has gone away the read returns 0xffff. */ 1544 if (status == 0xFFFFFFFF) 1545 break; 1546 1547 if (status) 1548 CSR_WRITE_4(sc, VGE_ISR, status); 1549 1550 if ((status & VGE_INTRS) == 0) 1551 break; 1552 1553 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1554 vge_rxeof(sc, -1); 1555 1556 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1557 vge_rxeof(sc, -1); 1558 ifp->if_ierrors++; 1559 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1560 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1561 } 1562 1563 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1564 vge_txeof(sc); 1565 1566 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1567 vge_init(sc); 1568 1569 if (status & VGE_ISR_LINKSTS) 1570 vge_tick(sc); 1571 } 1572 1573 /* Re-enable interrupts */ 1574 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1575 1576 if (!ifq_is_empty(&ifp->if_snd)) 1577 ifp->if_start(ifp); 1578 } 1579 1580 static int 1581 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1582 { 1583 struct vge_dmaload_arg arg; 1584 bus_dmamap_t map; 1585 int error; 1586 1587 arg.vge_flags = 0; 1588 1589 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1590 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1591 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1592 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1593 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1594 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1595 1596 arg.sc = sc; 1597 arg.vge_idx = idx; 1598 arg.vge_m0 = m_head; 1599 arg.vge_maxsegs = VGE_TX_FRAGS; 1600 1601 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1602 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, m_head, 1603 vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1604 if (error && error != EFBIG) { 1605 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 1606 error); 1607 goto fail; 1608 } 1609 1610 /* Too many segments to map, coalesce into a single mbuf */ 1611 if (error || arg.vge_maxsegs == 0) { 1612 struct mbuf *m_new; 1613 1614 m_new = m_defrag(m_head, MB_DONTWAIT); 1615 if (m_new == NULL) { 1616 error = ENOBUFS; 1617 goto fail; 1618 } else { 1619 m_head = m_new; 1620 } 1621 1622 arg.sc = sc; 1623 arg.vge_m0 = m_head; 1624 arg.vge_idx = idx; 1625 arg.vge_maxsegs = 1; 1626 1627 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1628 m_head, vge_dma_map_tx_desc, &arg, 1629 BUS_DMA_NOWAIT); 1630 if (error) { 1631 if_printf(&sc->arpcom.ac_if, 1632 "can't map mbuf (error %d)\n", error); 1633 goto fail; 1634 } 1635 } 1636 1637 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1638 sc->vge_ldata.vge_tx_free--; 1639 1640 /* 1641 * Set up hardware VLAN tagging. 1642 */ 1643 if (m_head->m_flags & M_VLANTAG) { 1644 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1645 htole32(htons(m_head->m_pkthdr.ether_vlantag) | 1646 VGE_TDCTL_VTAG); 1647 } 1648 1649 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1650 return (0); 1651 1652 fail: 1653 m_freem(m_head); 1654 return error; 1655 } 1656 1657 /* 1658 * Main transmit routine. 1659 */ 1660 1661 static void 1662 vge_start(struct ifnet *ifp) 1663 { 1664 struct vge_softc *sc = ifp->if_softc; 1665 struct mbuf *m_head = NULL; 1666 int idx, pidx = 0; 1667 1668 ASSERT_SERIALIZED(ifp->if_serializer); 1669 1670 if (!sc->vge_link || (ifp->if_flags & IFF_OACTIVE)) 1671 return; 1672 1673 if (ifq_is_empty(&ifp->if_snd)) 1674 return; 1675 1676 idx = sc->vge_ldata.vge_tx_prodidx; 1677 1678 pidx = idx - 1; 1679 if (pidx < 0) 1680 pidx = VGE_TX_DESC_CNT - 1; 1681 1682 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1683 m_head = ifq_poll(&ifp->if_snd); 1684 if (m_head == NULL) 1685 break; 1686 1687 if (sc->vge_ldata.vge_tx_free <= 2) { 1688 ifp->if_flags |= IFF_OACTIVE; 1689 break; 1690 } 1691 1692 m_head = ifq_dequeue(&ifp->if_snd, m_head); 1693 1694 if (vge_encap(sc, m_head, idx)) { 1695 /* If vge_encap() failed, it will free m_head for us */ 1696 ifp->if_flags |= IFF_OACTIVE; 1697 break; 1698 } 1699 1700 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1701 htole16(VGE_TXDESC_Q); 1702 1703 pidx = idx; 1704 VGE_TX_DESC_INC(idx); 1705 1706 /* 1707 * If there's a BPF listener, bounce a copy of this frame 1708 * to him. 1709 */ 1710 ETHER_BPF_MTAP(ifp, m_head); 1711 } 1712 1713 if (idx == sc->vge_ldata.vge_tx_prodidx) 1714 return; 1715 1716 /* Flush the TX descriptors */ 1717 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1718 sc->vge_ldata.vge_tx_list_map, 1719 BUS_DMASYNC_PREWRITE); 1720 1721 /* Issue a transmit command. */ 1722 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1723 1724 sc->vge_ldata.vge_tx_prodidx = idx; 1725 1726 /* 1727 * Use the countdown timer for interrupt moderation. 1728 * 'TX done' interrupts are disabled. Instead, we reset the 1729 * countdown timer, which will begin counting until it hits 1730 * the value in the SSTIMER register, and then trigger an 1731 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1732 * the timer count is reloaded. Only when the transmitter 1733 * is idle will the timer hit 0 and an interrupt fire. 1734 */ 1735 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1736 1737 /* 1738 * Set a timeout in case the chip goes out to lunch. 1739 */ 1740 ifp->if_timer = 5; 1741 } 1742 1743 static void 1744 vge_init(void *xsc) 1745 { 1746 struct vge_softc *sc = xsc; 1747 struct ifnet *ifp = &sc->arpcom.ac_if; 1748 struct mii_data *mii; 1749 int i; 1750 1751 ASSERT_SERIALIZED(ifp->if_serializer); 1752 1753 mii = device_get_softc(sc->vge_miibus); 1754 1755 /* 1756 * Cancel pending I/O and free all RX/TX buffers. 1757 */ 1758 vge_stop(sc); 1759 vge_reset(sc); 1760 1761 /* 1762 * Initialize the RX and TX descriptors and mbufs. 1763 */ 1764 vge_rx_list_init(sc); 1765 vge_tx_list_init(sc); 1766 1767 /* Set our station address */ 1768 for (i = 0; i < ETHER_ADDR_LEN; i++) 1769 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(ifp)[i]); 1770 1771 /* 1772 * Set receive FIFO threshold. Also allow transmission and 1773 * reception of VLAN tagged frames. 1774 */ 1775 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1776 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1777 1778 /* Set DMA burst length */ 1779 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1780 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1781 1782 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1783 1784 /* Set collision backoff algorithm */ 1785 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1786 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1787 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1788 1789 /* Disable LPSEL field in priority resolution */ 1790 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1791 1792 /* 1793 * Load the addresses of the DMA queues into the chip. 1794 * Note that we only use one transmit queue. 1795 */ 1796 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1797 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1798 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1799 1800 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1801 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1802 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1803 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1804 1805 /* Enable and wake up the RX descriptor queue */ 1806 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1807 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1808 1809 /* Enable the TX descriptor queue */ 1810 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1811 1812 /* Set up the receive filter -- allow large frames for VLANs. */ 1813 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1814 1815 /* If we want promiscuous mode, set the allframes bit. */ 1816 if (ifp->if_flags & IFF_PROMISC) 1817 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1818 1819 /* Set capture broadcast bit to capture broadcast frames. */ 1820 if (ifp->if_flags & IFF_BROADCAST) 1821 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1822 1823 /* Set multicast bit to capture multicast frames. */ 1824 if (ifp->if_flags & IFF_MULTICAST) 1825 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1826 1827 /* Init the cam filter. */ 1828 vge_cam_clear(sc); 1829 1830 /* Init the multicast filter. */ 1831 vge_setmulti(sc); 1832 1833 /* Enable flow control */ 1834 1835 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1836 1837 /* Enable jumbo frame reception (if desired) */ 1838 1839 /* Start the MAC. */ 1840 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1841 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1842 CSR_WRITE_1(sc, VGE_CRS0, 1843 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1844 1845 /* 1846 * Configure one-shot timer for microsecond 1847 * resulution and load it for 500 usecs. 1848 */ 1849 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1850 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1851 1852 /* 1853 * Configure interrupt moderation for receive. Enable 1854 * the holdoff counter and load it, and set the RX 1855 * suppression count to the number of descriptors we 1856 * want to allow before triggering an interrupt. 1857 * The holdoff timer is in units of 20 usecs. 1858 */ 1859 1860 #ifdef notyet 1861 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1862 /* Select the interrupt holdoff timer page. */ 1863 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1864 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1865 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1866 1867 /* Enable use of the holdoff timer. */ 1868 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1869 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1870 1871 /* Select the RX suppression threshold page. */ 1872 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1873 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1874 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1875 1876 /* Restore the page select bits. */ 1877 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1878 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1879 #endif 1880 1881 #ifdef DEVICE_POLLING 1882 /* Disable intr if polling(4) is enabled */ 1883 if (ifp->if_flags & IFF_POLLING) 1884 vge_disable_intr(sc); 1885 else 1886 #endif 1887 vge_enable_intr(sc, 0); 1888 1889 mii_mediachg(mii); 1890 1891 ifp->if_flags |= IFF_RUNNING; 1892 ifp->if_flags &= ~IFF_OACTIVE; 1893 1894 sc->vge_if_flags = 0; 1895 sc->vge_link = 0; 1896 } 1897 1898 /* 1899 * Set media options. 1900 */ 1901 static int 1902 vge_ifmedia_upd(struct ifnet *ifp) 1903 { 1904 struct vge_softc *sc = ifp->if_softc; 1905 struct mii_data *mii = device_get_softc(sc->vge_miibus); 1906 1907 mii_mediachg(mii); 1908 1909 return (0); 1910 } 1911 1912 /* 1913 * Report current media status. 1914 */ 1915 static void 1916 vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1917 { 1918 struct vge_softc *sc = ifp->if_softc; 1919 struct mii_data *mii = device_get_softc(sc->vge_miibus); 1920 1921 mii_pollstat(mii); 1922 ifmr->ifm_active = mii->mii_media_active; 1923 ifmr->ifm_status = mii->mii_media_status; 1924 } 1925 1926 static void 1927 vge_miibus_statchg(device_t dev) 1928 { 1929 struct vge_softc *sc; 1930 struct mii_data *mii; 1931 struct ifmedia_entry *ife; 1932 1933 sc = device_get_softc(dev); 1934 mii = device_get_softc(sc->vge_miibus); 1935 ife = mii->mii_media.ifm_cur; 1936 1937 /* 1938 * If the user manually selects a media mode, we need to turn 1939 * on the forced MAC mode bit in the DIAGCTL register. If the 1940 * user happens to choose a full duplex mode, we also need to 1941 * set the 'force full duplex' bit. This applies only to 1942 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1943 * mode is disabled, and in 1000baseT mode, full duplex is 1944 * always implied, so we turn on the forced mode bit but leave 1945 * the FDX bit cleared. 1946 */ 1947 1948 switch (IFM_SUBTYPE(ife->ifm_media)) { 1949 case IFM_AUTO: 1950 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1951 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1952 break; 1953 case IFM_1000_T: 1954 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1955 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1956 break; 1957 case IFM_100_TX: 1958 case IFM_10_T: 1959 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1960 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) 1961 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1962 else 1963 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1964 break; 1965 default: 1966 device_printf(dev, "unknown media type: %x\n", 1967 IFM_SUBTYPE(ife->ifm_media)); 1968 break; 1969 } 1970 } 1971 1972 static int 1973 vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1974 { 1975 struct vge_softc *sc = ifp->if_softc; 1976 struct ifreq *ifr = (struct ifreq *)data; 1977 struct mii_data *mii; 1978 int error = 0; 1979 1980 switch (command) { 1981 case SIOCSIFMTU: 1982 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 1983 error = EINVAL; 1984 ifp->if_mtu = ifr->ifr_mtu; 1985 break; 1986 case SIOCSIFFLAGS: 1987 if (ifp->if_flags & IFF_UP) { 1988 if ((ifp->if_flags & IFF_RUNNING) && 1989 (ifp->if_flags & IFF_PROMISC) && 1990 !(sc->vge_if_flags & IFF_PROMISC)) { 1991 CSR_SETBIT_1(sc, VGE_RXCTL, 1992 VGE_RXCTL_RX_PROMISC); 1993 vge_setmulti(sc); 1994 } else if ((ifp->if_flags & IFF_RUNNING) && 1995 !(ifp->if_flags & IFF_PROMISC) && 1996 (sc->vge_if_flags & IFF_PROMISC)) { 1997 CSR_CLRBIT_1(sc, VGE_RXCTL, 1998 VGE_RXCTL_RX_PROMISC); 1999 vge_setmulti(sc); 2000 } else { 2001 vge_init(sc); 2002 } 2003 } else { 2004 if (ifp->if_flags & IFF_RUNNING) 2005 vge_stop(sc); 2006 } 2007 sc->vge_if_flags = ifp->if_flags; 2008 break; 2009 case SIOCADDMULTI: 2010 case SIOCDELMULTI: 2011 vge_setmulti(sc); 2012 break; 2013 case SIOCGIFMEDIA: 2014 case SIOCSIFMEDIA: 2015 mii = device_get_softc(sc->vge_miibus); 2016 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2017 break; 2018 case SIOCSIFCAP: 2019 { 2020 uint32_t mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2021 2022 if (mask & IFCAP_HWCSUM) { 2023 ifp->if_capenable |= ifr->ifr_reqcap & (IFCAP_HWCSUM); 2024 if (ifp->if_capenable & IFCAP_TXCSUM) 2025 ifp->if_hwassist = VGE_CSUM_FEATURES; 2026 else 2027 ifp->if_hwassist = 0; 2028 if (ifp->if_flags & IFF_RUNNING) 2029 vge_init(sc); 2030 } 2031 } 2032 break; 2033 default: 2034 error = ether_ioctl(ifp, command, data); 2035 break; 2036 } 2037 return (error); 2038 } 2039 2040 static void 2041 vge_watchdog(struct ifnet *ifp) 2042 { 2043 struct vge_softc *sc = ifp->if_softc; 2044 2045 if_printf(ifp, "watchdog timeout\n"); 2046 ifp->if_oerrors++; 2047 2048 vge_txeof(sc); 2049 vge_rxeof(sc, -1); 2050 2051 vge_init(sc); 2052 } 2053 2054 /* 2055 * Stop the adapter and free any mbufs allocated to the 2056 * RX and TX lists. 2057 */ 2058 static void 2059 vge_stop(struct vge_softc *sc) 2060 { 2061 struct ifnet *ifp = &sc->arpcom.ac_if; 2062 int i; 2063 2064 ASSERT_SERIALIZED(ifp->if_serializer); 2065 2066 ifp->if_timer = 0; 2067 2068 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2069 2070 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2071 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2072 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2073 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2074 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2075 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2076 2077 if (sc->vge_head != NULL) { 2078 m_freem(sc->vge_head); 2079 sc->vge_head = sc->vge_tail = NULL; 2080 } 2081 2082 /* Free the TX list buffers. */ 2083 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2084 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2085 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2086 sc->vge_ldata.vge_tx_dmamap[i]); 2087 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2088 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2089 } 2090 } 2091 2092 /* Free the RX list buffers. */ 2093 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2094 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2095 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2096 sc->vge_ldata.vge_rx_dmamap[i]); 2097 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2098 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2099 } 2100 } 2101 } 2102 2103 /* 2104 * Device suspend routine. Stop the interface and save some PCI 2105 * settings in case the BIOS doesn't restore them properly on 2106 * resume. 2107 */ 2108 static int 2109 vge_suspend(device_t dev) 2110 { 2111 struct vge_softc *sc = device_get_softc(dev); 2112 struct ifnet *ifp = &sc->arpcom.ac_if; 2113 2114 lwkt_serialize_enter(ifp->if_serializer); 2115 vge_stop(sc); 2116 sc->suspended = 1; 2117 lwkt_serialize_exit(ifp->if_serializer); 2118 2119 return (0); 2120 } 2121 2122 /* 2123 * Device resume routine. Restore some PCI settings in case the BIOS 2124 * doesn't, re-enable busmastering, and restart the interface if 2125 * appropriate. 2126 */ 2127 static int 2128 vge_resume(device_t dev) 2129 { 2130 struct vge_softc *sc = device_get_softc(dev); 2131 struct ifnet *ifp = &sc->arpcom.ac_if; 2132 2133 /* reenable busmastering */ 2134 pci_enable_busmaster(dev); 2135 pci_enable_io(dev, SYS_RES_MEMORY); 2136 2137 lwkt_serialize_enter(ifp->if_serializer); 2138 /* reinitialize interface if necessary */ 2139 if (ifp->if_flags & IFF_UP) 2140 vge_init(sc); 2141 2142 sc->suspended = 0; 2143 lwkt_serialize_exit(ifp->if_serializer); 2144 2145 return (0); 2146 } 2147 2148 /* 2149 * Stop all chip I/O so that the kernel's probe routines don't 2150 * get confused by errant DMAs when rebooting. 2151 */ 2152 static void 2153 vge_shutdown(device_t dev) 2154 { 2155 struct vge_softc *sc = device_get_softc(dev); 2156 struct ifnet *ifp = &sc->arpcom.ac_if; 2157 2158 lwkt_serialize_enter(ifp->if_serializer); 2159 vge_stop(sc); 2160 lwkt_serialize_exit(ifp->if_serializer); 2161 } 2162 2163 static void 2164 vge_enable_intr(struct vge_softc *sc, uint32_t isr) 2165 { 2166 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2167 CSR_WRITE_4(sc, VGE_ISR, isr); 2168 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2169 } 2170 2171 #ifdef DEVICE_POLLING 2172 static void 2173 vge_disable_intr(struct vge_softc *sc) 2174 { 2175 CSR_WRITE_4(sc, VGE_IMR, 0); 2176 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2177 } 2178 #endif 2179