1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/tl/if_tl.c,v 1.22 2005/06/10 16:19:41 joerg Exp $ 34 */ 35 36 /* 37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 39 * the National Semiconductor DP83840A physical interface and the 40 * Microchip Technology 24Cxx series serial EEPROM. 41 * 42 * Written using the following four documents: 43 * 44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 45 * National Semiconductor DP83840A data sheet (www.national.com) 46 * Microchip Technology 24C02C data sheet (www.microchip.com) 47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 48 * 49 * Written by Bill Paul <wpaul@ctr.columbia.edu> 50 * Electrical Engineering Department 51 * Columbia University, New York City 52 */ 53 54 /* 55 * Some notes about the ThunderLAN: 56 * 57 * The ThunderLAN controller is a single chip containing PCI controller 58 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 59 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 60 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 61 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 62 * to act as a complete ethernet interface. 63 * 64 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 65 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 66 * in full or half duplex. Some of the Compaq Deskpro machines use a 67 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 68 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 69 * concert with the ThunderLAN's internal PHY to provide full 10/100 70 * support. This is cheaper than using a standalone external PHY for both 71 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 72 * A serial EEPROM is also attached to the ThunderLAN chip to provide 73 * power-up default register settings and for storing the adapter's 74 * station address. Although not supported by this driver, the ThunderLAN 75 * chip can also be connected to token ring PHYs. 76 * 77 * The ThunderLAN has a set of registers which can be used to issue 78 * commands, acknowledge interrupts, and to manipulate other internal 79 * registers on its DIO bus. The primary registers can be accessed 80 * using either programmed I/O (inb/outb) or via PCI memory mapping, 81 * depending on how the card is configured during the PCI probing 82 * phase. It is even possible to have both PIO and memory mapped 83 * access turned on at the same time. 84 * 85 * Frame reception and transmission with the ThunderLAN chip is done 86 * using frame 'lists.' A list structure looks more or less like this: 87 * 88 * struct tl_frag { 89 * u_int32_t fragment_address; 90 * u_int32_t fragment_size; 91 * }; 92 * struct tl_list { 93 * u_int32_t forward_pointer; 94 * u_int16_t cstat; 95 * u_int16_t frame_size; 96 * struct tl_frag fragments[10]; 97 * }; 98 * 99 * The forward pointer in the list header can be either a 0 or the address 100 * of another list, which allows several lists to be linked together. Each 101 * list contains up to 10 fragment descriptors. This means the chip allows 102 * ethernet frames to be broken up into up to 10 chunks for transfer to 103 * and from the SRAM. Note that the forward pointer and fragment buffer 104 * addresses are physical memory addresses, not virtual. Note also that 105 * a single ethernet frame can not span lists: if the host wants to 106 * transmit a frame and the frame data is split up over more than 10 107 * buffers, the frame has to collapsed before it can be transmitted. 108 * 109 * To receive frames, the driver sets up a number of lists and populates 110 * the fragment descriptors, then it sends an RX GO command to the chip. 111 * When a frame is received, the chip will DMA it into the memory regions 112 * specified by the fragment descriptors and then trigger an RX 'end of 113 * frame interrupt' when done. The driver may choose to use only one 114 * fragment per list; this may result is slighltly less efficient use 115 * of memory in exchange for improving performance. 116 * 117 * To transmit frames, the driver again sets up lists and fragment 118 * descriptors, only this time the buffers contain frame data that 119 * is to be DMA'ed into the chip instead of out of it. Once the chip 120 * has transfered the data into its on-board SRAM, it will trigger a 121 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 122 * interrupt when it reaches the end of the list. 123 */ 124 125 /* 126 * Some notes about this driver: 127 * 128 * The ThunderLAN chip provides a couple of different ways to organize 129 * reception, transmission and interrupt handling. The simplest approach 130 * is to use one list each for transmission and reception. In this mode, 131 * the ThunderLAN will generate two interrupts for every received frame 132 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 133 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 134 * performance to have to handle so many interrupts. 135 * 136 * Initially I wanted to create a circular list of receive buffers so 137 * that the ThunderLAN chip would think there was an infinitely long 138 * receive channel and never deliver an RXEOC interrupt. However this 139 * doesn't work correctly under heavy load: while the manual says the 140 * chip will trigger an RXEOF interrupt each time a frame is copied into 141 * memory, you can't count on the chip waiting around for you to acknowledge 142 * the interrupt before it starts trying to DMA the next frame. The result 143 * is that the chip might traverse the entire circular list and then wrap 144 * around before you have a chance to do anything about it. Consequently, 145 * the receive list is terminated (with a 0 in the forward pointer in the 146 * last element). Each time an RXEOF interrupt arrives, the used list 147 * is shifted to the end of the list. This gives the appearance of an 148 * infinitely large RX chain so long as the driver doesn't fall behind 149 * the chip and allow all of the lists to be filled up. 150 * 151 * If all the lists are filled, the adapter will deliver an RX 'end of 152 * channel' interrupt when it hits the 0 forward pointer at the end of 153 * the chain. The RXEOC handler then cleans out the RX chain and resets 154 * the list head pointer in the ch_parm register and restarts the receiver. 155 * 156 * For frame transmission, it is possible to program the ThunderLAN's 157 * transmit interrupt threshold so that the chip can acknowledge multiple 158 * lists with only a single TX EOF interrupt. This allows the driver to 159 * queue several frames in one shot, and only have to handle a total 160 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 161 * are transmitted. Frame transmission is done directly out of the 162 * mbufs passed to the tl_start() routine via the interface send queue. 163 * The driver simply sets up the fragment descriptors in the transmit 164 * lists to point to the mbuf data regions and sends a TX GO command. 165 * 166 * Note that since the RX and TX lists themselves are always used 167 * only by the driver, the are malloc()ed once at driver initialization 168 * time and never free()ed. 169 * 170 * Also, in order to remain as platform independent as possible, this 171 * driver uses memory mapped register access to manipulate the card 172 * as opposed to programmed I/O. This avoids the use of the inb/outb 173 * (and related) instructions which are specific to the i386 platform. 174 * 175 * Using these techniques, this driver achieves very high performance 176 * by minimizing the amount of interrupts generated during large 177 * transfers and by completely avoiding buffer copies. Frame transfer 178 * to and from the ThunderLAN chip is performed entirely by the chip 179 * itself thereby reducing the load on the host CPU. 180 */ 181 182 #include <sys/param.h> 183 #include <sys/systm.h> 184 #include <sys/sockio.h> 185 #include <sys/mbuf.h> 186 #include <sys/malloc.h> 187 #include <sys/kernel.h> 188 #include <sys/socket.h> 189 #include <sys/thread2.h> 190 191 #include <net/if.h> 192 #include <net/ifq_var.h> 193 #include <net/if_arp.h> 194 #include <net/ethernet.h> 195 #include <net/if_dl.h> 196 #include <net/if_media.h> 197 198 #include <net/bpf.h> 199 200 #include <vm/vm.h> /* for vtophys */ 201 #include <vm/pmap.h> /* for vtophys */ 202 #include <machine/clock.h> /* for DELAY */ 203 #include <machine/bus_memio.h> 204 #include <machine/bus_pio.h> 205 #include <machine/bus.h> 206 #include <machine/resource.h> 207 #include <sys/bus.h> 208 #include <sys/rman.h> 209 210 #include "../mii_layer/mii.h" 211 #include "../mii_layer/miivar.h" 212 213 #include <bus/pci/pcireg.h> 214 #include <bus/pci/pcivar.h> 215 216 /* 217 * Default to using PIO register access mode to pacify certain 218 * laptop docking stations with built-in ThunderLAN chips that 219 * don't seem to handle memory mapped mode properly. 220 */ 221 #define TL_USEIOSPACE 222 223 #include "if_tlreg.h" 224 225 /* "controller miibus0" required. See GENERIC if you get errors here. */ 226 #include "miibus_if.h" 227 228 /* 229 * Various supported device vendors/types and their names. 230 */ 231 232 static struct tl_type tl_devs[] = { 233 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 234 "Texas Instruments ThunderLAN" }, 235 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 236 "Compaq Netelligent 10" }, 237 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 238 "Compaq Netelligent 10/100" }, 239 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 240 "Compaq Netelligent 10/100 Proliant" }, 241 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 242 "Compaq Netelligent 10/100 Dual Port" }, 243 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 244 "Compaq NetFlex-3/P Integrated" }, 245 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 246 "Compaq NetFlex-3/P" }, 247 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 248 "Compaq NetFlex 3/P w/ BNC" }, 249 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 250 "Compaq Netelligent 10/100 TX Embedded UTP" }, 251 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 252 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 253 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 254 "Compaq Netelligent 10/100 TX UTP" }, 255 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 256 "Olicom OC-2183/2185" }, 257 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 258 "Olicom OC-2325" }, 259 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 260 "Olicom OC-2326 10/100 TX UTP" }, 261 { 0, 0, NULL } 262 }; 263 264 static int tl_probe (device_t); 265 static int tl_attach (device_t); 266 static int tl_detach (device_t); 267 static int tl_intvec_rxeoc (void *, u_int32_t); 268 static int tl_intvec_txeoc (void *, u_int32_t); 269 static int tl_intvec_txeof (void *, u_int32_t); 270 static int tl_intvec_rxeof (void *, u_int32_t); 271 static int tl_intvec_adchk (void *, u_int32_t); 272 static int tl_intvec_netsts (void *, u_int32_t); 273 274 static int tl_newbuf (struct tl_softc *, 275 struct tl_chain_onefrag *); 276 static void tl_stats_update (void *); 277 static int tl_encap (struct tl_softc *, struct tl_chain *, 278 struct mbuf *); 279 280 static void tl_intr (void *); 281 static void tl_start (struct ifnet *); 282 static int tl_ioctl (struct ifnet *, u_long, caddr_t, 283 struct ucred *); 284 static void tl_init (void *); 285 static void tl_stop (struct tl_softc *); 286 static void tl_watchdog (struct ifnet *); 287 static void tl_shutdown (device_t); 288 static int tl_ifmedia_upd (struct ifnet *); 289 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 290 291 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int); 292 static u_int8_t tl_eeprom_getbyte (struct tl_softc *, 293 int, u_int8_t *); 294 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int); 295 296 static void tl_mii_sync (struct tl_softc *); 297 static void tl_mii_send (struct tl_softc *, u_int32_t, int); 298 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *); 299 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *); 300 static int tl_miibus_readreg (device_t, int, int); 301 static int tl_miibus_writereg (device_t, int, int, int); 302 static void tl_miibus_statchg (device_t); 303 304 static void tl_setmode (struct tl_softc *, int); 305 static int tl_calchash (caddr_t); 306 static void tl_setmulti (struct tl_softc *); 307 static void tl_setfilt (struct tl_softc *, caddr_t, int); 308 static void tl_softreset (struct tl_softc *, int); 309 static void tl_hardreset (device_t); 310 static int tl_list_rx_init (struct tl_softc *); 311 static int tl_list_tx_init (struct tl_softc *); 312 313 static u_int8_t tl_dio_read8 (struct tl_softc *, int); 314 static u_int16_t tl_dio_read16 (struct tl_softc *, int); 315 static u_int32_t tl_dio_read32 (struct tl_softc *, int); 316 static void tl_dio_write8 (struct tl_softc *, int, int); 317 static void tl_dio_write16 (struct tl_softc *, int, int); 318 static void tl_dio_write32 (struct tl_softc *, int, int); 319 static void tl_dio_setbit (struct tl_softc *, int, int); 320 static void tl_dio_clrbit (struct tl_softc *, int, int); 321 static void tl_dio_setbit16 (struct tl_softc *, int, int); 322 static void tl_dio_clrbit16 (struct tl_softc *, int, int); 323 324 #ifdef TL_USEIOSPACE 325 #define TL_RES SYS_RES_IOPORT 326 #define TL_RID TL_PCI_LOIO 327 #else 328 #define TL_RES SYS_RES_MEMORY 329 #define TL_RID TL_PCI_LOMEM 330 #endif 331 332 static device_method_t tl_methods[] = { 333 /* Device interface */ 334 DEVMETHOD(device_probe, tl_probe), 335 DEVMETHOD(device_attach, tl_attach), 336 DEVMETHOD(device_detach, tl_detach), 337 DEVMETHOD(device_shutdown, tl_shutdown), 338 339 /* bus interface */ 340 DEVMETHOD(bus_print_child, bus_generic_print_child), 341 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 342 343 /* MII interface */ 344 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 345 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 346 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 347 348 { 0, 0 } 349 }; 350 351 static driver_t tl_driver = { 352 "tl", 353 tl_methods, 354 sizeof(struct tl_softc) 355 }; 356 357 static devclass_t tl_devclass; 358 359 DECLARE_DUMMY_MODULE(if_tl); 360 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0); 361 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 362 363 static u_int8_t tl_dio_read8(sc, reg) 364 struct tl_softc *sc; 365 int reg; 366 { 367 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 368 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 369 } 370 371 static u_int16_t tl_dio_read16(sc, reg) 372 struct tl_softc *sc; 373 int reg; 374 { 375 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 376 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 377 } 378 379 static u_int32_t tl_dio_read32(sc, reg) 380 struct tl_softc *sc; 381 int reg; 382 { 383 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 384 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 385 } 386 387 static void tl_dio_write8(sc, reg, val) 388 struct tl_softc *sc; 389 int reg; 390 int val; 391 { 392 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 393 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 394 return; 395 } 396 397 static void tl_dio_write16(sc, reg, val) 398 struct tl_softc *sc; 399 int reg; 400 int val; 401 { 402 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 403 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 404 return; 405 } 406 407 static void tl_dio_write32(sc, reg, val) 408 struct tl_softc *sc; 409 int reg; 410 int val; 411 { 412 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 413 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 414 return; 415 } 416 417 static void tl_dio_setbit(sc, reg, bit) 418 struct tl_softc *sc; 419 int reg; 420 int bit; 421 { 422 u_int8_t f; 423 424 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 425 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 426 f |= bit; 427 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 428 429 return; 430 } 431 432 static void tl_dio_clrbit(sc, reg, bit) 433 struct tl_softc *sc; 434 int reg; 435 int bit; 436 { 437 u_int8_t f; 438 439 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 440 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 441 f &= ~bit; 442 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 443 444 return; 445 } 446 447 static void tl_dio_setbit16(sc, reg, bit) 448 struct tl_softc *sc; 449 int reg; 450 int bit; 451 { 452 u_int16_t f; 453 454 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 455 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 456 f |= bit; 457 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 458 459 return; 460 } 461 462 static void tl_dio_clrbit16(sc, reg, bit) 463 struct tl_softc *sc; 464 int reg; 465 int bit; 466 { 467 u_int16_t f; 468 469 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 470 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 471 f &= ~bit; 472 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 473 474 return; 475 } 476 477 /* 478 * Send an instruction or address to the EEPROM, check for ACK. 479 */ 480 static u_int8_t tl_eeprom_putbyte(sc, byte) 481 struct tl_softc *sc; 482 int byte; 483 { 484 int i, ack = 0; 485 486 /* 487 * Make sure we're in TX mode. 488 */ 489 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 490 491 /* 492 * Feed in each bit and stobe the clock. 493 */ 494 for (i = 0x80; i; i >>= 1) { 495 if (byte & i) { 496 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 497 } else { 498 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 499 } 500 DELAY(1); 501 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 502 DELAY(1); 503 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 504 } 505 506 /* 507 * Turn off TX mode. 508 */ 509 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 510 511 /* 512 * Check for ack. 513 */ 514 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 515 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 516 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 517 518 return(ack); 519 } 520 521 /* 522 * Read a byte of data stored in the EEPROM at address 'addr.' 523 */ 524 static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 525 struct tl_softc *sc; 526 int addr; 527 u_int8_t *dest; 528 { 529 int i; 530 u_int8_t byte = 0; 531 532 tl_dio_write8(sc, TL_NETSIO, 0); 533 534 EEPROM_START; 535 536 /* 537 * Send write control code to EEPROM. 538 */ 539 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 540 printf("tl%d: failed to send write command, status: %x\n", 541 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 542 return(1); 543 } 544 545 /* 546 * Send address of byte we want to read. 547 */ 548 if (tl_eeprom_putbyte(sc, addr)) { 549 printf("tl%d: failed to send address, status: %x\n", 550 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 551 return(1); 552 } 553 554 EEPROM_STOP; 555 EEPROM_START; 556 /* 557 * Send read control code to EEPROM. 558 */ 559 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 560 printf("tl%d: failed to send write command, status: %x\n", 561 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 562 return(1); 563 } 564 565 /* 566 * Start reading bits from EEPROM. 567 */ 568 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 569 for (i = 0x80; i; i >>= 1) { 570 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 571 DELAY(1); 572 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 573 byte |= i; 574 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 575 DELAY(1); 576 } 577 578 EEPROM_STOP; 579 580 /* 581 * No ACK generated for read, so just return byte. 582 */ 583 584 *dest = byte; 585 586 return(0); 587 } 588 589 /* 590 * Read a sequence of bytes from the EEPROM. 591 */ 592 static int tl_read_eeprom(sc, dest, off, cnt) 593 struct tl_softc *sc; 594 caddr_t dest; 595 int off; 596 int cnt; 597 { 598 int err = 0, i; 599 u_int8_t byte = 0; 600 601 for (i = 0; i < cnt; i++) { 602 err = tl_eeprom_getbyte(sc, off + i, &byte); 603 if (err) 604 break; 605 *(dest + i) = byte; 606 } 607 608 return(err ? 1 : 0); 609 } 610 611 static void tl_mii_sync(sc) 612 struct tl_softc *sc; 613 { 614 int i; 615 616 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 617 618 for (i = 0; i < 32; i++) { 619 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 620 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 621 } 622 623 return; 624 } 625 626 static void tl_mii_send(sc, bits, cnt) 627 struct tl_softc *sc; 628 u_int32_t bits; 629 int cnt; 630 { 631 int i; 632 633 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 634 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 635 if (bits & i) { 636 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 637 } else { 638 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 639 } 640 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 641 } 642 } 643 644 static int tl_mii_readreg(sc, frame) 645 struct tl_softc *sc; 646 struct tl_mii_frame *frame; 647 648 { 649 int i, ack; 650 int minten = 0; 651 652 crit_enter(); 653 654 tl_mii_sync(sc); 655 656 /* 657 * Set up frame for RX. 658 */ 659 frame->mii_stdelim = TL_MII_STARTDELIM; 660 frame->mii_opcode = TL_MII_READOP; 661 frame->mii_turnaround = 0; 662 frame->mii_data = 0; 663 664 /* 665 * Turn off MII interrupt by forcing MINTEN low. 666 */ 667 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 668 if (minten) { 669 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 670 } 671 672 /* 673 * Turn on data xmit. 674 */ 675 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 676 677 /* 678 * Send command/address info. 679 */ 680 tl_mii_send(sc, frame->mii_stdelim, 2); 681 tl_mii_send(sc, frame->mii_opcode, 2); 682 tl_mii_send(sc, frame->mii_phyaddr, 5); 683 tl_mii_send(sc, frame->mii_regaddr, 5); 684 685 /* 686 * Turn off xmit. 687 */ 688 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 689 690 /* Idle bit */ 691 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 692 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 693 694 /* Check for ack */ 695 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 696 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 697 698 /* Complete the cycle */ 699 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 700 701 /* 702 * Now try reading data bits. If the ack failed, we still 703 * need to clock through 16 cycles to keep the PHYs in sync. 704 */ 705 if (ack) { 706 for(i = 0; i < 16; i++) { 707 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 708 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 709 } 710 goto fail; 711 } 712 713 for (i = 0x8000; i; i >>= 1) { 714 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 715 if (!ack) { 716 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 717 frame->mii_data |= i; 718 } 719 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 720 } 721 722 fail: 723 724 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 725 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 726 727 /* Reenable interrupts */ 728 if (minten) { 729 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 730 } 731 732 crit_exit(); 733 734 if (ack) 735 return(1); 736 return(0); 737 } 738 739 static int tl_mii_writereg(sc, frame) 740 struct tl_softc *sc; 741 struct tl_mii_frame *frame; 742 743 { 744 int minten; 745 746 tl_mii_sync(sc); 747 748 crit_enter(); 749 /* 750 * Set up frame for TX. 751 */ 752 753 frame->mii_stdelim = TL_MII_STARTDELIM; 754 frame->mii_opcode = TL_MII_WRITEOP; 755 frame->mii_turnaround = TL_MII_TURNAROUND; 756 757 /* 758 * Turn off MII interrupt by forcing MINTEN low. 759 */ 760 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 761 if (minten) { 762 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 763 } 764 765 /* 766 * Turn on data output. 767 */ 768 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 769 770 tl_mii_send(sc, frame->mii_stdelim, 2); 771 tl_mii_send(sc, frame->mii_opcode, 2); 772 tl_mii_send(sc, frame->mii_phyaddr, 5); 773 tl_mii_send(sc, frame->mii_regaddr, 5); 774 tl_mii_send(sc, frame->mii_turnaround, 2); 775 tl_mii_send(sc, frame->mii_data, 16); 776 777 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 778 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 779 780 /* 781 * Turn off xmit. 782 */ 783 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 784 785 /* Reenable interrupts */ 786 if (minten) 787 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 788 789 crit_exit(); 790 791 return(0); 792 } 793 794 static int tl_miibus_readreg(dev, phy, reg) 795 device_t dev; 796 int phy, reg; 797 { 798 struct tl_softc *sc; 799 struct tl_mii_frame frame; 800 801 sc = device_get_softc(dev); 802 bzero((char *)&frame, sizeof(frame)); 803 804 frame.mii_phyaddr = phy; 805 frame.mii_regaddr = reg; 806 tl_mii_readreg(sc, &frame); 807 808 return(frame.mii_data); 809 } 810 811 static int tl_miibus_writereg(dev, phy, reg, data) 812 device_t dev; 813 int phy, reg, data; 814 { 815 struct tl_softc *sc; 816 struct tl_mii_frame frame; 817 818 sc = device_get_softc(dev); 819 bzero((char *)&frame, sizeof(frame)); 820 821 frame.mii_phyaddr = phy; 822 frame.mii_regaddr = reg; 823 frame.mii_data = data; 824 825 tl_mii_writereg(sc, &frame); 826 827 return(0); 828 } 829 830 static void tl_miibus_statchg(dev) 831 device_t dev; 832 { 833 struct tl_softc *sc; 834 struct mii_data *mii; 835 836 sc = device_get_softc(dev); 837 mii = device_get_softc(sc->tl_miibus); 838 839 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 840 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 841 } else { 842 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 843 } 844 845 return; 846 } 847 848 /* 849 * Set modes for bitrate devices. 850 */ 851 static void tl_setmode(sc, media) 852 struct tl_softc *sc; 853 int media; 854 { 855 if (IFM_SUBTYPE(media) == IFM_10_5) 856 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 857 if (IFM_SUBTYPE(media) == IFM_10_T) { 858 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 859 if ((media & IFM_GMASK) == IFM_FDX) { 860 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 861 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 862 } else { 863 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 864 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 865 } 866 } 867 868 return; 869 } 870 871 /* 872 * Calculate the hash of a MAC address for programming the multicast hash 873 * table. This hash is simply the address split into 6-bit chunks 874 * XOR'd, e.g. 875 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 876 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 877 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 878 * the folded 24-bit value is split into 6-bit portions and XOR'd. 879 */ 880 static int tl_calchash(addr) 881 caddr_t addr; 882 { 883 int t; 884 885 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 886 (addr[2] ^ addr[5]); 887 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 888 } 889 890 /* 891 * The ThunderLAN has a perfect MAC address filter in addition to 892 * the multicast hash filter. The perfect filter can be programmed 893 * with up to four MAC addresses. The first one is always used to 894 * hold the station address, which leaves us free to use the other 895 * three for multicast addresses. 896 */ 897 static void tl_setfilt(sc, addr, slot) 898 struct tl_softc *sc; 899 caddr_t addr; 900 int slot; 901 { 902 int i; 903 u_int16_t regaddr; 904 905 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 906 907 for (i = 0; i < ETHER_ADDR_LEN; i++) 908 tl_dio_write8(sc, regaddr + i, *(addr + i)); 909 910 return; 911 } 912 913 /* 914 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 915 * linked list. This is fine, except addresses are added from the head 916 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 917 * group to always be in the perfect filter, but as more groups are added, 918 * the 224.0.0.1 entry (which is always added first) gets pushed down 919 * the list and ends up at the tail. So after 3 or 4 multicast groups 920 * are added, the all-hosts entry gets pushed out of the perfect filter 921 * and into the hash table. 922 * 923 * Because the multicast list is a doubly-linked list as opposed to a 924 * circular queue, we don't have the ability to just grab the tail of 925 * the list and traverse it backwards. Instead, we have to traverse 926 * the list once to find the tail, then traverse it again backwards to 927 * update the multicast filter. 928 */ 929 static void tl_setmulti(sc) 930 struct tl_softc *sc; 931 { 932 struct ifnet *ifp; 933 u_int32_t hashes[2] = { 0, 0 }; 934 int h, i; 935 struct ifmultiaddr *ifma; 936 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 937 ifp = &sc->arpcom.ac_if; 938 939 /* First, zot all the existing filters. */ 940 for (i = 1; i < 4; i++) 941 tl_setfilt(sc, (caddr_t)&dummy, i); 942 tl_dio_write32(sc, TL_HASH1, 0); 943 tl_dio_write32(sc, TL_HASH2, 0); 944 945 /* Now program new ones. */ 946 if (ifp->if_flags & IFF_ALLMULTI) { 947 hashes[0] = 0xFFFFFFFF; 948 hashes[1] = 0xFFFFFFFF; 949 } else { 950 i = 1; 951 /* First find the tail of the list. */ 952 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 953 ifma = ifma->ifma_link.le_next) { 954 if (ifma->ifma_link.le_next == NULL) 955 break; 956 } 957 /* Now traverse the list backwards. */ 958 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 959 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 960 if (ifma->ifma_addr->sa_family != AF_LINK) 961 continue; 962 /* 963 * Program the first three multicast groups 964 * into the perfect filter. For all others, 965 * use the hash table. 966 */ 967 if (i < 4) { 968 tl_setfilt(sc, 969 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 970 i++; 971 continue; 972 } 973 974 h = tl_calchash( 975 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 976 if (h < 32) 977 hashes[0] |= (1 << h); 978 else 979 hashes[1] |= (1 << (h - 32)); 980 } 981 } 982 983 tl_dio_write32(sc, TL_HASH1, hashes[0]); 984 tl_dio_write32(sc, TL_HASH2, hashes[1]); 985 986 return; 987 } 988 989 /* 990 * This routine is recommended by the ThunderLAN manual to insure that 991 * the internal PHY is powered up correctly. It also recommends a one 992 * second pause at the end to 'wait for the clocks to start' but in my 993 * experience this isn't necessary. 994 */ 995 static void tl_hardreset(dev) 996 device_t dev; 997 { 998 struct tl_softc *sc; 999 int i; 1000 u_int16_t flags; 1001 1002 sc = device_get_softc(dev); 1003 1004 tl_mii_sync(sc); 1005 1006 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 1007 1008 for (i = 0; i < MII_NPHY; i++) 1009 tl_miibus_writereg(dev, i, MII_BMCR, flags); 1010 1011 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 1012 DELAY(50000); 1013 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 1014 tl_mii_sync(sc); 1015 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 1016 1017 DELAY(50000); 1018 return; 1019 } 1020 1021 static void tl_softreset(sc, internal) 1022 struct tl_softc *sc; 1023 int internal; 1024 { 1025 u_int32_t cmd, dummy, i; 1026 1027 /* Assert the adapter reset bit. */ 1028 CMD_SET(sc, TL_CMD_ADRST); 1029 1030 /* Turn off interrupts */ 1031 CMD_SET(sc, TL_CMD_INTSOFF); 1032 1033 /* First, clear the stats registers. */ 1034 for (i = 0; i < 5; i++) 1035 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1036 1037 /* Clear Areg and Hash registers */ 1038 for (i = 0; i < 8; i++) 1039 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1040 1041 /* 1042 * Set up Netconfig register. Enable one channel and 1043 * one fragment mode. 1044 */ 1045 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1046 if (internal && !sc->tl_bitrate) { 1047 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1048 } else { 1049 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1050 } 1051 1052 /* Handle cards with bitrate devices. */ 1053 if (sc->tl_bitrate) 1054 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1055 1056 /* 1057 * Load adapter irq pacing timer and tx threshold. 1058 * We make the transmit threshold 1 initially but we may 1059 * change that later. 1060 */ 1061 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1062 cmd |= TL_CMD_NES; 1063 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1064 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1065 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1066 1067 /* Unreset the MII */ 1068 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1069 1070 /* Take the adapter out of reset */ 1071 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1072 1073 /* Wait for things to settle down a little. */ 1074 DELAY(500); 1075 1076 return; 1077 } 1078 1079 /* 1080 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1081 * against our list and return its name if we find a match. 1082 */ 1083 static int tl_probe(dev) 1084 device_t dev; 1085 { 1086 struct tl_type *t; 1087 1088 t = tl_devs; 1089 1090 while(t->tl_name != NULL) { 1091 if ((pci_get_vendor(dev) == t->tl_vid) && 1092 (pci_get_device(dev) == t->tl_did)) { 1093 device_set_desc(dev, t->tl_name); 1094 return(0); 1095 } 1096 t++; 1097 } 1098 1099 return(ENXIO); 1100 } 1101 1102 static int tl_attach(dev) 1103 device_t dev; 1104 { 1105 int i; 1106 u_int32_t command; 1107 u_int16_t did, vid; 1108 struct tl_type *t; 1109 struct ifnet *ifp; 1110 struct tl_softc *sc; 1111 int unit, error = 0, rid; 1112 1113 crit_enter(); 1114 1115 vid = pci_get_vendor(dev); 1116 did = pci_get_device(dev); 1117 sc = device_get_softc(dev); 1118 unit = device_get_unit(dev); 1119 bzero(sc, sizeof(struct tl_softc)); 1120 1121 t = tl_devs; 1122 while(t->tl_name != NULL) { 1123 if (vid == t->tl_vid && did == t->tl_did) 1124 break; 1125 t++; 1126 } 1127 1128 if (t->tl_name == NULL) { 1129 printf("tl%d: unknown device!?\n", unit); 1130 goto fail; 1131 } 1132 1133 /* 1134 * Map control/status registers. 1135 */ 1136 command = pci_read_config(dev, PCIR_COMMAND, 4); 1137 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1138 pci_write_config(dev, PCIR_COMMAND, command, 4); 1139 command = pci_read_config(dev, PCIR_COMMAND, 4); 1140 1141 #ifdef TL_USEIOSPACE 1142 if (!(command & PCIM_CMD_PORTEN)) { 1143 printf("tl%d: failed to enable I/O ports!\n", unit); 1144 error = ENXIO; 1145 goto fail; 1146 } 1147 1148 rid = TL_PCI_LOIO; 1149 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1150 RF_ACTIVE); 1151 1152 /* 1153 * Some cards have the I/O and memory mapped address registers 1154 * reversed. Try both combinations before giving up. 1155 */ 1156 if (sc->tl_res == NULL) { 1157 rid = TL_PCI_LOMEM; 1158 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1159 RF_ACTIVE); 1160 } 1161 #else 1162 if (!(command & PCIM_CMD_MEMEN)) { 1163 printf("tl%d: failed to enable memory mapping!\n", unit); 1164 error = ENXIO; 1165 goto fail; 1166 } 1167 1168 rid = TL_PCI_LOMEM; 1169 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1170 RF_ACTIVE); 1171 if (sc->tl_res == NULL) { 1172 rid = TL_PCI_LOIO; 1173 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1174 RF_ACTIVE); 1175 } 1176 #endif 1177 1178 if (sc->tl_res == NULL) { 1179 printf("tl%d: couldn't map ports/memory\n", unit); 1180 error = ENXIO; 1181 goto fail; 1182 } 1183 1184 sc->tl_btag = rman_get_bustag(sc->tl_res); 1185 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1186 1187 #ifdef notdef 1188 /* 1189 * The ThunderLAN manual suggests jacking the PCI latency 1190 * timer all the way up to its maximum value. I'm not sure 1191 * if this is really necessary, but what the manual wants, 1192 * the manual gets. 1193 */ 1194 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1195 command |= 0x0000FF00; 1196 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1197 #endif 1198 1199 /* Allocate interrupt */ 1200 rid = 0; 1201 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1202 RF_SHAREABLE | RF_ACTIVE); 1203 1204 if (sc->tl_irq == NULL) { 1205 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1206 printf("tl%d: couldn't map interrupt\n", unit); 1207 error = ENXIO; 1208 goto fail; 1209 } 1210 1211 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1212 tl_intr, sc, &sc->tl_intrhand, NULL); 1213 1214 if (error) { 1215 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1216 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1217 printf("tl%d: couldn't set up irq\n", unit); 1218 goto fail; 1219 } 1220 1221 /* 1222 * Now allocate memory for the TX and RX lists. 1223 */ 1224 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1225 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1226 1227 if (sc->tl_ldata == NULL) { 1228 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1229 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1230 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1231 printf("tl%d: no memory for list buffers!\n", unit); 1232 error = ENXIO; 1233 goto fail; 1234 } 1235 1236 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1237 1238 sc->tl_unit = unit; 1239 sc->tl_dinfo = t; 1240 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1241 sc->tl_eeaddr = TL_EEPROM_EADDR; 1242 if (t->tl_vid == OLICOM_VENDORID) 1243 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1244 1245 /* Reset the adapter. */ 1246 tl_softreset(sc, 1); 1247 tl_hardreset(dev); 1248 tl_softreset(sc, 1); 1249 1250 /* 1251 * Get station address from the EEPROM. 1252 */ 1253 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1254 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1255 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1256 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1257 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1258 contigfree(sc->tl_ldata, 1259 sizeof(struct tl_list_data), M_DEVBUF); 1260 printf("tl%d: failed to read station address\n", unit); 1261 error = ENXIO; 1262 goto fail; 1263 } 1264 1265 /* 1266 * XXX Olicom, in its desire to be different from the 1267 * rest of the world, has done strange things with the 1268 * encoding of the station address in the EEPROM. First 1269 * of all, they store the address at offset 0xF8 rather 1270 * than at 0x83 like the ThunderLAN manual suggests. 1271 * Second, they store the address in three 16-bit words in 1272 * network byte order, as opposed to storing it sequentially 1273 * like all the other ThunderLAN cards. In order to get 1274 * the station address in a form that matches what the Olicom 1275 * diagnostic utility specifies, we have to byte-swap each 1276 * word. To make things even more confusing, neither 00:00:28 1277 * nor 00:00:24 appear in the IEEE OUI database. 1278 */ 1279 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1280 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1281 u_int16_t *p; 1282 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1283 *p = ntohs(*p); 1284 } 1285 } 1286 1287 ifp = &sc->arpcom.ac_if; 1288 ifp->if_softc = sc; 1289 if_initname(ifp, "tl", sc->tl_unit); 1290 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1291 ifp->if_ioctl = tl_ioctl; 1292 ifp->if_start = tl_start; 1293 ifp->if_watchdog = tl_watchdog; 1294 ifp->if_init = tl_init; 1295 ifp->if_mtu = ETHERMTU; 1296 ifq_set_maxlen(&ifp->if_snd, TL_TX_LIST_CNT - 1); 1297 ifq_set_ready(&ifp->if_snd); 1298 callout_init(&sc->tl_stat_timer); 1299 1300 /* Reset the adapter again. */ 1301 tl_softreset(sc, 1); 1302 tl_hardreset(dev); 1303 tl_softreset(sc, 1); 1304 1305 /* 1306 * Do MII setup. If no PHYs are found, then this is a 1307 * bitrate ThunderLAN chip that only supports 10baseT 1308 * and AUI/BNC. 1309 */ 1310 if (mii_phy_probe(dev, &sc->tl_miibus, 1311 tl_ifmedia_upd, tl_ifmedia_sts)) { 1312 struct ifmedia *ifm; 1313 sc->tl_bitrate = 1; 1314 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1315 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1316 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1317 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1318 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1319 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1320 /* Reset again, this time setting bitrate mode. */ 1321 tl_softreset(sc, 1); 1322 ifm = &sc->ifmedia; 1323 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1324 tl_ifmedia_upd(ifp); 1325 } 1326 1327 /* 1328 * Call MI attach routine. 1329 */ 1330 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1331 1332 fail: 1333 crit_exit(); 1334 return(error); 1335 } 1336 1337 static int tl_detach(dev) 1338 device_t dev; 1339 { 1340 struct tl_softc *sc; 1341 struct ifnet *ifp; 1342 1343 crit_enter(); 1344 1345 sc = device_get_softc(dev); 1346 ifp = &sc->arpcom.ac_if; 1347 1348 tl_stop(sc); 1349 ether_ifdetach(ifp); 1350 1351 bus_generic_detach(dev); 1352 device_delete_child(dev, sc->tl_miibus); 1353 1354 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1355 if (sc->tl_bitrate) 1356 ifmedia_removeall(&sc->ifmedia); 1357 1358 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1359 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1360 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1361 1362 crit_exit(); 1363 1364 return(0); 1365 } 1366 1367 /* 1368 * Initialize the transmit lists. 1369 */ 1370 static int tl_list_tx_init(sc) 1371 struct tl_softc *sc; 1372 { 1373 struct tl_chain_data *cd; 1374 struct tl_list_data *ld; 1375 int i; 1376 1377 cd = &sc->tl_cdata; 1378 ld = sc->tl_ldata; 1379 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1380 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1381 if (i == (TL_TX_LIST_CNT - 1)) 1382 cd->tl_tx_chain[i].tl_next = NULL; 1383 else 1384 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1385 } 1386 1387 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1388 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1389 sc->tl_txeoc = 1; 1390 1391 return(0); 1392 } 1393 1394 /* 1395 * Initialize the RX lists and allocate mbufs for them. 1396 */ 1397 static int tl_list_rx_init(sc) 1398 struct tl_softc *sc; 1399 { 1400 struct tl_chain_data *cd; 1401 struct tl_list_data *ld; 1402 int i; 1403 1404 cd = &sc->tl_cdata; 1405 ld = sc->tl_ldata; 1406 1407 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1408 cd->tl_rx_chain[i].tl_ptr = 1409 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1410 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1411 return(ENOBUFS); 1412 if (i == (TL_RX_LIST_CNT - 1)) { 1413 cd->tl_rx_chain[i].tl_next = NULL; 1414 ld->tl_rx_list[i].tlist_fptr = 0; 1415 } else { 1416 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1417 ld->tl_rx_list[i].tlist_fptr = 1418 vtophys(&ld->tl_rx_list[i + 1]); 1419 } 1420 } 1421 1422 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1423 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1424 1425 return(0); 1426 } 1427 1428 static int tl_newbuf(sc, c) 1429 struct tl_softc *sc; 1430 struct tl_chain_onefrag *c; 1431 { 1432 struct mbuf *m_new = NULL; 1433 1434 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1435 if (m_new == NULL) 1436 return(ENOBUFS); 1437 1438 MCLGET(m_new, MB_DONTWAIT); 1439 if (!(m_new->m_flags & M_EXT)) { 1440 m_freem(m_new); 1441 return(ENOBUFS); 1442 } 1443 1444 c->tl_mbuf = m_new; 1445 c->tl_next = NULL; 1446 c->tl_ptr->tlist_frsize = MCLBYTES; 1447 c->tl_ptr->tlist_fptr = 0; 1448 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1449 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1450 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1451 1452 return(0); 1453 } 1454 /* 1455 * Interrupt handler for RX 'end of frame' condition (EOF). This 1456 * tells us that a full ethernet frame has been captured and we need 1457 * to handle it. 1458 * 1459 * Reception is done using 'lists' which consist of a header and a 1460 * series of 10 data count/data address pairs that point to buffers. 1461 * Initially you're supposed to create a list, populate it with pointers 1462 * to buffers, then load the physical address of the list into the 1463 * ch_parm register. The adapter is then supposed to DMA the received 1464 * frame into the buffers for you. 1465 * 1466 * To make things as fast as possible, we have the chip DMA directly 1467 * into mbufs. This saves us from having to do a buffer copy: we can 1468 * just hand the mbufs directly to ether_input(). Once the frame has 1469 * been sent on its way, the 'list' structure is assigned a new buffer 1470 * and moved to the end of the RX chain. As long we we stay ahead of 1471 * the chip, it will always think it has an endless receive channel. 1472 * 1473 * If we happen to fall behind and the chip manages to fill up all of 1474 * the buffers, it will generate an end of channel interrupt and wait 1475 * for us to empty the chain and restart the receiver. 1476 */ 1477 static int tl_intvec_rxeof(xsc, type) 1478 void *xsc; 1479 u_int32_t type; 1480 { 1481 struct tl_softc *sc; 1482 int r = 0, total_len = 0; 1483 struct ether_header *eh; 1484 struct mbuf *m; 1485 struct ifnet *ifp; 1486 struct tl_chain_onefrag *cur_rx; 1487 1488 sc = xsc; 1489 ifp = &sc->arpcom.ac_if; 1490 1491 while(sc->tl_cdata.tl_rx_head != NULL) { 1492 cur_rx = sc->tl_cdata.tl_rx_head; 1493 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1494 break; 1495 r++; 1496 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1497 m = cur_rx->tl_mbuf; 1498 total_len = cur_rx->tl_ptr->tlist_frsize; 1499 1500 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1501 ifp->if_ierrors++; 1502 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1503 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1504 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1505 continue; 1506 } 1507 1508 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1509 vtophys(cur_rx->tl_ptr); 1510 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1511 sc->tl_cdata.tl_rx_tail = cur_rx; 1512 1513 eh = mtod(m, struct ether_header *); 1514 m->m_pkthdr.rcvif = ifp; 1515 1516 /* 1517 * Note: when the ThunderLAN chip is in 'capture all 1518 * frames' mode, it will receive its own transmissions. 1519 * We drop don't need to process our own transmissions, 1520 * so we drop them here and continue. 1521 */ 1522 /*if (ifp->if_flags & IFF_PROMISC && */ 1523 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1524 ETHER_ADDR_LEN)) { 1525 m_freem(m); 1526 continue; 1527 } 1528 1529 (*ifp->if_input)(ifp, m); 1530 } 1531 1532 return(r); 1533 } 1534 1535 /* 1536 * The RX-EOC condition hits when the ch_parm address hasn't been 1537 * initialized or the adapter reached a list with a forward pointer 1538 * of 0 (which indicates the end of the chain). In our case, this means 1539 * the card has hit the end of the receive buffer chain and we need to 1540 * empty out the buffers and shift the pointer back to the beginning again. 1541 */ 1542 static int tl_intvec_rxeoc(xsc, type) 1543 void *xsc; 1544 u_int32_t type; 1545 { 1546 struct tl_softc *sc; 1547 int r; 1548 struct tl_chain_data *cd; 1549 1550 1551 sc = xsc; 1552 cd = &sc->tl_cdata; 1553 1554 /* Flush out the receive queue and ack RXEOF interrupts. */ 1555 r = tl_intvec_rxeof(xsc, type); 1556 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1557 r = 1; 1558 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1559 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1560 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1561 r |= (TL_CMD_GO|TL_CMD_RT); 1562 return(r); 1563 } 1564 1565 static int tl_intvec_txeof(xsc, type) 1566 void *xsc; 1567 u_int32_t type; 1568 { 1569 struct tl_softc *sc; 1570 int r = 0; 1571 struct tl_chain *cur_tx; 1572 1573 sc = xsc; 1574 1575 /* 1576 * Go through our tx list and free mbufs for those 1577 * frames that have been sent. 1578 */ 1579 while (sc->tl_cdata.tl_tx_head != NULL) { 1580 cur_tx = sc->tl_cdata.tl_tx_head; 1581 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1582 break; 1583 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1584 1585 r++; 1586 m_freem(cur_tx->tl_mbuf); 1587 cur_tx->tl_mbuf = NULL; 1588 1589 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1590 sc->tl_cdata.tl_tx_free = cur_tx; 1591 if (!cur_tx->tl_ptr->tlist_fptr) 1592 break; 1593 } 1594 1595 return(r); 1596 } 1597 1598 /* 1599 * The transmit end of channel interrupt. The adapter triggers this 1600 * interrupt to tell us it hit the end of the current transmit list. 1601 * 1602 * A note about this: it's possible for a condition to arise where 1603 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1604 * You have to avoid this since the chip expects things to go in a 1605 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1606 * When the TXEOF handler is called, it will free all of the transmitted 1607 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1608 * interrupt should be received and acknowledged before any more frames 1609 * are queued for transmission. If tl_statrt() is called after TXEOF 1610 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1611 * it could attempt to issue a transmit command prematurely. 1612 * 1613 * To guard against this, tl_start() will only issue transmit commands 1614 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1615 * can set this flag once tl_start() has cleared it. 1616 */ 1617 static int tl_intvec_txeoc(xsc, type) 1618 void *xsc; 1619 u_int32_t type; 1620 { 1621 struct tl_softc *sc; 1622 struct ifnet *ifp; 1623 u_int32_t cmd; 1624 1625 sc = xsc; 1626 ifp = &sc->arpcom.ac_if; 1627 1628 /* Clear the timeout timer. */ 1629 ifp->if_timer = 0; 1630 1631 if (sc->tl_cdata.tl_tx_head == NULL) { 1632 ifp->if_flags &= ~IFF_OACTIVE; 1633 sc->tl_cdata.tl_tx_tail = NULL; 1634 sc->tl_txeoc = 1; 1635 } else { 1636 sc->tl_txeoc = 0; 1637 /* First we have to ack the EOC interrupt. */ 1638 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1639 /* Then load the address of the next TX list. */ 1640 CSR_WRITE_4(sc, TL_CH_PARM, 1641 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1642 /* Restart TX channel. */ 1643 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1644 cmd &= ~TL_CMD_RT; 1645 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1646 CMD_PUT(sc, cmd); 1647 return(0); 1648 } 1649 1650 return(1); 1651 } 1652 1653 static int tl_intvec_adchk(xsc, type) 1654 void *xsc; 1655 u_int32_t type; 1656 { 1657 struct tl_softc *sc; 1658 1659 sc = xsc; 1660 1661 if (type) 1662 printf("tl%d: adapter check: %x\n", sc->tl_unit, 1663 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1664 1665 tl_softreset(sc, 1); 1666 tl_stop(sc); 1667 tl_init(sc); 1668 CMD_SET(sc, TL_CMD_INTSON); 1669 1670 return(0); 1671 } 1672 1673 static int tl_intvec_netsts(xsc, type) 1674 void *xsc; 1675 u_int32_t type; 1676 { 1677 struct tl_softc *sc; 1678 u_int16_t netsts; 1679 1680 sc = xsc; 1681 1682 netsts = tl_dio_read16(sc, TL_NETSTS); 1683 tl_dio_write16(sc, TL_NETSTS, netsts); 1684 1685 printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 1686 1687 return(1); 1688 } 1689 1690 static void tl_intr(xsc) 1691 void *xsc; 1692 { 1693 struct tl_softc *sc; 1694 struct ifnet *ifp; 1695 int r = 0; 1696 u_int32_t type = 0; 1697 u_int16_t ints = 0; 1698 u_int8_t ivec = 0; 1699 1700 sc = xsc; 1701 1702 /* Disable interrupts */ 1703 ints = CSR_READ_2(sc, TL_HOST_INT); 1704 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1705 type = (ints << 16) & 0xFFFF0000; 1706 ivec = (ints & TL_VEC_MASK) >> 5; 1707 ints = (ints & TL_INT_MASK) >> 2; 1708 1709 ifp = &sc->arpcom.ac_if; 1710 1711 switch(ints) { 1712 case (TL_INTR_INVALID): 1713 #ifdef DIAGNOSTIC 1714 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 1715 #endif 1716 /* Re-enable interrupts but don't ack this one. */ 1717 CMD_PUT(sc, type); 1718 r = 0; 1719 break; 1720 case (TL_INTR_TXEOF): 1721 r = tl_intvec_txeof((void *)sc, type); 1722 break; 1723 case (TL_INTR_TXEOC): 1724 r = tl_intvec_txeoc((void *)sc, type); 1725 break; 1726 case (TL_INTR_STATOFLOW): 1727 tl_stats_update(sc); 1728 r = 1; 1729 break; 1730 case (TL_INTR_RXEOF): 1731 r = tl_intvec_rxeof((void *)sc, type); 1732 break; 1733 case (TL_INTR_DUMMY): 1734 printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 1735 r = 1; 1736 break; 1737 case (TL_INTR_ADCHK): 1738 if (ivec) 1739 r = tl_intvec_adchk((void *)sc, type); 1740 else 1741 r = tl_intvec_netsts((void *)sc, type); 1742 break; 1743 case (TL_INTR_RXEOC): 1744 r = tl_intvec_rxeoc((void *)sc, type); 1745 break; 1746 default: 1747 printf("%s: bogus interrupt type\n", ifp->if_xname); 1748 break; 1749 } 1750 1751 /* Re-enable interrupts */ 1752 if (r) { 1753 CMD_PUT(sc, TL_CMD_ACK | r | type); 1754 } 1755 1756 if (!ifq_is_empty(&ifp->if_snd)) 1757 tl_start(ifp); 1758 1759 return; 1760 } 1761 1762 static void tl_stats_update(xsc) 1763 void *xsc; 1764 { 1765 struct tl_softc *sc; 1766 struct ifnet *ifp; 1767 struct tl_stats tl_stats; 1768 struct mii_data *mii; 1769 u_int32_t *p; 1770 1771 crit_enter(); 1772 1773 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1774 1775 sc = xsc; 1776 ifp = &sc->arpcom.ac_if; 1777 1778 p = (u_int32_t *)&tl_stats; 1779 1780 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1781 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1782 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1783 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1784 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1785 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1786 1787 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1788 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1789 tl_stats.tl_tx_multi_collision; 1790 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1791 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1792 tl_rx_overrun(tl_stats); 1793 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1794 1795 if (tl_tx_underrun(tl_stats)) { 1796 u_int8_t tx_thresh; 1797 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1798 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1799 tx_thresh >>= 4; 1800 tx_thresh++; 1801 printf("tl%d: tx underrun -- increasing " 1802 "tx threshold to %d bytes\n", sc->tl_unit, 1803 (64 * (tx_thresh * 4))); 1804 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1805 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1806 } 1807 } 1808 1809 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc); 1810 1811 if (!sc->tl_bitrate) { 1812 mii = device_get_softc(sc->tl_miibus); 1813 mii_tick(mii); 1814 } 1815 1816 crit_exit(); 1817 1818 return; 1819 } 1820 1821 /* 1822 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1823 * pointers to the fragment pointers. 1824 */ 1825 static int tl_encap(sc, c, m_head) 1826 struct tl_softc *sc; 1827 struct tl_chain *c; 1828 struct mbuf *m_head; 1829 { 1830 int frag = 0; 1831 struct tl_frag *f = NULL; 1832 int total_len; 1833 struct mbuf *m; 1834 1835 /* 1836 * Start packing the mbufs in this chain into 1837 * the fragment pointers. Stop when we run out 1838 * of fragments or hit the end of the mbuf chain. 1839 */ 1840 m = m_head; 1841 total_len = 0; 1842 1843 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1844 if (m->m_len != 0) { 1845 if (frag == TL_MAXFRAGS) 1846 break; 1847 total_len+= m->m_len; 1848 c->tl_ptr->tl_frag[frag].tlist_dadr = 1849 vtophys(mtod(m, vm_offset_t)); 1850 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1851 frag++; 1852 } 1853 } 1854 1855 /* 1856 * Handle special cases. 1857 * Special case #1: we used up all 10 fragments, but 1858 * we have more mbufs left in the chain. Copy the 1859 * data into an mbuf cluster. Note that we don't 1860 * bother clearing the values in the other fragment 1861 * pointers/counters; it wouldn't gain us anything, 1862 * and would waste cycles. 1863 */ 1864 if (m != NULL) { 1865 struct mbuf *m_new = NULL; 1866 1867 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1868 if (m_new == NULL) { 1869 printf("tl%d: no memory for tx list\n", sc->tl_unit); 1870 return(1); 1871 } 1872 if (m_head->m_pkthdr.len > MHLEN) { 1873 MCLGET(m_new, MB_DONTWAIT); 1874 if (!(m_new->m_flags & M_EXT)) { 1875 m_freem(m_new); 1876 printf("tl%d: no memory for tx list\n", 1877 sc->tl_unit); 1878 return(1); 1879 } 1880 } 1881 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1882 mtod(m_new, caddr_t)); 1883 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1884 m_freem(m_head); 1885 m_head = m_new; 1886 f = &c->tl_ptr->tl_frag[0]; 1887 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1888 f->tlist_dcnt = total_len = m_new->m_len; 1889 frag = 1; 1890 } 1891 1892 /* 1893 * Special case #2: the frame is smaller than the minimum 1894 * frame size. We have to pad it to make the chip happy. 1895 */ 1896 if (total_len < TL_MIN_FRAMELEN) { 1897 if (frag == TL_MAXFRAGS) 1898 printf("tl%d: all frags filled but " 1899 "frame still to small!\n", sc->tl_unit); 1900 f = &c->tl_ptr->tl_frag[frag]; 1901 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1902 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1903 total_len += f->tlist_dcnt; 1904 frag++; 1905 } 1906 1907 c->tl_mbuf = m_head; 1908 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1909 c->tl_ptr->tlist_frsize = total_len; 1910 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1911 c->tl_ptr->tlist_fptr = 0; 1912 1913 return(0); 1914 } 1915 1916 /* 1917 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1918 * to the mbuf data regions directly in the transmit lists. We also save a 1919 * copy of the pointers since the transmit list fragment pointers are 1920 * physical addresses. 1921 */ 1922 static void tl_start(ifp) 1923 struct ifnet *ifp; 1924 { 1925 struct tl_softc *sc; 1926 struct mbuf *m_head = NULL; 1927 u_int32_t cmd; 1928 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1929 1930 sc = ifp->if_softc; 1931 1932 /* 1933 * Check for an available queue slot. If there are none, 1934 * punt. 1935 */ 1936 if (sc->tl_cdata.tl_tx_free == NULL) { 1937 ifp->if_flags |= IFF_OACTIVE; 1938 return; 1939 } 1940 1941 start_tx = sc->tl_cdata.tl_tx_free; 1942 1943 while(sc->tl_cdata.tl_tx_free != NULL) { 1944 m_head = ifq_dequeue(&ifp->if_snd); 1945 if (m_head == NULL) 1946 break; 1947 1948 /* Pick a chain member off the free list. */ 1949 cur_tx = sc->tl_cdata.tl_tx_free; 1950 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1951 1952 cur_tx->tl_next = NULL; 1953 1954 /* Pack the data into the list. */ 1955 tl_encap(sc, cur_tx, m_head); 1956 1957 /* Chain it together */ 1958 if (prev != NULL) { 1959 prev->tl_next = cur_tx; 1960 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 1961 } 1962 prev = cur_tx; 1963 1964 BPF_MTAP(ifp, cur_tx->tl_mbuf); 1965 } 1966 1967 /* 1968 * If there are no packets queued, bail. 1969 */ 1970 if (cur_tx == NULL) 1971 return; 1972 1973 /* 1974 * That's all we can stands, we can't stands no more. 1975 * If there are no other transfers pending, then issue the 1976 * TX GO command to the adapter to start things moving. 1977 * Otherwise, just leave the data in the queue and let 1978 * the EOF/EOC interrupt handler send. 1979 */ 1980 if (sc->tl_cdata.tl_tx_head == NULL) { 1981 sc->tl_cdata.tl_tx_head = start_tx; 1982 sc->tl_cdata.tl_tx_tail = cur_tx; 1983 1984 if (sc->tl_txeoc) { 1985 sc->tl_txeoc = 0; 1986 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 1987 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1988 cmd &= ~TL_CMD_RT; 1989 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1990 CMD_PUT(sc, cmd); 1991 } 1992 } else { 1993 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 1994 sc->tl_cdata.tl_tx_tail = cur_tx; 1995 } 1996 1997 /* 1998 * Set a timeout in case the chip goes out to lunch. 1999 */ 2000 ifp->if_timer = 5; 2001 2002 return; 2003 } 2004 2005 static void tl_init(xsc) 2006 void *xsc; 2007 { 2008 struct tl_softc *sc = xsc; 2009 struct ifnet *ifp = &sc->arpcom.ac_if; 2010 struct mii_data *mii; 2011 2012 crit_enter(); 2013 2014 /* 2015 * Cancel pending I/O. 2016 */ 2017 tl_stop(sc); 2018 2019 /* Initialize TX FIFO threshold */ 2020 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 2021 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 2022 2023 /* Set PCI burst size */ 2024 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 2025 2026 /* 2027 * Set 'capture all frames' bit for promiscuous mode. 2028 */ 2029 if (ifp->if_flags & IFF_PROMISC) 2030 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2031 else 2032 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2033 2034 /* 2035 * Set capture broadcast bit to capture broadcast frames. 2036 */ 2037 if (ifp->if_flags & IFF_BROADCAST) 2038 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2039 else 2040 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2041 2042 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2043 2044 /* Init our MAC address */ 2045 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 2046 2047 /* Init multicast filter, if needed. */ 2048 tl_setmulti(sc); 2049 2050 /* Init circular RX list. */ 2051 if (tl_list_rx_init(sc) == ENOBUFS) { 2052 printf("tl%d: initialization failed: no " 2053 "memory for rx buffers\n", sc->tl_unit); 2054 tl_stop(sc); 2055 return; 2056 } 2057 2058 /* Init TX pointers. */ 2059 tl_list_tx_init(sc); 2060 2061 /* Enable PCI interrupts. */ 2062 CMD_SET(sc, TL_CMD_INTSON); 2063 2064 /* Load the address of the rx list */ 2065 CMD_SET(sc, TL_CMD_RT); 2066 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2067 2068 if (!sc->tl_bitrate) { 2069 if (sc->tl_miibus != NULL) { 2070 mii = device_get_softc(sc->tl_miibus); 2071 mii_mediachg(mii); 2072 } 2073 } 2074 2075 /* Send the RX go command */ 2076 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2077 2078 ifp->if_flags |= IFF_RUNNING; 2079 ifp->if_flags &= ~IFF_OACTIVE; 2080 2081 /* Start the stats update counter */ 2082 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc); 2083 2084 crit_exit(); 2085 } 2086 2087 /* 2088 * Set media options. 2089 */ 2090 static int tl_ifmedia_upd(ifp) 2091 struct ifnet *ifp; 2092 { 2093 struct tl_softc *sc; 2094 struct mii_data *mii = NULL; 2095 2096 sc = ifp->if_softc; 2097 2098 if (sc->tl_bitrate) 2099 tl_setmode(sc, sc->ifmedia.ifm_media); 2100 else { 2101 mii = device_get_softc(sc->tl_miibus); 2102 mii_mediachg(mii); 2103 } 2104 2105 return(0); 2106 } 2107 2108 /* 2109 * Report current media status. 2110 */ 2111 static void tl_ifmedia_sts(ifp, ifmr) 2112 struct ifnet *ifp; 2113 struct ifmediareq *ifmr; 2114 { 2115 struct tl_softc *sc; 2116 struct mii_data *mii; 2117 2118 sc = ifp->if_softc; 2119 2120 ifmr->ifm_active = IFM_ETHER; 2121 2122 if (sc->tl_bitrate) { 2123 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2124 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2125 else 2126 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2127 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2128 ifmr->ifm_active |= IFM_HDX; 2129 else 2130 ifmr->ifm_active |= IFM_FDX; 2131 return; 2132 } else { 2133 mii = device_get_softc(sc->tl_miibus); 2134 mii_pollstat(mii); 2135 ifmr->ifm_active = mii->mii_media_active; 2136 ifmr->ifm_status = mii->mii_media_status; 2137 } 2138 2139 return; 2140 } 2141 2142 static int tl_ioctl(ifp, command, data, cr) 2143 struct ifnet *ifp; 2144 u_long command; 2145 caddr_t data; 2146 struct ucred *cr; 2147 { 2148 struct tl_softc *sc = ifp->if_softc; 2149 struct ifreq *ifr = (struct ifreq *) data; 2150 int error = 0; 2151 2152 crit_enter(); 2153 2154 switch(command) { 2155 case SIOCSIFFLAGS: 2156 if (ifp->if_flags & IFF_UP) { 2157 if (ifp->if_flags & IFF_RUNNING && 2158 ifp->if_flags & IFF_PROMISC && 2159 !(sc->tl_if_flags & IFF_PROMISC)) { 2160 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2161 tl_setmulti(sc); 2162 } else if (ifp->if_flags & IFF_RUNNING && 2163 !(ifp->if_flags & IFF_PROMISC) && 2164 sc->tl_if_flags & IFF_PROMISC) { 2165 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2166 tl_setmulti(sc); 2167 } else 2168 tl_init(sc); 2169 } else { 2170 if (ifp->if_flags & IFF_RUNNING) { 2171 tl_stop(sc); 2172 } 2173 } 2174 sc->tl_if_flags = ifp->if_flags; 2175 error = 0; 2176 break; 2177 case SIOCADDMULTI: 2178 case SIOCDELMULTI: 2179 tl_setmulti(sc); 2180 error = 0; 2181 break; 2182 case SIOCSIFMEDIA: 2183 case SIOCGIFMEDIA: 2184 if (sc->tl_bitrate) 2185 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2186 else { 2187 struct mii_data *mii; 2188 mii = device_get_softc(sc->tl_miibus); 2189 error = ifmedia_ioctl(ifp, ifr, 2190 &mii->mii_media, command); 2191 } 2192 break; 2193 default: 2194 error = ether_ioctl(ifp, command, data); 2195 break; 2196 } 2197 2198 crit_exit(); 2199 2200 return(error); 2201 } 2202 2203 static void tl_watchdog(ifp) 2204 struct ifnet *ifp; 2205 { 2206 struct tl_softc *sc; 2207 2208 sc = ifp->if_softc; 2209 2210 printf("tl%d: device timeout\n", sc->tl_unit); 2211 2212 ifp->if_oerrors++; 2213 2214 tl_softreset(sc, 1); 2215 tl_init(sc); 2216 2217 return; 2218 } 2219 2220 /* 2221 * Stop the adapter and free any mbufs allocated to the 2222 * RX and TX lists. 2223 */ 2224 static void tl_stop(sc) 2225 struct tl_softc *sc; 2226 { 2227 int i; 2228 struct ifnet *ifp; 2229 2230 ifp = &sc->arpcom.ac_if; 2231 2232 /* Stop the stats updater. */ 2233 callout_stop(&sc->tl_stat_timer); 2234 2235 /* Stop the transmitter */ 2236 CMD_CLR(sc, TL_CMD_RT); 2237 CMD_SET(sc, TL_CMD_STOP); 2238 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2239 2240 /* Stop the receiver */ 2241 CMD_SET(sc, TL_CMD_RT); 2242 CMD_SET(sc, TL_CMD_STOP); 2243 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2244 2245 /* 2246 * Disable host interrupts. 2247 */ 2248 CMD_SET(sc, TL_CMD_INTSOFF); 2249 2250 /* 2251 * Clear list pointer. 2252 */ 2253 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2254 2255 /* 2256 * Free the RX lists. 2257 */ 2258 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2259 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2260 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2261 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2262 } 2263 } 2264 bzero((char *)&sc->tl_ldata->tl_rx_list, 2265 sizeof(sc->tl_ldata->tl_rx_list)); 2266 2267 /* 2268 * Free the TX list buffers. 2269 */ 2270 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2271 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2272 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2273 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2274 } 2275 } 2276 bzero((char *)&sc->tl_ldata->tl_tx_list, 2277 sizeof(sc->tl_ldata->tl_tx_list)); 2278 2279 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2280 2281 return; 2282 } 2283 2284 /* 2285 * Stop all chip I/O so that the kernel's probe routines don't 2286 * get confused by errant DMAs when rebooting. 2287 */ 2288 static void tl_shutdown(dev) 2289 device_t dev; 2290 { 2291 struct tl_softc *sc; 2292 2293 sc = device_get_softc(dev); 2294 2295 tl_stop(sc); 2296 2297 return; 2298 } 2299