1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.26 2005/06/06 23:12:07 okumoto Exp $ 34 */ 35 36 /* 37 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 38 * Manuals, sample driver and firmware source kits are available 39 * from http://www.alteon.com/support/openkits. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Electrical Engineering Department 43 * Columbia University, New York City 44 */ 45 46 /* 47 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 48 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 49 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 50 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 51 * filtering and jumbo (9014 byte) frames. The hardware is largely 52 * controlled by firmware, which must be loaded into the NIC during 53 * initialization. 54 * 55 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 56 * revision, which supports new features such as extended commands, 57 * extended jumbo receive ring desciptors and a mini receive ring. 58 * 59 * Alteon Networks is to be commended for releasing such a vast amount 60 * of development material for the Tigon NIC without requiring an NDA 61 * (although they really should have done it a long time ago). With 62 * any luck, the other vendors will finally wise up and follow Alteon's 63 * stellar example. 64 * 65 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 66 * this driver by #including it as a C header file. This bloats the 67 * driver somewhat, but it's the easiest method considering that the 68 * driver code and firmware code need to be kept in sync. The source 69 * for the firmware is not provided with the FreeBSD distribution since 70 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 71 * 72 * The following people deserve special thanks: 73 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 74 * for testing 75 * - Raymond Lee of Netgear, for providing a pair of Netgear 76 * GA620 Tigon 2 boards for testing 77 * - Ulf Zimmermann, for bringing the GA260 to my attention and 78 * convincing me to write this driver. 79 * - Andrew Gallatin for providing FreeBSD/Alpha support. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/sockio.h> 85 #include <sys/mbuf.h> 86 #include <sys/malloc.h> 87 #include <sys/kernel.h> 88 #include <sys/socket.h> 89 #include <sys/queue.h> 90 #include <sys/thread2.h> 91 92 #include <net/if.h> 93 #include <net/ifq_var.h> 94 #include <net/if_arp.h> 95 #include <net/ethernet.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_types.h> 99 #include <net/vlan/if_vlan_var.h> 100 101 #include <net/bpf.h> 102 103 #include <netinet/in_systm.h> 104 #include <netinet/in.h> 105 #include <netinet/ip.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/bus.h> 110 #include <machine/resource.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 114 #include <bus/pci/pcireg.h> 115 #include <bus/pci/pcivar.h> 116 117 #include "if_tireg.h" 118 #include "ti_fw.h" 119 #include "ti_fw2.h" 120 121 /* 122 * Temporarily disable the checksum offload support for now. 123 * Tests with ftp.freesoftware.com show that after about 12 hours, 124 * the firmware will begin calculating completely bogus TX checksums 125 * and refuse to stop until the interface is reset. Unfortunately, 126 * there isn't enough time to fully debug this before the 4.1 127 * release, so this will need to stay off for now. 128 */ 129 #ifdef notdef 130 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 131 #else 132 #define TI_CSUM_FEATURES 0 133 #endif 134 135 /* 136 * Various supported device vendors/types and their names. 137 */ 138 139 static struct ti_type ti_devs[] = { 140 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 141 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 142 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 143 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 144 { TC_VENDORID, TC_DEVICEID_3C985, 145 "3Com 3c985-SX Gigabit Ethernet" }, 146 { NG_VENDORID, NG_DEVICEID_GA620, 147 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 148 { NG_VENDORID, NG_DEVICEID_GA620T, 149 "Netgear GA620 1000baseT Gigabit Ethernet" }, 150 { SGI_VENDORID, SGI_DEVICEID_TIGON, 151 "Silicon Graphics Gigabit Ethernet" }, 152 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 153 "Farallon PN9000SX Gigabit Ethernet" }, 154 { 0, 0, NULL } 155 }; 156 157 static int ti_probe(device_t); 158 static int ti_attach(device_t); 159 static int ti_detach(device_t); 160 static void ti_txeof(struct ti_softc *); 161 static void ti_rxeof(struct ti_softc *); 162 163 static void ti_stats_update(struct ti_softc *); 164 static int ti_encap(struct ti_softc *, struct mbuf *, uint32_t *); 165 166 static void ti_intr(void *); 167 static void ti_start(struct ifnet *); 168 static int ti_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 169 static void ti_init(void *); 170 static void ti_init2(struct ti_softc *); 171 static void ti_stop(struct ti_softc *); 172 static void ti_watchdog(struct ifnet *); 173 static void ti_shutdown(device_t); 174 static int ti_ifmedia_upd(struct ifnet *); 175 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 176 177 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 178 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 179 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 180 181 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 182 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 183 static void ti_setmulti(struct ti_softc *); 184 185 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t); 186 static void ti_loadfw(struct ti_softc *); 187 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 188 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, 189 caddr_t, int); 190 static void ti_handle_events(struct ti_softc *); 191 static int ti_alloc_jumbo_mem(struct ti_softc *); 192 static struct ti_jslot * 193 ti_jalloc(struct ti_softc *); 194 static void ti_jfree(void *); 195 static void ti_jref(void *); 196 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 197 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 198 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 199 static int ti_init_rx_ring_std(struct ti_softc *); 200 static void ti_free_rx_ring_std(struct ti_softc *); 201 static int ti_init_rx_ring_jumbo(struct ti_softc *); 202 static void ti_free_rx_ring_jumbo(struct ti_softc *); 203 static int ti_init_rx_ring_mini(struct ti_softc *); 204 static void ti_free_rx_ring_mini(struct ti_softc *); 205 static void ti_free_tx_ring(struct ti_softc *); 206 static int ti_init_tx_ring(struct ti_softc *); 207 208 static int ti_64bitslot_war(struct ti_softc *); 209 static int ti_chipinit(struct ti_softc *); 210 static int ti_gibinit(struct ti_softc *); 211 212 static device_method_t ti_methods[] = { 213 /* Device interface */ 214 DEVMETHOD(device_probe, ti_probe), 215 DEVMETHOD(device_attach, ti_attach), 216 DEVMETHOD(device_detach, ti_detach), 217 DEVMETHOD(device_shutdown, ti_shutdown), 218 { 0, 0 } 219 }; 220 221 222 static DEFINE_CLASS_0(ti, ti_driver, ti_methods, sizeof(struct ti_softc)); 223 static devclass_t ti_devclass; 224 225 DECLARE_DUMMY_MODULE(if_ti); 226 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 227 228 /* 229 * Send an instruction or address to the EEPROM, check for ACK. 230 */ 231 static uint32_t 232 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 233 { 234 int ack = 0, i; 235 236 /* 237 * Make sure we're in TX mode. 238 */ 239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 240 241 /* 242 * Feed in each bit and stobe the clock. 243 */ 244 for (i = 0x80; i; i >>= 1) { 245 if (byte & i) 246 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 247 else 248 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 249 DELAY(1); 250 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 251 DELAY(1); 252 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 } 254 255 /* 256 * Turn off TX mode. 257 */ 258 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 259 260 /* 261 * Check for ack. 262 */ 263 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 264 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 265 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 266 267 return(ack); 268 } 269 270 /* 271 * Read a byte of data stored in the EEPROM at address 'addr.' 272 * We have to send two address bytes since the EEPROM can hold 273 * more than 256 bytes of data. 274 */ 275 static uint8_t 276 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 277 { 278 int i; 279 uint8_t byte = 0; 280 281 EEPROM_START; 282 283 /* 284 * Send write control code to EEPROM. 285 */ 286 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 287 printf("ti%d: failed to send write command, status: %x\n", 288 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 289 return(1); 290 } 291 292 /* 293 * Send first byte of address of byte we want to read. 294 */ 295 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 296 printf("ti%d: failed to send address, status: %x\n", 297 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 298 return(1); 299 } 300 /* 301 * Send second byte address of byte we want to read. 302 */ 303 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 304 printf("ti%d: failed to send address, status: %x\n", 305 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 306 return(1); 307 } 308 309 EEPROM_STOP; 310 EEPROM_START; 311 /* 312 * Send read control code to EEPROM. 313 */ 314 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 315 printf("ti%d: failed to send read command, status: %x\n", 316 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 317 return(1); 318 } 319 320 /* 321 * Start reading bits from EEPROM. 322 */ 323 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 324 for (i = 0x80; i; i >>= 1) { 325 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 326 DELAY(1); 327 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 328 byte |= i; 329 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 330 DELAY(1); 331 } 332 333 EEPROM_STOP; 334 335 /* 336 * No ACK generated for read, so just return byte. 337 */ 338 339 *dest = byte; 340 341 return(0); 342 } 343 344 /* 345 * Read a sequence of bytes from the EEPROM. 346 */ 347 static int 348 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 349 { 350 int err = 0, i; 351 uint8_t byte = 0; 352 353 for (i = 0; i < cnt; i++) { 354 err = ti_eeprom_getbyte(sc, off + i, &byte); 355 if (err) 356 break; 357 *(dest + i) = byte; 358 } 359 360 return(err ? 1 : 0); 361 } 362 363 /* 364 * NIC memory access function. Can be used to either clear a section 365 * of NIC local memory or (if buf is non-NULL) copy data into it. 366 */ 367 static void 368 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, caddr_t buf) 369 { 370 int cnt, segptr, segsize; 371 caddr_t ti_winbase, ptr; 372 373 segptr = addr; 374 cnt = len; 375 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 376 ptr = buf; 377 378 while(cnt) { 379 if (cnt < TI_WINLEN) 380 segsize = cnt; 381 else 382 segsize = TI_WINLEN - (segptr % TI_WINLEN); 383 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 384 if (buf == NULL) 385 bzero((char *)ti_winbase + (segptr & 386 (TI_WINLEN - 1)), segsize); 387 else { 388 bcopy((char *)ptr, (char *)ti_winbase + 389 (segptr & (TI_WINLEN - 1)), segsize); 390 ptr += segsize; 391 } 392 segptr += segsize; 393 cnt -= segsize; 394 } 395 } 396 397 /* 398 * Load firmware image into the NIC. Check that the firmware revision 399 * is acceptable and see if we want the firmware for the Tigon 1 or 400 * Tigon 2. 401 */ 402 static void 403 ti_loadfw(struct ti_softc *sc) 404 { 405 switch(sc->ti_hwrev) { 406 case TI_HWREV_TIGON: 407 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 408 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 409 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 410 printf("ti%d: firmware revision mismatch; want " 411 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 412 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 413 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 414 tigonFwReleaseMinor, tigonFwReleaseFix); 415 return; 416 } 417 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 418 (caddr_t)tigonFwText); 419 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 420 (caddr_t)tigonFwData); 421 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 422 (caddr_t)tigonFwRodata); 423 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 424 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 425 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 426 break; 427 case TI_HWREV_TIGON_II: 428 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 429 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 430 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 431 printf("ti%d: firmware revision mismatch; want " 432 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 433 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 434 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 435 tigon2FwReleaseMinor, tigon2FwReleaseFix); 436 return; 437 } 438 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 439 (caddr_t)tigon2FwText); 440 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 441 (caddr_t)tigon2FwData); 442 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 443 (caddr_t)tigon2FwRodata); 444 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 445 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 446 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 447 break; 448 default: 449 printf("ti%d: can't load firmware: unknown hardware rev\n", 450 sc->ti_unit); 451 break; 452 } 453 } 454 455 /* 456 * Send the NIC a command via the command ring. 457 */ 458 static void 459 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 460 { 461 uint32_t index; 462 463 if (sc->ti_rdata->ti_cmd_ring == NULL) 464 return; 465 466 index = sc->ti_cmd_saved_prodidx; 467 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 468 TI_INC(index, TI_CMD_RING_CNT); 469 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 470 sc->ti_cmd_saved_prodidx = index; 471 } 472 473 /* 474 * Send the NIC an extended command. The 'len' parameter specifies the 475 * number of command slots to include after the initial command. 476 */ 477 static void 478 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 479 { 480 uint32_t index; 481 int i; 482 483 if (sc->ti_rdata->ti_cmd_ring == NULL) 484 return; 485 486 index = sc->ti_cmd_saved_prodidx; 487 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 488 TI_INC(index, TI_CMD_RING_CNT); 489 for (i = 0; i < len; i++) { 490 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 491 *(uint32_t *)(&arg[i * 4])); 492 TI_INC(index, TI_CMD_RING_CNT); 493 } 494 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 495 sc->ti_cmd_saved_prodidx = index; 496 } 497 498 /* 499 * Handle events that have triggered interrupts. 500 */ 501 static void 502 ti_handle_events(struct ti_softc *sc) 503 { 504 struct ti_event_desc *e; 505 506 if (sc->ti_rdata->ti_event_ring == NULL) 507 return; 508 509 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 510 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 511 switch(e->ti_event) { 512 case TI_EV_LINKSTAT_CHANGED: 513 sc->ti_linkstat = e->ti_code; 514 if (e->ti_code == TI_EV_CODE_LINK_UP) 515 printf("ti%d: 10/100 link up\n", sc->ti_unit); 516 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 517 printf("ti%d: gigabit link up\n", sc->ti_unit); 518 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 519 printf("ti%d: link down\n", sc->ti_unit); 520 break; 521 case TI_EV_ERROR: 522 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 523 printf("ti%d: invalid command\n", sc->ti_unit); 524 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 525 printf("ti%d: unknown command\n", sc->ti_unit); 526 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 527 printf("ti%d: bad config data\n", sc->ti_unit); 528 break; 529 case TI_EV_FIRMWARE_UP: 530 ti_init2(sc); 531 break; 532 case TI_EV_STATS_UPDATED: 533 ti_stats_update(sc); 534 break; 535 case TI_EV_RESET_JUMBO_RING: 536 case TI_EV_MCAST_UPDATED: 537 /* Who cares. */ 538 break; 539 default: 540 printf("ti%d: unknown event: %d\n", 541 sc->ti_unit, e->ti_event); 542 break; 543 } 544 /* Advance the consumer index. */ 545 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 546 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 547 } 548 } 549 550 /* 551 * Memory management for the jumbo receive ring is a pain in the 552 * butt. We need to allocate at least 9018 bytes of space per frame, 553 * _and_ it has to be contiguous (unless you use the extended 554 * jumbo descriptor format). Using malloc() all the time won't 555 * work: malloc() allocates memory in powers of two, which means we 556 * would end up wasting a considerable amount of space by allocating 557 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 558 * to do our own memory management. 559 * 560 * The driver needs to allocate a contiguous chunk of memory at boot 561 * time. We then chop this up ourselves into 9K pieces and use them 562 * as external mbuf storage. 563 * 564 * One issue here is how much memory to allocate. The jumbo ring has 565 * 256 slots in it, but at 9K per slot than can consume over 2MB of 566 * RAM. This is a bit much, especially considering we also need 567 * RAM for the standard ring and mini ring (on the Tigon 2). To 568 * save space, we only actually allocate enough memory for 64 slots 569 * by default, which works out to between 500 and 600K. This can 570 * be tuned by changing a #define in if_tireg.h. 571 */ 572 573 static int 574 ti_alloc_jumbo_mem(struct ti_softc *sc) 575 { 576 struct ti_jslot *entry; 577 caddr_t ptr; 578 int i; 579 580 /* Grab a big chunk o' storage. */ 581 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 582 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 583 584 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 585 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 586 return(ENOBUFS); 587 } 588 589 SLIST_INIT(&sc->ti_jfree_listhead); 590 591 /* 592 * Now divide it up into 9K pieces and save the addresses 593 * in an array. Note that we play an evil trick here by using 594 * the first few bytes in the buffer to hold the the address 595 * of the softc structure for this interface. This is because 596 * ti_jfree() needs it, but it is called by the mbuf management 597 * code which will not pass it to us explicitly. 598 */ 599 ptr = sc->ti_cdata.ti_jumbo_buf; 600 for (i = 0; i < TI_JSLOTS; i++) { 601 entry = &sc->ti_cdata.ti_jslots[i]; 602 entry->ti_sc = sc; 603 entry->ti_buf = ptr; 604 entry->ti_inuse = 0; 605 entry->ti_slot = i; 606 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link); 607 ptr += TI_JLEN; 608 } 609 610 return(0); 611 } 612 613 /* 614 * Allocate a jumbo buffer. 615 */ 616 static struct ti_jslot * 617 ti_jalloc(struct ti_softc *sc) 618 { 619 struct ti_jslot *entry; 620 621 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 622 623 if (entry == NULL) { 624 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 625 return(NULL); 626 } 627 628 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jslot_link); 629 entry->ti_inuse = 1; 630 return(entry); 631 } 632 633 /* 634 * Adjust usage count on a jumbo buffer. In general this doesn't 635 * get used much because our jumbo buffers don't get passed around 636 * too much, but it's implemented for correctness. 637 */ 638 static void 639 ti_jref(void *arg) 640 { 641 struct ti_jslot *entry = (struct ti_jslot *)arg; 642 struct ti_softc *sc = entry->ti_sc; 643 644 if (sc == NULL) 645 panic("ti_jref: can't find softc pointer!"); 646 647 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry) 648 panic("ti_jref: asked to reference buffer " 649 "that we don't manage!"); 650 if (entry->ti_inuse == 0) 651 panic("ti_jref: buffer already free!"); 652 entry->ti_inuse++; 653 } 654 655 /* 656 * Release a jumbo buffer. 657 */ 658 static void 659 ti_jfree(void *arg) 660 { 661 struct ti_jslot *entry = (struct ti_jslot *)arg; 662 struct ti_softc *sc = entry->ti_sc; 663 664 if (sc == NULL) 665 panic("ti_jref: can't find softc pointer!"); 666 667 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry) 668 panic("ti_jref: asked to reference buffer " 669 "that we don't manage!"); 670 if (entry->ti_inuse == 0) 671 panic("ti_jref: buffer already free!"); 672 if (--entry->ti_inuse == 0) 673 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link); 674 } 675 676 677 /* 678 * Intialize a standard receive ring descriptor. 679 */ 680 static int 681 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m) 682 { 683 struct mbuf *m_new; 684 struct ti_rx_desc *r; 685 686 if (m == NULL) { 687 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 688 if (m_new == NULL) 689 return(ENOBUFS); 690 691 MCLGET(m_new, MB_DONTWAIT); 692 if (!(m_new->m_flags & M_EXT)) { 693 m_freem(m_new); 694 return(ENOBUFS); 695 } 696 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 697 } else { 698 m_new = m; 699 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 700 m_new->m_data = m_new->m_ext.ext_buf; 701 } 702 703 m_adj(m_new, ETHER_ALIGN); 704 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 705 r = &sc->ti_rdata->ti_rx_std_ring[i]; 706 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 707 r->ti_type = TI_BDTYPE_RECV_BD; 708 r->ti_flags = 0; 709 if (sc->arpcom.ac_if.if_hwassist) 710 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 711 r->ti_len = m_new->m_len; 712 r->ti_idx = i; 713 714 return(0); 715 } 716 717 /* 718 * Intialize a mini receive ring descriptor. This only applies to 719 * the Tigon 2. 720 */ 721 static int 722 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m) 723 { 724 struct mbuf *m_new; 725 struct ti_rx_desc *r; 726 727 if (m == NULL) { 728 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 729 if (m_new == NULL) { 730 return(ENOBUFS); 731 } 732 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 733 } else { 734 m_new = m; 735 m_new->m_data = m_new->m_pktdat; 736 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 737 } 738 739 m_adj(m_new, ETHER_ALIGN); 740 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 741 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 742 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 743 r->ti_type = TI_BDTYPE_RECV_BD; 744 r->ti_flags = TI_BDFLAG_MINI_RING; 745 if (sc->arpcom.ac_if.if_hwassist) 746 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 747 r->ti_len = m_new->m_len; 748 r->ti_idx = i; 749 750 return(0); 751 } 752 753 /* 754 * Initialize a jumbo receive ring descriptor. This allocates 755 * a jumbo buffer from the pool managed internally by the driver. 756 */ 757 static int 758 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 759 { 760 struct mbuf *m_new; 761 struct ti_rx_desc *r; 762 struct ti_jslot *buf; 763 764 if (m == NULL) { 765 /* Allocate the mbuf. */ 766 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 767 if (m_new == NULL) { 768 return(ENOBUFS); 769 } 770 771 /* Allocate the jumbo buffer */ 772 buf = ti_jalloc(sc); 773 if (buf == NULL) { 774 m_freem(m_new); 775 printf("ti%d: jumbo allocation failed " 776 "-- packet dropped!\n", sc->ti_unit); 777 return(ENOBUFS); 778 } 779 780 /* Attach the buffer to the mbuf. */ 781 m_new->m_ext.ext_arg = buf; 782 m_new->m_ext.ext_free = ti_jfree; 783 m_new->m_ext.ext_ref = ti_jref; 784 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 785 786 m_new->m_data = m_new->m_ext.ext_buf; 787 m_new->m_flags |= M_EXT; 788 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 789 } else { 790 m_new = m; 791 m_new->m_data = m_new->m_ext.ext_buf; 792 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 793 } 794 795 m_adj(m_new, ETHER_ALIGN); 796 /* Set up the descriptor. */ 797 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 798 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 799 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 800 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 801 r->ti_flags = TI_BDFLAG_JUMBO_RING; 802 if (sc->arpcom.ac_if.if_hwassist) 803 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 804 r->ti_len = m_new->m_len; 805 r->ti_idx = i; 806 807 return(0); 808 } 809 810 /* 811 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 812 * that's 1MB or memory, which is a lot. For now, we fill only the first 813 * 256 ring entries and hope that our CPU is fast enough to keep up with 814 * the NIC. 815 */ 816 static int 817 ti_init_rx_ring_std(struct ti_softc *sc) 818 { 819 int i; 820 struct ti_cmd_desc cmd; 821 822 for (i = 0; i < TI_SSLOTS; i++) { 823 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 824 return(ENOBUFS); 825 }; 826 827 TI_UPDATE_STDPROD(sc, i - 1); 828 sc->ti_std = i - 1; 829 830 return(0); 831 } 832 833 static void 834 ti_free_rx_ring_std(struct ti_softc *sc) 835 { 836 int i; 837 838 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 839 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 840 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 841 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 842 } 843 bzero(&sc->ti_rdata->ti_rx_std_ring[i], 844 sizeof(struct ti_rx_desc)); 845 } 846 } 847 848 static int 849 ti_init_rx_ring_jumbo(struct ti_softc *sc) 850 { 851 int i; 852 struct ti_cmd_desc cmd; 853 854 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 855 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 856 return(ENOBUFS); 857 } 858 859 TI_UPDATE_JUMBOPROD(sc, i - 1); 860 sc->ti_jumbo = i - 1; 861 862 return(0); 863 } 864 865 static void 866 ti_free_rx_ring_jumbo(struct ti_softc *sc) 867 { 868 int i; 869 870 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 871 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 872 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 873 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 874 } 875 bzero(&sc->ti_rdata->ti_rx_jumbo_ring[i], 876 sizeof(struct ti_rx_desc)); 877 } 878 } 879 880 static int 881 ti_init_rx_ring_mini(struct ti_softc *sc) 882 { 883 int i; 884 885 for (i = 0; i < TI_MSLOTS; i++) { 886 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 887 return(ENOBUFS); 888 } 889 890 TI_UPDATE_MINIPROD(sc, i - 1); 891 sc->ti_mini = i - 1; 892 893 return(0); 894 } 895 896 static void 897 ti_free_rx_ring_mini(struct ti_softc *sc) 898 { 899 int i; 900 901 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 902 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 903 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 904 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 905 } 906 bzero(&sc->ti_rdata->ti_rx_mini_ring[i], 907 sizeof(struct ti_rx_desc)); 908 } 909 } 910 911 static void 912 ti_free_tx_ring(struct ti_softc *sc) 913 { 914 int i; 915 916 if (sc->ti_rdata->ti_tx_ring == NULL) 917 return; 918 919 for (i = 0; i < TI_TX_RING_CNT; i++) { 920 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 921 m_freem(sc->ti_cdata.ti_tx_chain[i]); 922 sc->ti_cdata.ti_tx_chain[i] = NULL; 923 } 924 bzero(&sc->ti_rdata->ti_tx_ring[i], 925 sizeof(struct ti_tx_desc)); 926 } 927 } 928 929 static int 930 ti_init_tx_ring(struct ti_softc *sc) 931 { 932 sc->ti_txcnt = 0; 933 sc->ti_tx_saved_considx = 0; 934 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 935 return(0); 936 } 937 938 /* 939 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 940 * but we have to support the old way too so that Tigon 1 cards will 941 * work. 942 */ 943 static void 944 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 945 { 946 struct ti_cmd_desc cmd; 947 uint16_t *m; 948 uint32_t ext[2] = {0, 0}; 949 950 m = (uint16_t *)&addr->octet[0]; 951 952 switch(sc->ti_hwrev) { 953 case TI_HWREV_TIGON: 954 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 955 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 956 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 957 break; 958 case TI_HWREV_TIGON_II: 959 ext[0] = htons(m[0]); 960 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 961 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 962 break; 963 default: 964 printf("ti%d: unknown hwrev\n", sc->ti_unit); 965 break; 966 } 967 } 968 969 static void 970 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 971 { 972 struct ti_cmd_desc cmd; 973 uint16_t *m; 974 uint32_t ext[2] = {0, 0}; 975 976 m = (uint16_t *)&addr->octet[0]; 977 978 switch(sc->ti_hwrev) { 979 case TI_HWREV_TIGON: 980 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 981 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 982 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 983 break; 984 case TI_HWREV_TIGON_II: 985 ext[0] = htons(m[0]); 986 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 987 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 988 break; 989 default: 990 printf("ti%d: unknown hwrev\n", sc->ti_unit); 991 break; 992 } 993 } 994 995 /* 996 * Configure the Tigon's multicast address filter. 997 * 998 * The actual multicast table management is a bit of a pain, thanks to 999 * slight brain damage on the part of both Alteon and us. With our 1000 * multicast code, we are only alerted when the multicast address table 1001 * changes and at that point we only have the current list of addresses: 1002 * we only know the current state, not the previous state, so we don't 1003 * actually know what addresses were removed or added. The firmware has 1004 * state, but we can't get our grubby mits on it, and there is no 'delete 1005 * all multicast addresses' command. Hence, we have to maintain our own 1006 * state so we know what addresses have been programmed into the NIC at 1007 * any given time. 1008 */ 1009 static void 1010 ti_setmulti(struct ti_softc *sc) 1011 { 1012 struct ifnet *ifp = &sc->arpcom.ac_if; 1013 struct ifmultiaddr *ifma; 1014 struct ti_cmd_desc cmd; 1015 struct ti_mc_entry *mc; 1016 uint32_t intrs; 1017 1018 if (ifp->if_flags & IFF_ALLMULTI) { 1019 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1020 return; 1021 } 1022 1023 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1024 1025 /* Disable interrupts. */ 1026 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1027 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1028 1029 /* First, zot all the existing filters. */ 1030 while (sc->ti_mc_listhead.slh_first != NULL) { 1031 mc = sc->ti_mc_listhead.slh_first; 1032 ti_del_mcast(sc, &mc->mc_addr); 1033 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1034 free(mc, M_DEVBUF); 1035 } 1036 1037 /* Now program new ones. */ 1038 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1039 if (ifma->ifma_addr->sa_family != AF_LINK) 1040 continue; 1041 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT); 1042 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1043 &mc->mc_addr, ETHER_ADDR_LEN); 1044 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1045 ti_add_mcast(sc, &mc->mc_addr); 1046 } 1047 1048 /* Re-enable interrupts. */ 1049 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1050 } 1051 1052 /* 1053 * Check to see if the BIOS has configured us for a 64 bit slot when 1054 * we aren't actually in one. If we detect this condition, we can work 1055 * around it on the Tigon 2 by setting a bit in the PCI state register, 1056 * but for the Tigon 1 we must give up and abort the interface attach. 1057 */ 1058 static int 1059 ti_64bitslot_war(struct ti_softc *sc) 1060 { 1061 if ((CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS) == 0) { 1062 CSR_WRITE_4(sc, 0x600, 0); 1063 CSR_WRITE_4(sc, 0x604, 0); 1064 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1065 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1066 if (sc->ti_hwrev == TI_HWREV_TIGON) 1067 return(EINVAL); 1068 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_32BIT_BUS); 1069 return(0); 1070 } 1071 } 1072 1073 return(0); 1074 } 1075 1076 /* 1077 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1078 * self-test results. 1079 */ 1080 static int 1081 ti_chipinit(struct ti_softc *sc) 1082 { 1083 struct ifnet *ifp = &sc->arpcom.ac_if; 1084 uint32_t cacheline; 1085 uint32_t pci_writemax = 0; 1086 1087 /* Initialize link to down state. */ 1088 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1089 1090 if (ifp->if_capenable & IFCAP_HWCSUM) 1091 ifp->if_hwassist = TI_CSUM_FEATURES; 1092 else 1093 ifp->if_hwassist = 0; 1094 1095 /* Set endianness before we access any non-PCI registers. */ 1096 #if BYTE_ORDER == BIG_ENDIAN 1097 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1098 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1099 #else 1100 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1101 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1102 #endif 1103 1104 /* Check the ROM failed bit to see if self-tests passed. */ 1105 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1106 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1107 return(ENODEV); 1108 } 1109 1110 /* Halt the CPU. */ 1111 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1112 1113 /* Figure out the hardware revision. */ 1114 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1115 case TI_REV_TIGON_I: 1116 sc->ti_hwrev = TI_HWREV_TIGON; 1117 break; 1118 case TI_REV_TIGON_II: 1119 sc->ti_hwrev = TI_HWREV_TIGON_II; 1120 break; 1121 default: 1122 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1123 return(ENODEV); 1124 } 1125 1126 /* Do special setup for Tigon 2. */ 1127 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1128 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1129 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1130 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1131 } 1132 1133 /* Set up the PCI state register. */ 1134 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1135 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1136 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1137 } 1138 1139 /* Clear the read/write max DMA parameters. */ 1140 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1141 TI_PCISTATE_READ_MAXDMA)); 1142 1143 /* Get cache line size. */ 1144 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1145 1146 /* 1147 * If the system has set enabled the PCI memory write 1148 * and invalidate command in the command register, set 1149 * the write max parameter accordingly. This is necessary 1150 * to use MWI with the Tigon 2. 1151 */ 1152 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1153 switch(cacheline) { 1154 case 1: 1155 case 4: 1156 case 8: 1157 case 16: 1158 case 32: 1159 case 64: 1160 break; 1161 default: 1162 /* Disable PCI memory write and invalidate. */ 1163 if (bootverbose) 1164 printf("ti%d: cache line size %d not " 1165 "supported; disabling PCI MWI\n", 1166 sc->ti_unit, cacheline); 1167 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1168 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1169 break; 1170 } 1171 } 1172 1173 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1174 1175 /* This sets the min dma param all the way up (0xff). */ 1176 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1177 1178 /* Configure DMA variables. */ 1179 #if BYTE_ORDER == BIG_ENDIAN 1180 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1181 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1182 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1183 TI_OPMODE_DONT_FRAG_JUMBO); 1184 #else 1185 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1186 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1187 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1188 #endif 1189 1190 /* 1191 * Only allow 1 DMA channel to be active at a time. 1192 * I don't think this is a good idea, but without it 1193 * the firmware racks up lots of nicDmaReadRingFull 1194 * errors. This is not compatible with hardware checksums. 1195 */ 1196 if (sc->arpcom.ac_if.if_hwassist == 0) 1197 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1198 1199 /* Recommended settings from Tigon manual. */ 1200 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1201 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1202 1203 if (ti_64bitslot_war(sc)) { 1204 printf("ti%d: bios thinks we're in a 64 bit slot, " 1205 "but we aren't", sc->ti_unit); 1206 return(EINVAL); 1207 } 1208 1209 return(0); 1210 } 1211 1212 /* 1213 * Initialize the general information block and firmware, and 1214 * start the CPU(s) running. 1215 */ 1216 static int 1217 ti_gibinit(struct ti_softc *sc) 1218 { 1219 struct ifnet *ifp = &sc->arpcom.ac_if; 1220 struct ti_rcb *rcb; 1221 int i; 1222 1223 /* Disable interrupts for now. */ 1224 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1225 1226 /* Tell the chip where to find the general information block. */ 1227 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1228 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1229 1230 /* Load the firmware into SRAM. */ 1231 ti_loadfw(sc); 1232 1233 /* Set up the contents of the general info and ring control blocks. */ 1234 1235 /* Set up the event ring and producer pointer. */ 1236 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1237 1238 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1239 rcb->ti_flags = 0; 1240 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1241 vtophys(&sc->ti_ev_prodidx); 1242 sc->ti_ev_prodidx.ti_idx = 0; 1243 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1244 sc->ti_ev_saved_considx = 0; 1245 1246 /* Set up the command ring and producer mailbox. */ 1247 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1248 1249 sc->ti_rdata->ti_cmd_ring = 1250 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1251 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1252 rcb->ti_flags = 0; 1253 rcb->ti_max_len = 0; 1254 for (i = 0; i < TI_CMD_RING_CNT; i++) 1255 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1256 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1257 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1258 sc->ti_cmd_saved_prodidx = 0; 1259 1260 /* 1261 * Assign the address of the stats refresh buffer. 1262 * We re-use the current stats buffer for this to 1263 * conserve memory. 1264 */ 1265 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1266 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1267 1268 /* Set up the standard receive ring. */ 1269 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1270 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1271 rcb->ti_max_len = TI_FRAMELEN; 1272 rcb->ti_flags = 0; 1273 if (ifp->if_hwassist) 1274 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1275 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1276 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1277 1278 /* Set up the jumbo receive ring. */ 1279 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1280 TI_HOSTADDR(rcb->ti_hostaddr) = 1281 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1282 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1283 rcb->ti_flags = 0; 1284 if (ifp->if_hwassist) 1285 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1286 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1287 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1288 1289 /* 1290 * Set up the mini ring. Only activated on the 1291 * Tigon 2 but the slot in the config block is 1292 * still there on the Tigon 1. 1293 */ 1294 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1295 TI_HOSTADDR(rcb->ti_hostaddr) = 1296 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1297 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1298 if (sc->ti_hwrev == TI_HWREV_TIGON) 1299 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1300 else 1301 rcb->ti_flags = 0; 1302 if (ifp->if_hwassist) 1303 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1304 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1305 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1306 1307 /* 1308 * Set up the receive return ring. 1309 */ 1310 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1311 TI_HOSTADDR(rcb->ti_hostaddr) = 1312 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1313 rcb->ti_flags = 0; 1314 rcb->ti_max_len = TI_RETURN_RING_CNT; 1315 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1316 vtophys(&sc->ti_return_prodidx); 1317 1318 /* 1319 * Set up the tx ring. Note: for the Tigon 2, we have the option 1320 * of putting the transmit ring in the host's address space and 1321 * letting the chip DMA it instead of leaving the ring in the NIC's 1322 * memory and accessing it through the shared memory region. We 1323 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1324 * so we have to revert to the shared memory scheme if we detect 1325 * a Tigon 1 chip. 1326 */ 1327 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1328 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1329 sc->ti_rdata->ti_tx_ring_nic = 1330 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1331 } 1332 bzero(sc->ti_rdata->ti_tx_ring, 1333 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1334 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1335 if (sc->ti_hwrev == TI_HWREV_TIGON) 1336 rcb->ti_flags = 0; 1337 else 1338 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1339 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1340 if (ifp->if_hwassist) 1341 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1342 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1343 rcb->ti_max_len = TI_TX_RING_CNT; 1344 if (sc->ti_hwrev == TI_HWREV_TIGON) 1345 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1346 else 1347 TI_HOSTADDR(rcb->ti_hostaddr) = 1348 vtophys(&sc->ti_rdata->ti_tx_ring); 1349 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1350 vtophys(&sc->ti_tx_considx); 1351 1352 /* Set up tuneables */ 1353 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1354 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1355 (sc->ti_rx_coal_ticks / 10)); 1356 else 1357 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1358 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1359 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1360 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1361 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1362 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1363 1364 /* Turn interrupts on. */ 1365 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1366 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1367 1368 /* Start CPU. */ 1369 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1370 1371 return(0); 1372 } 1373 1374 /* 1375 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1376 * against our list and return its name if we find a match. 1377 */ 1378 static int 1379 ti_probe(device_t dev) 1380 { 1381 struct ti_type *t; 1382 uint16_t vendor, product; 1383 1384 vendor = pci_get_vendor(dev); 1385 product = pci_get_device(dev); 1386 1387 for (t = ti_devs; t->ti_name != NULL; t++) { 1388 if (vendor == t->ti_vid && product == t->ti_did) { 1389 device_set_desc(dev, t->ti_name); 1390 return(0); 1391 } 1392 } 1393 1394 return(ENXIO); 1395 } 1396 1397 static int 1398 ti_attach(device_t dev) 1399 { 1400 struct ti_softc *sc; 1401 struct ifnet *ifp; 1402 int error = 0, rid, unit; 1403 uint32_t command; 1404 1405 crit_enter(); 1406 1407 sc = device_get_softc(dev); 1408 unit = device_get_unit(dev); 1409 ifp = &sc->arpcom.ac_if; 1410 ifp->if_capabilities = IFCAP_HWCSUM; 1411 ifp->if_capenable = sc->arpcom.ac_if.if_capabilities; 1412 1413 /* 1414 * Map control/status registers. 1415 */ 1416 command = pci_read_config(dev, PCIR_COMMAND, 4); 1417 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1418 pci_write_config(dev, PCIR_COMMAND, command, 4); 1419 command = pci_read_config(dev, PCIR_COMMAND, 4); 1420 1421 if ((command & PCIM_CMD_MEMEN) == 0) { 1422 printf("ti%d: failed to enable memory mapping!\n", unit); 1423 error = ENXIO; 1424 goto fail; 1425 } 1426 1427 rid = TI_PCI_LOMEM; 1428 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1429 RF_ACTIVE); 1430 1431 if (sc->ti_res == NULL) { 1432 printf ("ti%d: couldn't map memory\n", unit); 1433 error = ENXIO; 1434 goto fail; 1435 } 1436 1437 sc->ti_btag = rman_get_bustag(sc->ti_res); 1438 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1439 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1440 1441 /* Allocate interrupt */ 1442 rid = 0; 1443 1444 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1445 RF_SHAREABLE | RF_ACTIVE); 1446 1447 if (sc->ti_irq == NULL) { 1448 printf("ti%d: couldn't map interrupt\n", unit); 1449 error = ENXIO; 1450 goto fail; 1451 } 1452 1453 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1454 ti_intr, sc, &sc->ti_intrhand, NULL); 1455 1456 if (error) { 1457 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1458 bus_release_resource(dev, SYS_RES_MEMORY, 1459 TI_PCI_LOMEM, sc->ti_res); 1460 printf("ti%d: couldn't set up irq\n", unit); 1461 goto fail; 1462 } 1463 1464 sc->ti_unit = unit; 1465 1466 if (ti_chipinit(sc)) { 1467 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1468 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1469 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1470 bus_release_resource(dev, SYS_RES_MEMORY, 1471 TI_PCI_LOMEM, sc->ti_res); 1472 error = ENXIO; 1473 goto fail; 1474 } 1475 1476 /* Zero out the NIC's on-board SRAM. */ 1477 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1478 1479 /* Init again -- zeroing memory may have clobbered some registers. */ 1480 if (ti_chipinit(sc)) { 1481 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1482 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1483 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1484 bus_release_resource(dev, SYS_RES_MEMORY, 1485 TI_PCI_LOMEM, sc->ti_res); 1486 error = ENXIO; 1487 goto fail; 1488 } 1489 1490 /* 1491 * Get station address from the EEPROM. Note: the manual states 1492 * that the MAC address is at offset 0x8c, however the data is 1493 * stored as two longwords (since that's how it's loaded into 1494 * the NIC). This means the MAC address is actually preceeded 1495 * by two zero bytes. We need to skip over those. 1496 */ 1497 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1498 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1499 printf("ti%d: failed to read station address\n", unit); 1500 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1501 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1502 bus_release_resource(dev, SYS_RES_MEMORY, 1503 TI_PCI_LOMEM, sc->ti_res); 1504 error = ENXIO; 1505 goto fail; 1506 } 1507 1508 /* Allocate the general information block and ring buffers. */ 1509 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1510 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1511 1512 if (sc->ti_rdata == NULL) { 1513 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1514 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1515 bus_release_resource(dev, SYS_RES_MEMORY, 1516 TI_PCI_LOMEM, sc->ti_res); 1517 error = ENXIO; 1518 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1519 goto fail; 1520 } 1521 1522 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1523 1524 /* Try to allocate memory for jumbo buffers. */ 1525 if (ti_alloc_jumbo_mem(sc)) { 1526 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1527 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1528 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1529 bus_release_resource(dev, SYS_RES_MEMORY, 1530 TI_PCI_LOMEM, sc->ti_res); 1531 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 1532 M_DEVBUF); 1533 error = ENXIO; 1534 goto fail; 1535 } 1536 1537 /* 1538 * We really need a better way to tell a 1000baseTX card 1539 * from a 1000baseSX one, since in theory there could be 1540 * OEMed 1000baseTX cards from lame vendors who aren't 1541 * clever enough to change the PCI ID. For the moment 1542 * though, the AceNIC is the only copper card available. 1543 */ 1544 if (pci_get_vendor(dev) == ALT_VENDORID && 1545 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1546 sc->ti_copper = 1; 1547 /* Ok, it's not the only copper card available. */ 1548 if (pci_get_vendor(dev) == NG_VENDORID && 1549 pci_get_device(dev) == NG_DEVICEID_GA620T) 1550 sc->ti_copper = 1; 1551 1552 /* Set default tuneable values. */ 1553 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1554 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1555 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1556 sc->ti_rx_max_coal_bds = 64; 1557 sc->ti_tx_max_coal_bds = 128; 1558 sc->ti_tx_buf_ratio = 21; 1559 1560 /* Set up ifnet structure */ 1561 ifp->if_softc = sc; 1562 if_initname(ifp, "ti", sc->ti_unit); 1563 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1564 ifp->if_ioctl = ti_ioctl; 1565 ifp->if_start = ti_start; 1566 ifp->if_watchdog = ti_watchdog; 1567 ifp->if_init = ti_init; 1568 ifp->if_mtu = ETHERMTU; 1569 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1); 1570 ifq_set_ready(&ifp->if_snd); 1571 1572 /* Set up ifmedia support. */ 1573 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1574 if (sc->ti_copper) { 1575 /* 1576 * Copper cards allow manual 10/100 mode selection, 1577 * but not manual 1000baseTX mode selection. Why? 1578 * Becuase currently there's no way to specify the 1579 * master/slave setting through the firmware interface, 1580 * so Alteon decided to just bag it and handle it 1581 * via autonegotiation. 1582 */ 1583 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1584 ifmedia_add(&sc->ifmedia, 1585 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1586 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1587 ifmedia_add(&sc->ifmedia, 1588 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1589 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1590 ifmedia_add(&sc->ifmedia, 1591 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL); 1592 } else { 1593 /* Fiber cards don't support 10/100 modes. */ 1594 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1595 ifmedia_add(&sc->ifmedia, 1596 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1597 } 1598 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1599 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1600 1601 /* 1602 * Call MI attach routine. 1603 */ 1604 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1605 1606 fail: 1607 crit_exit(); 1608 1609 return(error); 1610 } 1611 1612 static int 1613 ti_detach(device_t dev) 1614 { 1615 struct ti_softc *sc = device_get_softc(dev); 1616 struct ifnet *ifp = &sc->arpcom.ac_if; 1617 1618 crit_enter(); 1619 1620 ether_ifdetach(ifp); 1621 ti_stop(sc); 1622 1623 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1624 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1625 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1626 1627 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1628 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1629 ifmedia_removeall(&sc->ifmedia); 1630 1631 crit_exit(); 1632 1633 return(0); 1634 } 1635 1636 /* 1637 * Frame reception handling. This is called if there's a frame 1638 * on the receive return list. 1639 * 1640 * Note: we have to be able to handle three possibilities here: 1641 * 1) the frame is from the mini receive ring (can only happen) 1642 * on Tigon 2 boards) 1643 * 2) the frame is from the jumbo recieve ring 1644 * 3) the frame is from the standard receive ring 1645 */ 1646 static void 1647 ti_rxeof(struct ti_softc *sc) 1648 { 1649 struct ifnet *ifp = &sc->arpcom.ac_if; 1650 struct ti_cmd_desc cmd; 1651 1652 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1653 struct ti_rx_desc *cur_rx; 1654 uint32_t rxidx; 1655 struct mbuf *m; 1656 uint16_t vlan_tag = 0; 1657 int have_tag = 0; 1658 1659 cur_rx = 1660 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1661 rxidx = cur_rx->ti_idx; 1662 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1663 1664 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1665 have_tag = 1; 1666 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 1667 } 1668 1669 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1670 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1671 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1672 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1673 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1674 ifp->if_ierrors++; 1675 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1676 continue; 1677 } 1678 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1679 ifp->if_ierrors++; 1680 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1681 continue; 1682 } 1683 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1684 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1685 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1686 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1687 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1688 ifp->if_ierrors++; 1689 ti_newbuf_mini(sc, sc->ti_mini, m); 1690 continue; 1691 } 1692 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1693 ifp->if_ierrors++; 1694 ti_newbuf_mini(sc, sc->ti_mini, m); 1695 continue; 1696 } 1697 } else { 1698 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1699 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1700 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1701 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1702 ifp->if_ierrors++; 1703 ti_newbuf_std(sc, sc->ti_std, m); 1704 continue; 1705 } 1706 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1707 ifp->if_ierrors++; 1708 ti_newbuf_std(sc, sc->ti_std, m); 1709 continue; 1710 } 1711 } 1712 1713 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1714 ifp->if_ipackets++; 1715 m->m_pkthdr.rcvif = ifp; 1716 1717 if (ifp->if_hwassist) { 1718 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1719 CSUM_DATA_VALID; 1720 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1721 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1722 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1723 } 1724 1725 /* 1726 * If we received a packet with a vlan tag, pass it 1727 * to vlan_input() instead of ether_input(). 1728 */ 1729 if (have_tag) 1730 VLAN_INPUT_TAG(m, vlan_tag); 1731 else 1732 (*ifp->if_input)(ifp, m); 1733 } 1734 1735 /* Only necessary on the Tigon 1. */ 1736 if (sc->ti_hwrev == TI_HWREV_TIGON) 1737 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1738 sc->ti_rx_saved_considx); 1739 1740 TI_UPDATE_STDPROD(sc, sc->ti_std); 1741 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1742 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1743 } 1744 1745 static void 1746 ti_txeof(struct ti_softc *sc) 1747 { 1748 struct ifnet *ifp = &sc->arpcom.ac_if; 1749 struct ti_tx_desc *cur_tx = NULL; 1750 1751 /* 1752 * Go through our tx ring and free mbufs for those 1753 * frames that have been sent. 1754 */ 1755 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1756 uint32_t idx = 0; 1757 1758 idx = sc->ti_tx_saved_considx; 1759 if (sc->ti_hwrev != TI_HWREV_TIGON) { 1760 if (idx > 383) 1761 CSR_WRITE_4(sc, TI_WINBASE, 1762 TI_TX_RING_BASE + 6144); 1763 else if (idx > 255) 1764 CSR_WRITE_4(sc, TI_WINBASE, 1765 TI_TX_RING_BASE + 4096); 1766 else if (idx > 127) 1767 CSR_WRITE_4(sc, TI_WINBASE, 1768 TI_TX_RING_BASE + 2048); 1769 else 1770 CSR_WRITE_4(sc, TI_WINBASE, 1771 TI_TX_RING_BASE); 1772 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1773 } else 1774 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1775 if (cur_tx->ti_flags & TI_BDFLAG_END) 1776 ifp->if_opackets++; 1777 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1778 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1779 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1780 } 1781 sc->ti_txcnt--; 1782 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1783 ifp->if_timer = 0; 1784 } 1785 1786 if (cur_tx != NULL) 1787 ifp->if_flags &= ~IFF_OACTIVE; 1788 } 1789 1790 static void 1791 ti_intr(void *xsc) 1792 { 1793 struct ti_softc *sc = xsc; 1794 struct ifnet *ifp = &sc->arpcom.ac_if; 1795 1796 #ifdef notdef 1797 /* Avoid this for now -- checking this register is expensive. */ 1798 /* Make sure this is really our interrupt. */ 1799 if ((CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE) == 0) 1800 return; 1801 #endif 1802 1803 /* Ack interrupt and stop others from occuring. */ 1804 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1805 1806 if (ifp->if_flags & IFF_RUNNING) { 1807 /* Check RX return ring producer/consumer */ 1808 ti_rxeof(sc); 1809 1810 /* Check TX ring producer/consumer */ 1811 ti_txeof(sc); 1812 } 1813 1814 ti_handle_events(sc); 1815 1816 /* Re-enable interrupts. */ 1817 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1818 1819 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1820 ti_start(ifp); 1821 } 1822 1823 static void 1824 ti_stats_update(struct ti_softc *sc) 1825 { 1826 struct ifnet *ifp = &sc->arpcom.ac_if; 1827 1828 ifp->if_collisions += 1829 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1830 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1831 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1832 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1833 ifp->if_collisions; 1834 } 1835 1836 /* 1837 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1838 * pointers to descriptors. 1839 */ 1840 static int 1841 ti_encap(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1842 { 1843 struct ti_tx_desc *f = NULL; 1844 struct mbuf *m; 1845 struct ifvlan *ifv = NULL; 1846 uint32_t cnt = 0, cur, frag; 1847 uint16_t csum_flags = 0; 1848 1849 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1850 m_head->m_pkthdr.rcvif != NULL && 1851 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1852 ifv = m_head->m_pkthdr.rcvif->if_softc; 1853 1854 m = m_head; 1855 cur = frag = *txidx; 1856 1857 if (m_head->m_pkthdr.csum_flags) { 1858 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1859 csum_flags |= TI_BDFLAG_IP_CKSUM; 1860 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 1861 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 1862 if (m_head->m_flags & M_LASTFRAG) 1863 csum_flags |= TI_BDFLAG_IP_FRAG_END; 1864 else if (m_head->m_flags & M_FRAG) 1865 csum_flags |= TI_BDFLAG_IP_FRAG; 1866 } 1867 /* 1868 * Start packing the mbufs in this chain into 1869 * the fragment pointers. Stop when we run out 1870 * of fragments or hit the end of the mbuf chain. 1871 */ 1872 for (m = m_head; m != NULL; m = m->m_next) { 1873 if (m->m_len != 0) { 1874 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1875 if (frag > 383) 1876 CSR_WRITE_4(sc, TI_WINBASE, 1877 TI_TX_RING_BASE + 6144); 1878 else if (frag > 255) 1879 CSR_WRITE_4(sc, TI_WINBASE, 1880 TI_TX_RING_BASE + 4096); 1881 else if (frag > 127) 1882 CSR_WRITE_4(sc, TI_WINBASE, 1883 TI_TX_RING_BASE + 2048); 1884 else 1885 CSR_WRITE_4(sc, TI_WINBASE, 1886 TI_TX_RING_BASE); 1887 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 1888 } else 1889 f = &sc->ti_rdata->ti_tx_ring[frag]; 1890 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 1891 break; 1892 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 1893 f->ti_len = m->m_len; 1894 f->ti_flags = csum_flags; 1895 1896 if (ifv != NULL) { 1897 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 1898 f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 1899 } else { 1900 f->ti_vlan_tag = 0; 1901 } 1902 1903 /* 1904 * Sanity check: avoid coming within 16 descriptors 1905 * of the end of the ring. 1906 */ 1907 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 1908 return(ENOBUFS); 1909 cur = frag; 1910 TI_INC(frag, TI_TX_RING_CNT); 1911 cnt++; 1912 } 1913 } 1914 1915 if (m != NULL) 1916 return(ENOBUFS); 1917 1918 if (frag == sc->ti_tx_saved_considx) 1919 return(ENOBUFS); 1920 1921 if (sc->ti_hwrev == TI_HWREV_TIGON) 1922 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 1923 TI_BDFLAG_END; 1924 else 1925 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 1926 sc->ti_cdata.ti_tx_chain[cur] = m_head; 1927 sc->ti_txcnt += cnt; 1928 1929 *txidx = frag; 1930 1931 return(0); 1932 } 1933 1934 /* 1935 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1936 * to the mbuf data regions directly in the transmit descriptors. 1937 */ 1938 static void 1939 ti_start(struct ifnet *ifp) 1940 { 1941 struct ti_softc *sc = ifp->if_softc; 1942 struct mbuf *m_head = NULL; 1943 uint32_t prodidx = 0; 1944 1945 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 1946 1947 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 1948 m_head = ifq_poll(&ifp->if_snd); 1949 if (m_head == NULL) 1950 break; 1951 1952 /* 1953 * XXX 1954 * safety overkill. If this is a fragmented packet chain 1955 * with delayed TCP/UDP checksums, then only encapsulate 1956 * it if we have enough descriptors to handle the entire 1957 * chain at once. 1958 * (paranoia -- may not actually be needed) 1959 */ 1960 if (m_head->m_flags & M_FIRSTFRAG && 1961 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 1962 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 1963 m_head->m_pkthdr.csum_data + 16) { 1964 ifp->if_flags |= IFF_OACTIVE; 1965 break; 1966 } 1967 } 1968 1969 /* 1970 * Pack the data into the transmit ring. If we 1971 * don't have room, set the OACTIVE flag and wait 1972 * for the NIC to drain the ring. 1973 */ 1974 if (ti_encap(sc, m_head, &prodidx)) { 1975 ifp->if_flags |= IFF_OACTIVE; 1976 break; 1977 } 1978 1979 m_head = ifq_dequeue(&ifp->if_snd); 1980 BPF_MTAP(ifp, m_head); 1981 } 1982 1983 /* Transmit */ 1984 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 1985 1986 /* 1987 * Set a timeout in case the chip goes out to lunch. 1988 */ 1989 ifp->if_timer = 5; 1990 } 1991 1992 static void 1993 ti_init(void *xsc) 1994 { 1995 struct ti_softc *sc = xsc; 1996 1997 crit_enter(); 1998 1999 /* Cancel pending I/O and flush buffers. */ 2000 ti_stop(sc); 2001 2002 /* Init the gen info block, ring control blocks and firmware. */ 2003 if (ti_gibinit(sc)) { 2004 printf("ti%d: initialization failure\n", sc->ti_unit); 2005 crit_exit(); 2006 return; 2007 } 2008 2009 crit_exit(); 2010 } 2011 2012 static void 2013 ti_init2(struct ti_softc *sc) 2014 { 2015 struct ifnet *ifp = &sc->arpcom.ac_if; 2016 struct ti_cmd_desc cmd; 2017 uint16_t *m; 2018 struct ifmedia *ifm; 2019 int tmp; 2020 2021 /* Specify MTU and interface index. */ 2022 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit); 2023 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2024 ETHER_HDR_LEN + ETHER_CRC_LEN); 2025 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2026 2027 /* Load our MAC address. */ 2028 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 2029 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2030 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2031 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2032 2033 /* Enable or disable promiscuous mode as needed. */ 2034 if (ifp->if_flags & IFF_PROMISC) 2035 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2036 else 2037 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2038 2039 /* Program multicast filter. */ 2040 ti_setmulti(sc); 2041 2042 /* 2043 * If this is a Tigon 1, we should tell the 2044 * firmware to use software packet filtering. 2045 */ 2046 if (sc->ti_hwrev == TI_HWREV_TIGON) 2047 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2048 2049 /* Init RX ring. */ 2050 ti_init_rx_ring_std(sc); 2051 2052 /* Init jumbo RX ring. */ 2053 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2054 ti_init_rx_ring_jumbo(sc); 2055 2056 /* 2057 * If this is a Tigon 2, we can also configure the 2058 * mini ring. 2059 */ 2060 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2061 ti_init_rx_ring_mini(sc); 2062 2063 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2064 sc->ti_rx_saved_considx = 0; 2065 2066 /* Init TX ring. */ 2067 ti_init_tx_ring(sc); 2068 2069 /* Tell firmware we're alive. */ 2070 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2071 2072 /* Enable host interrupts. */ 2073 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2074 2075 ifp->if_flags |= IFF_RUNNING; 2076 ifp->if_flags &= ~IFF_OACTIVE; 2077 2078 /* 2079 * Make sure to set media properly. We have to do this 2080 * here since we have to issue commands in order to set 2081 * the link negotiation and we can't issue commands until 2082 * the firmware is running. 2083 */ 2084 ifm = &sc->ifmedia; 2085 tmp = ifm->ifm_media; 2086 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2087 ti_ifmedia_upd(ifp); 2088 ifm->ifm_media = tmp; 2089 } 2090 2091 /* 2092 * Set media options. 2093 */ 2094 static int 2095 ti_ifmedia_upd(struct ifnet *ifp) 2096 { 2097 struct ti_softc *sc = ifp->if_softc; 2098 struct ifmedia *ifm = &sc->ifmedia; 2099 struct ti_cmd_desc cmd; 2100 2101 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2102 return(EINVAL); 2103 2104 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2105 case IFM_AUTO: 2106 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB | 2107 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y | 2108 TI_GLNK_AUTONEGENB | TI_GLNK_ENB); 2109 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB | 2110 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX | 2111 TI_LNK_AUTONEGENB | TI_LNK_ENB); 2112 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2113 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2114 break; 2115 case IFM_1000_SX: 2116 case IFM_1000_T: 2117 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB | 2118 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2119 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2120 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2121 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2122 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2123 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2124 break; 2125 case IFM_100_FX: 2126 case IFM_10_FL: 2127 case IFM_100_TX: 2128 case IFM_10_T: 2129 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2130 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF); 2131 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2132 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) 2133 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2134 else 2135 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2136 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2137 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2138 else 2139 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2140 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2141 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2142 break; 2143 } 2144 2145 return(0); 2146 } 2147 2148 /* 2149 * Report current media status. 2150 */ 2151 static void 2152 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2153 { 2154 struct ti_softc *sc = ifp->if_softc; 2155 uint32_t media = 0; 2156 2157 ifmr->ifm_status = IFM_AVALID; 2158 ifmr->ifm_active = IFM_ETHER; 2159 2160 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2161 return; 2162 2163 ifmr->ifm_status |= IFM_ACTIVE; 2164 2165 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2166 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2167 if (sc->ti_copper) 2168 ifmr->ifm_active |= IFM_1000_T; 2169 else 2170 ifmr->ifm_active |= IFM_1000_SX; 2171 if (media & TI_GLNK_FULL_DUPLEX) 2172 ifmr->ifm_active |= IFM_FDX; 2173 else 2174 ifmr->ifm_active |= IFM_HDX; 2175 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2176 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2177 if (sc->ti_copper) { 2178 if (media & TI_LNK_100MB) 2179 ifmr->ifm_active |= IFM_100_TX; 2180 if (media & TI_LNK_10MB) 2181 ifmr->ifm_active |= IFM_10_T; 2182 } else { 2183 if (media & TI_LNK_100MB) 2184 ifmr->ifm_active |= IFM_100_FX; 2185 if (media & TI_LNK_10MB) 2186 ifmr->ifm_active |= IFM_10_FL; 2187 } 2188 if (media & TI_LNK_FULL_DUPLEX) 2189 ifmr->ifm_active |= IFM_FDX; 2190 if (media & TI_LNK_HALF_DUPLEX) 2191 ifmr->ifm_active |= IFM_HDX; 2192 } 2193 } 2194 2195 static int 2196 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2197 { 2198 struct ti_softc *sc = ifp->if_softc; 2199 struct ifreq *ifr = (struct ifreq *) data; 2200 struct ti_cmd_desc cmd; 2201 int error = 0, mask; 2202 2203 crit_enter(); 2204 2205 switch(command) { 2206 case SIOCSIFMTU: 2207 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2208 error = EINVAL; 2209 else { 2210 ifp->if_mtu = ifr->ifr_mtu; 2211 ti_init(sc); 2212 } 2213 break; 2214 case SIOCSIFFLAGS: 2215 if (ifp->if_flags & IFF_UP) { 2216 /* 2217 * If only the state of the PROMISC flag changed, 2218 * then just use the 'set promisc mode' command 2219 * instead of reinitializing the entire NIC. Doing 2220 * a full re-init means reloading the firmware and 2221 * waiting for it to start up, which may take a 2222 * second or two. 2223 */ 2224 if (ifp->if_flags & IFF_RUNNING && 2225 ifp->if_flags & IFF_PROMISC && 2226 !(sc->ti_if_flags & IFF_PROMISC)) { 2227 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2228 TI_CMD_CODE_PROMISC_ENB, 0); 2229 } else if (ifp->if_flags & IFF_RUNNING && 2230 !(ifp->if_flags & IFF_PROMISC) && 2231 sc->ti_if_flags & IFF_PROMISC) { 2232 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2233 TI_CMD_CODE_PROMISC_DIS, 0); 2234 } else 2235 ti_init(sc); 2236 } else if (ifp->if_flags & IFF_RUNNING) { 2237 ti_stop(sc); 2238 } 2239 sc->ti_if_flags = ifp->if_flags; 2240 error = 0; 2241 break; 2242 case SIOCADDMULTI: 2243 case SIOCDELMULTI: 2244 if (ifp->if_flags & IFF_RUNNING) { 2245 ti_setmulti(sc); 2246 error = 0; 2247 } 2248 break; 2249 case SIOCSIFMEDIA: 2250 case SIOCGIFMEDIA: 2251 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2252 break; 2253 case SIOCSIFCAP: 2254 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2255 if (mask & IFCAP_HWCSUM) { 2256 if (IFCAP_HWCSUM & ifp->if_capenable) 2257 ifp->if_capenable &= ~IFCAP_HWCSUM; 2258 else 2259 ifp->if_capenable |= IFCAP_HWCSUM; 2260 if (ifp->if_flags & IFF_RUNNING) 2261 ti_init(sc); 2262 } 2263 error = 0; 2264 break; 2265 default: 2266 error = ether_ioctl(ifp, command, data); 2267 break; 2268 } 2269 2270 crit_exit(); 2271 2272 return(error); 2273 } 2274 2275 static void 2276 ti_watchdog(struct ifnet *ifp) 2277 { 2278 struct ti_softc *sc = ifp->if_softc; 2279 2280 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2281 ti_stop(sc); 2282 ti_init(sc); 2283 2284 ifp->if_oerrors++; 2285 } 2286 2287 /* 2288 * Stop the adapter and free any mbufs allocated to the 2289 * RX and TX lists. 2290 */ 2291 static void 2292 ti_stop(struct ti_softc *sc) 2293 { 2294 struct ifnet *ifp = &sc->arpcom.ac_if; 2295 struct ti_cmd_desc cmd; 2296 2297 /* Disable host interrupts. */ 2298 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2299 /* 2300 * Tell firmware we're shutting down. 2301 */ 2302 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2303 2304 /* Halt and reinitialize. */ 2305 ti_chipinit(sc); 2306 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2307 ti_chipinit(sc); 2308 2309 /* Free the RX lists. */ 2310 ti_free_rx_ring_std(sc); 2311 2312 /* Free jumbo RX list. */ 2313 ti_free_rx_ring_jumbo(sc); 2314 2315 /* Free mini RX list. */ 2316 ti_free_rx_ring_mini(sc); 2317 2318 /* Free TX buffers. */ 2319 ti_free_tx_ring(sc); 2320 2321 sc->ti_ev_prodidx.ti_idx = 0; 2322 sc->ti_return_prodidx.ti_idx = 0; 2323 sc->ti_tx_considx.ti_idx = 0; 2324 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2325 2326 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2327 } 2328 2329 /* 2330 * Stop all chip I/O so that the kernel's probe routines don't 2331 * get confused by errant DMAs when rebooting. 2332 */ 2333 static void 2334 ti_shutdown(device_t dev) 2335 { 2336 struct ti_softc *sc = device_get_softc(dev); 2337 2338 ti_chipinit(sc); 2339 } 2340