1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.19 2005/05/05 22:57:45 swildner Exp $ 34 */ 35 36 /* 37 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 38 * Manuals, sample driver and firmware source kits are available 39 * from http://www.alteon.com/support/openkits. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Electrical Engineering Department 43 * Columbia University, New York City 44 */ 45 46 /* 47 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 48 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 49 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 50 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 51 * filtering and jumbo (9014 byte) frames. The hardware is largely 52 * controlled by firmware, which must be loaded into the NIC during 53 * initialization. 54 * 55 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 56 * revision, which supports new features such as extended commands, 57 * extended jumbo receive ring desciptors and a mini receive ring. 58 * 59 * Alteon Networks is to be commended for releasing such a vast amount 60 * of development material for the Tigon NIC without requiring an NDA 61 * (although they really should have done it a long time ago). With 62 * any luck, the other vendors will finally wise up and follow Alteon's 63 * stellar example. 64 * 65 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 66 * this driver by #including it as a C header file. This bloats the 67 * driver somewhat, but it's the easiest method considering that the 68 * driver code and firmware code need to be kept in sync. The source 69 * for the firmware is not provided with the FreeBSD distribution since 70 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 71 * 72 * The following people deserve special thanks: 73 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 74 * for testing 75 * - Raymond Lee of Netgear, for providing a pair of Netgear 76 * GA620 Tigon 2 boards for testing 77 * - Ulf Zimmermann, for bringing the GA260 to my attention and 78 * convincing me to write this driver. 79 * - Andrew Gallatin for providing FreeBSD/Alpha support. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/sockio.h> 85 #include <sys/mbuf.h> 86 #include <sys/malloc.h> 87 #include <sys/kernel.h> 88 #include <sys/socket.h> 89 #include <sys/queue.h> 90 91 #include <net/if.h> 92 #include <net/ifq_var.h> 93 #include <net/if_arp.h> 94 #include <net/ethernet.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_types.h> 98 #include <net/vlan/if_vlan_var.h> 99 100 #include <net/bpf.h> 101 102 #include <netinet/in_systm.h> 103 #include <netinet/in.h> 104 #include <netinet/ip.h> 105 106 #include <vm/vm.h> /* for vtophys */ 107 #include <vm/pmap.h> /* for vtophys */ 108 #include <machine/clock.h> /* for DELAY */ 109 #include <machine/bus_memio.h> 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <bus/pci/pcireg.h> 116 #include <bus/pci/pcivar.h> 117 118 #include "if_tireg.h" 119 #include "ti_fw.h" 120 #include "ti_fw2.h" 121 122 /* 123 * Temporarily disable the checksum offload support for now. 124 * Tests with ftp.freesoftware.com show that after about 12 hours, 125 * the firmware will begin calculating completely bogus TX checksums 126 * and refuse to stop until the interface is reset. Unfortunately, 127 * there isn't enough time to fully debug this before the 4.1 128 * release, so this will need to stay off for now. 129 */ 130 #ifdef notdef 131 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 132 #else 133 #define TI_CSUM_FEATURES 0 134 #endif 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static struct ti_type ti_devs[] = { 141 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 142 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 143 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 144 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 145 { TC_VENDORID, TC_DEVICEID_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { NG_VENDORID, NG_DEVICEID_GA620, 148 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 149 { NG_VENDORID, NG_DEVICEID_GA620T, 150 "Netgear GA620 1000baseT Gigabit Ethernet" }, 151 { SGI_VENDORID, SGI_DEVICEID_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 154 "Farallon PN9000SX Gigabit Ethernet" }, 155 { 0, 0, NULL } 156 }; 157 158 static int ti_probe (device_t); 159 static int ti_attach (device_t); 160 static int ti_detach (device_t); 161 static void ti_txeof (struct ti_softc *); 162 static void ti_rxeof (struct ti_softc *); 163 164 static void ti_stats_update (struct ti_softc *); 165 static int ti_encap (struct ti_softc *, struct mbuf *, 166 u_int32_t *); 167 168 static void ti_intr (void *); 169 static void ti_start (struct ifnet *); 170 static int ti_ioctl (struct ifnet *, u_long, caddr_t, 171 struct ucred *); 172 static void ti_init (void *); 173 static void ti_init2 (struct ti_softc *); 174 static void ti_stop (struct ti_softc *); 175 static void ti_watchdog (struct ifnet *); 176 static void ti_shutdown (device_t); 177 static int ti_ifmedia_upd (struct ifnet *); 178 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 179 180 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 181 static u_int8_t ti_eeprom_getbyte (struct ti_softc *, 182 int, u_int8_t *); 183 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 184 185 static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 186 static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 187 static void ti_setmulti (struct ti_softc *); 188 189 static void ti_mem (struct ti_softc *, u_int32_t, 190 u_int32_t, caddr_t); 191 static void ti_loadfw (struct ti_softc *); 192 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 193 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 194 caddr_t, int); 195 static void ti_handle_events (struct ti_softc *); 196 static int ti_alloc_jumbo_mem (struct ti_softc *); 197 static void *ti_jalloc (struct ti_softc *); 198 static void ti_jfree (caddr_t, u_int); 199 static void ti_jref (caddr_t, u_int); 200 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 201 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 202 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 203 static int ti_init_rx_ring_std (struct ti_softc *); 204 static void ti_free_rx_ring_std (struct ti_softc *); 205 static int ti_init_rx_ring_jumbo (struct ti_softc *); 206 static void ti_free_rx_ring_jumbo (struct ti_softc *); 207 static int ti_init_rx_ring_mini (struct ti_softc *); 208 static void ti_free_rx_ring_mini (struct ti_softc *); 209 static void ti_free_tx_ring (struct ti_softc *); 210 static int ti_init_tx_ring (struct ti_softc *); 211 212 static int ti_64bitslot_war (struct ti_softc *); 213 static int ti_chipinit (struct ti_softc *); 214 static int ti_gibinit (struct ti_softc *); 215 216 static device_method_t ti_methods[] = { 217 /* Device interface */ 218 DEVMETHOD(device_probe, ti_probe), 219 DEVMETHOD(device_attach, ti_attach), 220 DEVMETHOD(device_detach, ti_detach), 221 DEVMETHOD(device_shutdown, ti_shutdown), 222 { 0, 0 } 223 }; 224 225 static driver_t ti_driver = { 226 "ti", 227 ti_methods, 228 sizeof(struct ti_softc) 229 }; 230 231 static devclass_t ti_devclass; 232 233 DECLARE_DUMMY_MODULE(if_ti); 234 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 235 236 /* 237 * Send an instruction or address to the EEPROM, check for ACK. 238 */ 239 static u_int32_t ti_eeprom_putbyte(sc, byte) 240 struct ti_softc *sc; 241 int byte; 242 { 243 int i, ack = 0; 244 245 /* 246 * Make sure we're in TX mode. 247 */ 248 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 249 250 /* 251 * Feed in each bit and stobe the clock. 252 */ 253 for (i = 0x80; i; i >>= 1) { 254 if (byte & i) { 255 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 256 } else { 257 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 258 } 259 DELAY(1); 260 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 261 DELAY(1); 262 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 263 } 264 265 /* 266 * Turn off TX mode. 267 */ 268 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 269 270 /* 271 * Check for ack. 272 */ 273 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 274 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 275 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 276 277 return(ack); 278 } 279 280 /* 281 * Read a byte of data stored in the EEPROM at address 'addr.' 282 * We have to send two address bytes since the EEPROM can hold 283 * more than 256 bytes of data. 284 */ 285 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 286 struct ti_softc *sc; 287 int addr; 288 u_int8_t *dest; 289 { 290 int i; 291 u_int8_t byte = 0; 292 293 EEPROM_START; 294 295 /* 296 * Send write control code to EEPROM. 297 */ 298 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 299 printf("ti%d: failed to send write command, status: %x\n", 300 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 301 return(1); 302 } 303 304 /* 305 * Send first byte of address of byte we want to read. 306 */ 307 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 308 printf("ti%d: failed to send address, status: %x\n", 309 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 310 return(1); 311 } 312 /* 313 * Send second byte address of byte we want to read. 314 */ 315 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 316 printf("ti%d: failed to send address, status: %x\n", 317 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 318 return(1); 319 } 320 321 EEPROM_STOP; 322 EEPROM_START; 323 /* 324 * Send read control code to EEPROM. 325 */ 326 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 327 printf("ti%d: failed to send read command, status: %x\n", 328 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 329 return(1); 330 } 331 332 /* 333 * Start reading bits from EEPROM. 334 */ 335 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 336 for (i = 0x80; i; i >>= 1) { 337 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 338 DELAY(1); 339 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 340 byte |= i; 341 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 342 DELAY(1); 343 } 344 345 EEPROM_STOP; 346 347 /* 348 * No ACK generated for read, so just return byte. 349 */ 350 351 *dest = byte; 352 353 return(0); 354 } 355 356 /* 357 * Read a sequence of bytes from the EEPROM. 358 */ 359 static int ti_read_eeprom(sc, dest, off, cnt) 360 struct ti_softc *sc; 361 caddr_t dest; 362 int off; 363 int cnt; 364 { 365 int err = 0, i; 366 u_int8_t byte = 0; 367 368 for (i = 0; i < cnt; i++) { 369 err = ti_eeprom_getbyte(sc, off + i, &byte); 370 if (err) 371 break; 372 *(dest + i) = byte; 373 } 374 375 return(err ? 1 : 0); 376 } 377 378 /* 379 * NIC memory access function. Can be used to either clear a section 380 * of NIC local memory or (if buf is non-NULL) copy data into it. 381 */ 382 static void ti_mem(sc, addr, len, buf) 383 struct ti_softc *sc; 384 u_int32_t addr, len; 385 caddr_t buf; 386 { 387 int segptr, segsize, cnt; 388 caddr_t ti_winbase, ptr; 389 390 segptr = addr; 391 cnt = len; 392 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 393 ptr = buf; 394 395 while(cnt) { 396 if (cnt < TI_WINLEN) 397 segsize = cnt; 398 else 399 segsize = TI_WINLEN - (segptr % TI_WINLEN); 400 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 401 if (buf == NULL) 402 bzero((char *)ti_winbase + (segptr & 403 (TI_WINLEN - 1)), segsize); 404 else { 405 bcopy((char *)ptr, (char *)ti_winbase + 406 (segptr & (TI_WINLEN - 1)), segsize); 407 ptr += segsize; 408 } 409 segptr += segsize; 410 cnt -= segsize; 411 } 412 413 return; 414 } 415 416 /* 417 * Load firmware image into the NIC. Check that the firmware revision 418 * is acceptable and see if we want the firmware for the Tigon 1 or 419 * Tigon 2. 420 */ 421 static void ti_loadfw(sc) 422 struct ti_softc *sc; 423 { 424 switch(sc->ti_hwrev) { 425 case TI_HWREV_TIGON: 426 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 427 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 428 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 429 printf("ti%d: firmware revision mismatch; want " 430 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 431 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 432 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 433 tigonFwReleaseMinor, tigonFwReleaseFix); 434 return; 435 } 436 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 437 (caddr_t)tigonFwText); 438 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 439 (caddr_t)tigonFwData); 440 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 441 (caddr_t)tigonFwRodata); 442 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 443 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 444 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 445 break; 446 case TI_HWREV_TIGON_II: 447 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 448 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 449 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 450 printf("ti%d: firmware revision mismatch; want " 451 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 452 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 453 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 454 tigon2FwReleaseMinor, tigon2FwReleaseFix); 455 return; 456 } 457 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 458 (caddr_t)tigon2FwText); 459 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 460 (caddr_t)tigon2FwData); 461 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 462 (caddr_t)tigon2FwRodata); 463 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 464 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 465 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 466 break; 467 default: 468 printf("ti%d: can't load firmware: unknown hardware rev\n", 469 sc->ti_unit); 470 break; 471 } 472 473 return; 474 } 475 476 /* 477 * Send the NIC a command via the command ring. 478 */ 479 static void ti_cmd(sc, cmd) 480 struct ti_softc *sc; 481 struct ti_cmd_desc *cmd; 482 { 483 u_int32_t index; 484 485 if (sc->ti_rdata->ti_cmd_ring == NULL) 486 return; 487 488 index = sc->ti_cmd_saved_prodidx; 489 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 490 TI_INC(index, TI_CMD_RING_CNT); 491 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 492 sc->ti_cmd_saved_prodidx = index; 493 494 return; 495 } 496 497 /* 498 * Send the NIC an extended command. The 'len' parameter specifies the 499 * number of command slots to include after the initial command. 500 */ 501 static void ti_cmd_ext(sc, cmd, arg, len) 502 struct ti_softc *sc; 503 struct ti_cmd_desc *cmd; 504 caddr_t arg; 505 int len; 506 { 507 u_int32_t index; 508 int i; 509 510 if (sc->ti_rdata->ti_cmd_ring == NULL) 511 return; 512 513 index = sc->ti_cmd_saved_prodidx; 514 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 515 TI_INC(index, TI_CMD_RING_CNT); 516 for (i = 0; i < len; i++) { 517 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 518 *(u_int32_t *)(&arg[i * 4])); 519 TI_INC(index, TI_CMD_RING_CNT); 520 } 521 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 522 sc->ti_cmd_saved_prodidx = index; 523 524 return; 525 } 526 527 /* 528 * Handle events that have triggered interrupts. 529 */ 530 static void ti_handle_events(sc) 531 struct ti_softc *sc; 532 { 533 struct ti_event_desc *e; 534 535 if (sc->ti_rdata->ti_event_ring == NULL) 536 return; 537 538 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 539 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 540 switch(e->ti_event) { 541 case TI_EV_LINKSTAT_CHANGED: 542 sc->ti_linkstat = e->ti_code; 543 if (e->ti_code == TI_EV_CODE_LINK_UP) 544 printf("ti%d: 10/100 link up\n", sc->ti_unit); 545 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 546 printf("ti%d: gigabit link up\n", sc->ti_unit); 547 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 548 printf("ti%d: link down\n", sc->ti_unit); 549 break; 550 case TI_EV_ERROR: 551 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 552 printf("ti%d: invalid command\n", sc->ti_unit); 553 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 554 printf("ti%d: unknown command\n", sc->ti_unit); 555 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 556 printf("ti%d: bad config data\n", sc->ti_unit); 557 break; 558 case TI_EV_FIRMWARE_UP: 559 ti_init2(sc); 560 break; 561 case TI_EV_STATS_UPDATED: 562 ti_stats_update(sc); 563 break; 564 case TI_EV_RESET_JUMBO_RING: 565 case TI_EV_MCAST_UPDATED: 566 /* Who cares. */ 567 break; 568 default: 569 printf("ti%d: unknown event: %d\n", 570 sc->ti_unit, e->ti_event); 571 break; 572 } 573 /* Advance the consumer index. */ 574 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 575 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 576 } 577 578 return; 579 } 580 581 /* 582 * Memory management for the jumbo receive ring is a pain in the 583 * butt. We need to allocate at least 9018 bytes of space per frame, 584 * _and_ it has to be contiguous (unless you use the extended 585 * jumbo descriptor format). Using malloc() all the time won't 586 * work: malloc() allocates memory in powers of two, which means we 587 * would end up wasting a considerable amount of space by allocating 588 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 589 * to do our own memory management. 590 * 591 * The driver needs to allocate a contiguous chunk of memory at boot 592 * time. We then chop this up ourselves into 9K pieces and use them 593 * as external mbuf storage. 594 * 595 * One issue here is how much memory to allocate. The jumbo ring has 596 * 256 slots in it, but at 9K per slot than can consume over 2MB of 597 * RAM. This is a bit much, especially considering we also need 598 * RAM for the standard ring and mini ring (on the Tigon 2). To 599 * save space, we only actually allocate enough memory for 64 slots 600 * by default, which works out to between 500 and 600K. This can 601 * be tuned by changing a #define in if_tireg.h. 602 */ 603 604 static int ti_alloc_jumbo_mem(sc) 605 struct ti_softc *sc; 606 { 607 caddr_t ptr; 608 int i; 609 struct ti_jpool_entry *entry; 610 611 /* Grab a big chunk o' storage. */ 612 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 613 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 614 615 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 616 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 617 return(ENOBUFS); 618 } 619 620 SLIST_INIT(&sc->ti_jfree_listhead); 621 SLIST_INIT(&sc->ti_jinuse_listhead); 622 623 /* 624 * Now divide it up into 9K pieces and save the addresses 625 * in an array. Note that we play an evil trick here by using 626 * the first few bytes in the buffer to hold the the address 627 * of the softc structure for this interface. This is because 628 * ti_jfree() needs it, but it is called by the mbuf management 629 * code which will not pass it to us explicitly. 630 */ 631 ptr = sc->ti_cdata.ti_jumbo_buf; 632 for (i = 0; i < TI_JSLOTS; i++) { 633 u_int64_t **aptr; 634 aptr = (u_int64_t **)ptr; 635 aptr[0] = (u_int64_t *)sc; 636 ptr += sizeof(u_int64_t); 637 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 638 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 639 ptr += (TI_JLEN - sizeof(u_int64_t)); 640 entry = malloc(sizeof(struct ti_jpool_entry), 641 M_DEVBUF, M_WAITOK); 642 if (entry == NULL) { 643 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 644 M_DEVBUF); 645 sc->ti_cdata.ti_jumbo_buf = NULL; 646 printf("ti%d: no memory for jumbo " 647 "buffer queue!\n", sc->ti_unit); 648 return(ENOBUFS); 649 } 650 entry->slot = i; 651 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 652 } 653 654 return(0); 655 } 656 657 /* 658 * Allocate a jumbo buffer. 659 */ 660 static void *ti_jalloc(sc) 661 struct ti_softc *sc; 662 { 663 struct ti_jpool_entry *entry; 664 665 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 666 667 if (entry == NULL) { 668 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 669 return(NULL); 670 } 671 672 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 673 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 674 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 675 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 676 } 677 678 /* 679 * Adjust usage count on a jumbo buffer. In general this doesn't 680 * get used much because our jumbo buffers don't get passed around 681 * too much, but it's implemented for correctness. 682 */ 683 static void ti_jref(buf, size) 684 caddr_t buf; 685 u_int size; 686 { 687 struct ti_softc *sc; 688 u_int64_t **aptr; 689 int i; 690 691 /* Extract the softc struct pointer. */ 692 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 693 sc = (struct ti_softc *)(aptr[0]); 694 695 if (sc == NULL) 696 panic("ti_jref: can't find softc pointer!"); 697 698 if (size != TI_JUMBO_FRAMELEN) 699 panic("ti_jref: adjusting refcount of buf of wrong size!"); 700 701 /* calculate the slot this buffer belongs to */ 702 703 i = ((vm_offset_t)aptr 704 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 705 706 if ((i < 0) || (i >= TI_JSLOTS)) 707 panic("ti_jref: asked to reference buffer " 708 "that we don't manage!"); 709 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 710 panic("ti_jref: buffer already free!"); 711 else 712 sc->ti_cdata.ti_jslots[i].ti_inuse++; 713 714 return; 715 } 716 717 /* 718 * Release a jumbo buffer. 719 */ 720 static void ti_jfree(buf, size) 721 caddr_t buf; 722 u_int size; 723 { 724 struct ti_softc *sc; 725 u_int64_t **aptr; 726 int i; 727 struct ti_jpool_entry *entry; 728 729 /* Extract the softc struct pointer. */ 730 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 731 sc = (struct ti_softc *)(aptr[0]); 732 733 if (sc == NULL) 734 panic("ti_jfree: can't find softc pointer!"); 735 736 if (size != TI_JUMBO_FRAMELEN) 737 panic("ti_jfree: freeing buffer of wrong size!"); 738 739 /* calculate the slot this buffer belongs to */ 740 741 i = ((vm_offset_t)aptr 742 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 743 744 if ((i < 0) || (i >= TI_JSLOTS)) 745 panic("ti_jfree: asked to free buffer that we don't manage!"); 746 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 747 panic("ti_jfree: buffer already free!"); 748 else { 749 sc->ti_cdata.ti_jslots[i].ti_inuse--; 750 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 751 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 752 if (entry == NULL) 753 panic("ti_jfree: buffer not in use!"); 754 entry->slot = i; 755 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 756 jpool_entries); 757 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 758 entry, jpool_entries); 759 } 760 } 761 762 return; 763 } 764 765 766 /* 767 * Intialize a standard receive ring descriptor. 768 */ 769 static int ti_newbuf_std(sc, i, m) 770 struct ti_softc *sc; 771 int i; 772 struct mbuf *m; 773 { 774 struct mbuf *m_new = NULL; 775 struct ti_rx_desc *r; 776 777 if (m == NULL) { 778 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 779 if (m_new == NULL) 780 return(ENOBUFS); 781 782 MCLGET(m_new, MB_DONTWAIT); 783 if (!(m_new->m_flags & M_EXT)) { 784 m_freem(m_new); 785 return(ENOBUFS); 786 } 787 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 788 } else { 789 m_new = m; 790 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 791 m_new->m_data = m_new->m_ext.ext_buf; 792 } 793 794 m_adj(m_new, ETHER_ALIGN); 795 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 796 r = &sc->ti_rdata->ti_rx_std_ring[i]; 797 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 798 r->ti_type = TI_BDTYPE_RECV_BD; 799 r->ti_flags = 0; 800 if (sc->arpcom.ac_if.if_hwassist) 801 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 802 r->ti_len = m_new->m_len; 803 r->ti_idx = i; 804 805 return(0); 806 } 807 808 /* 809 * Intialize a mini receive ring descriptor. This only applies to 810 * the Tigon 2. 811 */ 812 static int ti_newbuf_mini(sc, i, m) 813 struct ti_softc *sc; 814 int i; 815 struct mbuf *m; 816 { 817 struct mbuf *m_new = NULL; 818 struct ti_rx_desc *r; 819 820 if (m == NULL) { 821 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 822 if (m_new == NULL) { 823 return(ENOBUFS); 824 } 825 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 826 } else { 827 m_new = m; 828 m_new->m_data = m_new->m_pktdat; 829 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 830 } 831 832 m_adj(m_new, ETHER_ALIGN); 833 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 834 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 835 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 836 r->ti_type = TI_BDTYPE_RECV_BD; 837 r->ti_flags = TI_BDFLAG_MINI_RING; 838 if (sc->arpcom.ac_if.if_hwassist) 839 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 840 r->ti_len = m_new->m_len; 841 r->ti_idx = i; 842 843 return(0); 844 } 845 846 /* 847 * Initialize a jumbo receive ring descriptor. This allocates 848 * a jumbo buffer from the pool managed internally by the driver. 849 */ 850 static int ti_newbuf_jumbo(sc, i, m) 851 struct ti_softc *sc; 852 int i; 853 struct mbuf *m; 854 { 855 struct mbuf *m_new = NULL; 856 struct ti_rx_desc *r; 857 858 if (m == NULL) { 859 caddr_t *buf = NULL; 860 861 /* Allocate the mbuf. */ 862 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 863 if (m_new == NULL) { 864 return(ENOBUFS); 865 } 866 867 /* Allocate the jumbo buffer */ 868 buf = ti_jalloc(sc); 869 if (buf == NULL) { 870 m_freem(m_new); 871 printf("ti%d: jumbo allocation failed " 872 "-- packet dropped!\n", sc->ti_unit); 873 return(ENOBUFS); 874 } 875 876 /* Attach the buffer to the mbuf. */ 877 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 878 m_new->m_flags |= M_EXT | M_EXT_OLD; 879 m_new->m_len = m_new->m_pkthdr.len = 880 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 881 m_new->m_ext.ext_nfree.old = ti_jfree; 882 m_new->m_ext.ext_nref.old = ti_jref; 883 } else { 884 m_new = m; 885 m_new->m_data = m_new->m_ext.ext_buf; 886 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 887 } 888 889 m_adj(m_new, ETHER_ALIGN); 890 /* Set up the descriptor. */ 891 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 892 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 893 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 894 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 895 r->ti_flags = TI_BDFLAG_JUMBO_RING; 896 if (sc->arpcom.ac_if.if_hwassist) 897 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 898 r->ti_len = m_new->m_len; 899 r->ti_idx = i; 900 901 return(0); 902 } 903 904 /* 905 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 906 * that's 1MB or memory, which is a lot. For now, we fill only the first 907 * 256 ring entries and hope that our CPU is fast enough to keep up with 908 * the NIC. 909 */ 910 static int ti_init_rx_ring_std(sc) 911 struct ti_softc *sc; 912 { 913 int i; 914 struct ti_cmd_desc cmd; 915 916 for (i = 0; i < TI_SSLOTS; i++) { 917 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 918 return(ENOBUFS); 919 }; 920 921 TI_UPDATE_STDPROD(sc, i - 1); 922 sc->ti_std = i - 1; 923 924 return(0); 925 } 926 927 static void ti_free_rx_ring_std(sc) 928 struct ti_softc *sc; 929 { 930 int i; 931 932 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 933 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 934 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 935 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 936 } 937 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 938 sizeof(struct ti_rx_desc)); 939 } 940 941 return; 942 } 943 944 static int ti_init_rx_ring_jumbo(sc) 945 struct ti_softc *sc; 946 { 947 int i; 948 struct ti_cmd_desc cmd; 949 950 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 951 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 952 return(ENOBUFS); 953 }; 954 955 TI_UPDATE_JUMBOPROD(sc, i - 1); 956 sc->ti_jumbo = i - 1; 957 958 return(0); 959 } 960 961 static void ti_free_rx_ring_jumbo(sc) 962 struct ti_softc *sc; 963 { 964 int i; 965 966 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 967 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 968 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 969 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 970 } 971 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 972 sizeof(struct ti_rx_desc)); 973 } 974 975 return; 976 } 977 978 static int ti_init_rx_ring_mini(sc) 979 struct ti_softc *sc; 980 { 981 int i; 982 983 for (i = 0; i < TI_MSLOTS; i++) { 984 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 985 return(ENOBUFS); 986 }; 987 988 TI_UPDATE_MINIPROD(sc, i - 1); 989 sc->ti_mini = i - 1; 990 991 return(0); 992 } 993 994 static void ti_free_rx_ring_mini(sc) 995 struct ti_softc *sc; 996 { 997 int i; 998 999 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1000 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1001 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1002 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1003 } 1004 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1005 sizeof(struct ti_rx_desc)); 1006 } 1007 1008 return; 1009 } 1010 1011 static void ti_free_tx_ring(sc) 1012 struct ti_softc *sc; 1013 { 1014 int i; 1015 1016 if (sc->ti_rdata->ti_tx_ring == NULL) 1017 return; 1018 1019 for (i = 0; i < TI_TX_RING_CNT; i++) { 1020 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1021 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1022 sc->ti_cdata.ti_tx_chain[i] = NULL; 1023 } 1024 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1025 sizeof(struct ti_tx_desc)); 1026 } 1027 1028 return; 1029 } 1030 1031 static int ti_init_tx_ring(sc) 1032 struct ti_softc *sc; 1033 { 1034 sc->ti_txcnt = 0; 1035 sc->ti_tx_saved_considx = 0; 1036 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1037 return(0); 1038 } 1039 1040 /* 1041 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1042 * but we have to support the old way too so that Tigon 1 cards will 1043 * work. 1044 */ 1045 void ti_add_mcast(sc, addr) 1046 struct ti_softc *sc; 1047 struct ether_addr *addr; 1048 { 1049 struct ti_cmd_desc cmd; 1050 u_int16_t *m; 1051 u_int32_t ext[2] = {0, 0}; 1052 1053 m = (u_int16_t *)&addr->octet[0]; 1054 1055 switch(sc->ti_hwrev) { 1056 case TI_HWREV_TIGON: 1057 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1058 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1059 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1060 break; 1061 case TI_HWREV_TIGON_II: 1062 ext[0] = htons(m[0]); 1063 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1064 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1065 break; 1066 default: 1067 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1068 break; 1069 } 1070 1071 return; 1072 } 1073 1074 void ti_del_mcast(sc, addr) 1075 struct ti_softc *sc; 1076 struct ether_addr *addr; 1077 { 1078 struct ti_cmd_desc cmd; 1079 u_int16_t *m; 1080 u_int32_t ext[2] = {0, 0}; 1081 1082 m = (u_int16_t *)&addr->octet[0]; 1083 1084 switch(sc->ti_hwrev) { 1085 case TI_HWREV_TIGON: 1086 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1087 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1088 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1089 break; 1090 case TI_HWREV_TIGON_II: 1091 ext[0] = htons(m[0]); 1092 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1093 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1094 break; 1095 default: 1096 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1097 break; 1098 } 1099 1100 return; 1101 } 1102 1103 /* 1104 * Configure the Tigon's multicast address filter. 1105 * 1106 * The actual multicast table management is a bit of a pain, thanks to 1107 * slight brain damage on the part of both Alteon and us. With our 1108 * multicast code, we are only alerted when the multicast address table 1109 * changes and at that point we only have the current list of addresses: 1110 * we only know the current state, not the previous state, so we don't 1111 * actually know what addresses were removed or added. The firmware has 1112 * state, but we can't get our grubby mits on it, and there is no 'delete 1113 * all multicast addresses' command. Hence, we have to maintain our own 1114 * state so we know what addresses have been programmed into the NIC at 1115 * any given time. 1116 */ 1117 static void ti_setmulti(sc) 1118 struct ti_softc *sc; 1119 { 1120 struct ifnet *ifp; 1121 struct ifmultiaddr *ifma; 1122 struct ti_cmd_desc cmd; 1123 struct ti_mc_entry *mc; 1124 u_int32_t intrs; 1125 1126 ifp = &sc->arpcom.ac_if; 1127 1128 if (ifp->if_flags & IFF_ALLMULTI) { 1129 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1130 return; 1131 } else { 1132 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1133 } 1134 1135 /* Disable interrupts. */ 1136 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1137 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1138 1139 /* First, zot all the existing filters. */ 1140 while (sc->ti_mc_listhead.slh_first != NULL) { 1141 mc = sc->ti_mc_listhead.slh_first; 1142 ti_del_mcast(sc, &mc->mc_addr); 1143 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1144 free(mc, M_DEVBUF); 1145 } 1146 1147 /* Now program new ones. */ 1148 for (ifma = ifp->if_multiaddrs.lh_first; 1149 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1150 if (ifma->ifma_addr->sa_family != AF_LINK) 1151 continue; 1152 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT); 1153 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1154 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1155 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1156 ti_add_mcast(sc, &mc->mc_addr); 1157 } 1158 1159 /* Re-enable interrupts. */ 1160 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1161 1162 return; 1163 } 1164 1165 /* 1166 * Check to see if the BIOS has configured us for a 64 bit slot when 1167 * we aren't actually in one. If we detect this condition, we can work 1168 * around it on the Tigon 2 by setting a bit in the PCI state register, 1169 * but for the Tigon 1 we must give up and abort the interface attach. 1170 */ 1171 static int ti_64bitslot_war(sc) 1172 struct ti_softc *sc; 1173 { 1174 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1175 CSR_WRITE_4(sc, 0x600, 0); 1176 CSR_WRITE_4(sc, 0x604, 0); 1177 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1178 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1179 if (sc->ti_hwrev == TI_HWREV_TIGON) 1180 return(EINVAL); 1181 else { 1182 TI_SETBIT(sc, TI_PCI_STATE, 1183 TI_PCISTATE_32BIT_BUS); 1184 return(0); 1185 } 1186 } 1187 } 1188 1189 return(0); 1190 } 1191 1192 /* 1193 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1194 * self-test results. 1195 */ 1196 static int ti_chipinit(sc) 1197 struct ti_softc *sc; 1198 { 1199 u_int32_t cacheline; 1200 u_int32_t pci_writemax = 0; 1201 1202 /* Initialize link to down state. */ 1203 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1204 1205 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1206 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1207 else 1208 sc->arpcom.ac_if.if_hwassist = 0; 1209 1210 /* Set endianness before we access any non-PCI registers. */ 1211 #if BYTE_ORDER == BIG_ENDIAN 1212 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1213 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1214 #else 1215 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1216 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1217 #endif 1218 1219 /* Check the ROM failed bit to see if self-tests passed. */ 1220 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1221 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1222 return(ENODEV); 1223 } 1224 1225 /* Halt the CPU. */ 1226 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1227 1228 /* Figure out the hardware revision. */ 1229 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1230 case TI_REV_TIGON_I: 1231 sc->ti_hwrev = TI_HWREV_TIGON; 1232 break; 1233 case TI_REV_TIGON_II: 1234 sc->ti_hwrev = TI_HWREV_TIGON_II; 1235 break; 1236 default: 1237 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1238 return(ENODEV); 1239 } 1240 1241 /* Do special setup for Tigon 2. */ 1242 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1243 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1245 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1246 } 1247 1248 /* Set up the PCI state register. */ 1249 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1250 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1251 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1252 } 1253 1254 /* Clear the read/write max DMA parameters. */ 1255 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1256 TI_PCISTATE_READ_MAXDMA)); 1257 1258 /* Get cache line size. */ 1259 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1260 1261 /* 1262 * If the system has set enabled the PCI memory write 1263 * and invalidate command in the command register, set 1264 * the write max parameter accordingly. This is necessary 1265 * to use MWI with the Tigon 2. 1266 */ 1267 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1268 switch(cacheline) { 1269 case 1: 1270 case 4: 1271 case 8: 1272 case 16: 1273 case 32: 1274 case 64: 1275 break; 1276 default: 1277 /* Disable PCI memory write and invalidate. */ 1278 if (bootverbose) 1279 printf("ti%d: cache line size %d not " 1280 "supported; disabling PCI MWI\n", 1281 sc->ti_unit, cacheline); 1282 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1283 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1284 break; 1285 } 1286 } 1287 1288 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1289 1290 /* This sets the min dma param all the way up (0xff). */ 1291 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1292 1293 /* Configure DMA variables. */ 1294 #if BYTE_ORDER == BIG_ENDIAN 1295 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1296 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1297 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1298 TI_OPMODE_DONT_FRAG_JUMBO); 1299 #else 1300 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1301 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1302 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1303 #endif 1304 1305 /* 1306 * Only allow 1 DMA channel to be active at a time. 1307 * I don't think this is a good idea, but without it 1308 * the firmware racks up lots of nicDmaReadRingFull 1309 * errors. This is not compatible with hardware checksums. 1310 */ 1311 if (sc->arpcom.ac_if.if_hwassist == 0) 1312 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1313 1314 /* Recommended settings from Tigon manual. */ 1315 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1316 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1317 1318 if (ti_64bitslot_war(sc)) { 1319 printf("ti%d: bios thinks we're in a 64 bit slot, " 1320 "but we aren't", sc->ti_unit); 1321 return(EINVAL); 1322 } 1323 1324 return(0); 1325 } 1326 1327 /* 1328 * Initialize the general information block and firmware, and 1329 * start the CPU(s) running. 1330 */ 1331 static int ti_gibinit(sc) 1332 struct ti_softc *sc; 1333 { 1334 struct ti_rcb *rcb; 1335 int i; 1336 struct ifnet *ifp; 1337 1338 ifp = &sc->arpcom.ac_if; 1339 1340 /* Disable interrupts for now. */ 1341 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1342 1343 /* Tell the chip where to find the general information block. */ 1344 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1345 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1346 1347 /* Load the firmware into SRAM. */ 1348 ti_loadfw(sc); 1349 1350 /* Set up the contents of the general info and ring control blocks. */ 1351 1352 /* Set up the event ring and producer pointer. */ 1353 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1354 1355 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1356 rcb->ti_flags = 0; 1357 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1358 vtophys(&sc->ti_ev_prodidx); 1359 sc->ti_ev_prodidx.ti_idx = 0; 1360 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1361 sc->ti_ev_saved_considx = 0; 1362 1363 /* Set up the command ring and producer mailbox. */ 1364 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1365 1366 sc->ti_rdata->ti_cmd_ring = 1367 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1368 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1369 rcb->ti_flags = 0; 1370 rcb->ti_max_len = 0; 1371 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1372 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1373 } 1374 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1375 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1376 sc->ti_cmd_saved_prodidx = 0; 1377 1378 /* 1379 * Assign the address of the stats refresh buffer. 1380 * We re-use the current stats buffer for this to 1381 * conserve memory. 1382 */ 1383 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1384 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1385 1386 /* Set up the standard receive ring. */ 1387 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1388 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1389 rcb->ti_max_len = TI_FRAMELEN; 1390 rcb->ti_flags = 0; 1391 if (sc->arpcom.ac_if.if_hwassist) 1392 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1393 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1394 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1395 1396 /* Set up the jumbo receive ring. */ 1397 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1398 TI_HOSTADDR(rcb->ti_hostaddr) = 1399 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1400 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1401 rcb->ti_flags = 0; 1402 if (sc->arpcom.ac_if.if_hwassist) 1403 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1404 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1405 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1406 1407 /* 1408 * Set up the mini ring. Only activated on the 1409 * Tigon 2 but the slot in the config block is 1410 * still there on the Tigon 1. 1411 */ 1412 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1413 TI_HOSTADDR(rcb->ti_hostaddr) = 1414 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1415 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1416 if (sc->ti_hwrev == TI_HWREV_TIGON) 1417 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1418 else 1419 rcb->ti_flags = 0; 1420 if (sc->arpcom.ac_if.if_hwassist) 1421 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1422 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1423 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1424 1425 /* 1426 * Set up the receive return ring. 1427 */ 1428 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1429 TI_HOSTADDR(rcb->ti_hostaddr) = 1430 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1431 rcb->ti_flags = 0; 1432 rcb->ti_max_len = TI_RETURN_RING_CNT; 1433 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1434 vtophys(&sc->ti_return_prodidx); 1435 1436 /* 1437 * Set up the tx ring. Note: for the Tigon 2, we have the option 1438 * of putting the transmit ring in the host's address space and 1439 * letting the chip DMA it instead of leaving the ring in the NIC's 1440 * memory and accessing it through the shared memory region. We 1441 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1442 * so we have to revert to the shared memory scheme if we detect 1443 * a Tigon 1 chip. 1444 */ 1445 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1446 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1447 sc->ti_rdata->ti_tx_ring_nic = 1448 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1449 } 1450 bzero((char *)sc->ti_rdata->ti_tx_ring, 1451 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1452 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1453 if (sc->ti_hwrev == TI_HWREV_TIGON) 1454 rcb->ti_flags = 0; 1455 else 1456 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1457 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1458 if (sc->arpcom.ac_if.if_hwassist) 1459 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1460 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1461 rcb->ti_max_len = TI_TX_RING_CNT; 1462 if (sc->ti_hwrev == TI_HWREV_TIGON) 1463 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1464 else 1465 TI_HOSTADDR(rcb->ti_hostaddr) = 1466 vtophys(&sc->ti_rdata->ti_tx_ring); 1467 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1468 vtophys(&sc->ti_tx_considx); 1469 1470 /* Set up tuneables */ 1471 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1472 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1473 (sc->ti_rx_coal_ticks / 10)); 1474 else 1475 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1476 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1477 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1478 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1479 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1480 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1481 1482 /* Turn interrupts on. */ 1483 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1484 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1485 1486 /* Start CPU. */ 1487 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1488 1489 return(0); 1490 } 1491 1492 /* 1493 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1494 * against our list and return its name if we find a match. 1495 */ 1496 static int ti_probe(dev) 1497 device_t dev; 1498 { 1499 struct ti_type *t; 1500 1501 t = ti_devs; 1502 1503 while(t->ti_name != NULL) { 1504 if ((pci_get_vendor(dev) == t->ti_vid) && 1505 (pci_get_device(dev) == t->ti_did)) { 1506 device_set_desc(dev, t->ti_name); 1507 return(0); 1508 } 1509 t++; 1510 } 1511 1512 return(ENXIO); 1513 } 1514 1515 static int ti_attach(dev) 1516 device_t dev; 1517 { 1518 int s; 1519 u_int32_t command; 1520 struct ifnet *ifp; 1521 struct ti_softc *sc; 1522 int unit, error = 0, rid; 1523 1524 s = splimp(); 1525 1526 sc = device_get_softc(dev); 1527 unit = device_get_unit(dev); 1528 bzero(sc, sizeof(struct ti_softc)); 1529 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM; 1530 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 1531 1532 /* 1533 * Map control/status registers. 1534 */ 1535 command = pci_read_config(dev, PCIR_COMMAND, 4); 1536 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1537 pci_write_config(dev, PCIR_COMMAND, command, 4); 1538 command = pci_read_config(dev, PCIR_COMMAND, 4); 1539 1540 if (!(command & PCIM_CMD_MEMEN)) { 1541 printf("ti%d: failed to enable memory mapping!\n", unit); 1542 error = ENXIO; 1543 goto fail; 1544 } 1545 1546 rid = TI_PCI_LOMEM; 1547 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1548 0, ~0, 1, RF_ACTIVE); 1549 1550 if (sc->ti_res == NULL) { 1551 printf ("ti%d: couldn't map memory\n", unit); 1552 error = ENXIO; 1553 goto fail; 1554 } 1555 1556 sc->ti_btag = rman_get_bustag(sc->ti_res); 1557 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1558 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1559 1560 /* Allocate interrupt */ 1561 rid = 0; 1562 1563 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1564 RF_SHAREABLE | RF_ACTIVE); 1565 1566 if (sc->ti_irq == NULL) { 1567 printf("ti%d: couldn't map interrupt\n", unit); 1568 error = ENXIO; 1569 goto fail; 1570 } 1571 1572 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1573 ti_intr, sc, &sc->ti_intrhand); 1574 1575 if (error) { 1576 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1577 bus_release_resource(dev, SYS_RES_MEMORY, 1578 TI_PCI_LOMEM, sc->ti_res); 1579 printf("ti%d: couldn't set up irq\n", unit); 1580 goto fail; 1581 } 1582 1583 sc->ti_unit = unit; 1584 1585 if (ti_chipinit(sc)) { 1586 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1587 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1589 bus_release_resource(dev, SYS_RES_MEMORY, 1590 TI_PCI_LOMEM, sc->ti_res); 1591 error = ENXIO; 1592 goto fail; 1593 } 1594 1595 /* Zero out the NIC's on-board SRAM. */ 1596 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1597 1598 /* Init again -- zeroing memory may have clobbered some registers. */ 1599 if (ti_chipinit(sc)) { 1600 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1601 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1602 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1603 bus_release_resource(dev, SYS_RES_MEMORY, 1604 TI_PCI_LOMEM, sc->ti_res); 1605 error = ENXIO; 1606 goto fail; 1607 } 1608 1609 /* 1610 * Get station address from the EEPROM. Note: the manual states 1611 * that the MAC address is at offset 0x8c, however the data is 1612 * stored as two longwords (since that's how it's loaded into 1613 * the NIC). This means the MAC address is actually preceeded 1614 * by two zero bytes. We need to skip over those. 1615 */ 1616 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1617 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1618 printf("ti%d: failed to read station address\n", unit); 1619 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1620 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1621 bus_release_resource(dev, SYS_RES_MEMORY, 1622 TI_PCI_LOMEM, sc->ti_res); 1623 error = ENXIO; 1624 goto fail; 1625 } 1626 1627 /* Allocate the general information block and ring buffers. */ 1628 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1629 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1630 1631 if (sc->ti_rdata == NULL) { 1632 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1633 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1634 bus_release_resource(dev, SYS_RES_MEMORY, 1635 TI_PCI_LOMEM, sc->ti_res); 1636 error = ENXIO; 1637 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1638 goto fail; 1639 } 1640 1641 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1642 1643 /* Try to allocate memory for jumbo buffers. */ 1644 if (ti_alloc_jumbo_mem(sc)) { 1645 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1646 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1647 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1648 bus_release_resource(dev, SYS_RES_MEMORY, 1649 TI_PCI_LOMEM, sc->ti_res); 1650 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 1651 M_DEVBUF); 1652 error = ENXIO; 1653 goto fail; 1654 } 1655 1656 /* 1657 * We really need a better way to tell a 1000baseTX card 1658 * from a 1000baseSX one, since in theory there could be 1659 * OEMed 1000baseTX cards from lame vendors who aren't 1660 * clever enough to change the PCI ID. For the moment 1661 * though, the AceNIC is the only copper card available. 1662 */ 1663 if (pci_get_vendor(dev) == ALT_VENDORID && 1664 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1665 sc->ti_copper = 1; 1666 /* Ok, it's not the only copper card available. */ 1667 if (pci_get_vendor(dev) == NG_VENDORID && 1668 pci_get_device(dev) == NG_DEVICEID_GA620T) 1669 sc->ti_copper = 1; 1670 1671 /* Set default tuneable values. */ 1672 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1673 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1674 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1675 sc->ti_rx_max_coal_bds = 64; 1676 sc->ti_tx_max_coal_bds = 128; 1677 sc->ti_tx_buf_ratio = 21; 1678 1679 /* Set up ifnet structure */ 1680 ifp = &sc->arpcom.ac_if; 1681 ifp->if_softc = sc; 1682 if_initname(ifp, "ti", sc->ti_unit); 1683 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1684 ifp->if_ioctl = ti_ioctl; 1685 ifp->if_start = ti_start; 1686 ifp->if_watchdog = ti_watchdog; 1687 ifp->if_init = ti_init; 1688 ifp->if_mtu = ETHERMTU; 1689 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1); 1690 ifq_set_ready(&ifp->if_snd); 1691 1692 /* Set up ifmedia support. */ 1693 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1694 if (sc->ti_copper) { 1695 /* 1696 * Copper cards allow manual 10/100 mode selection, 1697 * but not manual 1000baseTX mode selection. Why? 1698 * Becuase currently there's no way to specify the 1699 * master/slave setting through the firmware interface, 1700 * so Alteon decided to just bag it and handle it 1701 * via autonegotiation. 1702 */ 1703 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1704 ifmedia_add(&sc->ifmedia, 1705 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1706 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1707 ifmedia_add(&sc->ifmedia, 1708 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1709 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1710 ifmedia_add(&sc->ifmedia, 1711 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL); 1712 } else { 1713 /* Fiber cards don't support 10/100 modes. */ 1714 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1715 ifmedia_add(&sc->ifmedia, 1716 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1717 } 1718 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1719 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1720 1721 /* 1722 * Call MI attach routine. 1723 */ 1724 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1725 1726 fail: 1727 splx(s); 1728 1729 return(error); 1730 } 1731 1732 static int ti_detach(dev) 1733 device_t dev; 1734 { 1735 struct ti_softc *sc; 1736 struct ifnet *ifp; 1737 int s; 1738 1739 s = splimp(); 1740 1741 sc = device_get_softc(dev); 1742 ifp = &sc->arpcom.ac_if; 1743 1744 ether_ifdetach(ifp); 1745 ti_stop(sc); 1746 1747 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1748 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1749 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1750 1751 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1752 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1753 ifmedia_removeall(&sc->ifmedia); 1754 1755 splx(s); 1756 1757 return(0); 1758 } 1759 1760 /* 1761 * Frame reception handling. This is called if there's a frame 1762 * on the receive return list. 1763 * 1764 * Note: we have to be able to handle three possibilities here: 1765 * 1) the frame is from the mini receive ring (can only happen) 1766 * on Tigon 2 boards) 1767 * 2) the frame is from the jumbo recieve ring 1768 * 3) the frame is from the standard receive ring 1769 */ 1770 1771 static void ti_rxeof(sc) 1772 struct ti_softc *sc; 1773 { 1774 struct ifnet *ifp; 1775 struct ti_cmd_desc cmd; 1776 1777 ifp = &sc->arpcom.ac_if; 1778 1779 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1780 struct ti_rx_desc *cur_rx; 1781 u_int32_t rxidx; 1782 struct mbuf *m = NULL; 1783 u_int16_t vlan_tag = 0; 1784 int have_tag = 0; 1785 1786 cur_rx = 1787 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1788 rxidx = cur_rx->ti_idx; 1789 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1790 1791 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1792 have_tag = 1; 1793 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 1794 } 1795 1796 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1797 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1798 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1799 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1800 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1801 ifp->if_ierrors++; 1802 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1803 continue; 1804 } 1805 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1806 ifp->if_ierrors++; 1807 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1808 continue; 1809 } 1810 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1811 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1812 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1813 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1814 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1815 ifp->if_ierrors++; 1816 ti_newbuf_mini(sc, sc->ti_mini, m); 1817 continue; 1818 } 1819 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1820 ifp->if_ierrors++; 1821 ti_newbuf_mini(sc, sc->ti_mini, m); 1822 continue; 1823 } 1824 } else { 1825 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1826 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1827 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1828 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1829 ifp->if_ierrors++; 1830 ti_newbuf_std(sc, sc->ti_std, m); 1831 continue; 1832 } 1833 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1834 ifp->if_ierrors++; 1835 ti_newbuf_std(sc, sc->ti_std, m); 1836 continue; 1837 } 1838 } 1839 1840 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1841 ifp->if_ipackets++; 1842 m->m_pkthdr.rcvif = ifp; 1843 1844 if (ifp->if_hwassist) { 1845 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1846 CSUM_DATA_VALID; 1847 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1848 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1849 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1850 } 1851 1852 /* 1853 * If we received a packet with a vlan tag, pass it 1854 * to vlan_input() instead of ether_input(). 1855 */ 1856 if (have_tag) { 1857 VLAN_INPUT_TAG(m, vlan_tag); 1858 have_tag = vlan_tag = 0; 1859 } else { 1860 (*ifp->if_input)(ifp, m); 1861 } 1862 } 1863 1864 /* Only necessary on the Tigon 1. */ 1865 if (sc->ti_hwrev == TI_HWREV_TIGON) 1866 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1867 sc->ti_rx_saved_considx); 1868 1869 TI_UPDATE_STDPROD(sc, sc->ti_std); 1870 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1871 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1872 1873 return; 1874 } 1875 1876 static void ti_txeof(sc) 1877 struct ti_softc *sc; 1878 { 1879 struct ti_tx_desc *cur_tx = NULL; 1880 struct ifnet *ifp; 1881 1882 ifp = &sc->arpcom.ac_if; 1883 1884 /* 1885 * Go through our tx ring and free mbufs for those 1886 * frames that have been sent. 1887 */ 1888 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1889 u_int32_t idx = 0; 1890 1891 idx = sc->ti_tx_saved_considx; 1892 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1893 if (idx > 383) 1894 CSR_WRITE_4(sc, TI_WINBASE, 1895 TI_TX_RING_BASE + 6144); 1896 else if (idx > 255) 1897 CSR_WRITE_4(sc, TI_WINBASE, 1898 TI_TX_RING_BASE + 4096); 1899 else if (idx > 127) 1900 CSR_WRITE_4(sc, TI_WINBASE, 1901 TI_TX_RING_BASE + 2048); 1902 else 1903 CSR_WRITE_4(sc, TI_WINBASE, 1904 TI_TX_RING_BASE); 1905 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1906 } else 1907 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1908 if (cur_tx->ti_flags & TI_BDFLAG_END) 1909 ifp->if_opackets++; 1910 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1911 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1912 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1913 } 1914 sc->ti_txcnt--; 1915 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1916 ifp->if_timer = 0; 1917 } 1918 1919 if (cur_tx != NULL) 1920 ifp->if_flags &= ~IFF_OACTIVE; 1921 1922 return; 1923 } 1924 1925 static void ti_intr(xsc) 1926 void *xsc; 1927 { 1928 struct ti_softc *sc; 1929 struct ifnet *ifp; 1930 1931 sc = xsc; 1932 ifp = &sc->arpcom.ac_if; 1933 1934 #ifdef notdef 1935 /* Avoid this for now -- checking this register is expensive. */ 1936 /* Make sure this is really our interrupt. */ 1937 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1938 return; 1939 #endif 1940 1941 /* Ack interrupt and stop others from occuring. */ 1942 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1943 1944 if (ifp->if_flags & IFF_RUNNING) { 1945 /* Check RX return ring producer/consumer */ 1946 ti_rxeof(sc); 1947 1948 /* Check TX ring producer/consumer */ 1949 ti_txeof(sc); 1950 } 1951 1952 ti_handle_events(sc); 1953 1954 /* Re-enable interrupts. */ 1955 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1956 1957 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1958 ti_start(ifp); 1959 1960 return; 1961 } 1962 1963 static void ti_stats_update(sc) 1964 struct ti_softc *sc; 1965 { 1966 struct ifnet *ifp; 1967 1968 ifp = &sc->arpcom.ac_if; 1969 1970 ifp->if_collisions += 1971 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1972 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1973 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1974 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1975 ifp->if_collisions; 1976 1977 return; 1978 } 1979 1980 /* 1981 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1982 * pointers to descriptors. 1983 */ 1984 static int ti_encap(sc, m_head, txidx) 1985 struct ti_softc *sc; 1986 struct mbuf *m_head; 1987 u_int32_t *txidx; 1988 { 1989 struct ti_tx_desc *f = NULL; 1990 struct mbuf *m; 1991 u_int32_t frag, cur, cnt = 0; 1992 u_int16_t csum_flags = 0; 1993 struct ifvlan *ifv = NULL; 1994 1995 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1996 m_head->m_pkthdr.rcvif != NULL && 1997 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1998 ifv = m_head->m_pkthdr.rcvif->if_softc; 1999 2000 m = m_head; 2001 cur = frag = *txidx; 2002 2003 if (m_head->m_pkthdr.csum_flags) { 2004 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2005 csum_flags |= TI_BDFLAG_IP_CKSUM; 2006 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2007 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2008 if (m_head->m_flags & M_LASTFRAG) 2009 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2010 else if (m_head->m_flags & M_FRAG) 2011 csum_flags |= TI_BDFLAG_IP_FRAG; 2012 } 2013 /* 2014 * Start packing the mbufs in this chain into 2015 * the fragment pointers. Stop when we run out 2016 * of fragments or hit the end of the mbuf chain. 2017 */ 2018 for (m = m_head; m != NULL; m = m->m_next) { 2019 if (m->m_len != 0) { 2020 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2021 if (frag > 383) 2022 CSR_WRITE_4(sc, TI_WINBASE, 2023 TI_TX_RING_BASE + 6144); 2024 else if (frag > 255) 2025 CSR_WRITE_4(sc, TI_WINBASE, 2026 TI_TX_RING_BASE + 4096); 2027 else if (frag > 127) 2028 CSR_WRITE_4(sc, TI_WINBASE, 2029 TI_TX_RING_BASE + 2048); 2030 else 2031 CSR_WRITE_4(sc, TI_WINBASE, 2032 TI_TX_RING_BASE); 2033 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2034 } else 2035 f = &sc->ti_rdata->ti_tx_ring[frag]; 2036 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2037 break; 2038 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2039 f->ti_len = m->m_len; 2040 f->ti_flags = csum_flags; 2041 2042 if (ifv != NULL) { 2043 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2044 f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 2045 } else { 2046 f->ti_vlan_tag = 0; 2047 } 2048 2049 /* 2050 * Sanity check: avoid coming within 16 descriptors 2051 * of the end of the ring. 2052 */ 2053 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2054 return(ENOBUFS); 2055 cur = frag; 2056 TI_INC(frag, TI_TX_RING_CNT); 2057 cnt++; 2058 } 2059 } 2060 2061 if (m != NULL) 2062 return(ENOBUFS); 2063 2064 if (frag == sc->ti_tx_saved_considx) 2065 return(ENOBUFS); 2066 2067 if (sc->ti_hwrev == TI_HWREV_TIGON) 2068 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2069 TI_BDFLAG_END; 2070 else 2071 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2072 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2073 sc->ti_txcnt += cnt; 2074 2075 *txidx = frag; 2076 2077 return(0); 2078 } 2079 2080 /* 2081 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2082 * to the mbuf data regions directly in the transmit descriptors. 2083 */ 2084 static void ti_start(ifp) 2085 struct ifnet *ifp; 2086 { 2087 struct ti_softc *sc; 2088 struct mbuf *m_head = NULL; 2089 u_int32_t prodidx = 0; 2090 2091 sc = ifp->if_softc; 2092 2093 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2094 2095 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2096 m_head = ifq_poll(&ifp->if_snd); 2097 if (m_head == NULL) 2098 break; 2099 2100 /* 2101 * XXX 2102 * safety overkill. If this is a fragmented packet chain 2103 * with delayed TCP/UDP checksums, then only encapsulate 2104 * it if we have enough descriptors to handle the entire 2105 * chain at once. 2106 * (paranoia -- may not actually be needed) 2107 */ 2108 if (m_head->m_flags & M_FIRSTFRAG && 2109 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2110 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2111 m_head->m_pkthdr.csum_data + 16) { 2112 ifp->if_flags |= IFF_OACTIVE; 2113 break; 2114 } 2115 } 2116 2117 /* 2118 * Pack the data into the transmit ring. If we 2119 * don't have room, set the OACTIVE flag and wait 2120 * for the NIC to drain the ring. 2121 */ 2122 if (ti_encap(sc, m_head, &prodidx)) { 2123 ifp->if_flags |= IFF_OACTIVE; 2124 break; 2125 } 2126 2127 m_head = ifq_dequeue(&ifp->if_snd); 2128 BPF_MTAP(ifp, m_head); 2129 } 2130 2131 /* Transmit */ 2132 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2133 2134 /* 2135 * Set a timeout in case the chip goes out to lunch. 2136 */ 2137 ifp->if_timer = 5; 2138 2139 return; 2140 } 2141 2142 static void ti_init(xsc) 2143 void *xsc; 2144 { 2145 struct ti_softc *sc = xsc; 2146 int s; 2147 2148 s = splimp(); 2149 2150 /* Cancel pending I/O and flush buffers. */ 2151 ti_stop(sc); 2152 2153 /* Init the gen info block, ring control blocks and firmware. */ 2154 if (ti_gibinit(sc)) { 2155 printf("ti%d: initialization failure\n", sc->ti_unit); 2156 splx(s); 2157 return; 2158 } 2159 2160 splx(s); 2161 2162 return; 2163 } 2164 2165 static void ti_init2(sc) 2166 struct ti_softc *sc; 2167 { 2168 struct ti_cmd_desc cmd; 2169 struct ifnet *ifp; 2170 u_int16_t *m; 2171 struct ifmedia *ifm; 2172 int tmp; 2173 2174 ifp = &sc->arpcom.ac_if; 2175 2176 /* Specify MTU and interface index. */ 2177 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit); 2178 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2179 ETHER_HDR_LEN + ETHER_CRC_LEN); 2180 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2181 2182 /* Load our MAC address. */ 2183 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2184 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2185 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2186 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2187 2188 /* Enable or disable promiscuous mode as needed. */ 2189 if (ifp->if_flags & IFF_PROMISC) { 2190 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2191 } else { 2192 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2193 } 2194 2195 /* Program multicast filter. */ 2196 ti_setmulti(sc); 2197 2198 /* 2199 * If this is a Tigon 1, we should tell the 2200 * firmware to use software packet filtering. 2201 */ 2202 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2203 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2204 } 2205 2206 /* Init RX ring. */ 2207 ti_init_rx_ring_std(sc); 2208 2209 /* Init jumbo RX ring. */ 2210 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2211 ti_init_rx_ring_jumbo(sc); 2212 2213 /* 2214 * If this is a Tigon 2, we can also configure the 2215 * mini ring. 2216 */ 2217 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2218 ti_init_rx_ring_mini(sc); 2219 2220 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2221 sc->ti_rx_saved_considx = 0; 2222 2223 /* Init TX ring. */ 2224 ti_init_tx_ring(sc); 2225 2226 /* Tell firmware we're alive. */ 2227 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2228 2229 /* Enable host interrupts. */ 2230 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2231 2232 ifp->if_flags |= IFF_RUNNING; 2233 ifp->if_flags &= ~IFF_OACTIVE; 2234 2235 /* 2236 * Make sure to set media properly. We have to do this 2237 * here since we have to issue commands in order to set 2238 * the link negotiation and we can't issue commands until 2239 * the firmware is running. 2240 */ 2241 ifm = &sc->ifmedia; 2242 tmp = ifm->ifm_media; 2243 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2244 ti_ifmedia_upd(ifp); 2245 ifm->ifm_media = tmp; 2246 2247 return; 2248 } 2249 2250 /* 2251 * Set media options. 2252 */ 2253 static int ti_ifmedia_upd(ifp) 2254 struct ifnet *ifp; 2255 { 2256 struct ti_softc *sc; 2257 struct ifmedia *ifm; 2258 struct ti_cmd_desc cmd; 2259 2260 sc = ifp->if_softc; 2261 ifm = &sc->ifmedia; 2262 2263 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2264 return(EINVAL); 2265 2266 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2267 case IFM_AUTO: 2268 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2269 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2270 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2271 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2272 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2273 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2274 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2275 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2276 break; 2277 case IFM_1000_SX: 2278 case IFM_1000_T: 2279 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2280 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2281 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2282 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2283 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2284 } 2285 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2286 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2287 break; 2288 case IFM_100_FX: 2289 case IFM_10_FL: 2290 case IFM_100_TX: 2291 case IFM_10_T: 2292 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2293 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2294 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2295 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2296 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2297 } else { 2298 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2299 } 2300 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2301 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2302 } else { 2303 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2304 } 2305 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2306 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2307 break; 2308 } 2309 2310 return(0); 2311 } 2312 2313 /* 2314 * Report current media status. 2315 */ 2316 static void ti_ifmedia_sts(ifp, ifmr) 2317 struct ifnet *ifp; 2318 struct ifmediareq *ifmr; 2319 { 2320 struct ti_softc *sc; 2321 u_int32_t media = 0; 2322 2323 sc = ifp->if_softc; 2324 2325 ifmr->ifm_status = IFM_AVALID; 2326 ifmr->ifm_active = IFM_ETHER; 2327 2328 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2329 return; 2330 2331 ifmr->ifm_status |= IFM_ACTIVE; 2332 2333 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2334 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2335 if (sc->ti_copper) 2336 ifmr->ifm_active |= IFM_1000_T; 2337 else 2338 ifmr->ifm_active |= IFM_1000_SX; 2339 if (media & TI_GLNK_FULL_DUPLEX) 2340 ifmr->ifm_active |= IFM_FDX; 2341 else 2342 ifmr->ifm_active |= IFM_HDX; 2343 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2344 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2345 if (sc->ti_copper) { 2346 if (media & TI_LNK_100MB) 2347 ifmr->ifm_active |= IFM_100_TX; 2348 if (media & TI_LNK_10MB) 2349 ifmr->ifm_active |= IFM_10_T; 2350 } else { 2351 if (media & TI_LNK_100MB) 2352 ifmr->ifm_active |= IFM_100_FX; 2353 if (media & TI_LNK_10MB) 2354 ifmr->ifm_active |= IFM_10_FL; 2355 } 2356 if (media & TI_LNK_FULL_DUPLEX) 2357 ifmr->ifm_active |= IFM_FDX; 2358 if (media & TI_LNK_HALF_DUPLEX) 2359 ifmr->ifm_active |= IFM_HDX; 2360 } 2361 2362 return; 2363 } 2364 2365 static int ti_ioctl(ifp, command, data, cr) 2366 struct ifnet *ifp; 2367 u_long command; 2368 caddr_t data; 2369 struct ucred *cr; 2370 { 2371 struct ti_softc *sc = ifp->if_softc; 2372 struct ifreq *ifr = (struct ifreq *) data; 2373 int s, mask, error = 0; 2374 struct ti_cmd_desc cmd; 2375 2376 s = splimp(); 2377 2378 switch(command) { 2379 case SIOCSIFADDR: 2380 case SIOCGIFADDR: 2381 error = ether_ioctl(ifp, command, data); 2382 break; 2383 case SIOCSIFMTU: 2384 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2385 error = EINVAL; 2386 else { 2387 ifp->if_mtu = ifr->ifr_mtu; 2388 ti_init(sc); 2389 } 2390 break; 2391 case SIOCSIFFLAGS: 2392 if (ifp->if_flags & IFF_UP) { 2393 /* 2394 * If only the state of the PROMISC flag changed, 2395 * then just use the 'set promisc mode' command 2396 * instead of reinitializing the entire NIC. Doing 2397 * a full re-init means reloading the firmware and 2398 * waiting for it to start up, which may take a 2399 * second or two. 2400 */ 2401 if (ifp->if_flags & IFF_RUNNING && 2402 ifp->if_flags & IFF_PROMISC && 2403 !(sc->ti_if_flags & IFF_PROMISC)) { 2404 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2405 TI_CMD_CODE_PROMISC_ENB, 0); 2406 } else if (ifp->if_flags & IFF_RUNNING && 2407 !(ifp->if_flags & IFF_PROMISC) && 2408 sc->ti_if_flags & IFF_PROMISC) { 2409 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2410 TI_CMD_CODE_PROMISC_DIS, 0); 2411 } else 2412 ti_init(sc); 2413 } else { 2414 if (ifp->if_flags & IFF_RUNNING) { 2415 ti_stop(sc); 2416 } 2417 } 2418 sc->ti_if_flags = ifp->if_flags; 2419 error = 0; 2420 break; 2421 case SIOCADDMULTI: 2422 case SIOCDELMULTI: 2423 if (ifp->if_flags & IFF_RUNNING) { 2424 ti_setmulti(sc); 2425 error = 0; 2426 } 2427 break; 2428 case SIOCSIFMEDIA: 2429 case SIOCGIFMEDIA: 2430 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2431 break; 2432 case SIOCSIFCAP: 2433 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2434 if (mask & IFCAP_HWCSUM) { 2435 if (IFCAP_HWCSUM & ifp->if_capenable) 2436 ifp->if_capenable &= ~IFCAP_HWCSUM; 2437 else 2438 ifp->if_capenable |= IFCAP_HWCSUM; 2439 if (ifp->if_flags & IFF_RUNNING) 2440 ti_init(sc); 2441 } 2442 error = 0; 2443 break; 2444 default: 2445 error = EINVAL; 2446 break; 2447 } 2448 2449 (void)splx(s); 2450 2451 return(error); 2452 } 2453 2454 static void ti_watchdog(ifp) 2455 struct ifnet *ifp; 2456 { 2457 struct ti_softc *sc; 2458 2459 sc = ifp->if_softc; 2460 2461 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2462 ti_stop(sc); 2463 ti_init(sc); 2464 2465 ifp->if_oerrors++; 2466 2467 return; 2468 } 2469 2470 /* 2471 * Stop the adapter and free any mbufs allocated to the 2472 * RX and TX lists. 2473 */ 2474 static void ti_stop(sc) 2475 struct ti_softc *sc; 2476 { 2477 struct ifnet *ifp; 2478 struct ti_cmd_desc cmd; 2479 2480 ifp = &sc->arpcom.ac_if; 2481 2482 /* Disable host interrupts. */ 2483 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2484 /* 2485 * Tell firmware we're shutting down. 2486 */ 2487 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2488 2489 /* Halt and reinitialize. */ 2490 ti_chipinit(sc); 2491 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2492 ti_chipinit(sc); 2493 2494 /* Free the RX lists. */ 2495 ti_free_rx_ring_std(sc); 2496 2497 /* Free jumbo RX list. */ 2498 ti_free_rx_ring_jumbo(sc); 2499 2500 /* Free mini RX list. */ 2501 ti_free_rx_ring_mini(sc); 2502 2503 /* Free TX buffers. */ 2504 ti_free_tx_ring(sc); 2505 2506 sc->ti_ev_prodidx.ti_idx = 0; 2507 sc->ti_return_prodidx.ti_idx = 0; 2508 sc->ti_tx_considx.ti_idx = 0; 2509 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2510 2511 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2512 2513 return; 2514 } 2515 2516 /* 2517 * Stop all chip I/O so that the kernel's probe routines don't 2518 * get confused by errant DMAs when rebooting. 2519 */ 2520 static void ti_shutdown(dev) 2521 device_t dev; 2522 { 2523 struct ti_softc *sc; 2524 2525 sc = device_get_softc(dev); 2526 2527 ti_chipinit(sc); 2528 2529 return; 2530 } 2531