1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.20 2005/06/06 23:12:07 okumoto Exp $ 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/thread2.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/vlan/if_vlan_var.h> 52 53 #include <net/bpf.h> 54 55 #include <vm/vm.h> /* for vtophys */ 56 #include <vm/pmap.h> /* for vtophys */ 57 #include <machine/clock.h> /* for DELAY */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus_pio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include "../mii_layer/mii.h" 66 #include "../mii_layer/miivar.h" 67 68 #include <bus/pci/pcireg.h> 69 #include <bus/pci/pcivar.h> 70 71 /* "controller miibus0" required. See GENERIC if you get errors here. */ 72 #include "miibus_if.h" 73 74 #define STE_USEIOSPACE 75 76 #include "if_stereg.h" 77 78 /* 79 * Various supported device vendors/types and their names. 80 */ 81 static struct ste_type ste_devs[] = { 82 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 83 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 84 { 0, 0, NULL } 85 }; 86 87 static int ste_probe (device_t); 88 static int ste_attach (device_t); 89 static int ste_detach (device_t); 90 static void ste_init (void *); 91 static void ste_intr (void *); 92 static void ste_rxeof (struct ste_softc *); 93 static void ste_txeoc (struct ste_softc *); 94 static void ste_txeof (struct ste_softc *); 95 static void ste_stats_update (void *); 96 static void ste_stop (struct ste_softc *); 97 static void ste_reset (struct ste_softc *); 98 static int ste_ioctl (struct ifnet *, u_long, caddr_t, 99 struct ucred *); 100 static int ste_encap (struct ste_softc *, struct ste_chain *, 101 struct mbuf *); 102 static void ste_start (struct ifnet *); 103 static void ste_watchdog (struct ifnet *); 104 static void ste_shutdown (device_t); 105 static int ste_newbuf (struct ste_softc *, 106 struct ste_chain_onefrag *, 107 struct mbuf *); 108 static int ste_ifmedia_upd (struct ifnet *); 109 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 111 static void ste_mii_sync (struct ste_softc *); 112 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 113 static int ste_mii_readreg (struct ste_softc *, 114 struct ste_mii_frame *); 115 static int ste_mii_writereg (struct ste_softc *, 116 struct ste_mii_frame *); 117 static int ste_miibus_readreg (device_t, int, int); 118 static int ste_miibus_writereg (device_t, int, int, int); 119 static void ste_miibus_statchg (device_t); 120 121 static int ste_eeprom_wait (struct ste_softc *); 122 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 123 int, int); 124 static void ste_wait (struct ste_softc *); 125 static u_int8_t ste_calchash (caddr_t); 126 static void ste_setmulti (struct ste_softc *); 127 static int ste_init_rx_list (struct ste_softc *); 128 static void ste_init_tx_list (struct ste_softc *); 129 130 #ifdef STE_USEIOSPACE 131 #define STE_RES SYS_RES_IOPORT 132 #define STE_RID STE_PCI_LOIO 133 #else 134 #define STE_RES SYS_RES_MEMORY 135 #define STE_RID STE_PCI_LOMEM 136 #endif 137 138 static device_method_t ste_methods[] = { 139 /* Device interface */ 140 DEVMETHOD(device_probe, ste_probe), 141 DEVMETHOD(device_attach, ste_attach), 142 DEVMETHOD(device_detach, ste_detach), 143 DEVMETHOD(device_shutdown, ste_shutdown), 144 145 /* bus interface */ 146 DEVMETHOD(bus_print_child, bus_generic_print_child), 147 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 148 149 /* MII interface */ 150 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 151 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 152 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 153 154 { 0, 0 } 155 }; 156 157 static driver_t ste_driver = { 158 "ste", 159 ste_methods, 160 sizeof(struct ste_softc) 161 }; 162 163 static devclass_t ste_devclass; 164 165 DECLARE_DUMMY_MODULE(if_ste); 166 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 167 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 168 169 #define STE_SETBIT4(sc, reg, x) \ 170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 171 172 #define STE_CLRBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 174 175 #define STE_SETBIT2(sc, reg, x) \ 176 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 177 178 #define STE_CLRBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 180 181 #define STE_SETBIT1(sc, reg, x) \ 182 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 183 184 #define STE_CLRBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 186 187 188 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 189 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 190 191 /* 192 * Sync the PHYs by setting data bit and strobing the clock 32 times. 193 */ 194 static void ste_mii_sync(sc) 195 struct ste_softc *sc; 196 { 197 int i; 198 199 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 200 201 for (i = 0; i < 32; i++) { 202 MII_SET(STE_PHYCTL_MCLK); 203 DELAY(1); 204 MII_CLR(STE_PHYCTL_MCLK); 205 DELAY(1); 206 } 207 208 return; 209 } 210 211 /* 212 * Clock a series of bits through the MII. 213 */ 214 static void ste_mii_send(sc, bits, cnt) 215 struct ste_softc *sc; 216 u_int32_t bits; 217 int cnt; 218 { 219 int i; 220 221 MII_CLR(STE_PHYCTL_MCLK); 222 223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 224 if (bits & i) { 225 MII_SET(STE_PHYCTL_MDATA); 226 } else { 227 MII_CLR(STE_PHYCTL_MDATA); 228 } 229 DELAY(1); 230 MII_CLR(STE_PHYCTL_MCLK); 231 DELAY(1); 232 MII_SET(STE_PHYCTL_MCLK); 233 } 234 } 235 236 /* 237 * Read an PHY register through the MII. 238 */ 239 static int ste_mii_readreg(sc, frame) 240 struct ste_softc *sc; 241 struct ste_mii_frame *frame; 242 243 { 244 int i, ack; 245 246 crit_enter(); 247 248 /* 249 * Set up frame for RX. 250 */ 251 frame->mii_stdelim = STE_MII_STARTDELIM; 252 frame->mii_opcode = STE_MII_READOP; 253 frame->mii_turnaround = 0; 254 frame->mii_data = 0; 255 256 CSR_WRITE_2(sc, STE_PHYCTL, 0); 257 /* 258 * Turn on data xmit. 259 */ 260 MII_SET(STE_PHYCTL_MDIR); 261 262 ste_mii_sync(sc); 263 264 /* 265 * Send command/address info. 266 */ 267 ste_mii_send(sc, frame->mii_stdelim, 2); 268 ste_mii_send(sc, frame->mii_opcode, 2); 269 ste_mii_send(sc, frame->mii_phyaddr, 5); 270 ste_mii_send(sc, frame->mii_regaddr, 5); 271 272 /* Turn off xmit. */ 273 MII_CLR(STE_PHYCTL_MDIR); 274 275 /* Idle bit */ 276 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 277 DELAY(1); 278 MII_SET(STE_PHYCTL_MCLK); 279 DELAY(1); 280 281 /* Check for ack */ 282 MII_CLR(STE_PHYCTL_MCLK); 283 DELAY(1); 284 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 285 MII_SET(STE_PHYCTL_MCLK); 286 DELAY(1); 287 288 /* 289 * Now try reading data bits. If the ack failed, we still 290 * need to clock through 16 cycles to keep the PHY(s) in sync. 291 */ 292 if (ack) { 293 for(i = 0; i < 16; i++) { 294 MII_CLR(STE_PHYCTL_MCLK); 295 DELAY(1); 296 MII_SET(STE_PHYCTL_MCLK); 297 DELAY(1); 298 } 299 goto fail; 300 } 301 302 for (i = 0x8000; i; i >>= 1) { 303 MII_CLR(STE_PHYCTL_MCLK); 304 DELAY(1); 305 if (!ack) { 306 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 307 frame->mii_data |= i; 308 DELAY(1); 309 } 310 MII_SET(STE_PHYCTL_MCLK); 311 DELAY(1); 312 } 313 314 fail: 315 316 MII_CLR(STE_PHYCTL_MCLK); 317 DELAY(1); 318 MII_SET(STE_PHYCTL_MCLK); 319 DELAY(1); 320 321 crit_exit(); 322 323 if (ack) 324 return(1); 325 return(0); 326 } 327 328 /* 329 * Write to a PHY register through the MII. 330 */ 331 static int ste_mii_writereg(sc, frame) 332 struct ste_softc *sc; 333 struct ste_mii_frame *frame; 334 335 { 336 337 crit_enter(); 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 crit_exit(); 372 373 return(0); 374 } 375 376 static int ste_miibus_readreg(dev, phy, reg) 377 device_t dev; 378 int phy, reg; 379 { 380 struct ste_softc *sc; 381 struct ste_mii_frame frame; 382 383 sc = device_get_softc(dev); 384 385 if ( sc->ste_one_phy && phy != 0 ) 386 return (0); 387 388 bzero((char *)&frame, sizeof(frame)); 389 390 frame.mii_phyaddr = phy; 391 frame.mii_regaddr = reg; 392 ste_mii_readreg(sc, &frame); 393 394 return(frame.mii_data); 395 } 396 397 static int ste_miibus_writereg(dev, phy, reg, data) 398 device_t dev; 399 int phy, reg, data; 400 { 401 struct ste_softc *sc; 402 struct ste_mii_frame frame; 403 404 sc = device_get_softc(dev); 405 bzero((char *)&frame, sizeof(frame)); 406 407 frame.mii_phyaddr = phy; 408 frame.mii_regaddr = reg; 409 frame.mii_data = data; 410 411 ste_mii_writereg(sc, &frame); 412 413 return(0); 414 } 415 416 static void ste_miibus_statchg(dev) 417 device_t dev; 418 { 419 struct ste_softc *sc; 420 struct mii_data *mii; 421 int i; 422 423 sc = device_get_softc(dev); 424 mii = device_get_softc(sc->ste_miibus); 425 426 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 427 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 428 } else { 429 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 430 } 431 432 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 433 STE_ASICCTL_TX_RESET); 434 for (i = 0; i < STE_TIMEOUT; i++) { 435 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 436 break; 437 } 438 if (i == STE_TIMEOUT) 439 printf("ste%d: rx reset never completed\n", sc->ste_unit); 440 441 return; 442 } 443 444 static int ste_ifmedia_upd(ifp) 445 struct ifnet *ifp; 446 { 447 struct ste_softc *sc; 448 struct mii_data *mii; 449 450 sc = ifp->if_softc; 451 mii = device_get_softc(sc->ste_miibus); 452 sc->ste_link = 0; 453 if (mii->mii_instance) { 454 struct mii_softc *miisc; 455 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 456 miisc = LIST_NEXT(miisc, mii_list)) 457 mii_phy_reset(miisc); 458 } 459 mii_mediachg(mii); 460 461 return(0); 462 } 463 464 static void ste_ifmedia_sts(ifp, ifmr) 465 struct ifnet *ifp; 466 struct ifmediareq *ifmr; 467 { 468 struct ste_softc *sc; 469 struct mii_data *mii; 470 471 sc = ifp->if_softc; 472 mii = device_get_softc(sc->ste_miibus); 473 474 mii_pollstat(mii); 475 ifmr->ifm_active = mii->mii_media_active; 476 ifmr->ifm_status = mii->mii_media_status; 477 478 return; 479 } 480 481 static void ste_wait(sc) 482 struct ste_softc *sc; 483 { 484 int i; 485 486 for (i = 0; i < STE_TIMEOUT; i++) { 487 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 488 break; 489 } 490 491 if (i == STE_TIMEOUT) 492 printf("ste%d: command never completed!\n", sc->ste_unit); 493 494 return; 495 } 496 497 /* 498 * The EEPROM is slow: give it time to come ready after issuing 499 * it a command. 500 */ 501 static int ste_eeprom_wait(sc) 502 struct ste_softc *sc; 503 { 504 int i; 505 506 DELAY(1000); 507 508 for (i = 0; i < 100; i++) { 509 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 510 DELAY(1000); 511 else 512 break; 513 } 514 515 if (i == 100) { 516 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 517 return(1); 518 } 519 520 return(0); 521 } 522 523 /* 524 * Read a sequence of words from the EEPROM. Note that ethernet address 525 * data is stored in the EEPROM in network byte order. 526 */ 527 static int ste_read_eeprom(sc, dest, off, cnt, swap) 528 struct ste_softc *sc; 529 caddr_t dest; 530 int off; 531 int cnt; 532 int swap; 533 { 534 int err = 0, i; 535 u_int16_t word = 0, *ptr; 536 537 if (ste_eeprom_wait(sc)) 538 return(1); 539 540 for (i = 0; i < cnt; i++) { 541 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 542 err = ste_eeprom_wait(sc); 543 if (err) 544 break; 545 word = CSR_READ_2(sc, STE_EEPROM_DATA); 546 ptr = (u_int16_t *)(dest + (i * 2)); 547 if (swap) 548 *ptr = ntohs(word); 549 else 550 *ptr = word; 551 } 552 553 return(err ? 1 : 0); 554 } 555 556 static u_int8_t ste_calchash(addr) 557 caddr_t addr; 558 { 559 560 u_int32_t crc, carry; 561 int i, j; 562 u_int8_t c; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xFFFFFFFF; /* initial value */ 566 567 for (i = 0; i < 6; i++) { 568 c = *(addr + i); 569 for (j = 0; j < 8; j++) { 570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 571 crc <<= 1; 572 c >>= 1; 573 if (carry) 574 crc = (crc ^ 0x04c11db6) | carry; 575 } 576 } 577 578 /* return the filter bit position */ 579 return(crc & 0x0000003F); 580 } 581 582 static void ste_setmulti(sc) 583 struct ste_softc *sc; 584 { 585 struct ifnet *ifp; 586 int h = 0; 587 u_int32_t hashes[2] = { 0, 0 }; 588 struct ifmultiaddr *ifma; 589 590 ifp = &sc->arpcom.ac_if; 591 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 592 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 593 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 594 return; 595 } 596 597 /* first, zot all the existing hash bits */ 598 CSR_WRITE_2(sc, STE_MAR0, 0); 599 CSR_WRITE_2(sc, STE_MAR1, 0); 600 CSR_WRITE_2(sc, STE_MAR2, 0); 601 CSR_WRITE_2(sc, STE_MAR3, 0); 602 603 /* now program new ones */ 604 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 605 ifma = ifma->ifma_link.le_next) { 606 if (ifma->ifma_addr->sa_family != AF_LINK) 607 continue; 608 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 609 if (h < 32) 610 hashes[0] |= (1 << h); 611 else 612 hashes[1] |= (1 << (h - 32)); 613 } 614 615 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 617 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 619 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 620 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 621 622 return; 623 } 624 625 static void ste_intr(xsc) 626 void *xsc; 627 { 628 struct ste_softc *sc; 629 struct ifnet *ifp; 630 u_int16_t status; 631 632 sc = xsc; 633 ifp = &sc->arpcom.ac_if; 634 635 /* See if this is really our interrupt. */ 636 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 637 return; 638 639 for (;;) { 640 status = CSR_READ_2(sc, STE_ISR_ACK); 641 642 if (!(status & STE_INTRS)) 643 break; 644 645 if (status & STE_ISR_RX_DMADONE) 646 ste_rxeof(sc); 647 648 if (status & STE_ISR_TX_DMADONE) 649 ste_txeof(sc); 650 651 if (status & STE_ISR_TX_DONE) 652 ste_txeoc(sc); 653 654 if (status & STE_ISR_STATS_OFLOW) { 655 callout_stop(&sc->ste_stat_timer); 656 ste_stats_update(sc); 657 } 658 659 if (status & STE_ISR_LINKEVENT) 660 mii_pollstat(device_get_softc(sc->ste_miibus)); 661 662 if (status & STE_ISR_HOSTERR) { 663 ste_reset(sc); 664 ste_init(sc); 665 } 666 } 667 668 /* Re-enable interrupts */ 669 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 670 671 if (!ifq_is_empty(&ifp->if_snd)) 672 ste_start(ifp); 673 674 return; 675 } 676 677 /* 678 * A frame has been uploaded: pass the resulting mbuf chain up to 679 * the higher level protocols. 680 */ 681 static void ste_rxeof(sc) 682 struct ste_softc *sc; 683 { 684 struct mbuf *m; 685 struct ifnet *ifp; 686 struct ste_chain_onefrag *cur_rx; 687 int total_len = 0, count=0; 688 u_int32_t rxstat; 689 690 ifp = &sc->arpcom.ac_if; 691 692 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 693 & STE_RXSTAT_DMADONE) { 694 if ((STE_RX_LIST_CNT - count) < 3) { 695 break; 696 } 697 698 cur_rx = sc->ste_cdata.ste_rx_head; 699 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 700 701 /* 702 * If an error occurs, update stats, clear the 703 * status word and leave the mbuf cluster in place: 704 * it should simply get re-used next time this descriptor 705 * comes up in the ring. 706 */ 707 if (rxstat & STE_RXSTAT_FRAME_ERR) { 708 ifp->if_ierrors++; 709 cur_rx->ste_ptr->ste_status = 0; 710 continue; 711 } 712 713 /* 714 * If there error bit was not set, the upload complete 715 * bit should be set which means we have a valid packet. 716 * If not, something truly strange has happened. 717 */ 718 if (!(rxstat & STE_RXSTAT_DMADONE)) { 719 printf("ste%d: bad receive status -- packet dropped", 720 sc->ste_unit); 721 ifp->if_ierrors++; 722 cur_rx->ste_ptr->ste_status = 0; 723 continue; 724 } 725 726 /* No errors; receive the packet. */ 727 m = cur_rx->ste_mbuf; 728 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 729 730 /* 731 * Try to conjure up a new mbuf cluster. If that 732 * fails, it means we have an out of memory condition and 733 * should leave the buffer in place and continue. This will 734 * result in a lost packet, but there's little else we 735 * can do in this situation. 736 */ 737 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 738 ifp->if_ierrors++; 739 cur_rx->ste_ptr->ste_status = 0; 740 continue; 741 } 742 743 ifp->if_ipackets++; 744 m->m_pkthdr.rcvif = ifp; 745 m->m_pkthdr.len = m->m_len = total_len; 746 747 (*ifp->if_input)(ifp, m); 748 749 cur_rx->ste_ptr->ste_status = 0; 750 count++; 751 } 752 753 return; 754 } 755 756 static void ste_txeoc(sc) 757 struct ste_softc *sc; 758 { 759 u_int8_t txstat; 760 struct ifnet *ifp; 761 762 ifp = &sc->arpcom.ac_if; 763 764 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 765 STE_TXSTATUS_TXDONE) { 766 if (txstat & STE_TXSTATUS_UNDERRUN || 767 txstat & STE_TXSTATUS_EXCESSCOLLS || 768 txstat & STE_TXSTATUS_RECLAIMERR) { 769 ifp->if_oerrors++; 770 printf("ste%d: transmission error: %x\n", 771 sc->ste_unit, txstat); 772 773 ste_reset(sc); 774 ste_init(sc); 775 776 if (txstat & STE_TXSTATUS_UNDERRUN && 777 sc->ste_tx_thresh < STE_PACKET_SIZE) { 778 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 779 printf("ste%d: tx underrun, increasing tx" 780 " start threshold to %d bytes\n", 781 sc->ste_unit, sc->ste_tx_thresh); 782 } 783 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 784 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 785 (STE_PACKET_SIZE >> 4)); 786 } 787 ste_init(sc); 788 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 789 } 790 791 return; 792 } 793 794 static void ste_txeof(sc) 795 struct ste_softc *sc; 796 { 797 struct ste_chain *cur_tx = NULL; 798 struct ifnet *ifp; 799 int idx; 800 801 ifp = &sc->arpcom.ac_if; 802 803 idx = sc->ste_cdata.ste_tx_cons; 804 while(idx != sc->ste_cdata.ste_tx_prod) { 805 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 806 807 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 808 break; 809 810 if (cur_tx->ste_mbuf != NULL) { 811 m_freem(cur_tx->ste_mbuf); 812 cur_tx->ste_mbuf = NULL; 813 } 814 815 ifp->if_opackets++; 816 817 sc->ste_cdata.ste_tx_cnt--; 818 STE_INC(idx, STE_TX_LIST_CNT); 819 ifp->if_timer = 0; 820 } 821 822 sc->ste_cdata.ste_tx_cons = idx; 823 824 if (cur_tx != NULL) 825 ifp->if_flags &= ~IFF_OACTIVE; 826 827 return; 828 } 829 830 static void ste_stats_update(xsc) 831 void *xsc; 832 { 833 struct ste_softc *sc; 834 struct ifnet *ifp; 835 struct mii_data *mii; 836 837 crit_enter(); 838 839 sc = xsc; 840 ifp = &sc->arpcom.ac_if; 841 mii = device_get_softc(sc->ste_miibus); 842 843 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 844 + CSR_READ_1(sc, STE_MULTI_COLLS) 845 + CSR_READ_1(sc, STE_SINGLE_COLLS); 846 847 if (!sc->ste_link) { 848 mii_pollstat(mii); 849 if (mii->mii_media_status & IFM_ACTIVE && 850 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 851 sc->ste_link++; 852 /* 853 * we don't get a call-back on re-init so do it 854 * otherwise we get stuck in the wrong link state 855 */ 856 ste_miibus_statchg(sc->ste_dev); 857 if (!ifq_is_empty(&ifp->if_snd)) 858 ste_start(ifp); 859 } 860 } 861 862 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 863 crit_exit(); 864 865 return; 866 } 867 868 869 /* 870 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 871 * IDs against our list and return a device name if we find a match. 872 */ 873 static int ste_probe(dev) 874 device_t dev; 875 { 876 struct ste_type *t; 877 878 t = ste_devs; 879 880 while(t->ste_name != NULL) { 881 if ((pci_get_vendor(dev) == t->ste_vid) && 882 (pci_get_device(dev) == t->ste_did)) { 883 device_set_desc(dev, t->ste_name); 884 return(0); 885 } 886 t++; 887 } 888 889 return(ENXIO); 890 } 891 892 /* 893 * Attach the interface. Allocate softc structures, do ifmedia 894 * setup and ethernet/BPF attach. 895 */ 896 static int ste_attach(dev) 897 device_t dev; 898 { 899 u_int32_t command; 900 struct ste_softc *sc; 901 struct ifnet *ifp; 902 int unit, error = 0, rid; 903 904 crit_enter(); 905 906 sc = device_get_softc(dev); 907 unit = device_get_unit(dev); 908 bzero(sc, sizeof(struct ste_softc)); 909 sc->ste_dev = dev; 910 911 /* 912 * Only use one PHY since this chip reports multiple 913 * Note on the DFE-550 the PHY is at 1 on the DFE-580 914 * it is at 0 & 1. It is rev 0x12. 915 */ 916 if (pci_get_vendor(dev) == DL_VENDORID && 917 pci_get_device(dev) == DL_DEVICEID_550TX && 918 pci_get_revid(dev) == 0x12 ) 919 sc->ste_one_phy = 1; 920 921 /* 922 * Handle power management nonsense. 923 */ 924 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 925 if (command == 0x01) { 926 927 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 928 if (command & STE_PSTATE_MASK) { 929 u_int32_t iobase, membase, irq; 930 931 /* Save important PCI config data. */ 932 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 933 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 934 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 935 936 /* Reset the power state. */ 937 printf("ste%d: chip is in D%d power mode " 938 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 939 command &= 0xFFFFFFFC; 940 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 941 942 /* Restore PCI config data. */ 943 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 944 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 945 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 946 } 947 } 948 949 /* 950 * Map control/status registers. 951 */ 952 command = pci_read_config(dev, PCIR_COMMAND, 4); 953 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 954 pci_write_config(dev, PCIR_COMMAND, command, 4); 955 command = pci_read_config(dev, PCIR_COMMAND, 4); 956 957 #ifdef STE_USEIOSPACE 958 if (!(command & PCIM_CMD_PORTEN)) { 959 printf("ste%d: failed to enable I/O ports!\n", unit); 960 error = ENXIO; 961 goto fail; 962 } 963 #else 964 if (!(command & PCIM_CMD_MEMEN)) { 965 printf("ste%d: failed to enable memory mapping!\n", unit); 966 error = ENXIO; 967 goto fail; 968 } 969 #endif 970 971 rid = STE_RID; 972 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 973 974 if (sc->ste_res == NULL) { 975 printf ("ste%d: couldn't map ports/memory\n", unit); 976 error = ENXIO; 977 goto fail; 978 } 979 980 sc->ste_btag = rman_get_bustag(sc->ste_res); 981 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 982 983 rid = 0; 984 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 985 RF_SHAREABLE | RF_ACTIVE); 986 987 if (sc->ste_irq == NULL) { 988 printf("ste%d: couldn't map interrupt\n", unit); 989 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 990 error = ENXIO; 991 goto fail; 992 } 993 994 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 995 ste_intr, sc, &sc->ste_intrhand, NULL); 996 997 if (error) { 998 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 999 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1000 printf("ste%d: couldn't set up irq\n", unit); 1001 goto fail; 1002 } 1003 1004 callout_init(&sc->ste_stat_timer); 1005 1006 /* Reset the adapter. */ 1007 ste_reset(sc); 1008 1009 /* 1010 * Get station address from the EEPROM. 1011 */ 1012 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1013 STE_EEADDR_NODE0, 3, 0)) { 1014 printf("ste%d: failed to read station address\n", unit); 1015 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1016 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1017 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1018 error = ENXIO;; 1019 goto fail; 1020 } 1021 1022 sc->ste_unit = unit; 1023 1024 /* Allocate the descriptor queues. */ 1025 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1026 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1027 1028 if (sc->ste_ldata == NULL) { 1029 printf("ste%d: no memory for list buffers!\n", unit); 1030 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1031 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1032 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1033 error = ENXIO; 1034 goto fail; 1035 } 1036 1037 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1038 1039 /* Do MII setup. */ 1040 if (mii_phy_probe(dev, &sc->ste_miibus, 1041 ste_ifmedia_upd, ste_ifmedia_sts)) { 1042 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1043 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1044 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1045 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1046 contigfree(sc->ste_ldata, 1047 sizeof(struct ste_list_data), M_DEVBUF); 1048 error = ENXIO; 1049 goto fail; 1050 } 1051 1052 ifp = &sc->arpcom.ac_if; 1053 ifp->if_softc = sc; 1054 if_initname(ifp, "ste", unit); 1055 ifp->if_mtu = ETHERMTU; 1056 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1057 ifp->if_ioctl = ste_ioctl; 1058 ifp->if_start = ste_start; 1059 ifp->if_watchdog = ste_watchdog; 1060 ifp->if_init = ste_init; 1061 ifp->if_baudrate = 10000000; 1062 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1063 ifq_set_ready(&ifp->if_snd); 1064 1065 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1066 1067 /* 1068 * Call MI attach routine. 1069 */ 1070 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1071 1072 /* 1073 * Tell the upper layer(s) we support long frames. 1074 */ 1075 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1076 1077 fail: 1078 crit_exit(); 1079 return(error); 1080 } 1081 1082 static int ste_detach(dev) 1083 device_t dev; 1084 { 1085 struct ste_softc *sc; 1086 struct ifnet *ifp; 1087 1088 crit_enter(); 1089 1090 sc = device_get_softc(dev); 1091 ifp = &sc->arpcom.ac_if; 1092 1093 ste_stop(sc); 1094 ether_ifdetach(ifp); 1095 1096 bus_generic_detach(dev); 1097 device_delete_child(dev, sc->ste_miibus); 1098 1099 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1100 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1101 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1102 1103 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1104 1105 crit_exit(); 1106 1107 return(0); 1108 } 1109 1110 static int ste_newbuf(sc, c, m) 1111 struct ste_softc *sc; 1112 struct ste_chain_onefrag *c; 1113 struct mbuf *m; 1114 { 1115 struct mbuf *m_new = NULL; 1116 1117 if (m == NULL) { 1118 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1119 if (m_new == NULL) 1120 return(ENOBUFS); 1121 MCLGET(m_new, MB_DONTWAIT); 1122 if (!(m_new->m_flags & M_EXT)) { 1123 m_freem(m_new); 1124 return(ENOBUFS); 1125 } 1126 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1127 } else { 1128 m_new = m; 1129 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1130 m_new->m_data = m_new->m_ext.ext_buf; 1131 } 1132 1133 m_adj(m_new, ETHER_ALIGN); 1134 1135 c->ste_mbuf = m_new; 1136 c->ste_ptr->ste_status = 0; 1137 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1138 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1139 1140 return(0); 1141 } 1142 1143 static int ste_init_rx_list(sc) 1144 struct ste_softc *sc; 1145 { 1146 struct ste_chain_data *cd; 1147 struct ste_list_data *ld; 1148 int i; 1149 1150 cd = &sc->ste_cdata; 1151 ld = sc->ste_ldata; 1152 1153 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1154 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1155 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1156 return(ENOBUFS); 1157 if (i == (STE_RX_LIST_CNT - 1)) { 1158 cd->ste_rx_chain[i].ste_next = 1159 &cd->ste_rx_chain[0]; 1160 ld->ste_rx_list[i].ste_next = 1161 vtophys(&ld->ste_rx_list[0]); 1162 } else { 1163 cd->ste_rx_chain[i].ste_next = 1164 &cd->ste_rx_chain[i + 1]; 1165 ld->ste_rx_list[i].ste_next = 1166 vtophys(&ld->ste_rx_list[i + 1]); 1167 } 1168 ld->ste_rx_list[i].ste_status = 0; 1169 } 1170 1171 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1172 1173 return(0); 1174 } 1175 1176 static void ste_init_tx_list(sc) 1177 struct ste_softc *sc; 1178 { 1179 struct ste_chain_data *cd; 1180 struct ste_list_data *ld; 1181 int i; 1182 1183 cd = &sc->ste_cdata; 1184 ld = sc->ste_ldata; 1185 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1186 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1187 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1188 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1189 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1190 if (i == (STE_TX_LIST_CNT - 1)) 1191 cd->ste_tx_chain[i].ste_next = 1192 &cd->ste_tx_chain[0]; 1193 else 1194 cd->ste_tx_chain[i].ste_next = 1195 &cd->ste_tx_chain[i + 1]; 1196 if (i == 0) 1197 cd->ste_tx_chain[i].ste_prev = 1198 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1199 else 1200 cd->ste_tx_chain[i].ste_prev = 1201 &cd->ste_tx_chain[i - 1]; 1202 } 1203 1204 cd->ste_tx_prod = 0; 1205 cd->ste_tx_cons = 0; 1206 cd->ste_tx_cnt = 0; 1207 1208 return; 1209 } 1210 1211 static void ste_init(xsc) 1212 void *xsc; 1213 { 1214 struct ste_softc *sc; 1215 int i; 1216 struct ifnet *ifp; 1217 struct mii_data *mii; 1218 1219 crit_enter(); 1220 1221 sc = xsc; 1222 ifp = &sc->arpcom.ac_if; 1223 mii = device_get_softc(sc->ste_miibus); 1224 1225 ste_stop(sc); 1226 1227 /* Init our MAC address */ 1228 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1229 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1230 } 1231 1232 /* Init RX list */ 1233 if (ste_init_rx_list(sc) == ENOBUFS) { 1234 printf("ste%d: initialization failed: no " 1235 "memory for RX buffers\n", sc->ste_unit); 1236 ste_stop(sc); 1237 crit_exit(); 1238 return; 1239 } 1240 1241 /* Set RX polling interval */ 1242 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1243 1244 /* Init TX descriptors */ 1245 ste_init_tx_list(sc); 1246 1247 /* Set the TX freethresh value */ 1248 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1249 1250 /* Set the TX start threshold for best performance. */ 1251 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1252 1253 /* Set the TX reclaim threshold. */ 1254 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1255 1256 /* Set up the RX filter. */ 1257 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1258 1259 /* If we want promiscuous mode, set the allframes bit. */ 1260 if (ifp->if_flags & IFF_PROMISC) { 1261 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1262 } else { 1263 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1264 } 1265 1266 /* Set capture broadcast bit to accept broadcast frames. */ 1267 if (ifp->if_flags & IFF_BROADCAST) { 1268 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1269 } else { 1270 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1271 } 1272 1273 ste_setmulti(sc); 1274 1275 /* Load the address of the RX list. */ 1276 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1277 ste_wait(sc); 1278 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1279 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1280 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1281 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1282 1283 /* Set TX polling interval (defer until we TX first packet */ 1284 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1285 1286 /* Load address of the TX list */ 1287 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1288 ste_wait(sc); 1289 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1290 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1291 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1292 ste_wait(sc); 1293 sc->ste_tx_prev_idx=-1; 1294 1295 /* Enable receiver and transmitter */ 1296 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1297 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1298 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1299 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1300 1301 /* Enable stats counters. */ 1302 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1303 1304 /* Enable interrupts. */ 1305 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1306 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1307 1308 /* Accept VLAN length packets */ 1309 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1310 1311 ste_ifmedia_upd(ifp); 1312 1313 ifp->if_flags |= IFF_RUNNING; 1314 ifp->if_flags &= ~IFF_OACTIVE; 1315 1316 crit_exit(); 1317 1318 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 1319 1320 return; 1321 } 1322 1323 static void ste_stop(sc) 1324 struct ste_softc *sc; 1325 { 1326 int i; 1327 struct ifnet *ifp; 1328 1329 ifp = &sc->arpcom.ac_if; 1330 1331 callout_stop(&sc->ste_stat_timer); 1332 1333 CSR_WRITE_2(sc, STE_IMR, 0); 1334 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1335 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1336 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1337 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1338 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1339 ste_wait(sc); 1340 /* 1341 * Try really hard to stop the RX engine or under heavy RX 1342 * data chip will write into de-allocated memory. 1343 */ 1344 ste_reset(sc); 1345 1346 sc->ste_link = 0; 1347 1348 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1349 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1350 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1351 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1352 } 1353 } 1354 1355 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1356 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1357 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1358 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1359 } 1360 } 1361 1362 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1363 1364 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1365 1366 return; 1367 } 1368 1369 static void ste_reset(sc) 1370 struct ste_softc *sc; 1371 { 1372 int i; 1373 1374 STE_SETBIT4(sc, STE_ASICCTL, 1375 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1376 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1377 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1378 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1379 STE_ASICCTL_EXTRESET_RESET); 1380 1381 DELAY(100000); 1382 1383 for (i = 0; i < STE_TIMEOUT; i++) { 1384 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1385 break; 1386 } 1387 1388 if (i == STE_TIMEOUT) 1389 printf("ste%d: global reset never completed\n", sc->ste_unit); 1390 1391 return; 1392 } 1393 1394 static int ste_ioctl(ifp, command, data, cr) 1395 struct ifnet *ifp; 1396 u_long command; 1397 caddr_t data; 1398 struct ucred *cr; 1399 { 1400 struct ste_softc *sc; 1401 struct ifreq *ifr; 1402 struct mii_data *mii; 1403 int error = 0; 1404 1405 crit_enter(); 1406 1407 sc = ifp->if_softc; 1408 ifr = (struct ifreq *)data; 1409 1410 switch(command) { 1411 case SIOCSIFFLAGS: 1412 if (ifp->if_flags & IFF_UP) { 1413 if (ifp->if_flags & IFF_RUNNING && 1414 ifp->if_flags & IFF_PROMISC && 1415 !(sc->ste_if_flags & IFF_PROMISC)) { 1416 STE_SETBIT1(sc, STE_RX_MODE, 1417 STE_RXMODE_PROMISC); 1418 } else if (ifp->if_flags & IFF_RUNNING && 1419 !(ifp->if_flags & IFF_PROMISC) && 1420 sc->ste_if_flags & IFF_PROMISC) { 1421 STE_CLRBIT1(sc, STE_RX_MODE, 1422 STE_RXMODE_PROMISC); 1423 } 1424 if (!(ifp->if_flags & IFF_RUNNING)) { 1425 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1426 ste_init(sc); 1427 } 1428 } else { 1429 if (ifp->if_flags & IFF_RUNNING) 1430 ste_stop(sc); 1431 } 1432 sc->ste_if_flags = ifp->if_flags; 1433 error = 0; 1434 break; 1435 case SIOCADDMULTI: 1436 case SIOCDELMULTI: 1437 ste_setmulti(sc); 1438 error = 0; 1439 break; 1440 case SIOCGIFMEDIA: 1441 case SIOCSIFMEDIA: 1442 mii = device_get_softc(sc->ste_miibus); 1443 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1444 break; 1445 default: 1446 error = ether_ioctl(ifp, command, data); 1447 break; 1448 } 1449 1450 crit_exit(); 1451 1452 return(error); 1453 } 1454 1455 static int ste_encap(sc, c, m_head) 1456 struct ste_softc *sc; 1457 struct ste_chain *c; 1458 struct mbuf *m_head; 1459 { 1460 int frag = 0; 1461 struct ste_frag *f = NULL; 1462 struct mbuf *m; 1463 struct ste_desc *d; 1464 int total_len = 0; 1465 1466 d = c->ste_ptr; 1467 d->ste_ctl = 0; 1468 1469 encap_retry: 1470 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1471 if (m->m_len != 0) { 1472 if (frag == STE_MAXFRAGS) 1473 break; 1474 total_len += m->m_len; 1475 f = &d->ste_frags[frag]; 1476 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1477 f->ste_len = m->m_len; 1478 frag++; 1479 } 1480 } 1481 1482 if (m != NULL) { 1483 struct mbuf *mn; 1484 1485 /* 1486 * We ran out of segments. We have to recopy this 1487 * mbuf chain first. Bail out if we can't get the 1488 * new buffers. Code borrowed from if_fxp.c. 1489 */ 1490 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1491 if (mn == NULL) { 1492 m_freem(m_head); 1493 return ENOMEM; 1494 } 1495 if (m_head->m_pkthdr.len > MHLEN) { 1496 MCLGET(mn, MB_DONTWAIT); 1497 if ((mn->m_flags & M_EXT) == 0) { 1498 m_freem(mn); 1499 m_freem(m_head); 1500 return ENOMEM; 1501 } 1502 } 1503 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1504 mtod(mn, caddr_t)); 1505 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1506 m_freem(m_head); 1507 m_head = mn; 1508 goto encap_retry; 1509 } 1510 1511 c->ste_mbuf = m_head; 1512 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1513 d->ste_ctl = 1; 1514 1515 return(0); 1516 } 1517 1518 static void ste_start(ifp) 1519 struct ifnet *ifp; 1520 { 1521 struct ste_softc *sc; 1522 struct mbuf *m_head = NULL; 1523 struct ste_chain *cur_tx = NULL; 1524 int idx; 1525 1526 sc = ifp->if_softc; 1527 1528 if (!sc->ste_link) 1529 return; 1530 1531 if (ifp->if_flags & IFF_OACTIVE) 1532 return; 1533 1534 idx = sc->ste_cdata.ste_tx_prod; 1535 1536 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1537 1538 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1539 ifp->if_flags |= IFF_OACTIVE; 1540 break; 1541 } 1542 1543 m_head = ifq_dequeue(&ifp->if_snd); 1544 if (m_head == NULL) 1545 break; 1546 1547 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1548 1549 if (ste_encap(sc, cur_tx, m_head) != 0) 1550 break; 1551 1552 cur_tx->ste_ptr->ste_next = 0; 1553 1554 if(sc->ste_tx_prev_idx < 0){ 1555 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1556 /* Load address of the TX list */ 1557 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1558 ste_wait(sc); 1559 1560 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1561 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1562 1563 /* Set TX polling interval to start TX engine */ 1564 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1565 1566 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1567 ste_wait(sc); 1568 }else{ 1569 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1570 sc->ste_cdata.ste_tx_chain[ 1571 sc->ste_tx_prev_idx].ste_ptr->ste_next 1572 = cur_tx->ste_phys; 1573 } 1574 1575 sc->ste_tx_prev_idx=idx; 1576 1577 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1578 1579 STE_INC(idx, STE_TX_LIST_CNT); 1580 sc->ste_cdata.ste_tx_cnt++; 1581 ifp->if_timer = 5; 1582 sc->ste_cdata.ste_tx_prod = idx; 1583 } 1584 1585 return; 1586 } 1587 1588 static void ste_watchdog(ifp) 1589 struct ifnet *ifp; 1590 { 1591 struct ste_softc *sc; 1592 1593 sc = ifp->if_softc; 1594 1595 ifp->if_oerrors++; 1596 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1597 1598 ste_txeoc(sc); 1599 ste_txeof(sc); 1600 ste_rxeof(sc); 1601 ste_reset(sc); 1602 ste_init(sc); 1603 1604 if (!ifq_is_empty(&ifp->if_snd)) 1605 ste_start(ifp); 1606 1607 return; 1608 } 1609 1610 static void ste_shutdown(dev) 1611 device_t dev; 1612 { 1613 struct ste_softc *sc; 1614 1615 sc = device_get_softc(dev); 1616 1617 ste_stop(sc); 1618 1619 return; 1620 } 1621