1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.15 2005/02/20 02:59:57 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 46 #include <net/if.h> 47 #include <net/ifq_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/vlan/if_vlan_var.h> 53 54 #include <net/bpf.h> 55 56 #include <vm/vm.h> /* for vtophys */ 57 #include <vm/pmap.h> /* for vtophys */ 58 #include <machine/clock.h> /* for DELAY */ 59 #include <machine/bus_memio.h> 60 #include <machine/bus_pio.h> 61 #include <machine/bus.h> 62 #include <machine/resource.h> 63 #include <sys/bus.h> 64 #include <sys/rman.h> 65 66 #include "../mii_layer/mii.h" 67 #include "../mii_layer/miivar.h" 68 69 #include <bus/pci/pcireg.h> 70 #include <bus/pci/pcivar.h> 71 72 /* "controller miibus0" required. See GENERIC if you get errors here. */ 73 #include "miibus_if.h" 74 75 #define STE_USEIOSPACE 76 77 #include "if_stereg.h" 78 79 /* 80 * Various supported device vendors/types and their names. 81 */ 82 static struct ste_type ste_devs[] = { 83 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 84 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 85 { 0, 0, NULL } 86 }; 87 88 static int ste_probe (device_t); 89 static int ste_attach (device_t); 90 static int ste_detach (device_t); 91 static void ste_init (void *); 92 static void ste_intr (void *); 93 static void ste_rxeof (struct ste_softc *); 94 static void ste_txeoc (struct ste_softc *); 95 static void ste_txeof (struct ste_softc *); 96 static void ste_stats_update (void *); 97 static void ste_stop (struct ste_softc *); 98 static void ste_reset (struct ste_softc *); 99 static int ste_ioctl (struct ifnet *, u_long, caddr_t, 100 struct ucred *); 101 static int ste_encap (struct ste_softc *, struct ste_chain *, 102 struct mbuf *); 103 static void ste_start (struct ifnet *); 104 static void ste_watchdog (struct ifnet *); 105 static void ste_shutdown (device_t); 106 static int ste_newbuf (struct ste_softc *, 107 struct ste_chain_onefrag *, 108 struct mbuf *); 109 static int ste_ifmedia_upd (struct ifnet *); 110 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111 112 static void ste_mii_sync (struct ste_softc *); 113 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 114 static int ste_mii_readreg (struct ste_softc *, 115 struct ste_mii_frame *); 116 static int ste_mii_writereg (struct ste_softc *, 117 struct ste_mii_frame *); 118 static int ste_miibus_readreg (device_t, int, int); 119 static int ste_miibus_writereg (device_t, int, int, int); 120 static void ste_miibus_statchg (device_t); 121 122 static int ste_eeprom_wait (struct ste_softc *); 123 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 124 int, int); 125 static void ste_wait (struct ste_softc *); 126 static u_int8_t ste_calchash (caddr_t); 127 static void ste_setmulti (struct ste_softc *); 128 static int ste_init_rx_list (struct ste_softc *); 129 static void ste_init_tx_list (struct ste_softc *); 130 131 #ifdef STE_USEIOSPACE 132 #define STE_RES SYS_RES_IOPORT 133 #define STE_RID STE_PCI_LOIO 134 #else 135 #define STE_RES SYS_RES_MEMORY 136 #define STE_RID STE_PCI_LOMEM 137 #endif 138 139 static device_method_t ste_methods[] = { 140 /* Device interface */ 141 DEVMETHOD(device_probe, ste_probe), 142 DEVMETHOD(device_attach, ste_attach), 143 DEVMETHOD(device_detach, ste_detach), 144 DEVMETHOD(device_shutdown, ste_shutdown), 145 146 /* bus interface */ 147 DEVMETHOD(bus_print_child, bus_generic_print_child), 148 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 149 150 /* MII interface */ 151 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 152 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 153 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 154 155 { 0, 0 } 156 }; 157 158 static driver_t ste_driver = { 159 "ste", 160 ste_methods, 161 sizeof(struct ste_softc) 162 }; 163 164 static devclass_t ste_devclass; 165 166 DECLARE_DUMMY_MODULE(if_ste); 167 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 168 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 169 170 #define STE_SETBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 172 173 #define STE_CLRBIT4(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 175 176 #define STE_SETBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 178 179 #define STE_CLRBIT2(sc, reg, x) \ 180 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 181 182 #define STE_SETBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 184 185 #define STE_CLRBIT1(sc, reg, x) \ 186 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 187 188 189 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 190 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 191 192 /* 193 * Sync the PHYs by setting data bit and strobing the clock 32 times. 194 */ 195 static void ste_mii_sync(sc) 196 struct ste_softc *sc; 197 { 198 int i; 199 200 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 201 202 for (i = 0; i < 32; i++) { 203 MII_SET(STE_PHYCTL_MCLK); 204 DELAY(1); 205 MII_CLR(STE_PHYCTL_MCLK); 206 DELAY(1); 207 } 208 209 return; 210 } 211 212 /* 213 * Clock a series of bits through the MII. 214 */ 215 static void ste_mii_send(sc, bits, cnt) 216 struct ste_softc *sc; 217 u_int32_t bits; 218 int cnt; 219 { 220 int i; 221 222 MII_CLR(STE_PHYCTL_MCLK); 223 224 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 225 if (bits & i) { 226 MII_SET(STE_PHYCTL_MDATA); 227 } else { 228 MII_CLR(STE_PHYCTL_MDATA); 229 } 230 DELAY(1); 231 MII_CLR(STE_PHYCTL_MCLK); 232 DELAY(1); 233 MII_SET(STE_PHYCTL_MCLK); 234 } 235 } 236 237 /* 238 * Read an PHY register through the MII. 239 */ 240 static int ste_mii_readreg(sc, frame) 241 struct ste_softc *sc; 242 struct ste_mii_frame *frame; 243 244 { 245 int i, ack, s; 246 247 s = splimp(); 248 249 /* 250 * Set up frame for RX. 251 */ 252 frame->mii_stdelim = STE_MII_STARTDELIM; 253 frame->mii_opcode = STE_MII_READOP; 254 frame->mii_turnaround = 0; 255 frame->mii_data = 0; 256 257 CSR_WRITE_2(sc, STE_PHYCTL, 0); 258 /* 259 * Turn on data xmit. 260 */ 261 MII_SET(STE_PHYCTL_MDIR); 262 263 ste_mii_sync(sc); 264 265 /* 266 * Send command/address info. 267 */ 268 ste_mii_send(sc, frame->mii_stdelim, 2); 269 ste_mii_send(sc, frame->mii_opcode, 2); 270 ste_mii_send(sc, frame->mii_phyaddr, 5); 271 ste_mii_send(sc, frame->mii_regaddr, 5); 272 273 /* Turn off xmit. */ 274 MII_CLR(STE_PHYCTL_MDIR); 275 276 /* Idle bit */ 277 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 278 DELAY(1); 279 MII_SET(STE_PHYCTL_MCLK); 280 DELAY(1); 281 282 /* Check for ack */ 283 MII_CLR(STE_PHYCTL_MCLK); 284 DELAY(1); 285 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 286 MII_SET(STE_PHYCTL_MCLK); 287 DELAY(1); 288 289 /* 290 * Now try reading data bits. If the ack failed, we still 291 * need to clock through 16 cycles to keep the PHY(s) in sync. 292 */ 293 if (ack) { 294 for(i = 0; i < 16; i++) { 295 MII_CLR(STE_PHYCTL_MCLK); 296 DELAY(1); 297 MII_SET(STE_PHYCTL_MCLK); 298 DELAY(1); 299 } 300 goto fail; 301 } 302 303 for (i = 0x8000; i; i >>= 1) { 304 MII_CLR(STE_PHYCTL_MCLK); 305 DELAY(1); 306 if (!ack) { 307 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 308 frame->mii_data |= i; 309 DELAY(1); 310 } 311 MII_SET(STE_PHYCTL_MCLK); 312 DELAY(1); 313 } 314 315 fail: 316 317 MII_CLR(STE_PHYCTL_MCLK); 318 DELAY(1); 319 MII_SET(STE_PHYCTL_MCLK); 320 DELAY(1); 321 322 splx(s); 323 324 if (ack) 325 return(1); 326 return(0); 327 } 328 329 /* 330 * Write to a PHY register through the MII. 331 */ 332 static int ste_mii_writereg(sc, frame) 333 struct ste_softc *sc; 334 struct ste_mii_frame *frame; 335 336 { 337 int s; 338 339 s = splimp(); 340 /* 341 * Set up frame for TX. 342 */ 343 344 frame->mii_stdelim = STE_MII_STARTDELIM; 345 frame->mii_opcode = STE_MII_WRITEOP; 346 frame->mii_turnaround = STE_MII_TURNAROUND; 347 348 /* 349 * Turn on data output. 350 */ 351 MII_SET(STE_PHYCTL_MDIR); 352 353 ste_mii_sync(sc); 354 355 ste_mii_send(sc, frame->mii_stdelim, 2); 356 ste_mii_send(sc, frame->mii_opcode, 2); 357 ste_mii_send(sc, frame->mii_phyaddr, 5); 358 ste_mii_send(sc, frame->mii_regaddr, 5); 359 ste_mii_send(sc, frame->mii_turnaround, 2); 360 ste_mii_send(sc, frame->mii_data, 16); 361 362 /* Idle bit. */ 363 MII_SET(STE_PHYCTL_MCLK); 364 DELAY(1); 365 MII_CLR(STE_PHYCTL_MCLK); 366 DELAY(1); 367 368 /* 369 * Turn off xmit. 370 */ 371 MII_CLR(STE_PHYCTL_MDIR); 372 373 splx(s); 374 375 return(0); 376 } 377 378 static int ste_miibus_readreg(dev, phy, reg) 379 device_t dev; 380 int phy, reg; 381 { 382 struct ste_softc *sc; 383 struct ste_mii_frame frame; 384 385 sc = device_get_softc(dev); 386 387 if ( sc->ste_one_phy && phy != 0 ) 388 return (0); 389 390 bzero((char *)&frame, sizeof(frame)); 391 392 frame.mii_phyaddr = phy; 393 frame.mii_regaddr = reg; 394 ste_mii_readreg(sc, &frame); 395 396 return(frame.mii_data); 397 } 398 399 static int ste_miibus_writereg(dev, phy, reg, data) 400 device_t dev; 401 int phy, reg, data; 402 { 403 struct ste_softc *sc; 404 struct ste_mii_frame frame; 405 406 sc = device_get_softc(dev); 407 bzero((char *)&frame, sizeof(frame)); 408 409 frame.mii_phyaddr = phy; 410 frame.mii_regaddr = reg; 411 frame.mii_data = data; 412 413 ste_mii_writereg(sc, &frame); 414 415 return(0); 416 } 417 418 static void ste_miibus_statchg(dev) 419 device_t dev; 420 { 421 struct ste_softc *sc; 422 struct mii_data *mii; 423 int i; 424 425 sc = device_get_softc(dev); 426 mii = device_get_softc(sc->ste_miibus); 427 428 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 429 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 430 } else { 431 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 432 } 433 434 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 435 STE_ASICCTL_TX_RESET); 436 for (i = 0; i < STE_TIMEOUT; i++) { 437 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 438 break; 439 } 440 if (i == STE_TIMEOUT) 441 printf("ste%d: rx reset never completed\n", sc->ste_unit); 442 443 return; 444 } 445 446 static int ste_ifmedia_upd(ifp) 447 struct ifnet *ifp; 448 { 449 struct ste_softc *sc; 450 struct mii_data *mii; 451 452 sc = ifp->if_softc; 453 mii = device_get_softc(sc->ste_miibus); 454 sc->ste_link = 0; 455 if (mii->mii_instance) { 456 struct mii_softc *miisc; 457 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 458 miisc = LIST_NEXT(miisc, mii_list)) 459 mii_phy_reset(miisc); 460 } 461 mii_mediachg(mii); 462 463 return(0); 464 } 465 466 static void ste_ifmedia_sts(ifp, ifmr) 467 struct ifnet *ifp; 468 struct ifmediareq *ifmr; 469 { 470 struct ste_softc *sc; 471 struct mii_data *mii; 472 473 sc = ifp->if_softc; 474 mii = device_get_softc(sc->ste_miibus); 475 476 mii_pollstat(mii); 477 ifmr->ifm_active = mii->mii_media_active; 478 ifmr->ifm_status = mii->mii_media_status; 479 480 return; 481 } 482 483 static void ste_wait(sc) 484 struct ste_softc *sc; 485 { 486 int i; 487 488 for (i = 0; i < STE_TIMEOUT; i++) { 489 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 490 break; 491 } 492 493 if (i == STE_TIMEOUT) 494 printf("ste%d: command never completed!\n", sc->ste_unit); 495 496 return; 497 } 498 499 /* 500 * The EEPROM is slow: give it time to come ready after issuing 501 * it a command. 502 */ 503 static int ste_eeprom_wait(sc) 504 struct ste_softc *sc; 505 { 506 int i; 507 508 DELAY(1000); 509 510 for (i = 0; i < 100; i++) { 511 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 512 DELAY(1000); 513 else 514 break; 515 } 516 517 if (i == 100) { 518 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 519 return(1); 520 } 521 522 return(0); 523 } 524 525 /* 526 * Read a sequence of words from the EEPROM. Note that ethernet address 527 * data is stored in the EEPROM in network byte order. 528 */ 529 static int ste_read_eeprom(sc, dest, off, cnt, swap) 530 struct ste_softc *sc; 531 caddr_t dest; 532 int off; 533 int cnt; 534 int swap; 535 { 536 int err = 0, i; 537 u_int16_t word = 0, *ptr; 538 539 if (ste_eeprom_wait(sc)) 540 return(1); 541 542 for (i = 0; i < cnt; i++) { 543 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 544 err = ste_eeprom_wait(sc); 545 if (err) 546 break; 547 word = CSR_READ_2(sc, STE_EEPROM_DATA); 548 ptr = (u_int16_t *)(dest + (i * 2)); 549 if (swap) 550 *ptr = ntohs(word); 551 else 552 *ptr = word; 553 } 554 555 return(err ? 1 : 0); 556 } 557 558 static u_int8_t ste_calchash(addr) 559 caddr_t addr; 560 { 561 562 u_int32_t crc, carry; 563 int i, j; 564 u_int8_t c; 565 566 /* Compute CRC for the address value. */ 567 crc = 0xFFFFFFFF; /* initial value */ 568 569 for (i = 0; i < 6; i++) { 570 c = *(addr + i); 571 for (j = 0; j < 8; j++) { 572 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 573 crc <<= 1; 574 c >>= 1; 575 if (carry) 576 crc = (crc ^ 0x04c11db6) | carry; 577 } 578 } 579 580 /* return the filter bit position */ 581 return(crc & 0x0000003F); 582 } 583 584 static void ste_setmulti(sc) 585 struct ste_softc *sc; 586 { 587 struct ifnet *ifp; 588 int h = 0; 589 u_int32_t hashes[2] = { 0, 0 }; 590 struct ifmultiaddr *ifma; 591 592 ifp = &sc->arpcom.ac_if; 593 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 594 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 595 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 596 return; 597 } 598 599 /* first, zot all the existing hash bits */ 600 CSR_WRITE_2(sc, STE_MAR0, 0); 601 CSR_WRITE_2(sc, STE_MAR1, 0); 602 CSR_WRITE_2(sc, STE_MAR2, 0); 603 CSR_WRITE_2(sc, STE_MAR3, 0); 604 605 /* now program new ones */ 606 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 607 ifma = ifma->ifma_link.le_next) { 608 if (ifma->ifma_addr->sa_family != AF_LINK) 609 continue; 610 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 611 if (h < 32) 612 hashes[0] |= (1 << h); 613 else 614 hashes[1] |= (1 << (h - 32)); 615 } 616 617 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 619 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 620 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 621 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 622 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 623 624 return; 625 } 626 627 static void ste_intr(xsc) 628 void *xsc; 629 { 630 struct ste_softc *sc; 631 struct ifnet *ifp; 632 u_int16_t status; 633 634 sc = xsc; 635 ifp = &sc->arpcom.ac_if; 636 637 /* See if this is really our interrupt. */ 638 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 639 return; 640 641 for (;;) { 642 status = CSR_READ_2(sc, STE_ISR_ACK); 643 644 if (!(status & STE_INTRS)) 645 break; 646 647 if (status & STE_ISR_RX_DMADONE) 648 ste_rxeof(sc); 649 650 if (status & STE_ISR_TX_DMADONE) 651 ste_txeof(sc); 652 653 if (status & STE_ISR_TX_DONE) 654 ste_txeoc(sc); 655 656 if (status & STE_ISR_STATS_OFLOW) { 657 callout_stop(&sc->ste_stat_timer); 658 ste_stats_update(sc); 659 } 660 661 if (status & STE_ISR_LINKEVENT) 662 mii_pollstat(device_get_softc(sc->ste_miibus)); 663 664 if (status & STE_ISR_HOSTERR) { 665 ste_reset(sc); 666 ste_init(sc); 667 } 668 } 669 670 /* Re-enable interrupts */ 671 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 672 673 if (!ifq_is_empty(&ifp->if_snd)) 674 ste_start(ifp); 675 676 return; 677 } 678 679 /* 680 * A frame has been uploaded: pass the resulting mbuf chain up to 681 * the higher level protocols. 682 */ 683 static void ste_rxeof(sc) 684 struct ste_softc *sc; 685 { 686 struct mbuf *m; 687 struct ifnet *ifp; 688 struct ste_chain_onefrag *cur_rx; 689 int total_len = 0, count=0; 690 u_int32_t rxstat; 691 692 ifp = &sc->arpcom.ac_if; 693 694 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 695 & STE_RXSTAT_DMADONE) { 696 if ((STE_RX_LIST_CNT - count) < 3) { 697 break; 698 } 699 700 cur_rx = sc->ste_cdata.ste_rx_head; 701 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 702 703 /* 704 * If an error occurs, update stats, clear the 705 * status word and leave the mbuf cluster in place: 706 * it should simply get re-used next time this descriptor 707 * comes up in the ring. 708 */ 709 if (rxstat & STE_RXSTAT_FRAME_ERR) { 710 ifp->if_ierrors++; 711 cur_rx->ste_ptr->ste_status = 0; 712 continue; 713 } 714 715 /* 716 * If there error bit was not set, the upload complete 717 * bit should be set which means we have a valid packet. 718 * If not, something truly strange has happened. 719 */ 720 if (!(rxstat & STE_RXSTAT_DMADONE)) { 721 printf("ste%d: bad receive status -- packet dropped", 722 sc->ste_unit); 723 ifp->if_ierrors++; 724 cur_rx->ste_ptr->ste_status = 0; 725 continue; 726 } 727 728 /* No errors; receive the packet. */ 729 m = cur_rx->ste_mbuf; 730 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 731 732 /* 733 * Try to conjure up a new mbuf cluster. If that 734 * fails, it means we have an out of memory condition and 735 * should leave the buffer in place and continue. This will 736 * result in a lost packet, but there's little else we 737 * can do in this situation. 738 */ 739 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 740 ifp->if_ierrors++; 741 cur_rx->ste_ptr->ste_status = 0; 742 continue; 743 } 744 745 ifp->if_ipackets++; 746 m->m_pkthdr.rcvif = ifp; 747 m->m_pkthdr.len = m->m_len = total_len; 748 749 (*ifp->if_input)(ifp, m); 750 751 cur_rx->ste_ptr->ste_status = 0; 752 count++; 753 } 754 755 return; 756 } 757 758 static void ste_txeoc(sc) 759 struct ste_softc *sc; 760 { 761 u_int8_t txstat; 762 struct ifnet *ifp; 763 764 ifp = &sc->arpcom.ac_if; 765 766 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 767 STE_TXSTATUS_TXDONE) { 768 if (txstat & STE_TXSTATUS_UNDERRUN || 769 txstat & STE_TXSTATUS_EXCESSCOLLS || 770 txstat & STE_TXSTATUS_RECLAIMERR) { 771 ifp->if_oerrors++; 772 printf("ste%d: transmission error: %x\n", 773 sc->ste_unit, txstat); 774 775 ste_reset(sc); 776 ste_init(sc); 777 778 if (txstat & STE_TXSTATUS_UNDERRUN && 779 sc->ste_tx_thresh < STE_PACKET_SIZE) { 780 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 781 printf("ste%d: tx underrun, increasing tx" 782 " start threshold to %d bytes\n", 783 sc->ste_unit, sc->ste_tx_thresh); 784 } 785 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 786 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 787 (STE_PACKET_SIZE >> 4)); 788 } 789 ste_init(sc); 790 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 791 } 792 793 return; 794 } 795 796 static void ste_txeof(sc) 797 struct ste_softc *sc; 798 { 799 struct ste_chain *cur_tx = NULL; 800 struct ifnet *ifp; 801 int idx; 802 803 ifp = &sc->arpcom.ac_if; 804 805 idx = sc->ste_cdata.ste_tx_cons; 806 while(idx != sc->ste_cdata.ste_tx_prod) { 807 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 808 809 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 810 break; 811 812 if (cur_tx->ste_mbuf != NULL) { 813 m_freem(cur_tx->ste_mbuf); 814 cur_tx->ste_mbuf = NULL; 815 } 816 817 ifp->if_opackets++; 818 819 sc->ste_cdata.ste_tx_cnt--; 820 STE_INC(idx, STE_TX_LIST_CNT); 821 ifp->if_timer = 0; 822 } 823 824 sc->ste_cdata.ste_tx_cons = idx; 825 826 if (cur_tx != NULL) 827 ifp->if_flags &= ~IFF_OACTIVE; 828 829 return; 830 } 831 832 static void ste_stats_update(xsc) 833 void *xsc; 834 { 835 struct ste_softc *sc; 836 struct ifnet *ifp; 837 struct mii_data *mii; 838 int s; 839 840 s = splimp(); 841 842 sc = xsc; 843 ifp = &sc->arpcom.ac_if; 844 mii = device_get_softc(sc->ste_miibus); 845 846 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 847 + CSR_READ_1(sc, STE_MULTI_COLLS) 848 + CSR_READ_1(sc, STE_SINGLE_COLLS); 849 850 if (!sc->ste_link) { 851 mii_pollstat(mii); 852 if (mii->mii_media_status & IFM_ACTIVE && 853 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 854 sc->ste_link++; 855 /* 856 * we don't get a call-back on re-init so do it 857 * otherwise we get stuck in the wrong link state 858 */ 859 ste_miibus_statchg(sc->ste_dev); 860 if (!ifq_is_empty(&ifp->if_snd)) 861 ste_start(ifp); 862 } 863 } 864 865 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 866 splx(s); 867 868 return; 869 } 870 871 872 /* 873 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 874 * IDs against our list and return a device name if we find a match. 875 */ 876 static int ste_probe(dev) 877 device_t dev; 878 { 879 struct ste_type *t; 880 881 t = ste_devs; 882 883 while(t->ste_name != NULL) { 884 if ((pci_get_vendor(dev) == t->ste_vid) && 885 (pci_get_device(dev) == t->ste_did)) { 886 device_set_desc(dev, t->ste_name); 887 return(0); 888 } 889 t++; 890 } 891 892 return(ENXIO); 893 } 894 895 /* 896 * Attach the interface. Allocate softc structures, do ifmedia 897 * setup and ethernet/BPF attach. 898 */ 899 static int ste_attach(dev) 900 device_t dev; 901 { 902 int s; 903 u_int32_t command; 904 struct ste_softc *sc; 905 struct ifnet *ifp; 906 int unit, error = 0, rid; 907 908 s = splimp(); 909 910 sc = device_get_softc(dev); 911 unit = device_get_unit(dev); 912 bzero(sc, sizeof(struct ste_softc)); 913 sc->ste_dev = dev; 914 915 /* 916 * Only use one PHY since this chip reports multiple 917 * Note on the DFE-550 the PHY is at 1 on the DFE-580 918 * it is at 0 & 1. It is rev 0x12. 919 */ 920 if (pci_get_vendor(dev) == DL_VENDORID && 921 pci_get_device(dev) == DL_DEVICEID_550TX && 922 pci_get_revid(dev) == 0x12 ) 923 sc->ste_one_phy = 1; 924 925 /* 926 * Handle power management nonsense. 927 */ 928 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 929 if (command == 0x01) { 930 931 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 932 if (command & STE_PSTATE_MASK) { 933 u_int32_t iobase, membase, irq; 934 935 /* Save important PCI config data. */ 936 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 937 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 938 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 939 940 /* Reset the power state. */ 941 printf("ste%d: chip is in D%d power mode " 942 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 943 command &= 0xFFFFFFFC; 944 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 945 946 /* Restore PCI config data. */ 947 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 948 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 949 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 950 } 951 } 952 953 /* 954 * Map control/status registers. 955 */ 956 command = pci_read_config(dev, PCIR_COMMAND, 4); 957 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 958 pci_write_config(dev, PCIR_COMMAND, command, 4); 959 command = pci_read_config(dev, PCIR_COMMAND, 4); 960 961 #ifdef STE_USEIOSPACE 962 if (!(command & PCIM_CMD_PORTEN)) { 963 printf("ste%d: failed to enable I/O ports!\n", unit); 964 error = ENXIO; 965 goto fail; 966 } 967 #else 968 if (!(command & PCIM_CMD_MEMEN)) { 969 printf("ste%d: failed to enable memory mapping!\n", unit); 970 error = ENXIO; 971 goto fail; 972 } 973 #endif 974 975 rid = STE_RID; 976 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 977 0, ~0, 1, RF_ACTIVE); 978 979 if (sc->ste_res == NULL) { 980 printf ("ste%d: couldn't map ports/memory\n", unit); 981 error = ENXIO; 982 goto fail; 983 } 984 985 sc->ste_btag = rman_get_bustag(sc->ste_res); 986 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 987 988 rid = 0; 989 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 990 RF_SHAREABLE | RF_ACTIVE); 991 992 if (sc->ste_irq == NULL) { 993 printf("ste%d: couldn't map interrupt\n", unit); 994 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 995 error = ENXIO; 996 goto fail; 997 } 998 999 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1000 ste_intr, sc, &sc->ste_intrhand); 1001 1002 if (error) { 1003 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1004 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1005 printf("ste%d: couldn't set up irq\n", unit); 1006 goto fail; 1007 } 1008 1009 callout_init(&sc->ste_stat_timer); 1010 1011 /* Reset the adapter. */ 1012 ste_reset(sc); 1013 1014 /* 1015 * Get station address from the EEPROM. 1016 */ 1017 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1018 STE_EEADDR_NODE0, 3, 0)) { 1019 printf("ste%d: failed to read station address\n", unit); 1020 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1021 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1022 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1023 error = ENXIO;; 1024 goto fail; 1025 } 1026 1027 sc->ste_unit = unit; 1028 1029 /* Allocate the descriptor queues. */ 1030 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1031 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1032 1033 if (sc->ste_ldata == NULL) { 1034 printf("ste%d: no memory for list buffers!\n", unit); 1035 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1036 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1037 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1038 error = ENXIO; 1039 goto fail; 1040 } 1041 1042 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1043 1044 /* Do MII setup. */ 1045 if (mii_phy_probe(dev, &sc->ste_miibus, 1046 ste_ifmedia_upd, ste_ifmedia_sts)) { 1047 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1048 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1049 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1050 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1051 contigfree(sc->ste_ldata, 1052 sizeof(struct ste_list_data), M_DEVBUF); 1053 error = ENXIO; 1054 goto fail; 1055 } 1056 1057 ifp = &sc->arpcom.ac_if; 1058 ifp->if_softc = sc; 1059 if_initname(ifp, "ste", unit); 1060 ifp->if_mtu = ETHERMTU; 1061 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1062 ifp->if_ioctl = ste_ioctl; 1063 ifp->if_start = ste_start; 1064 ifp->if_watchdog = ste_watchdog; 1065 ifp->if_init = ste_init; 1066 ifp->if_baudrate = 10000000; 1067 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1068 ifq_set_ready(&ifp->if_snd); 1069 1070 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1071 1072 /* 1073 * Call MI attach routine. 1074 */ 1075 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1076 1077 /* 1078 * Tell the upper layer(s) we support long frames. 1079 */ 1080 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1081 1082 fail: 1083 splx(s); 1084 return(error); 1085 } 1086 1087 static int ste_detach(dev) 1088 device_t dev; 1089 { 1090 struct ste_softc *sc; 1091 struct ifnet *ifp; 1092 int s; 1093 1094 s = splimp(); 1095 1096 sc = device_get_softc(dev); 1097 ifp = &sc->arpcom.ac_if; 1098 1099 ste_stop(sc); 1100 ether_ifdetach(ifp); 1101 1102 bus_generic_detach(dev); 1103 device_delete_child(dev, sc->ste_miibus); 1104 1105 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1106 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1107 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1108 1109 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1110 1111 splx(s); 1112 1113 return(0); 1114 } 1115 1116 static int ste_newbuf(sc, c, m) 1117 struct ste_softc *sc; 1118 struct ste_chain_onefrag *c; 1119 struct mbuf *m; 1120 { 1121 struct mbuf *m_new = NULL; 1122 1123 if (m == NULL) { 1124 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1125 if (m_new == NULL) 1126 return(ENOBUFS); 1127 MCLGET(m_new, MB_DONTWAIT); 1128 if (!(m_new->m_flags & M_EXT)) { 1129 m_freem(m_new); 1130 return(ENOBUFS); 1131 } 1132 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1133 } else { 1134 m_new = m; 1135 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1136 m_new->m_data = m_new->m_ext.ext_buf; 1137 } 1138 1139 m_adj(m_new, ETHER_ALIGN); 1140 1141 c->ste_mbuf = m_new; 1142 c->ste_ptr->ste_status = 0; 1143 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1144 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1145 1146 return(0); 1147 } 1148 1149 static int ste_init_rx_list(sc) 1150 struct ste_softc *sc; 1151 { 1152 struct ste_chain_data *cd; 1153 struct ste_list_data *ld; 1154 int i; 1155 1156 cd = &sc->ste_cdata; 1157 ld = sc->ste_ldata; 1158 1159 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1160 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1161 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1162 return(ENOBUFS); 1163 if (i == (STE_RX_LIST_CNT - 1)) { 1164 cd->ste_rx_chain[i].ste_next = 1165 &cd->ste_rx_chain[0]; 1166 ld->ste_rx_list[i].ste_next = 1167 vtophys(&ld->ste_rx_list[0]); 1168 } else { 1169 cd->ste_rx_chain[i].ste_next = 1170 &cd->ste_rx_chain[i + 1]; 1171 ld->ste_rx_list[i].ste_next = 1172 vtophys(&ld->ste_rx_list[i + 1]); 1173 } 1174 ld->ste_rx_list[i].ste_status = 0; 1175 } 1176 1177 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1178 1179 return(0); 1180 } 1181 1182 static void ste_init_tx_list(sc) 1183 struct ste_softc *sc; 1184 { 1185 struct ste_chain_data *cd; 1186 struct ste_list_data *ld; 1187 int i; 1188 1189 cd = &sc->ste_cdata; 1190 ld = sc->ste_ldata; 1191 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1192 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1193 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1194 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1195 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1196 if (i == (STE_TX_LIST_CNT - 1)) 1197 cd->ste_tx_chain[i].ste_next = 1198 &cd->ste_tx_chain[0]; 1199 else 1200 cd->ste_tx_chain[i].ste_next = 1201 &cd->ste_tx_chain[i + 1]; 1202 if (i == 0) 1203 cd->ste_tx_chain[i].ste_prev = 1204 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1205 else 1206 cd->ste_tx_chain[i].ste_prev = 1207 &cd->ste_tx_chain[i - 1]; 1208 } 1209 1210 cd->ste_tx_prod = 0; 1211 cd->ste_tx_cons = 0; 1212 cd->ste_tx_cnt = 0; 1213 1214 return; 1215 } 1216 1217 static void ste_init(xsc) 1218 void *xsc; 1219 { 1220 struct ste_softc *sc; 1221 int i, s; 1222 struct ifnet *ifp; 1223 struct mii_data *mii; 1224 1225 s = splimp(); 1226 1227 sc = xsc; 1228 ifp = &sc->arpcom.ac_if; 1229 mii = device_get_softc(sc->ste_miibus); 1230 1231 ste_stop(sc); 1232 1233 /* Init our MAC address */ 1234 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1235 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1236 } 1237 1238 /* Init RX list */ 1239 if (ste_init_rx_list(sc) == ENOBUFS) { 1240 printf("ste%d: initialization failed: no " 1241 "memory for RX buffers\n", sc->ste_unit); 1242 ste_stop(sc); 1243 splx(s); 1244 return; 1245 } 1246 1247 /* Set RX polling interval */ 1248 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1249 1250 /* Init TX descriptors */ 1251 ste_init_tx_list(sc); 1252 1253 /* Set the TX freethresh value */ 1254 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1255 1256 /* Set the TX start threshold for best performance. */ 1257 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1258 1259 /* Set the TX reclaim threshold. */ 1260 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1261 1262 /* Set up the RX filter. */ 1263 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1264 1265 /* If we want promiscuous mode, set the allframes bit. */ 1266 if (ifp->if_flags & IFF_PROMISC) { 1267 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1268 } else { 1269 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1270 } 1271 1272 /* Set capture broadcast bit to accept broadcast frames. */ 1273 if (ifp->if_flags & IFF_BROADCAST) { 1274 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1275 } else { 1276 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1277 } 1278 1279 ste_setmulti(sc); 1280 1281 /* Load the address of the RX list. */ 1282 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1283 ste_wait(sc); 1284 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1285 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1286 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1287 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1288 1289 /* Set TX polling interval (defer until we TX first packet */ 1290 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1291 1292 /* Load address of the TX list */ 1293 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1294 ste_wait(sc); 1295 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1296 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1297 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1298 ste_wait(sc); 1299 sc->ste_tx_prev_idx=-1; 1300 1301 /* Enable receiver and transmitter */ 1302 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1303 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1304 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1305 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1306 1307 /* Enable stats counters. */ 1308 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1309 1310 /* Enable interrupts. */ 1311 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1312 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1313 1314 /* Accept VLAN length packets */ 1315 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1316 1317 ste_ifmedia_upd(ifp); 1318 1319 ifp->if_flags |= IFF_RUNNING; 1320 ifp->if_flags &= ~IFF_OACTIVE; 1321 1322 splx(s); 1323 1324 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 1325 1326 return; 1327 } 1328 1329 static void ste_stop(sc) 1330 struct ste_softc *sc; 1331 { 1332 int i; 1333 struct ifnet *ifp; 1334 1335 ifp = &sc->arpcom.ac_if; 1336 1337 callout_stop(&sc->ste_stat_timer); 1338 1339 CSR_WRITE_2(sc, STE_IMR, 0); 1340 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1341 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1342 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1343 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1344 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1345 ste_wait(sc); 1346 /* 1347 * Try really hard to stop the RX engine or under heavy RX 1348 * data chip will write into de-allocated memory. 1349 */ 1350 ste_reset(sc); 1351 1352 sc->ste_link = 0; 1353 1354 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1355 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1356 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1357 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1358 } 1359 } 1360 1361 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1362 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1363 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1364 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1365 } 1366 } 1367 1368 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1369 1370 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1371 1372 return; 1373 } 1374 1375 static void ste_reset(sc) 1376 struct ste_softc *sc; 1377 { 1378 int i; 1379 1380 STE_SETBIT4(sc, STE_ASICCTL, 1381 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1382 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1383 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1384 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1385 STE_ASICCTL_EXTRESET_RESET); 1386 1387 DELAY(100000); 1388 1389 for (i = 0; i < STE_TIMEOUT; i++) { 1390 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1391 break; 1392 } 1393 1394 if (i == STE_TIMEOUT) 1395 printf("ste%d: global reset never completed\n", sc->ste_unit); 1396 1397 return; 1398 } 1399 1400 static int ste_ioctl(ifp, command, data, cr) 1401 struct ifnet *ifp; 1402 u_long command; 1403 caddr_t data; 1404 struct ucred *cr; 1405 { 1406 struct ste_softc *sc; 1407 struct ifreq *ifr; 1408 struct mii_data *mii; 1409 int error = 0, s; 1410 1411 s = splimp(); 1412 1413 sc = ifp->if_softc; 1414 ifr = (struct ifreq *)data; 1415 1416 switch(command) { 1417 case SIOCSIFADDR: 1418 case SIOCGIFADDR: 1419 case SIOCSIFMTU: 1420 error = ether_ioctl(ifp, command, data); 1421 break; 1422 case SIOCSIFFLAGS: 1423 if (ifp->if_flags & IFF_UP) { 1424 if (ifp->if_flags & IFF_RUNNING && 1425 ifp->if_flags & IFF_PROMISC && 1426 !(sc->ste_if_flags & IFF_PROMISC)) { 1427 STE_SETBIT1(sc, STE_RX_MODE, 1428 STE_RXMODE_PROMISC); 1429 } else if (ifp->if_flags & IFF_RUNNING && 1430 !(ifp->if_flags & IFF_PROMISC) && 1431 sc->ste_if_flags & IFF_PROMISC) { 1432 STE_CLRBIT1(sc, STE_RX_MODE, 1433 STE_RXMODE_PROMISC); 1434 } 1435 if (!(ifp->if_flags & IFF_RUNNING)) { 1436 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1437 ste_init(sc); 1438 } 1439 } else { 1440 if (ifp->if_flags & IFF_RUNNING) 1441 ste_stop(sc); 1442 } 1443 sc->ste_if_flags = ifp->if_flags; 1444 error = 0; 1445 break; 1446 case SIOCADDMULTI: 1447 case SIOCDELMULTI: 1448 ste_setmulti(sc); 1449 error = 0; 1450 break; 1451 case SIOCGIFMEDIA: 1452 case SIOCSIFMEDIA: 1453 mii = device_get_softc(sc->ste_miibus); 1454 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1455 break; 1456 default: 1457 error = EINVAL; 1458 break; 1459 } 1460 1461 splx(s); 1462 1463 return(error); 1464 } 1465 1466 static int ste_encap(sc, c, m_head) 1467 struct ste_softc *sc; 1468 struct ste_chain *c; 1469 struct mbuf *m_head; 1470 { 1471 int frag = 0; 1472 struct ste_frag *f = NULL; 1473 struct mbuf *m; 1474 struct ste_desc *d; 1475 int total_len = 0; 1476 1477 d = c->ste_ptr; 1478 d->ste_ctl = 0; 1479 1480 encap_retry: 1481 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1482 if (m->m_len != 0) { 1483 if (frag == STE_MAXFRAGS) 1484 break; 1485 total_len += m->m_len; 1486 f = &d->ste_frags[frag]; 1487 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1488 f->ste_len = m->m_len; 1489 frag++; 1490 } 1491 } 1492 1493 if (m != NULL) { 1494 struct mbuf *mn; 1495 1496 /* 1497 * We ran out of segments. We have to recopy this 1498 * mbuf chain first. Bail out if we can't get the 1499 * new buffers. Code borrowed from if_fxp.c. 1500 */ 1501 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1502 if (mn == NULL) { 1503 m_freem(m_head); 1504 return ENOMEM; 1505 } 1506 if (m_head->m_pkthdr.len > MHLEN) { 1507 MCLGET(mn, MB_DONTWAIT); 1508 if ((mn->m_flags & M_EXT) == 0) { 1509 m_freem(mn); 1510 m_freem(m_head); 1511 return ENOMEM; 1512 } 1513 } 1514 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1515 mtod(mn, caddr_t)); 1516 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1517 m_freem(m_head); 1518 m_head = mn; 1519 goto encap_retry; 1520 } 1521 1522 c->ste_mbuf = m_head; 1523 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1524 d->ste_ctl = 1; 1525 1526 return(0); 1527 } 1528 1529 static void ste_start(ifp) 1530 struct ifnet *ifp; 1531 { 1532 struct ste_softc *sc; 1533 struct mbuf *m_head = NULL; 1534 struct ste_chain *cur_tx = NULL; 1535 int idx; 1536 1537 sc = ifp->if_softc; 1538 1539 if (!sc->ste_link) 1540 return; 1541 1542 if (ifp->if_flags & IFF_OACTIVE) 1543 return; 1544 1545 idx = sc->ste_cdata.ste_tx_prod; 1546 1547 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1548 1549 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1550 ifp->if_flags |= IFF_OACTIVE; 1551 break; 1552 } 1553 1554 m_head = ifq_dequeue(&ifp->if_snd); 1555 if (m_head == NULL) 1556 break; 1557 1558 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1559 1560 if (ste_encap(sc, cur_tx, m_head) != 0) 1561 break; 1562 1563 cur_tx->ste_ptr->ste_next = 0; 1564 1565 if(sc->ste_tx_prev_idx < 0){ 1566 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1567 /* Load address of the TX list */ 1568 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1569 ste_wait(sc); 1570 1571 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1572 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1573 1574 /* Set TX polling interval to start TX engine */ 1575 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1576 1577 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1578 ste_wait(sc); 1579 }else{ 1580 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1581 sc->ste_cdata.ste_tx_chain[ 1582 sc->ste_tx_prev_idx].ste_ptr->ste_next 1583 = cur_tx->ste_phys; 1584 } 1585 1586 sc->ste_tx_prev_idx=idx; 1587 1588 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1589 1590 STE_INC(idx, STE_TX_LIST_CNT); 1591 sc->ste_cdata.ste_tx_cnt++; 1592 ifp->if_timer = 5; 1593 sc->ste_cdata.ste_tx_prod = idx; 1594 } 1595 1596 return; 1597 } 1598 1599 static void ste_watchdog(ifp) 1600 struct ifnet *ifp; 1601 { 1602 struct ste_softc *sc; 1603 1604 sc = ifp->if_softc; 1605 1606 ifp->if_oerrors++; 1607 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1608 1609 ste_txeoc(sc); 1610 ste_txeof(sc); 1611 ste_rxeof(sc); 1612 ste_reset(sc); 1613 ste_init(sc); 1614 1615 if (!ifq_is_empty(&ifp->if_snd)) 1616 ste_start(ifp); 1617 1618 return; 1619 } 1620 1621 static void ste_shutdown(dev) 1622 device_t dev; 1623 { 1624 struct ste_softc *sc; 1625 1626 sc = device_get_softc(dev); 1627 1628 ste_stop(sc); 1629 1630 return; 1631 } 1632