1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.31 2005/11/28 17:13:44 dillon Exp $ 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/serialize.h> 44 #include <sys/thread2.h> 45 46 #include <net/if.h> 47 #include <net/ifq_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/vlan/if_vlan_var.h> 53 54 #include <net/bpf.h> 55 56 #include <vm/vm.h> /* for vtophys */ 57 #include <vm/pmap.h> /* for vtophys */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus_pio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include "../mii_layer/mii.h" 66 #include "../mii_layer/miivar.h" 67 68 #include <bus/pci/pcireg.h> 69 #include <bus/pci/pcivar.h> 70 71 /* "controller miibus0" required. See GENERIC if you get errors here. */ 72 #include "miibus_if.h" 73 74 #define STE_USEIOSPACE 75 76 #include "if_stereg.h" 77 78 /* 79 * Various supported device vendors/types and their names. 80 */ 81 static struct ste_type ste_devs[] = { 82 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 83 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 84 { 0, 0, NULL } 85 }; 86 87 static int ste_probe (device_t); 88 static int ste_attach (device_t); 89 static int ste_detach (device_t); 90 static void ste_init (void *); 91 static void ste_intr (void *); 92 static void ste_rxeof (struct ste_softc *); 93 static void ste_txeoc (struct ste_softc *); 94 static void ste_txeof (struct ste_softc *); 95 static void ste_stats_update (void *); 96 static void ste_stop (struct ste_softc *); 97 static void ste_reset (struct ste_softc *); 98 static int ste_ioctl (struct ifnet *, u_long, caddr_t, 99 struct ucred *); 100 static int ste_encap (struct ste_softc *, struct ste_chain *, 101 struct mbuf *); 102 static void ste_start (struct ifnet *); 103 static void ste_watchdog (struct ifnet *); 104 static void ste_shutdown (device_t); 105 static int ste_newbuf (struct ste_softc *, 106 struct ste_chain_onefrag *, 107 struct mbuf *); 108 static int ste_ifmedia_upd (struct ifnet *); 109 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 111 static void ste_mii_sync (struct ste_softc *); 112 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 113 static int ste_mii_readreg (struct ste_softc *, 114 struct ste_mii_frame *); 115 static int ste_mii_writereg (struct ste_softc *, 116 struct ste_mii_frame *); 117 static int ste_miibus_readreg (device_t, int, int); 118 static int ste_miibus_writereg (device_t, int, int, int); 119 static void ste_miibus_statchg (device_t); 120 121 static int ste_eeprom_wait (struct ste_softc *); 122 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 123 int, int); 124 static void ste_wait (struct ste_softc *); 125 static void ste_setmulti (struct ste_softc *); 126 static int ste_init_rx_list (struct ste_softc *); 127 static void ste_init_tx_list (struct ste_softc *); 128 129 #ifdef STE_USEIOSPACE 130 #define STE_RES SYS_RES_IOPORT 131 #define STE_RID STE_PCI_LOIO 132 #else 133 #define STE_RES SYS_RES_MEMORY 134 #define STE_RID STE_PCI_LOMEM 135 #endif 136 137 static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154 }; 155 156 static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160 }; 161 162 static devclass_t ste_devclass; 163 164 DECLARE_DUMMY_MODULE(if_ste); 165 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 166 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 167 168 #define STE_SETBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 170 171 #define STE_CLRBIT4(sc, reg, x) \ 172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 173 174 #define STE_SETBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 176 177 #define STE_CLRBIT2(sc, reg, x) \ 178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 179 180 #define STE_SETBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 182 183 #define STE_CLRBIT1(sc, reg, x) \ 184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 185 186 187 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 188 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 189 190 /* 191 * Sync the PHYs by setting data bit and strobing the clock 32 times. 192 */ 193 static void ste_mii_sync(sc) 194 struct ste_softc *sc; 195 { 196 int i; 197 198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 199 200 for (i = 0; i < 32; i++) { 201 MII_SET(STE_PHYCTL_MCLK); 202 DELAY(1); 203 MII_CLR(STE_PHYCTL_MCLK); 204 DELAY(1); 205 } 206 207 return; 208 } 209 210 /* 211 * Clock a series of bits through the MII. 212 */ 213 static void ste_mii_send(sc, bits, cnt) 214 struct ste_softc *sc; 215 u_int32_t bits; 216 int cnt; 217 { 218 int i; 219 220 MII_CLR(STE_PHYCTL_MCLK); 221 222 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 223 if (bits & i) { 224 MII_SET(STE_PHYCTL_MDATA); 225 } else { 226 MII_CLR(STE_PHYCTL_MDATA); 227 } 228 DELAY(1); 229 MII_CLR(STE_PHYCTL_MCLK); 230 DELAY(1); 231 MII_SET(STE_PHYCTL_MCLK); 232 } 233 } 234 235 /* 236 * Read an PHY register through the MII. 237 */ 238 static int ste_mii_readreg(sc, frame) 239 struct ste_softc *sc; 240 struct ste_mii_frame *frame; 241 242 { 243 int i, ack; 244 245 /* 246 * Set up frame for RX. 247 */ 248 frame->mii_stdelim = STE_MII_STARTDELIM; 249 frame->mii_opcode = STE_MII_READOP; 250 frame->mii_turnaround = 0; 251 frame->mii_data = 0; 252 253 CSR_WRITE_2(sc, STE_PHYCTL, 0); 254 /* 255 * Turn on data xmit. 256 */ 257 MII_SET(STE_PHYCTL_MDIR); 258 259 ste_mii_sync(sc); 260 261 /* 262 * Send command/address info. 263 */ 264 ste_mii_send(sc, frame->mii_stdelim, 2); 265 ste_mii_send(sc, frame->mii_opcode, 2); 266 ste_mii_send(sc, frame->mii_phyaddr, 5); 267 ste_mii_send(sc, frame->mii_regaddr, 5); 268 269 /* Turn off xmit. */ 270 MII_CLR(STE_PHYCTL_MDIR); 271 272 /* Idle bit */ 273 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 274 DELAY(1); 275 MII_SET(STE_PHYCTL_MCLK); 276 DELAY(1); 277 278 /* Check for ack */ 279 MII_CLR(STE_PHYCTL_MCLK); 280 DELAY(1); 281 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 285 /* 286 * Now try reading data bits. If the ack failed, we still 287 * need to clock through 16 cycles to keep the PHY(s) in sync. 288 */ 289 if (ack) { 290 for(i = 0; i < 16; i++) { 291 MII_CLR(STE_PHYCTL_MCLK); 292 DELAY(1); 293 MII_SET(STE_PHYCTL_MCLK); 294 DELAY(1); 295 } 296 goto fail; 297 } 298 299 for (i = 0x8000; i; i >>= 1) { 300 MII_CLR(STE_PHYCTL_MCLK); 301 DELAY(1); 302 if (!ack) { 303 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 304 frame->mii_data |= i; 305 DELAY(1); 306 } 307 MII_SET(STE_PHYCTL_MCLK); 308 DELAY(1); 309 } 310 311 fail: 312 313 MII_CLR(STE_PHYCTL_MCLK); 314 DELAY(1); 315 MII_SET(STE_PHYCTL_MCLK); 316 DELAY(1); 317 318 if (ack) 319 return(1); 320 return(0); 321 } 322 323 /* 324 * Write to a PHY register through the MII. 325 */ 326 static int ste_mii_writereg(sc, frame) 327 struct ste_softc *sc; 328 struct ste_mii_frame *frame; 329 330 { 331 /* 332 * Set up frame for TX. 333 */ 334 335 frame->mii_stdelim = STE_MII_STARTDELIM; 336 frame->mii_opcode = STE_MII_WRITEOP; 337 frame->mii_turnaround = STE_MII_TURNAROUND; 338 339 /* 340 * Turn on data output. 341 */ 342 MII_SET(STE_PHYCTL_MDIR); 343 344 ste_mii_sync(sc); 345 346 ste_mii_send(sc, frame->mii_stdelim, 2); 347 ste_mii_send(sc, frame->mii_opcode, 2); 348 ste_mii_send(sc, frame->mii_phyaddr, 5); 349 ste_mii_send(sc, frame->mii_regaddr, 5); 350 ste_mii_send(sc, frame->mii_turnaround, 2); 351 ste_mii_send(sc, frame->mii_data, 16); 352 353 /* Idle bit. */ 354 MII_SET(STE_PHYCTL_MCLK); 355 DELAY(1); 356 MII_CLR(STE_PHYCTL_MCLK); 357 DELAY(1); 358 359 /* 360 * Turn off xmit. 361 */ 362 MII_CLR(STE_PHYCTL_MDIR); 363 364 return(0); 365 } 366 367 static int ste_miibus_readreg(dev, phy, reg) 368 device_t dev; 369 int phy, reg; 370 { 371 struct ste_softc *sc; 372 struct ste_mii_frame frame; 373 374 sc = device_get_softc(dev); 375 376 if ( sc->ste_one_phy && phy != 0 ) 377 return (0); 378 379 bzero((char *)&frame, sizeof(frame)); 380 381 frame.mii_phyaddr = phy; 382 frame.mii_regaddr = reg; 383 ste_mii_readreg(sc, &frame); 384 385 return(frame.mii_data); 386 } 387 388 static int ste_miibus_writereg(dev, phy, reg, data) 389 device_t dev; 390 int phy, reg, data; 391 { 392 struct ste_softc *sc; 393 struct ste_mii_frame frame; 394 395 sc = device_get_softc(dev); 396 bzero((char *)&frame, sizeof(frame)); 397 398 frame.mii_phyaddr = phy; 399 frame.mii_regaddr = reg; 400 frame.mii_data = data; 401 402 ste_mii_writereg(sc, &frame); 403 404 return(0); 405 } 406 407 static void ste_miibus_statchg(dev) 408 device_t dev; 409 { 410 struct ste_softc *sc; 411 struct mii_data *mii; 412 int i; 413 414 sc = device_get_softc(dev); 415 mii = device_get_softc(sc->ste_miibus); 416 417 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 418 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 419 } else { 420 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 421 } 422 423 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 424 STE_ASICCTL_TX_RESET); 425 for (i = 0; i < STE_TIMEOUT; i++) { 426 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 427 break; 428 } 429 if (i == STE_TIMEOUT) 430 if_printf(&sc->arpcom.ac_if, "rx reset never completed\n"); 431 432 return; 433 } 434 435 static int ste_ifmedia_upd(ifp) 436 struct ifnet *ifp; 437 { 438 struct ste_softc *sc; 439 struct mii_data *mii; 440 441 sc = ifp->if_softc; 442 mii = device_get_softc(sc->ste_miibus); 443 sc->ste_link = 0; 444 if (mii->mii_instance) { 445 struct mii_softc *miisc; 446 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 447 miisc = LIST_NEXT(miisc, mii_list)) 448 mii_phy_reset(miisc); 449 } 450 mii_mediachg(mii); 451 452 return(0); 453 } 454 455 static void ste_ifmedia_sts(ifp, ifmr) 456 struct ifnet *ifp; 457 struct ifmediareq *ifmr; 458 { 459 struct ste_softc *sc; 460 struct mii_data *mii; 461 462 sc = ifp->if_softc; 463 mii = device_get_softc(sc->ste_miibus); 464 465 mii_pollstat(mii); 466 ifmr->ifm_active = mii->mii_media_active; 467 ifmr->ifm_status = mii->mii_media_status; 468 469 return; 470 } 471 472 static void ste_wait(sc) 473 struct ste_softc *sc; 474 { 475 int i; 476 477 for (i = 0; i < STE_TIMEOUT; i++) { 478 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 479 break; 480 } 481 482 if (i == STE_TIMEOUT) 483 if_printf(&sc->arpcom.ac_if, "command never completed!\n"); 484 485 return; 486 } 487 488 /* 489 * The EEPROM is slow: give it time to come ready after issuing 490 * it a command. 491 */ 492 static int ste_eeprom_wait(sc) 493 struct ste_softc *sc; 494 { 495 int i; 496 497 DELAY(1000); 498 499 for (i = 0; i < 100; i++) { 500 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 501 DELAY(1000); 502 else 503 break; 504 } 505 506 if (i == 100) { 507 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 508 return(1); 509 } 510 511 return(0); 512 } 513 514 /* 515 * Read a sequence of words from the EEPROM. Note that ethernet address 516 * data is stored in the EEPROM in network byte order. 517 */ 518 static int ste_read_eeprom(sc, dest, off, cnt, swap) 519 struct ste_softc *sc; 520 caddr_t dest; 521 int off; 522 int cnt; 523 int swap; 524 { 525 int err = 0, i; 526 u_int16_t word = 0, *ptr; 527 528 if (ste_eeprom_wait(sc)) 529 return(1); 530 531 for (i = 0; i < cnt; i++) { 532 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 533 err = ste_eeprom_wait(sc); 534 if (err) 535 break; 536 word = CSR_READ_2(sc, STE_EEPROM_DATA); 537 ptr = (u_int16_t *)(dest + (i * 2)); 538 if (swap) 539 *ptr = ntohs(word); 540 else 541 *ptr = word; 542 } 543 544 return(err ? 1 : 0); 545 } 546 547 static void ste_setmulti(sc) 548 struct ste_softc *sc; 549 { 550 struct ifnet *ifp; 551 int h = 0; 552 u_int32_t hashes[2] = { 0, 0 }; 553 struct ifmultiaddr *ifma; 554 555 ifp = &sc->arpcom.ac_if; 556 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 557 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 558 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 559 return; 560 } 561 562 /* first, zot all the existing hash bits */ 563 CSR_WRITE_2(sc, STE_MAR0, 0); 564 CSR_WRITE_2(sc, STE_MAR1, 0); 565 CSR_WRITE_2(sc, STE_MAR2, 0); 566 CSR_WRITE_2(sc, STE_MAR3, 0); 567 568 /* now program new ones */ 569 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 570 if (ifma->ifma_addr->sa_family != AF_LINK) 571 continue; 572 h = ether_crc32_be( 573 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 574 ETHER_ADDR_LEN) & 0x3f; 575 if (h < 32) 576 hashes[0] |= (1 << h); 577 else 578 hashes[1] |= (1 << (h - 32)); 579 } 580 581 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 582 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 583 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 584 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 585 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 586 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 587 588 return; 589 } 590 591 static void ste_intr(xsc) 592 void *xsc; 593 { 594 struct ste_softc *sc; 595 struct ifnet *ifp; 596 u_int16_t status; 597 598 sc = xsc; 599 ifp = &sc->arpcom.ac_if; 600 601 /* See if this is really our interrupt. */ 602 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 603 return; 604 605 for (;;) { 606 status = CSR_READ_2(sc, STE_ISR_ACK); 607 608 if (!(status & STE_INTRS)) 609 break; 610 611 if (status & STE_ISR_RX_DMADONE) 612 ste_rxeof(sc); 613 614 if (status & STE_ISR_TX_DMADONE) 615 ste_txeof(sc); 616 617 if (status & STE_ISR_TX_DONE) 618 ste_txeoc(sc); 619 620 if (status & STE_ISR_STATS_OFLOW) { 621 callout_stop(&sc->ste_stat_timer); 622 ste_stats_update(sc); 623 } 624 625 if (status & STE_ISR_LINKEVENT) 626 mii_pollstat(device_get_softc(sc->ste_miibus)); 627 628 if (status & STE_ISR_HOSTERR) { 629 ste_reset(sc); 630 ste_init(sc); 631 } 632 } 633 634 /* Re-enable interrupts */ 635 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 636 637 if (!ifq_is_empty(&ifp->if_snd)) 638 ste_start(ifp); 639 640 return; 641 } 642 643 /* 644 * A frame has been uploaded: pass the resulting mbuf chain up to 645 * the higher level protocols. 646 */ 647 static void ste_rxeof(sc) 648 struct ste_softc *sc; 649 { 650 struct mbuf *m; 651 struct ifnet *ifp; 652 struct ste_chain_onefrag *cur_rx; 653 int total_len = 0, count=0; 654 u_int32_t rxstat; 655 656 ifp = &sc->arpcom.ac_if; 657 658 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 659 & STE_RXSTAT_DMADONE) { 660 if ((STE_RX_LIST_CNT - count) < 3) { 661 break; 662 } 663 664 cur_rx = sc->ste_cdata.ste_rx_head; 665 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 666 667 /* 668 * If an error occurs, update stats, clear the 669 * status word and leave the mbuf cluster in place: 670 * it should simply get re-used next time this descriptor 671 * comes up in the ring. 672 */ 673 if (rxstat & STE_RXSTAT_FRAME_ERR) { 674 ifp->if_ierrors++; 675 cur_rx->ste_ptr->ste_status = 0; 676 continue; 677 } 678 679 /* 680 * If there error bit was not set, the upload complete 681 * bit should be set which means we have a valid packet. 682 * If not, something truly strange has happened. 683 */ 684 if (!(rxstat & STE_RXSTAT_DMADONE)) { 685 if_printf(ifp, "bad receive status -- packet dropped"); 686 ifp->if_ierrors++; 687 cur_rx->ste_ptr->ste_status = 0; 688 continue; 689 } 690 691 /* No errors; receive the packet. */ 692 m = cur_rx->ste_mbuf; 693 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 694 695 /* 696 * Try to conjure up a new mbuf cluster. If that 697 * fails, it means we have an out of memory condition and 698 * should leave the buffer in place and continue. This will 699 * result in a lost packet, but there's little else we 700 * can do in this situation. 701 */ 702 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 703 ifp->if_ierrors++; 704 cur_rx->ste_ptr->ste_status = 0; 705 continue; 706 } 707 708 ifp->if_ipackets++; 709 m->m_pkthdr.rcvif = ifp; 710 m->m_pkthdr.len = m->m_len = total_len; 711 712 ifp->if_input(ifp, m); 713 714 cur_rx->ste_ptr->ste_status = 0; 715 count++; 716 } 717 718 return; 719 } 720 721 static void ste_txeoc(sc) 722 struct ste_softc *sc; 723 { 724 u_int8_t txstat; 725 struct ifnet *ifp; 726 727 ifp = &sc->arpcom.ac_if; 728 729 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 730 STE_TXSTATUS_TXDONE) { 731 if (txstat & STE_TXSTATUS_UNDERRUN || 732 txstat & STE_TXSTATUS_EXCESSCOLLS || 733 txstat & STE_TXSTATUS_RECLAIMERR) { 734 ifp->if_oerrors++; 735 if_printf(ifp, "transmission error: %x\n", txstat); 736 737 ste_reset(sc); 738 ste_init(sc); 739 740 if (txstat & STE_TXSTATUS_UNDERRUN && 741 sc->ste_tx_thresh < STE_PACKET_SIZE) { 742 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 743 if_printf(ifp, "tx underrun, increasing tx" 744 " start threshold to %d bytes\n", 745 sc->ste_tx_thresh); 746 } 747 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 748 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 749 (STE_PACKET_SIZE >> 4)); 750 } 751 ste_init(sc); 752 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 753 } 754 755 return; 756 } 757 758 static void ste_txeof(sc) 759 struct ste_softc *sc; 760 { 761 struct ste_chain *cur_tx = NULL; 762 struct ifnet *ifp; 763 int idx; 764 765 ifp = &sc->arpcom.ac_if; 766 767 idx = sc->ste_cdata.ste_tx_cons; 768 while(idx != sc->ste_cdata.ste_tx_prod) { 769 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 770 771 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 772 break; 773 774 if (cur_tx->ste_mbuf != NULL) { 775 m_freem(cur_tx->ste_mbuf); 776 cur_tx->ste_mbuf = NULL; 777 } 778 779 ifp->if_opackets++; 780 781 sc->ste_cdata.ste_tx_cnt--; 782 STE_INC(idx, STE_TX_LIST_CNT); 783 ifp->if_timer = 0; 784 } 785 786 sc->ste_cdata.ste_tx_cons = idx; 787 788 if (cur_tx != NULL) 789 ifp->if_flags &= ~IFF_OACTIVE; 790 791 return; 792 } 793 794 static void ste_stats_update(xsc) 795 void *xsc; 796 { 797 struct ste_softc *sc; 798 struct ifnet *ifp; 799 struct mii_data *mii; 800 801 sc = xsc; 802 ifp = &sc->arpcom.ac_if; 803 mii = device_get_softc(sc->ste_miibus); 804 805 lwkt_serialize_enter(ifp->if_serializer); 806 807 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 808 + CSR_READ_1(sc, STE_MULTI_COLLS) 809 + CSR_READ_1(sc, STE_SINGLE_COLLS); 810 811 if (!sc->ste_link) { 812 mii_pollstat(mii); 813 if (mii->mii_media_status & IFM_ACTIVE && 814 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 815 sc->ste_link++; 816 /* 817 * we don't get a call-back on re-init so do it 818 * otherwise we get stuck in the wrong link state 819 */ 820 ste_miibus_statchg(sc->ste_dev); 821 if (!ifq_is_empty(&ifp->if_snd)) 822 ste_start(ifp); 823 } 824 } 825 826 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 827 lwkt_serialize_exit(ifp->if_serializer); 828 } 829 830 831 /* 832 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 833 * IDs against our list and return a device name if we find a match. 834 */ 835 static int ste_probe(dev) 836 device_t dev; 837 { 838 struct ste_type *t; 839 840 t = ste_devs; 841 842 while(t->ste_name != NULL) { 843 if ((pci_get_vendor(dev) == t->ste_vid) && 844 (pci_get_device(dev) == t->ste_did)) { 845 device_set_desc(dev, t->ste_name); 846 return(0); 847 } 848 t++; 849 } 850 851 return(ENXIO); 852 } 853 854 /* 855 * Attach the interface. Allocate softc structures, do ifmedia 856 * setup and ethernet/BPF attach. 857 */ 858 static int ste_attach(dev) 859 device_t dev; 860 { 861 struct ste_softc *sc; 862 struct ifnet *ifp; 863 int error = 0, rid; 864 uint8_t eaddr[ETHER_ADDR_LEN]; 865 866 sc = device_get_softc(dev); 867 sc->ste_dev = dev; 868 869 /* 870 * Only use one PHY since this chip reports multiple 871 * Note on the DFE-550 the PHY is at 1 on the DFE-580 872 * it is at 0 & 1. It is rev 0x12. 873 */ 874 if (pci_get_vendor(dev) == DL_VENDORID && 875 pci_get_device(dev) == DL_DEVICEID_550TX && 876 pci_get_revid(dev) == 0x12 ) 877 sc->ste_one_phy = 1; 878 879 /* 880 * Handle power management nonsense. 881 */ 882 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 883 u_int32_t iobase, membase, irq; 884 885 /* Save important PCI config data. */ 886 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 887 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 888 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 889 890 /* Reset the power state. */ 891 device_printf(dev, "chip is in D%d power mode " 892 "-- setting to D0\n", pci_get_powerstate(dev)); 893 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 894 895 /* Restore PCI config data. */ 896 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 897 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 898 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 899 } 900 901 /* 902 * Map control/status registers. 903 */ 904 pci_enable_busmaster(dev); 905 906 rid = STE_RID; 907 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 908 909 if (sc->ste_res == NULL) { 910 device_printf(dev, "couldn't map ports/memory\n"); 911 error = ENXIO; 912 goto fail; 913 } 914 915 sc->ste_btag = rman_get_bustag(sc->ste_res); 916 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 917 918 rid = 0; 919 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 920 RF_SHAREABLE | RF_ACTIVE); 921 922 if (sc->ste_irq == NULL) { 923 device_printf(dev, "couldn't map interrupt\n"); 924 error = ENXIO; 925 goto fail; 926 } 927 928 callout_init(&sc->ste_stat_timer); 929 930 ifp = &sc->arpcom.ac_if; 931 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 932 933 /* Reset the adapter. */ 934 ste_reset(sc); 935 936 /* 937 * Get station address from the EEPROM. 938 */ 939 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, 3, 0)) { 940 device_printf(dev, "failed to read station address\n"); 941 error = ENXIO; 942 goto fail; 943 } 944 945 /* Allocate the descriptor queues. */ 946 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 947 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 948 949 if (sc->ste_ldata == NULL) { 950 device_printf(dev, "no memory for list buffers!\n"); 951 error = ENXIO; 952 goto fail; 953 } 954 955 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 956 957 /* Do MII setup. */ 958 if (mii_phy_probe(dev, &sc->ste_miibus, 959 ste_ifmedia_upd, ste_ifmedia_sts)) { 960 device_printf(dev, "MII without any phy!\n"); 961 error = ENXIO; 962 goto fail; 963 } 964 965 ifp->if_softc = sc; 966 ifp->if_mtu = ETHERMTU; 967 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 968 ifp->if_ioctl = ste_ioctl; 969 ifp->if_start = ste_start; 970 ifp->if_watchdog = ste_watchdog; 971 ifp->if_init = ste_init; 972 ifp->if_baudrate = 10000000; 973 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1); 974 ifq_set_ready(&ifp->if_snd); 975 976 sc->ste_tx_thresh = STE_TXSTART_THRESH; 977 978 /* 979 * Call MI attach routine. 980 */ 981 ether_ifattach(ifp, eaddr, NULL); 982 983 /* 984 * Tell the upper layer(s) we support long frames. 985 */ 986 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 987 988 error = bus_setup_intr(dev, sc->ste_irq, INTR_NETSAFE, 989 ste_intr, sc, &sc->ste_intrhand, 990 ifp->if_serializer); 991 if (error) { 992 device_printf(dev, "couldn't set up irq\n"); 993 ether_ifdetach(ifp); 994 goto fail; 995 } 996 997 return 0; 998 999 fail: 1000 ste_detach(dev); 1001 return(error); 1002 } 1003 1004 static int ste_detach(dev) 1005 device_t dev; 1006 { 1007 struct ste_softc *sc; 1008 struct ifnet *ifp; 1009 1010 sc = device_get_softc(dev); 1011 ifp = &sc->arpcom.ac_if; 1012 lwkt_serialize_enter(ifp->if_serializer); 1013 1014 if (device_is_attached(dev)) { 1015 if (bus_child_present(dev)) 1016 ste_stop(sc); 1017 ether_ifdetach(ifp); 1018 } 1019 if (sc->ste_miibus != NULL) 1020 device_delete_child(dev, sc->ste_miibus); 1021 bus_generic_detach(dev); 1022 1023 if (sc->ste_intrhand != NULL) 1024 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1025 1026 if (sc->ste_irq != NULL) 1027 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1028 if (sc->ste_res != NULL) 1029 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1030 if (sc->ste_ldata != NULL) { 1031 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1032 M_DEVBUF); 1033 } 1034 lwkt_serialize_exit(ifp->if_serializer); 1035 1036 return(0); 1037 } 1038 1039 static int ste_newbuf(sc, c, m) 1040 struct ste_softc *sc; 1041 struct ste_chain_onefrag *c; 1042 struct mbuf *m; 1043 { 1044 struct mbuf *m_new = NULL; 1045 1046 if (m == NULL) { 1047 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1048 if (m_new == NULL) 1049 return(ENOBUFS); 1050 MCLGET(m_new, MB_DONTWAIT); 1051 if (!(m_new->m_flags & M_EXT)) { 1052 m_freem(m_new); 1053 return(ENOBUFS); 1054 } 1055 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1056 } else { 1057 m_new = m; 1058 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1059 m_new->m_data = m_new->m_ext.ext_buf; 1060 } 1061 1062 m_adj(m_new, ETHER_ALIGN); 1063 1064 c->ste_mbuf = m_new; 1065 c->ste_ptr->ste_status = 0; 1066 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1067 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1068 1069 return(0); 1070 } 1071 1072 static int ste_init_rx_list(sc) 1073 struct ste_softc *sc; 1074 { 1075 struct ste_chain_data *cd; 1076 struct ste_list_data *ld; 1077 int i; 1078 1079 cd = &sc->ste_cdata; 1080 ld = sc->ste_ldata; 1081 1082 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1083 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1084 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1085 return(ENOBUFS); 1086 if (i == (STE_RX_LIST_CNT - 1)) { 1087 cd->ste_rx_chain[i].ste_next = 1088 &cd->ste_rx_chain[0]; 1089 ld->ste_rx_list[i].ste_next = 1090 vtophys(&ld->ste_rx_list[0]); 1091 } else { 1092 cd->ste_rx_chain[i].ste_next = 1093 &cd->ste_rx_chain[i + 1]; 1094 ld->ste_rx_list[i].ste_next = 1095 vtophys(&ld->ste_rx_list[i + 1]); 1096 } 1097 ld->ste_rx_list[i].ste_status = 0; 1098 } 1099 1100 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1101 1102 return(0); 1103 } 1104 1105 static void ste_init_tx_list(sc) 1106 struct ste_softc *sc; 1107 { 1108 struct ste_chain_data *cd; 1109 struct ste_list_data *ld; 1110 int i; 1111 1112 cd = &sc->ste_cdata; 1113 ld = sc->ste_ldata; 1114 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1115 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1116 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1117 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1118 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1119 if (i == (STE_TX_LIST_CNT - 1)) 1120 cd->ste_tx_chain[i].ste_next = 1121 &cd->ste_tx_chain[0]; 1122 else 1123 cd->ste_tx_chain[i].ste_next = 1124 &cd->ste_tx_chain[i + 1]; 1125 if (i == 0) 1126 cd->ste_tx_chain[i].ste_prev = 1127 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1128 else 1129 cd->ste_tx_chain[i].ste_prev = 1130 &cd->ste_tx_chain[i - 1]; 1131 } 1132 1133 cd->ste_tx_prod = 0; 1134 cd->ste_tx_cons = 0; 1135 cd->ste_tx_cnt = 0; 1136 1137 return; 1138 } 1139 1140 static void ste_init(xsc) 1141 void *xsc; 1142 { 1143 struct ste_softc *sc; 1144 int i; 1145 struct ifnet *ifp; 1146 struct mii_data *mii; 1147 1148 sc = xsc; 1149 ifp = &sc->arpcom.ac_if; 1150 mii = device_get_softc(sc->ste_miibus); 1151 1152 ste_stop(sc); 1153 1154 /* Init our MAC address */ 1155 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1156 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1157 } 1158 1159 /* Init RX list */ 1160 if (ste_init_rx_list(sc) == ENOBUFS) { 1161 if_printf(ifp, "initialization failed: no " 1162 "memory for RX buffers\n"); 1163 ste_stop(sc); 1164 return; 1165 } 1166 1167 /* Set RX polling interval */ 1168 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1169 1170 /* Init TX descriptors */ 1171 ste_init_tx_list(sc); 1172 1173 /* Set the TX freethresh value */ 1174 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1175 1176 /* Set the TX start threshold for best performance. */ 1177 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1178 1179 /* Set the TX reclaim threshold. */ 1180 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1181 1182 /* Set up the RX filter. */ 1183 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1184 1185 /* If we want promiscuous mode, set the allframes bit. */ 1186 if (ifp->if_flags & IFF_PROMISC) { 1187 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1188 } else { 1189 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1190 } 1191 1192 /* Set capture broadcast bit to accept broadcast frames. */ 1193 if (ifp->if_flags & IFF_BROADCAST) { 1194 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1195 } else { 1196 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1197 } 1198 1199 ste_setmulti(sc); 1200 1201 /* Load the address of the RX list. */ 1202 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1203 ste_wait(sc); 1204 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1205 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1206 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1207 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1208 1209 /* Set TX polling interval (defer until we TX first packet */ 1210 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1211 1212 /* Load address of the TX list */ 1213 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1214 ste_wait(sc); 1215 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1216 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1217 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1218 ste_wait(sc); 1219 sc->ste_tx_prev_idx=-1; 1220 1221 /* Enable receiver and transmitter */ 1222 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1223 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1224 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1225 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1226 1227 /* Enable stats counters. */ 1228 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1229 1230 /* Enable interrupts. */ 1231 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1232 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1233 1234 /* Accept VLAN length packets */ 1235 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1236 1237 ste_ifmedia_upd(ifp); 1238 1239 ifp->if_flags |= IFF_RUNNING; 1240 ifp->if_flags &= ~IFF_OACTIVE; 1241 1242 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 1243 } 1244 1245 static void ste_stop(sc) 1246 struct ste_softc *sc; 1247 { 1248 int i; 1249 struct ifnet *ifp; 1250 1251 ifp = &sc->arpcom.ac_if; 1252 1253 callout_stop(&sc->ste_stat_timer); 1254 1255 CSR_WRITE_2(sc, STE_IMR, 0); 1256 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1257 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1258 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1259 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1260 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1261 ste_wait(sc); 1262 /* 1263 * Try really hard to stop the RX engine or under heavy RX 1264 * data chip will write into de-allocated memory. 1265 */ 1266 ste_reset(sc); 1267 1268 sc->ste_link = 0; 1269 1270 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1271 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1272 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1273 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1274 } 1275 } 1276 1277 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1278 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1279 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1280 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1281 } 1282 } 1283 1284 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1285 1286 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1287 1288 return; 1289 } 1290 1291 static void ste_reset(sc) 1292 struct ste_softc *sc; 1293 { 1294 int i; 1295 1296 STE_SETBIT4(sc, STE_ASICCTL, 1297 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1298 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1299 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1300 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1301 STE_ASICCTL_EXTRESET_RESET); 1302 1303 DELAY(100000); 1304 1305 for (i = 0; i < STE_TIMEOUT; i++) { 1306 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1307 break; 1308 } 1309 1310 if (i == STE_TIMEOUT) 1311 if_printf(&sc->arpcom.ac_if, "global reset never completed\n"); 1312 1313 return; 1314 } 1315 1316 static int ste_ioctl(ifp, command, data, cr) 1317 struct ifnet *ifp; 1318 u_long command; 1319 caddr_t data; 1320 struct ucred *cr; 1321 { 1322 struct ste_softc *sc; 1323 struct ifreq *ifr; 1324 struct mii_data *mii; 1325 int error = 0; 1326 1327 sc = ifp->if_softc; 1328 ifr = (struct ifreq *)data; 1329 1330 switch(command) { 1331 case SIOCSIFFLAGS: 1332 if (ifp->if_flags & IFF_UP) { 1333 if (ifp->if_flags & IFF_RUNNING && 1334 ifp->if_flags & IFF_PROMISC && 1335 !(sc->ste_if_flags & IFF_PROMISC)) { 1336 STE_SETBIT1(sc, STE_RX_MODE, 1337 STE_RXMODE_PROMISC); 1338 } else if (ifp->if_flags & IFF_RUNNING && 1339 !(ifp->if_flags & IFF_PROMISC) && 1340 sc->ste_if_flags & IFF_PROMISC) { 1341 STE_CLRBIT1(sc, STE_RX_MODE, 1342 STE_RXMODE_PROMISC); 1343 } 1344 if (!(ifp->if_flags & IFF_RUNNING)) { 1345 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1346 ste_init(sc); 1347 } 1348 } else { 1349 if (ifp->if_flags & IFF_RUNNING) 1350 ste_stop(sc); 1351 } 1352 sc->ste_if_flags = ifp->if_flags; 1353 error = 0; 1354 break; 1355 case SIOCADDMULTI: 1356 case SIOCDELMULTI: 1357 ste_setmulti(sc); 1358 error = 0; 1359 break; 1360 case SIOCGIFMEDIA: 1361 case SIOCSIFMEDIA: 1362 mii = device_get_softc(sc->ste_miibus); 1363 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1364 break; 1365 default: 1366 error = ether_ioctl(ifp, command, data); 1367 break; 1368 } 1369 return(error); 1370 } 1371 1372 static int ste_encap(sc, c, m_head) 1373 struct ste_softc *sc; 1374 struct ste_chain *c; 1375 struct mbuf *m_head; 1376 { 1377 int frag = 0; 1378 struct ste_frag *f = NULL; 1379 struct mbuf *m; 1380 struct ste_desc *d; 1381 int total_len = 0; 1382 1383 d = c->ste_ptr; 1384 d->ste_ctl = 0; 1385 1386 encap_retry: 1387 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1388 if (m->m_len != 0) { 1389 if (frag == STE_MAXFRAGS) 1390 break; 1391 total_len += m->m_len; 1392 f = &d->ste_frags[frag]; 1393 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1394 f->ste_len = m->m_len; 1395 frag++; 1396 } 1397 } 1398 1399 if (m != NULL) { 1400 struct mbuf *mn; 1401 1402 /* 1403 * We ran out of segments. We have to recopy this 1404 * mbuf chain first. Bail out if we can't get the 1405 * new buffers. Code borrowed from if_fxp.c. 1406 */ 1407 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1408 if (mn == NULL) { 1409 m_freem(m_head); 1410 return ENOMEM; 1411 } 1412 if (m_head->m_pkthdr.len > MHLEN) { 1413 MCLGET(mn, MB_DONTWAIT); 1414 if ((mn->m_flags & M_EXT) == 0) { 1415 m_freem(mn); 1416 m_freem(m_head); 1417 return ENOMEM; 1418 } 1419 } 1420 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1421 mtod(mn, caddr_t)); 1422 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1423 m_freem(m_head); 1424 m_head = mn; 1425 goto encap_retry; 1426 } 1427 1428 c->ste_mbuf = m_head; 1429 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1430 d->ste_ctl = 1; 1431 1432 return(0); 1433 } 1434 1435 static void ste_start(ifp) 1436 struct ifnet *ifp; 1437 { 1438 struct ste_softc *sc; 1439 struct mbuf *m_head = NULL; 1440 struct ste_chain *cur_tx = NULL; 1441 int idx; 1442 1443 sc = ifp->if_softc; 1444 1445 if (!sc->ste_link) 1446 return; 1447 1448 if (ifp->if_flags & IFF_OACTIVE) 1449 return; 1450 1451 idx = sc->ste_cdata.ste_tx_prod; 1452 1453 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1454 1455 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1456 ifp->if_flags |= IFF_OACTIVE; 1457 break; 1458 } 1459 1460 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1461 if (m_head == NULL) 1462 break; 1463 1464 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1465 1466 if (ste_encap(sc, cur_tx, m_head) != 0) 1467 break; 1468 1469 cur_tx->ste_ptr->ste_next = 0; 1470 1471 if(sc->ste_tx_prev_idx < 0){ 1472 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1473 /* Load address of the TX list */ 1474 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1475 ste_wait(sc); 1476 1477 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1478 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1479 1480 /* Set TX polling interval to start TX engine */ 1481 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1482 1483 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1484 ste_wait(sc); 1485 }else{ 1486 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1487 sc->ste_cdata.ste_tx_chain[ 1488 sc->ste_tx_prev_idx].ste_ptr->ste_next 1489 = cur_tx->ste_phys; 1490 } 1491 1492 sc->ste_tx_prev_idx=idx; 1493 1494 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1495 1496 STE_INC(idx, STE_TX_LIST_CNT); 1497 sc->ste_cdata.ste_tx_cnt++; 1498 ifp->if_timer = 5; 1499 sc->ste_cdata.ste_tx_prod = idx; 1500 } 1501 1502 return; 1503 } 1504 1505 static void ste_watchdog(ifp) 1506 struct ifnet *ifp; 1507 { 1508 struct ste_softc *sc; 1509 1510 sc = ifp->if_softc; 1511 1512 ifp->if_oerrors++; 1513 if_printf(ifp, "watchdog timeout\n"); 1514 1515 ste_txeoc(sc); 1516 ste_txeof(sc); 1517 ste_rxeof(sc); 1518 ste_reset(sc); 1519 ste_init(sc); 1520 1521 if (!ifq_is_empty(&ifp->if_snd)) 1522 ste_start(ifp); 1523 1524 return; 1525 } 1526 1527 static void ste_shutdown(dev) 1528 device_t dev; 1529 { 1530 struct ste_softc *sc; 1531 1532 sc = device_get_softc(dev); 1533 1534 ste_stop(sc); 1535 1536 return; 1537 } 1538