1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.25 2005/06/09 19:29:00 joerg Exp $ 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/thread2.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/vlan/if_vlan_var.h> 52 53 #include <net/bpf.h> 54 55 #include <vm/vm.h> /* for vtophys */ 56 #include <vm/pmap.h> /* for vtophys */ 57 #include <machine/bus_memio.h> 58 #include <machine/bus_pio.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/bus.h> 62 #include <sys/rman.h> 63 64 #include "../mii_layer/mii.h" 65 #include "../mii_layer/miivar.h" 66 67 #include <bus/pci/pcireg.h> 68 #include <bus/pci/pcivar.h> 69 70 /* "controller miibus0" required. See GENERIC if you get errors here. */ 71 #include "miibus_if.h" 72 73 #define STE_USEIOSPACE 74 75 #include "if_stereg.h" 76 77 /* 78 * Various supported device vendors/types and their names. 79 */ 80 static struct ste_type ste_devs[] = { 81 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 82 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 83 { 0, 0, NULL } 84 }; 85 86 static int ste_probe (device_t); 87 static int ste_attach (device_t); 88 static int ste_detach (device_t); 89 static void ste_init (void *); 90 static void ste_intr (void *); 91 static void ste_rxeof (struct ste_softc *); 92 static void ste_txeoc (struct ste_softc *); 93 static void ste_txeof (struct ste_softc *); 94 static void ste_stats_update (void *); 95 static void ste_stop (struct ste_softc *); 96 static void ste_reset (struct ste_softc *); 97 static int ste_ioctl (struct ifnet *, u_long, caddr_t, 98 struct ucred *); 99 static int ste_encap (struct ste_softc *, struct ste_chain *, 100 struct mbuf *); 101 static void ste_start (struct ifnet *); 102 static void ste_watchdog (struct ifnet *); 103 static void ste_shutdown (device_t); 104 static int ste_newbuf (struct ste_softc *, 105 struct ste_chain_onefrag *, 106 struct mbuf *); 107 static int ste_ifmedia_upd (struct ifnet *); 108 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 109 110 static void ste_mii_sync (struct ste_softc *); 111 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 112 static int ste_mii_readreg (struct ste_softc *, 113 struct ste_mii_frame *); 114 static int ste_mii_writereg (struct ste_softc *, 115 struct ste_mii_frame *); 116 static int ste_miibus_readreg (device_t, int, int); 117 static int ste_miibus_writereg (device_t, int, int, int); 118 static void ste_miibus_statchg (device_t); 119 120 static int ste_eeprom_wait (struct ste_softc *); 121 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 122 int, int); 123 static void ste_wait (struct ste_softc *); 124 static void ste_setmulti (struct ste_softc *); 125 static int ste_init_rx_list (struct ste_softc *); 126 static void ste_init_tx_list (struct ste_softc *); 127 128 #ifdef STE_USEIOSPACE 129 #define STE_RES SYS_RES_IOPORT 130 #define STE_RID STE_PCI_LOIO 131 #else 132 #define STE_RES SYS_RES_MEMORY 133 #define STE_RID STE_PCI_LOMEM 134 #endif 135 136 static device_method_t ste_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, ste_probe), 139 DEVMETHOD(device_attach, ste_attach), 140 DEVMETHOD(device_detach, ste_detach), 141 DEVMETHOD(device_shutdown, ste_shutdown), 142 143 /* bus interface */ 144 DEVMETHOD(bus_print_child, bus_generic_print_child), 145 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 146 147 /* MII interface */ 148 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 149 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 150 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 151 152 { 0, 0 } 153 }; 154 155 static driver_t ste_driver = { 156 "ste", 157 ste_methods, 158 sizeof(struct ste_softc) 159 }; 160 161 static devclass_t ste_devclass; 162 163 DECLARE_DUMMY_MODULE(if_ste); 164 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 165 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167 #define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 169 170 #define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 172 173 #define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 175 176 #define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 178 179 #define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 181 182 #define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 184 185 186 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189 /* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192 static void ste_mii_sync(sc) 193 struct ste_softc *sc; 194 { 195 int i; 196 197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 198 199 for (i = 0; i < 32; i++) { 200 MII_SET(STE_PHYCTL_MCLK); 201 DELAY(1); 202 MII_CLR(STE_PHYCTL_MCLK); 203 DELAY(1); 204 } 205 206 return; 207 } 208 209 /* 210 * Clock a series of bits through the MII. 211 */ 212 static void ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216 { 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232 } 233 234 /* 235 * Read an PHY register through the MII. 236 */ 237 static int ste_mii_readreg(sc, frame) 238 struct ste_softc *sc; 239 struct ste_mii_frame *frame; 240 241 { 242 int i, ack; 243 244 crit_enter(); 245 246 /* 247 * Set up frame for RX. 248 */ 249 frame->mii_stdelim = STE_MII_STARTDELIM; 250 frame->mii_opcode = STE_MII_READOP; 251 frame->mii_turnaround = 0; 252 frame->mii_data = 0; 253 254 CSR_WRITE_2(sc, STE_PHYCTL, 0); 255 /* 256 * Turn on data xmit. 257 */ 258 MII_SET(STE_PHYCTL_MDIR); 259 260 ste_mii_sync(sc); 261 262 /* 263 * Send command/address info. 264 */ 265 ste_mii_send(sc, frame->mii_stdelim, 2); 266 ste_mii_send(sc, frame->mii_opcode, 2); 267 ste_mii_send(sc, frame->mii_phyaddr, 5); 268 ste_mii_send(sc, frame->mii_regaddr, 5); 269 270 /* Turn off xmit. */ 271 MII_CLR(STE_PHYCTL_MDIR); 272 273 /* Idle bit */ 274 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 275 DELAY(1); 276 MII_SET(STE_PHYCTL_MCLK); 277 DELAY(1); 278 279 /* Check for ack */ 280 MII_CLR(STE_PHYCTL_MCLK); 281 DELAY(1); 282 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 283 MII_SET(STE_PHYCTL_MCLK); 284 DELAY(1); 285 286 /* 287 * Now try reading data bits. If the ack failed, we still 288 * need to clock through 16 cycles to keep the PHY(s) in sync. 289 */ 290 if (ack) { 291 for(i = 0; i < 16; i++) { 292 MII_CLR(STE_PHYCTL_MCLK); 293 DELAY(1); 294 MII_SET(STE_PHYCTL_MCLK); 295 DELAY(1); 296 } 297 goto fail; 298 } 299 300 for (i = 0x8000; i; i >>= 1) { 301 MII_CLR(STE_PHYCTL_MCLK); 302 DELAY(1); 303 if (!ack) { 304 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 305 frame->mii_data |= i; 306 DELAY(1); 307 } 308 MII_SET(STE_PHYCTL_MCLK); 309 DELAY(1); 310 } 311 312 fail: 313 314 MII_CLR(STE_PHYCTL_MCLK); 315 DELAY(1); 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 319 crit_exit(); 320 321 if (ack) 322 return(1); 323 return(0); 324 } 325 326 /* 327 * Write to a PHY register through the MII. 328 */ 329 static int ste_mii_writereg(sc, frame) 330 struct ste_softc *sc; 331 struct ste_mii_frame *frame; 332 333 { 334 335 crit_enter(); 336 /* 337 * Set up frame for TX. 338 */ 339 340 frame->mii_stdelim = STE_MII_STARTDELIM; 341 frame->mii_opcode = STE_MII_WRITEOP; 342 frame->mii_turnaround = STE_MII_TURNAROUND; 343 344 /* 345 * Turn on data output. 346 */ 347 MII_SET(STE_PHYCTL_MDIR); 348 349 ste_mii_sync(sc); 350 351 ste_mii_send(sc, frame->mii_stdelim, 2); 352 ste_mii_send(sc, frame->mii_opcode, 2); 353 ste_mii_send(sc, frame->mii_phyaddr, 5); 354 ste_mii_send(sc, frame->mii_regaddr, 5); 355 ste_mii_send(sc, frame->mii_turnaround, 2); 356 ste_mii_send(sc, frame->mii_data, 16); 357 358 /* Idle bit. */ 359 MII_SET(STE_PHYCTL_MCLK); 360 DELAY(1); 361 MII_CLR(STE_PHYCTL_MCLK); 362 DELAY(1); 363 364 /* 365 * Turn off xmit. 366 */ 367 MII_CLR(STE_PHYCTL_MDIR); 368 369 crit_exit(); 370 371 return(0); 372 } 373 374 static int ste_miibus_readreg(dev, phy, reg) 375 device_t dev; 376 int phy, reg; 377 { 378 struct ste_softc *sc; 379 struct ste_mii_frame frame; 380 381 sc = device_get_softc(dev); 382 383 if ( sc->ste_one_phy && phy != 0 ) 384 return (0); 385 386 bzero((char *)&frame, sizeof(frame)); 387 388 frame.mii_phyaddr = phy; 389 frame.mii_regaddr = reg; 390 ste_mii_readreg(sc, &frame); 391 392 return(frame.mii_data); 393 } 394 395 static int ste_miibus_writereg(dev, phy, reg, data) 396 device_t dev; 397 int phy, reg, data; 398 { 399 struct ste_softc *sc; 400 struct ste_mii_frame frame; 401 402 sc = device_get_softc(dev); 403 bzero((char *)&frame, sizeof(frame)); 404 405 frame.mii_phyaddr = phy; 406 frame.mii_regaddr = reg; 407 frame.mii_data = data; 408 409 ste_mii_writereg(sc, &frame); 410 411 return(0); 412 } 413 414 static void ste_miibus_statchg(dev) 415 device_t dev; 416 { 417 struct ste_softc *sc; 418 struct mii_data *mii; 419 int i; 420 421 sc = device_get_softc(dev); 422 mii = device_get_softc(sc->ste_miibus); 423 424 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 425 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 426 } else { 427 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 428 } 429 430 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 431 STE_ASICCTL_TX_RESET); 432 for (i = 0; i < STE_TIMEOUT; i++) { 433 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 434 break; 435 } 436 if (i == STE_TIMEOUT) 437 if_printf(&sc->arpcom.ac_if, "rx reset never completed\n"); 438 439 return; 440 } 441 442 static int ste_ifmedia_upd(ifp) 443 struct ifnet *ifp; 444 { 445 struct ste_softc *sc; 446 struct mii_data *mii; 447 448 sc = ifp->if_softc; 449 mii = device_get_softc(sc->ste_miibus); 450 sc->ste_link = 0; 451 if (mii->mii_instance) { 452 struct mii_softc *miisc; 453 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 454 miisc = LIST_NEXT(miisc, mii_list)) 455 mii_phy_reset(miisc); 456 } 457 mii_mediachg(mii); 458 459 return(0); 460 } 461 462 static void ste_ifmedia_sts(ifp, ifmr) 463 struct ifnet *ifp; 464 struct ifmediareq *ifmr; 465 { 466 struct ste_softc *sc; 467 struct mii_data *mii; 468 469 sc = ifp->if_softc; 470 mii = device_get_softc(sc->ste_miibus); 471 472 mii_pollstat(mii); 473 ifmr->ifm_active = mii->mii_media_active; 474 ifmr->ifm_status = mii->mii_media_status; 475 476 return; 477 } 478 479 static void ste_wait(sc) 480 struct ste_softc *sc; 481 { 482 int i; 483 484 for (i = 0; i < STE_TIMEOUT; i++) { 485 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 486 break; 487 } 488 489 if (i == STE_TIMEOUT) 490 if_printf(&sc->arpcom.ac_if, "command never completed!\n"); 491 492 return; 493 } 494 495 /* 496 * The EEPROM is slow: give it time to come ready after issuing 497 * it a command. 498 */ 499 static int ste_eeprom_wait(sc) 500 struct ste_softc *sc; 501 { 502 int i; 503 504 DELAY(1000); 505 506 for (i = 0; i < 100; i++) { 507 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 508 DELAY(1000); 509 else 510 break; 511 } 512 513 if (i == 100) { 514 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 515 return(1); 516 } 517 518 return(0); 519 } 520 521 /* 522 * Read a sequence of words from the EEPROM. Note that ethernet address 523 * data is stored in the EEPROM in network byte order. 524 */ 525 static int ste_read_eeprom(sc, dest, off, cnt, swap) 526 struct ste_softc *sc; 527 caddr_t dest; 528 int off; 529 int cnt; 530 int swap; 531 { 532 int err = 0, i; 533 u_int16_t word = 0, *ptr; 534 535 if (ste_eeprom_wait(sc)) 536 return(1); 537 538 for (i = 0; i < cnt; i++) { 539 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 540 err = ste_eeprom_wait(sc); 541 if (err) 542 break; 543 word = CSR_READ_2(sc, STE_EEPROM_DATA); 544 ptr = (u_int16_t *)(dest + (i * 2)); 545 if (swap) 546 *ptr = ntohs(word); 547 else 548 *ptr = word; 549 } 550 551 return(err ? 1 : 0); 552 } 553 554 static void ste_setmulti(sc) 555 struct ste_softc *sc; 556 { 557 struct ifnet *ifp; 558 int h = 0; 559 u_int32_t hashes[2] = { 0, 0 }; 560 struct ifmultiaddr *ifma; 561 562 ifp = &sc->arpcom.ac_if; 563 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 564 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 565 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 566 return; 567 } 568 569 /* first, zot all the existing hash bits */ 570 CSR_WRITE_2(sc, STE_MAR0, 0); 571 CSR_WRITE_2(sc, STE_MAR1, 0); 572 CSR_WRITE_2(sc, STE_MAR2, 0); 573 CSR_WRITE_2(sc, STE_MAR3, 0); 574 575 /* now program new ones */ 576 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 577 ifma = ifma->ifma_link.le_next) { 578 if (ifma->ifma_addr->sa_family != AF_LINK) 579 continue; 580 h = ether_crc32_be( 581 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 582 ETHER_ADDR_LEN) & 0x3f; 583 if (h < 32) 584 hashes[0] |= (1 << h); 585 else 586 hashes[1] |= (1 << (h - 32)); 587 } 588 589 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 590 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 591 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 592 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 593 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 594 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 595 596 return; 597 } 598 599 static void ste_intr(xsc) 600 void *xsc; 601 { 602 struct ste_softc *sc; 603 struct ifnet *ifp; 604 u_int16_t status; 605 606 sc = xsc; 607 ifp = &sc->arpcom.ac_if; 608 609 /* See if this is really our interrupt. */ 610 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 611 return; 612 613 for (;;) { 614 status = CSR_READ_2(sc, STE_ISR_ACK); 615 616 if (!(status & STE_INTRS)) 617 break; 618 619 if (status & STE_ISR_RX_DMADONE) 620 ste_rxeof(sc); 621 622 if (status & STE_ISR_TX_DMADONE) 623 ste_txeof(sc); 624 625 if (status & STE_ISR_TX_DONE) 626 ste_txeoc(sc); 627 628 if (status & STE_ISR_STATS_OFLOW) { 629 callout_stop(&sc->ste_stat_timer); 630 ste_stats_update(sc); 631 } 632 633 if (status & STE_ISR_LINKEVENT) 634 mii_pollstat(device_get_softc(sc->ste_miibus)); 635 636 if (status & STE_ISR_HOSTERR) { 637 ste_reset(sc); 638 ste_init(sc); 639 } 640 } 641 642 /* Re-enable interrupts */ 643 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 644 645 if (!ifq_is_empty(&ifp->if_snd)) 646 ste_start(ifp); 647 648 return; 649 } 650 651 /* 652 * A frame has been uploaded: pass the resulting mbuf chain up to 653 * the higher level protocols. 654 */ 655 static void ste_rxeof(sc) 656 struct ste_softc *sc; 657 { 658 struct mbuf *m; 659 struct ifnet *ifp; 660 struct ste_chain_onefrag *cur_rx; 661 int total_len = 0, count=0; 662 u_int32_t rxstat; 663 664 ifp = &sc->arpcom.ac_if; 665 666 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 667 & STE_RXSTAT_DMADONE) { 668 if ((STE_RX_LIST_CNT - count) < 3) { 669 break; 670 } 671 672 cur_rx = sc->ste_cdata.ste_rx_head; 673 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 674 675 /* 676 * If an error occurs, update stats, clear the 677 * status word and leave the mbuf cluster in place: 678 * it should simply get re-used next time this descriptor 679 * comes up in the ring. 680 */ 681 if (rxstat & STE_RXSTAT_FRAME_ERR) { 682 ifp->if_ierrors++; 683 cur_rx->ste_ptr->ste_status = 0; 684 continue; 685 } 686 687 /* 688 * If there error bit was not set, the upload complete 689 * bit should be set which means we have a valid packet. 690 * If not, something truly strange has happened. 691 */ 692 if (!(rxstat & STE_RXSTAT_DMADONE)) { 693 if_printf(ifp, "bad receive status -- packet dropped"); 694 ifp->if_ierrors++; 695 cur_rx->ste_ptr->ste_status = 0; 696 continue; 697 } 698 699 /* No errors; receive the packet. */ 700 m = cur_rx->ste_mbuf; 701 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 702 703 /* 704 * Try to conjure up a new mbuf cluster. If that 705 * fails, it means we have an out of memory condition and 706 * should leave the buffer in place and continue. This will 707 * result in a lost packet, but there's little else we 708 * can do in this situation. 709 */ 710 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 711 ifp->if_ierrors++; 712 cur_rx->ste_ptr->ste_status = 0; 713 continue; 714 } 715 716 ifp->if_ipackets++; 717 m->m_pkthdr.rcvif = ifp; 718 m->m_pkthdr.len = m->m_len = total_len; 719 720 (*ifp->if_input)(ifp, m); 721 722 cur_rx->ste_ptr->ste_status = 0; 723 count++; 724 } 725 726 return; 727 } 728 729 static void ste_txeoc(sc) 730 struct ste_softc *sc; 731 { 732 u_int8_t txstat; 733 struct ifnet *ifp; 734 735 ifp = &sc->arpcom.ac_if; 736 737 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 738 STE_TXSTATUS_TXDONE) { 739 if (txstat & STE_TXSTATUS_UNDERRUN || 740 txstat & STE_TXSTATUS_EXCESSCOLLS || 741 txstat & STE_TXSTATUS_RECLAIMERR) { 742 ifp->if_oerrors++; 743 if_printf(ifp, "transmission error: %x\n", txstat); 744 745 ste_reset(sc); 746 ste_init(sc); 747 748 if (txstat & STE_TXSTATUS_UNDERRUN && 749 sc->ste_tx_thresh < STE_PACKET_SIZE) { 750 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 751 if_printf(ifp, "tx underrun, increasing tx" 752 " start threshold to %d bytes\n", 753 sc->ste_tx_thresh); 754 } 755 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 756 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 757 (STE_PACKET_SIZE >> 4)); 758 } 759 ste_init(sc); 760 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 761 } 762 763 return; 764 } 765 766 static void ste_txeof(sc) 767 struct ste_softc *sc; 768 { 769 struct ste_chain *cur_tx = NULL; 770 struct ifnet *ifp; 771 int idx; 772 773 ifp = &sc->arpcom.ac_if; 774 775 idx = sc->ste_cdata.ste_tx_cons; 776 while(idx != sc->ste_cdata.ste_tx_prod) { 777 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 778 779 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 780 break; 781 782 if (cur_tx->ste_mbuf != NULL) { 783 m_freem(cur_tx->ste_mbuf); 784 cur_tx->ste_mbuf = NULL; 785 } 786 787 ifp->if_opackets++; 788 789 sc->ste_cdata.ste_tx_cnt--; 790 STE_INC(idx, STE_TX_LIST_CNT); 791 ifp->if_timer = 0; 792 } 793 794 sc->ste_cdata.ste_tx_cons = idx; 795 796 if (cur_tx != NULL) 797 ifp->if_flags &= ~IFF_OACTIVE; 798 799 return; 800 } 801 802 static void ste_stats_update(xsc) 803 void *xsc; 804 { 805 struct ste_softc *sc; 806 struct ifnet *ifp; 807 struct mii_data *mii; 808 809 crit_enter(); 810 811 sc = xsc; 812 ifp = &sc->arpcom.ac_if; 813 mii = device_get_softc(sc->ste_miibus); 814 815 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 816 + CSR_READ_1(sc, STE_MULTI_COLLS) 817 + CSR_READ_1(sc, STE_SINGLE_COLLS); 818 819 if (!sc->ste_link) { 820 mii_pollstat(mii); 821 if (mii->mii_media_status & IFM_ACTIVE && 822 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 823 sc->ste_link++; 824 /* 825 * we don't get a call-back on re-init so do it 826 * otherwise we get stuck in the wrong link state 827 */ 828 ste_miibus_statchg(sc->ste_dev); 829 if (!ifq_is_empty(&ifp->if_snd)) 830 ste_start(ifp); 831 } 832 } 833 834 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 835 crit_exit(); 836 837 return; 838 } 839 840 841 /* 842 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 843 * IDs against our list and return a device name if we find a match. 844 */ 845 static int ste_probe(dev) 846 device_t dev; 847 { 848 struct ste_type *t; 849 850 t = ste_devs; 851 852 while(t->ste_name != NULL) { 853 if ((pci_get_vendor(dev) == t->ste_vid) && 854 (pci_get_device(dev) == t->ste_did)) { 855 device_set_desc(dev, t->ste_name); 856 return(0); 857 } 858 t++; 859 } 860 861 return(ENXIO); 862 } 863 864 /* 865 * Attach the interface. Allocate softc structures, do ifmedia 866 * setup and ethernet/BPF attach. 867 */ 868 static int ste_attach(dev) 869 device_t dev; 870 { 871 u_int32_t command; 872 struct ste_softc *sc; 873 struct ifnet *ifp; 874 int error = 0, rid; 875 876 sc = device_get_softc(dev); 877 sc->ste_dev = dev; 878 879 /* 880 * Only use one PHY since this chip reports multiple 881 * Note on the DFE-550 the PHY is at 1 on the DFE-580 882 * it is at 0 & 1. It is rev 0x12. 883 */ 884 if (pci_get_vendor(dev) == DL_VENDORID && 885 pci_get_device(dev) == DL_DEVICEID_550TX && 886 pci_get_revid(dev) == 0x12 ) 887 sc->ste_one_phy = 1; 888 889 /* 890 * Handle power management nonsense. 891 */ 892 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 893 u_int32_t iobase, membase, irq; 894 895 /* Save important PCI config data. */ 896 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 897 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 898 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 899 900 /* Reset the power state. */ 901 device_printf(dev, "chip is in D%d power mode " 902 "-- setting to D0\n", pci_get_powerstate(dev)); 903 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 904 905 /* Restore PCI config data. */ 906 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 907 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 908 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 909 } 910 911 /* 912 * Map control/status registers. 913 */ 914 pci_enable_busmaster(dev); 915 pci_enable_io(dev, SYS_RES_IOPORT); 916 pci_enable_io(dev, SYS_RES_MEMORY); 917 command = pci_read_config(dev, PCIR_COMMAND, 4); 918 919 #ifdef STE_USEIOSPACE 920 if (!(command & PCIM_CMD_PORTEN)) { 921 device_printf(dev, "failed to enable I/O ports!\n"); 922 error = ENXIO; 923 goto fail; 924 } 925 #else 926 if (!(command & PCIM_CMD_MEMEN)) { 927 device_printf(dev, "failed to enable memory mapping!\n"); 928 error = ENXIO; 929 goto fail; 930 } 931 #endif 932 933 rid = STE_RID; 934 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 935 936 if (sc->ste_res == NULL) { 937 device_printf(dev, "couldn't map ports/memory\n"); 938 error = ENXIO; 939 goto fail; 940 } 941 942 sc->ste_btag = rman_get_bustag(sc->ste_res); 943 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 944 945 rid = 0; 946 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 947 RF_SHAREABLE | RF_ACTIVE); 948 949 if (sc->ste_irq == NULL) { 950 device_printf(dev, "couldn't map interrupt\n"); 951 error = ENXIO; 952 goto fail; 953 } 954 955 callout_init(&sc->ste_stat_timer); 956 957 ifp = &sc->arpcom.ac_if; 958 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 959 960 /* Reset the adapter. */ 961 ste_reset(sc); 962 963 /* 964 * Get station address from the EEPROM. 965 */ 966 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 967 STE_EEADDR_NODE0, 3, 0)) { 968 device_printf(dev, "failed to read station address\n"); 969 error = ENXIO;; 970 goto fail; 971 } 972 973 /* Allocate the descriptor queues. */ 974 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 975 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 976 977 if (sc->ste_ldata == NULL) { 978 device_printf(dev, "no memory for list buffers!\n"); 979 error = ENXIO; 980 goto fail; 981 } 982 983 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 984 985 /* Do MII setup. */ 986 if (mii_phy_probe(dev, &sc->ste_miibus, 987 ste_ifmedia_upd, ste_ifmedia_sts)) { 988 device_printf(dev, "MII without any phy!\n"); 989 error = ENXIO; 990 goto fail; 991 } 992 993 ifp->if_softc = sc; 994 ifp->if_mtu = ETHERMTU; 995 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 996 ifp->if_ioctl = ste_ioctl; 997 ifp->if_start = ste_start; 998 ifp->if_watchdog = ste_watchdog; 999 ifp->if_init = ste_init; 1000 ifp->if_baudrate = 10000000; 1001 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1002 ifq_set_ready(&ifp->if_snd); 1003 1004 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1005 1006 /* 1007 * Call MI attach routine. 1008 */ 1009 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1010 1011 /* 1012 * Tell the upper layer(s) we support long frames. 1013 */ 1014 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1015 1016 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1017 ste_intr, sc, &sc->ste_intrhand, NULL); 1018 if (error) { 1019 device_printf(dev, "couldn't set up irq\n"); 1020 ether_ifdetach(ifp); 1021 goto fail; 1022 } 1023 1024 return 0; 1025 1026 fail: 1027 ste_detach(dev); 1028 return(error); 1029 } 1030 1031 static int ste_detach(dev) 1032 device_t dev; 1033 { 1034 struct ste_softc *sc; 1035 struct ifnet *ifp; 1036 1037 crit_enter(); 1038 1039 sc = device_get_softc(dev); 1040 ifp = &sc->arpcom.ac_if; 1041 1042 if (device_is_attached(dev)) { 1043 if (bus_child_present(dev)) 1044 ste_stop(sc); 1045 ether_ifdetach(ifp); 1046 } 1047 if (sc->ste_miibus != NULL) 1048 device_delete_child(dev, sc->ste_miibus); 1049 bus_generic_detach(dev); 1050 1051 if (sc->ste_intrhand != NULL) 1052 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1053 1054 crit_exit(); 1055 1056 if (sc->ste_irq != NULL) 1057 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1058 if (sc->ste_res != NULL) 1059 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1060 if (sc->ste_ldata != NULL) { 1061 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1062 M_DEVBUF); 1063 } 1064 1065 return(0); 1066 } 1067 1068 static int ste_newbuf(sc, c, m) 1069 struct ste_softc *sc; 1070 struct ste_chain_onefrag *c; 1071 struct mbuf *m; 1072 { 1073 struct mbuf *m_new = NULL; 1074 1075 if (m == NULL) { 1076 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1077 if (m_new == NULL) 1078 return(ENOBUFS); 1079 MCLGET(m_new, MB_DONTWAIT); 1080 if (!(m_new->m_flags & M_EXT)) { 1081 m_freem(m_new); 1082 return(ENOBUFS); 1083 } 1084 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1085 } else { 1086 m_new = m; 1087 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1088 m_new->m_data = m_new->m_ext.ext_buf; 1089 } 1090 1091 m_adj(m_new, ETHER_ALIGN); 1092 1093 c->ste_mbuf = m_new; 1094 c->ste_ptr->ste_status = 0; 1095 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1096 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1097 1098 return(0); 1099 } 1100 1101 static int ste_init_rx_list(sc) 1102 struct ste_softc *sc; 1103 { 1104 struct ste_chain_data *cd; 1105 struct ste_list_data *ld; 1106 int i; 1107 1108 cd = &sc->ste_cdata; 1109 ld = sc->ste_ldata; 1110 1111 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1112 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1113 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1114 return(ENOBUFS); 1115 if (i == (STE_RX_LIST_CNT - 1)) { 1116 cd->ste_rx_chain[i].ste_next = 1117 &cd->ste_rx_chain[0]; 1118 ld->ste_rx_list[i].ste_next = 1119 vtophys(&ld->ste_rx_list[0]); 1120 } else { 1121 cd->ste_rx_chain[i].ste_next = 1122 &cd->ste_rx_chain[i + 1]; 1123 ld->ste_rx_list[i].ste_next = 1124 vtophys(&ld->ste_rx_list[i + 1]); 1125 } 1126 ld->ste_rx_list[i].ste_status = 0; 1127 } 1128 1129 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1130 1131 return(0); 1132 } 1133 1134 static void ste_init_tx_list(sc) 1135 struct ste_softc *sc; 1136 { 1137 struct ste_chain_data *cd; 1138 struct ste_list_data *ld; 1139 int i; 1140 1141 cd = &sc->ste_cdata; 1142 ld = sc->ste_ldata; 1143 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1144 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1145 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1146 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1147 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1148 if (i == (STE_TX_LIST_CNT - 1)) 1149 cd->ste_tx_chain[i].ste_next = 1150 &cd->ste_tx_chain[0]; 1151 else 1152 cd->ste_tx_chain[i].ste_next = 1153 &cd->ste_tx_chain[i + 1]; 1154 if (i == 0) 1155 cd->ste_tx_chain[i].ste_prev = 1156 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1157 else 1158 cd->ste_tx_chain[i].ste_prev = 1159 &cd->ste_tx_chain[i - 1]; 1160 } 1161 1162 cd->ste_tx_prod = 0; 1163 cd->ste_tx_cons = 0; 1164 cd->ste_tx_cnt = 0; 1165 1166 return; 1167 } 1168 1169 static void ste_init(xsc) 1170 void *xsc; 1171 { 1172 struct ste_softc *sc; 1173 int i; 1174 struct ifnet *ifp; 1175 struct mii_data *mii; 1176 1177 crit_enter(); 1178 1179 sc = xsc; 1180 ifp = &sc->arpcom.ac_if; 1181 mii = device_get_softc(sc->ste_miibus); 1182 1183 ste_stop(sc); 1184 1185 /* Init our MAC address */ 1186 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1187 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1188 } 1189 1190 /* Init RX list */ 1191 if (ste_init_rx_list(sc) == ENOBUFS) { 1192 if_printf(ifp, "initialization failed: no " 1193 "memory for RX buffers\n"); 1194 ste_stop(sc); 1195 crit_exit(); 1196 return; 1197 } 1198 1199 /* Set RX polling interval */ 1200 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1201 1202 /* Init TX descriptors */ 1203 ste_init_tx_list(sc); 1204 1205 /* Set the TX freethresh value */ 1206 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1207 1208 /* Set the TX start threshold for best performance. */ 1209 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1210 1211 /* Set the TX reclaim threshold. */ 1212 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1213 1214 /* Set up the RX filter. */ 1215 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1216 1217 /* If we want promiscuous mode, set the allframes bit. */ 1218 if (ifp->if_flags & IFF_PROMISC) { 1219 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1220 } else { 1221 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1222 } 1223 1224 /* Set capture broadcast bit to accept broadcast frames. */ 1225 if (ifp->if_flags & IFF_BROADCAST) { 1226 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1227 } else { 1228 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1229 } 1230 1231 ste_setmulti(sc); 1232 1233 /* Load the address of the RX list. */ 1234 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1235 ste_wait(sc); 1236 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1237 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1238 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1239 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1240 1241 /* Set TX polling interval (defer until we TX first packet */ 1242 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1243 1244 /* Load address of the TX list */ 1245 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1246 ste_wait(sc); 1247 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1248 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1249 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1250 ste_wait(sc); 1251 sc->ste_tx_prev_idx=-1; 1252 1253 /* Enable receiver and transmitter */ 1254 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1255 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1256 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1257 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1258 1259 /* Enable stats counters. */ 1260 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1261 1262 /* Enable interrupts. */ 1263 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1264 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1265 1266 /* Accept VLAN length packets */ 1267 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1268 1269 ste_ifmedia_upd(ifp); 1270 1271 ifp->if_flags |= IFF_RUNNING; 1272 ifp->if_flags &= ~IFF_OACTIVE; 1273 1274 crit_exit(); 1275 1276 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 1277 1278 return; 1279 } 1280 1281 static void ste_stop(sc) 1282 struct ste_softc *sc; 1283 { 1284 int i; 1285 struct ifnet *ifp; 1286 1287 ifp = &sc->arpcom.ac_if; 1288 1289 callout_stop(&sc->ste_stat_timer); 1290 1291 CSR_WRITE_2(sc, STE_IMR, 0); 1292 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1293 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1294 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1295 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1296 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1297 ste_wait(sc); 1298 /* 1299 * Try really hard to stop the RX engine or under heavy RX 1300 * data chip will write into de-allocated memory. 1301 */ 1302 ste_reset(sc); 1303 1304 sc->ste_link = 0; 1305 1306 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1307 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1308 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1309 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1310 } 1311 } 1312 1313 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1314 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1315 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1316 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1317 } 1318 } 1319 1320 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1321 1322 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1323 1324 return; 1325 } 1326 1327 static void ste_reset(sc) 1328 struct ste_softc *sc; 1329 { 1330 int i; 1331 1332 STE_SETBIT4(sc, STE_ASICCTL, 1333 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1334 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1335 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1336 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1337 STE_ASICCTL_EXTRESET_RESET); 1338 1339 DELAY(100000); 1340 1341 for (i = 0; i < STE_TIMEOUT; i++) { 1342 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1343 break; 1344 } 1345 1346 if (i == STE_TIMEOUT) 1347 if_printf(&sc->arpcom.ac_if, "global reset never completed\n"); 1348 1349 return; 1350 } 1351 1352 static int ste_ioctl(ifp, command, data, cr) 1353 struct ifnet *ifp; 1354 u_long command; 1355 caddr_t data; 1356 struct ucred *cr; 1357 { 1358 struct ste_softc *sc; 1359 struct ifreq *ifr; 1360 struct mii_data *mii; 1361 int error = 0; 1362 1363 crit_enter(); 1364 1365 sc = ifp->if_softc; 1366 ifr = (struct ifreq *)data; 1367 1368 switch(command) { 1369 case SIOCSIFFLAGS: 1370 if (ifp->if_flags & IFF_UP) { 1371 if (ifp->if_flags & IFF_RUNNING && 1372 ifp->if_flags & IFF_PROMISC && 1373 !(sc->ste_if_flags & IFF_PROMISC)) { 1374 STE_SETBIT1(sc, STE_RX_MODE, 1375 STE_RXMODE_PROMISC); 1376 } else if (ifp->if_flags & IFF_RUNNING && 1377 !(ifp->if_flags & IFF_PROMISC) && 1378 sc->ste_if_flags & IFF_PROMISC) { 1379 STE_CLRBIT1(sc, STE_RX_MODE, 1380 STE_RXMODE_PROMISC); 1381 } 1382 if (!(ifp->if_flags & IFF_RUNNING)) { 1383 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1384 ste_init(sc); 1385 } 1386 } else { 1387 if (ifp->if_flags & IFF_RUNNING) 1388 ste_stop(sc); 1389 } 1390 sc->ste_if_flags = ifp->if_flags; 1391 error = 0; 1392 break; 1393 case SIOCADDMULTI: 1394 case SIOCDELMULTI: 1395 ste_setmulti(sc); 1396 error = 0; 1397 break; 1398 case SIOCGIFMEDIA: 1399 case SIOCSIFMEDIA: 1400 mii = device_get_softc(sc->ste_miibus); 1401 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1402 break; 1403 default: 1404 error = ether_ioctl(ifp, command, data); 1405 break; 1406 } 1407 1408 crit_exit(); 1409 1410 return(error); 1411 } 1412 1413 static int ste_encap(sc, c, m_head) 1414 struct ste_softc *sc; 1415 struct ste_chain *c; 1416 struct mbuf *m_head; 1417 { 1418 int frag = 0; 1419 struct ste_frag *f = NULL; 1420 struct mbuf *m; 1421 struct ste_desc *d; 1422 int total_len = 0; 1423 1424 d = c->ste_ptr; 1425 d->ste_ctl = 0; 1426 1427 encap_retry: 1428 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1429 if (m->m_len != 0) { 1430 if (frag == STE_MAXFRAGS) 1431 break; 1432 total_len += m->m_len; 1433 f = &d->ste_frags[frag]; 1434 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1435 f->ste_len = m->m_len; 1436 frag++; 1437 } 1438 } 1439 1440 if (m != NULL) { 1441 struct mbuf *mn; 1442 1443 /* 1444 * We ran out of segments. We have to recopy this 1445 * mbuf chain first. Bail out if we can't get the 1446 * new buffers. Code borrowed from if_fxp.c. 1447 */ 1448 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1449 if (mn == NULL) { 1450 m_freem(m_head); 1451 return ENOMEM; 1452 } 1453 if (m_head->m_pkthdr.len > MHLEN) { 1454 MCLGET(mn, MB_DONTWAIT); 1455 if ((mn->m_flags & M_EXT) == 0) { 1456 m_freem(mn); 1457 m_freem(m_head); 1458 return ENOMEM; 1459 } 1460 } 1461 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1462 mtod(mn, caddr_t)); 1463 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1464 m_freem(m_head); 1465 m_head = mn; 1466 goto encap_retry; 1467 } 1468 1469 c->ste_mbuf = m_head; 1470 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1471 d->ste_ctl = 1; 1472 1473 return(0); 1474 } 1475 1476 static void ste_start(ifp) 1477 struct ifnet *ifp; 1478 { 1479 struct ste_softc *sc; 1480 struct mbuf *m_head = NULL; 1481 struct ste_chain *cur_tx = NULL; 1482 int idx; 1483 1484 sc = ifp->if_softc; 1485 1486 if (!sc->ste_link) 1487 return; 1488 1489 if (ifp->if_flags & IFF_OACTIVE) 1490 return; 1491 1492 idx = sc->ste_cdata.ste_tx_prod; 1493 1494 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1495 1496 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1497 ifp->if_flags |= IFF_OACTIVE; 1498 break; 1499 } 1500 1501 m_head = ifq_dequeue(&ifp->if_snd); 1502 if (m_head == NULL) 1503 break; 1504 1505 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1506 1507 if (ste_encap(sc, cur_tx, m_head) != 0) 1508 break; 1509 1510 cur_tx->ste_ptr->ste_next = 0; 1511 1512 if(sc->ste_tx_prev_idx < 0){ 1513 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1514 /* Load address of the TX list */ 1515 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1516 ste_wait(sc); 1517 1518 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1519 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1520 1521 /* Set TX polling interval to start TX engine */ 1522 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1523 1524 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1525 ste_wait(sc); 1526 }else{ 1527 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1528 sc->ste_cdata.ste_tx_chain[ 1529 sc->ste_tx_prev_idx].ste_ptr->ste_next 1530 = cur_tx->ste_phys; 1531 } 1532 1533 sc->ste_tx_prev_idx=idx; 1534 1535 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1536 1537 STE_INC(idx, STE_TX_LIST_CNT); 1538 sc->ste_cdata.ste_tx_cnt++; 1539 ifp->if_timer = 5; 1540 sc->ste_cdata.ste_tx_prod = idx; 1541 } 1542 1543 return; 1544 } 1545 1546 static void ste_watchdog(ifp) 1547 struct ifnet *ifp; 1548 { 1549 struct ste_softc *sc; 1550 1551 sc = ifp->if_softc; 1552 1553 ifp->if_oerrors++; 1554 if_printf(ifp, "watchdog timeout\n"); 1555 1556 ste_txeoc(sc); 1557 ste_txeof(sc); 1558 ste_rxeof(sc); 1559 ste_reset(sc); 1560 ste_init(sc); 1561 1562 if (!ifq_is_empty(&ifp->if_snd)) 1563 ste_start(ifp); 1564 1565 return; 1566 } 1567 1568 static void ste_shutdown(dev) 1569 device_t dev; 1570 { 1571 struct ste_softc *sc; 1572 1573 sc = device_get_softc(dev); 1574 1575 ste_stop(sc); 1576 1577 return; 1578 } 1579