1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.6 2003/11/20 22:07:31 dillon Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/vlan/if_vlan_var.h> 52 53 #include <net/bpf.h> 54 55 #include <vm/vm.h> /* for vtophys */ 56 #include <vm/pmap.h> /* for vtophys */ 57 #include <machine/clock.h> /* for DELAY */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus_pio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include "../mii_layer/mii.h" 66 #include "../mii_layer/miivar.h" 67 68 #include <bus/pci/pcireg.h> 69 #include <bus/pci/pcivar.h> 70 71 /* "controller miibus0" required. See GENERIC if you get errors here. */ 72 #include "miibus_if.h" 73 74 #define STE_USEIOSPACE 75 76 #include "if_stereg.h" 77 78 /* 79 * Various supported device vendors/types and their names. 80 */ 81 static struct ste_type ste_devs[] = { 82 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 83 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 84 { 0, 0, NULL } 85 }; 86 87 static int ste_probe (device_t); 88 static int ste_attach (device_t); 89 static int ste_detach (device_t); 90 static void ste_init (void *); 91 static void ste_intr (void *); 92 static void ste_rxeof (struct ste_softc *); 93 static void ste_txeoc (struct ste_softc *); 94 static void ste_txeof (struct ste_softc *); 95 static void ste_stats_update (void *); 96 static void ste_stop (struct ste_softc *); 97 static void ste_reset (struct ste_softc *); 98 static int ste_ioctl (struct ifnet *, u_long, caddr_t); 99 static int ste_encap (struct ste_softc *, struct ste_chain *, 100 struct mbuf *); 101 static void ste_start (struct ifnet *); 102 static void ste_watchdog (struct ifnet *); 103 static void ste_shutdown (device_t); 104 static int ste_newbuf (struct ste_softc *, 105 struct ste_chain_onefrag *, 106 struct mbuf *); 107 static int ste_ifmedia_upd (struct ifnet *); 108 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 109 110 static void ste_mii_sync (struct ste_softc *); 111 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 112 static int ste_mii_readreg (struct ste_softc *, 113 struct ste_mii_frame *); 114 static int ste_mii_writereg (struct ste_softc *, 115 struct ste_mii_frame *); 116 static int ste_miibus_readreg (device_t, int, int); 117 static int ste_miibus_writereg (device_t, int, int, int); 118 static void ste_miibus_statchg (device_t); 119 120 static int ste_eeprom_wait (struct ste_softc *); 121 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 122 int, int); 123 static void ste_wait (struct ste_softc *); 124 static u_int8_t ste_calchash (caddr_t); 125 static void ste_setmulti (struct ste_softc *); 126 static int ste_init_rx_list (struct ste_softc *); 127 static void ste_init_tx_list (struct ste_softc *); 128 129 #ifdef STE_USEIOSPACE 130 #define STE_RES SYS_RES_IOPORT 131 #define STE_RID STE_PCI_LOIO 132 #else 133 #define STE_RES SYS_RES_MEMORY 134 #define STE_RID STE_PCI_LOMEM 135 #endif 136 137 static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154 }; 155 156 static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160 }; 161 162 static devclass_t ste_devclass; 163 164 DECLARE_DUMMY_MODULE(if_ste); 165 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 166 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 167 168 #define STE_SETBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 170 171 #define STE_CLRBIT4(sc, reg, x) \ 172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 173 174 #define STE_SETBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 176 177 #define STE_CLRBIT2(sc, reg, x) \ 178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 179 180 #define STE_SETBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 182 183 #define STE_CLRBIT1(sc, reg, x) \ 184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 185 186 187 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 188 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 189 190 /* 191 * Sync the PHYs by setting data bit and strobing the clock 32 times. 192 */ 193 static void ste_mii_sync(sc) 194 struct ste_softc *sc; 195 { 196 int i; 197 198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 199 200 for (i = 0; i < 32; i++) { 201 MII_SET(STE_PHYCTL_MCLK); 202 DELAY(1); 203 MII_CLR(STE_PHYCTL_MCLK); 204 DELAY(1); 205 } 206 207 return; 208 } 209 210 /* 211 * Clock a series of bits through the MII. 212 */ 213 static void ste_mii_send(sc, bits, cnt) 214 struct ste_softc *sc; 215 u_int32_t bits; 216 int cnt; 217 { 218 int i; 219 220 MII_CLR(STE_PHYCTL_MCLK); 221 222 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 223 if (bits & i) { 224 MII_SET(STE_PHYCTL_MDATA); 225 } else { 226 MII_CLR(STE_PHYCTL_MDATA); 227 } 228 DELAY(1); 229 MII_CLR(STE_PHYCTL_MCLK); 230 DELAY(1); 231 MII_SET(STE_PHYCTL_MCLK); 232 } 233 } 234 235 /* 236 * Read an PHY register through the MII. 237 */ 238 static int ste_mii_readreg(sc, frame) 239 struct ste_softc *sc; 240 struct ste_mii_frame *frame; 241 242 { 243 int i, ack, s; 244 245 s = splimp(); 246 247 /* 248 * Set up frame for RX. 249 */ 250 frame->mii_stdelim = STE_MII_STARTDELIM; 251 frame->mii_opcode = STE_MII_READOP; 252 frame->mii_turnaround = 0; 253 frame->mii_data = 0; 254 255 CSR_WRITE_2(sc, STE_PHYCTL, 0); 256 /* 257 * Turn on data xmit. 258 */ 259 MII_SET(STE_PHYCTL_MDIR); 260 261 ste_mii_sync(sc); 262 263 /* 264 * Send command/address info. 265 */ 266 ste_mii_send(sc, frame->mii_stdelim, 2); 267 ste_mii_send(sc, frame->mii_opcode, 2); 268 ste_mii_send(sc, frame->mii_phyaddr, 5); 269 ste_mii_send(sc, frame->mii_regaddr, 5); 270 271 /* Turn off xmit. */ 272 MII_CLR(STE_PHYCTL_MDIR); 273 274 /* Idle bit */ 275 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 276 DELAY(1); 277 MII_SET(STE_PHYCTL_MCLK); 278 DELAY(1); 279 280 /* Check for ack */ 281 MII_CLR(STE_PHYCTL_MCLK); 282 DELAY(1); 283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* 288 * Now try reading data bits. If the ack failed, we still 289 * need to clock through 16 cycles to keep the PHY(s) in sync. 290 */ 291 if (ack) { 292 for(i = 0; i < 16; i++) { 293 MII_CLR(STE_PHYCTL_MCLK); 294 DELAY(1); 295 MII_SET(STE_PHYCTL_MCLK); 296 DELAY(1); 297 } 298 goto fail; 299 } 300 301 for (i = 0x8000; i; i >>= 1) { 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 if (!ack) { 305 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 306 frame->mii_data |= i; 307 DELAY(1); 308 } 309 MII_SET(STE_PHYCTL_MCLK); 310 DELAY(1); 311 } 312 313 fail: 314 315 MII_CLR(STE_PHYCTL_MCLK); 316 DELAY(1); 317 MII_SET(STE_PHYCTL_MCLK); 318 DELAY(1); 319 320 splx(s); 321 322 if (ack) 323 return(1); 324 return(0); 325 } 326 327 /* 328 * Write to a PHY register through the MII. 329 */ 330 static int ste_mii_writereg(sc, frame) 331 struct ste_softc *sc; 332 struct ste_mii_frame *frame; 333 334 { 335 int s; 336 337 s = splimp(); 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 splx(s); 372 373 return(0); 374 } 375 376 static int ste_miibus_readreg(dev, phy, reg) 377 device_t dev; 378 int phy, reg; 379 { 380 struct ste_softc *sc; 381 struct ste_mii_frame frame; 382 383 sc = device_get_softc(dev); 384 385 if ( sc->ste_one_phy && phy != 0 ) 386 return (0); 387 388 bzero((char *)&frame, sizeof(frame)); 389 390 frame.mii_phyaddr = phy; 391 frame.mii_regaddr = reg; 392 ste_mii_readreg(sc, &frame); 393 394 return(frame.mii_data); 395 } 396 397 static int ste_miibus_writereg(dev, phy, reg, data) 398 device_t dev; 399 int phy, reg, data; 400 { 401 struct ste_softc *sc; 402 struct ste_mii_frame frame; 403 404 sc = device_get_softc(dev); 405 bzero((char *)&frame, sizeof(frame)); 406 407 frame.mii_phyaddr = phy; 408 frame.mii_regaddr = reg; 409 frame.mii_data = data; 410 411 ste_mii_writereg(sc, &frame); 412 413 return(0); 414 } 415 416 static void ste_miibus_statchg(dev) 417 device_t dev; 418 { 419 struct ste_softc *sc; 420 struct mii_data *mii; 421 int i; 422 423 sc = device_get_softc(dev); 424 mii = device_get_softc(sc->ste_miibus); 425 426 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 427 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 428 } else { 429 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 430 } 431 432 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 433 STE_ASICCTL_TX_RESET); 434 for (i = 0; i < STE_TIMEOUT; i++) { 435 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 436 break; 437 } 438 if (i == STE_TIMEOUT) 439 printf("ste%d: rx reset never completed\n", sc->ste_unit); 440 441 return; 442 } 443 444 static int ste_ifmedia_upd(ifp) 445 struct ifnet *ifp; 446 { 447 struct ste_softc *sc; 448 struct mii_data *mii; 449 450 sc = ifp->if_softc; 451 mii = device_get_softc(sc->ste_miibus); 452 sc->ste_link = 0; 453 if (mii->mii_instance) { 454 struct mii_softc *miisc; 455 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 456 miisc = LIST_NEXT(miisc, mii_list)) 457 mii_phy_reset(miisc); 458 } 459 mii_mediachg(mii); 460 461 return(0); 462 } 463 464 static void ste_ifmedia_sts(ifp, ifmr) 465 struct ifnet *ifp; 466 struct ifmediareq *ifmr; 467 { 468 struct ste_softc *sc; 469 struct mii_data *mii; 470 471 sc = ifp->if_softc; 472 mii = device_get_softc(sc->ste_miibus); 473 474 mii_pollstat(mii); 475 ifmr->ifm_active = mii->mii_media_active; 476 ifmr->ifm_status = mii->mii_media_status; 477 478 return; 479 } 480 481 static void ste_wait(sc) 482 struct ste_softc *sc; 483 { 484 int i; 485 486 for (i = 0; i < STE_TIMEOUT; i++) { 487 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 488 break; 489 } 490 491 if (i == STE_TIMEOUT) 492 printf("ste%d: command never completed!\n", sc->ste_unit); 493 494 return; 495 } 496 497 /* 498 * The EEPROM is slow: give it time to come ready after issuing 499 * it a command. 500 */ 501 static int ste_eeprom_wait(sc) 502 struct ste_softc *sc; 503 { 504 int i; 505 506 DELAY(1000); 507 508 for (i = 0; i < 100; i++) { 509 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 510 DELAY(1000); 511 else 512 break; 513 } 514 515 if (i == 100) { 516 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 517 return(1); 518 } 519 520 return(0); 521 } 522 523 /* 524 * Read a sequence of words from the EEPROM. Note that ethernet address 525 * data is stored in the EEPROM in network byte order. 526 */ 527 static int ste_read_eeprom(sc, dest, off, cnt, swap) 528 struct ste_softc *sc; 529 caddr_t dest; 530 int off; 531 int cnt; 532 int swap; 533 { 534 int err = 0, i; 535 u_int16_t word = 0, *ptr; 536 537 if (ste_eeprom_wait(sc)) 538 return(1); 539 540 for (i = 0; i < cnt; i++) { 541 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 542 err = ste_eeprom_wait(sc); 543 if (err) 544 break; 545 word = CSR_READ_2(sc, STE_EEPROM_DATA); 546 ptr = (u_int16_t *)(dest + (i * 2)); 547 if (swap) 548 *ptr = ntohs(word); 549 else 550 *ptr = word; 551 } 552 553 return(err ? 1 : 0); 554 } 555 556 static u_int8_t ste_calchash(addr) 557 caddr_t addr; 558 { 559 560 u_int32_t crc, carry; 561 int i, j; 562 u_int8_t c; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xFFFFFFFF; /* initial value */ 566 567 for (i = 0; i < 6; i++) { 568 c = *(addr + i); 569 for (j = 0; j < 8; j++) { 570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 571 crc <<= 1; 572 c >>= 1; 573 if (carry) 574 crc = (crc ^ 0x04c11db6) | carry; 575 } 576 } 577 578 /* return the filter bit position */ 579 return(crc & 0x0000003F); 580 } 581 582 static void ste_setmulti(sc) 583 struct ste_softc *sc; 584 { 585 struct ifnet *ifp; 586 int h = 0; 587 u_int32_t hashes[2] = { 0, 0 }; 588 struct ifmultiaddr *ifma; 589 590 ifp = &sc->arpcom.ac_if; 591 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 592 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 593 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 594 return; 595 } 596 597 /* first, zot all the existing hash bits */ 598 CSR_WRITE_2(sc, STE_MAR0, 0); 599 CSR_WRITE_2(sc, STE_MAR1, 0); 600 CSR_WRITE_2(sc, STE_MAR2, 0); 601 CSR_WRITE_2(sc, STE_MAR3, 0); 602 603 /* now program new ones */ 604 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 605 ifma = ifma->ifma_link.le_next) { 606 if (ifma->ifma_addr->sa_family != AF_LINK) 607 continue; 608 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 609 if (h < 32) 610 hashes[0] |= (1 << h); 611 else 612 hashes[1] |= (1 << (h - 32)); 613 } 614 615 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 617 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 619 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 620 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 621 622 return; 623 } 624 625 static void ste_intr(xsc) 626 void *xsc; 627 { 628 struct ste_softc *sc; 629 struct ifnet *ifp; 630 u_int16_t status; 631 632 sc = xsc; 633 ifp = &sc->arpcom.ac_if; 634 635 /* See if this is really our interrupt. */ 636 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 637 return; 638 639 for (;;) { 640 status = CSR_READ_2(sc, STE_ISR_ACK); 641 642 if (!(status & STE_INTRS)) 643 break; 644 645 if (status & STE_ISR_RX_DMADONE) 646 ste_rxeof(sc); 647 648 if (status & STE_ISR_TX_DMADONE) 649 ste_txeof(sc); 650 651 if (status & STE_ISR_TX_DONE) 652 ste_txeoc(sc); 653 654 if (status & STE_ISR_STATS_OFLOW) { 655 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 656 ste_stats_update(sc); 657 } 658 659 if (status & STE_ISR_LINKEVENT) 660 mii_pollstat(device_get_softc(sc->ste_miibus)); 661 662 if (status & STE_ISR_HOSTERR) { 663 ste_reset(sc); 664 ste_init(sc); 665 } 666 } 667 668 /* Re-enable interrupts */ 669 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 670 671 if (ifp->if_snd.ifq_head != NULL) 672 ste_start(ifp); 673 674 return; 675 } 676 677 /* 678 * A frame has been uploaded: pass the resulting mbuf chain up to 679 * the higher level protocols. 680 */ 681 static void ste_rxeof(sc) 682 struct ste_softc *sc; 683 { 684 struct ether_header *eh; 685 struct mbuf *m; 686 struct ifnet *ifp; 687 struct ste_chain_onefrag *cur_rx; 688 int total_len = 0, count=0; 689 u_int32_t rxstat; 690 691 ifp = &sc->arpcom.ac_if; 692 693 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 694 & STE_RXSTAT_DMADONE) { 695 if ((STE_RX_LIST_CNT - count) < 3) { 696 break; 697 } 698 699 cur_rx = sc->ste_cdata.ste_rx_head; 700 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 701 702 /* 703 * If an error occurs, update stats, clear the 704 * status word and leave the mbuf cluster in place: 705 * it should simply get re-used next time this descriptor 706 * comes up in the ring. 707 */ 708 if (rxstat & STE_RXSTAT_FRAME_ERR) { 709 ifp->if_ierrors++; 710 cur_rx->ste_ptr->ste_status = 0; 711 continue; 712 } 713 714 /* 715 * If there error bit was not set, the upload complete 716 * bit should be set which means we have a valid packet. 717 * If not, something truly strange has happened. 718 */ 719 if (!(rxstat & STE_RXSTAT_DMADONE)) { 720 printf("ste%d: bad receive status -- packet dropped", 721 sc->ste_unit); 722 ifp->if_ierrors++; 723 cur_rx->ste_ptr->ste_status = 0; 724 continue; 725 } 726 727 /* No errors; receive the packet. */ 728 m = cur_rx->ste_mbuf; 729 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 730 731 /* 732 * Try to conjure up a new mbuf cluster. If that 733 * fails, it means we have an out of memory condition and 734 * should leave the buffer in place and continue. This will 735 * result in a lost packet, but there's little else we 736 * can do in this situation. 737 */ 738 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 739 ifp->if_ierrors++; 740 cur_rx->ste_ptr->ste_status = 0; 741 continue; 742 } 743 744 ifp->if_ipackets++; 745 eh = mtod(m, struct ether_header *); 746 m->m_pkthdr.rcvif = ifp; 747 m->m_pkthdr.len = m->m_len = total_len; 748 749 /* Remove header from mbuf and pass it on. */ 750 m_adj(m, sizeof(struct ether_header)); 751 ether_input(ifp, eh, m); 752 753 cur_rx->ste_ptr->ste_status = 0; 754 count++; 755 } 756 757 return; 758 } 759 760 static void ste_txeoc(sc) 761 struct ste_softc *sc; 762 { 763 u_int8_t txstat; 764 struct ifnet *ifp; 765 766 ifp = &sc->arpcom.ac_if; 767 768 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 769 STE_TXSTATUS_TXDONE) { 770 if (txstat & STE_TXSTATUS_UNDERRUN || 771 txstat & STE_TXSTATUS_EXCESSCOLLS || 772 txstat & STE_TXSTATUS_RECLAIMERR) { 773 ifp->if_oerrors++; 774 printf("ste%d: transmission error: %x\n", 775 sc->ste_unit, txstat); 776 777 ste_reset(sc); 778 ste_init(sc); 779 780 if (txstat & STE_TXSTATUS_UNDERRUN && 781 sc->ste_tx_thresh < STE_PACKET_SIZE) { 782 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 783 printf("ste%d: tx underrun, increasing tx" 784 " start threshold to %d bytes\n", 785 sc->ste_unit, sc->ste_tx_thresh); 786 } 787 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 788 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 789 (STE_PACKET_SIZE >> 4)); 790 } 791 ste_init(sc); 792 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 793 } 794 795 return; 796 } 797 798 static void ste_txeof(sc) 799 struct ste_softc *sc; 800 { 801 struct ste_chain *cur_tx = NULL; 802 struct ifnet *ifp; 803 int idx; 804 805 ifp = &sc->arpcom.ac_if; 806 807 idx = sc->ste_cdata.ste_tx_cons; 808 while(idx != sc->ste_cdata.ste_tx_prod) { 809 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 810 811 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 812 break; 813 814 if (cur_tx->ste_mbuf != NULL) { 815 m_freem(cur_tx->ste_mbuf); 816 cur_tx->ste_mbuf = NULL; 817 } 818 819 ifp->if_opackets++; 820 821 sc->ste_cdata.ste_tx_cnt--; 822 STE_INC(idx, STE_TX_LIST_CNT); 823 ifp->if_timer = 0; 824 } 825 826 sc->ste_cdata.ste_tx_cons = idx; 827 828 if (cur_tx != NULL) 829 ifp->if_flags &= ~IFF_OACTIVE; 830 831 return; 832 } 833 834 static void ste_stats_update(xsc) 835 void *xsc; 836 { 837 struct ste_softc *sc; 838 struct ifnet *ifp; 839 struct mii_data *mii; 840 int s; 841 842 s = splimp(); 843 844 sc = xsc; 845 ifp = &sc->arpcom.ac_if; 846 mii = device_get_softc(sc->ste_miibus); 847 848 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 849 + CSR_READ_1(sc, STE_MULTI_COLLS) 850 + CSR_READ_1(sc, STE_SINGLE_COLLS); 851 852 if (!sc->ste_link) { 853 mii_pollstat(mii); 854 if (mii->mii_media_status & IFM_ACTIVE && 855 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 856 sc->ste_link++; 857 /* 858 * we don't get a call-back on re-init so do it 859 * otherwise we get stuck in the wrong link state 860 */ 861 ste_miibus_statchg(sc->ste_dev); 862 if (ifp->if_snd.ifq_head != NULL) 863 ste_start(ifp); 864 } 865 } 866 867 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 868 splx(s); 869 870 return; 871 } 872 873 874 /* 875 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 876 * IDs against our list and return a device name if we find a match. 877 */ 878 static int ste_probe(dev) 879 device_t dev; 880 { 881 struct ste_type *t; 882 883 t = ste_devs; 884 885 while(t->ste_name != NULL) { 886 if ((pci_get_vendor(dev) == t->ste_vid) && 887 (pci_get_device(dev) == t->ste_did)) { 888 device_set_desc(dev, t->ste_name); 889 return(0); 890 } 891 t++; 892 } 893 894 return(ENXIO); 895 } 896 897 /* 898 * Attach the interface. Allocate softc structures, do ifmedia 899 * setup and ethernet/BPF attach. 900 */ 901 static int ste_attach(dev) 902 device_t dev; 903 { 904 int s; 905 u_int32_t command; 906 struct ste_softc *sc; 907 struct ifnet *ifp; 908 int unit, error = 0, rid; 909 910 s = splimp(); 911 912 sc = device_get_softc(dev); 913 unit = device_get_unit(dev); 914 bzero(sc, sizeof(struct ste_softc)); 915 sc->ste_dev = dev; 916 917 /* 918 * Only use one PHY since this chip reports multiple 919 * Note on the DFE-550 the PHY is at 1 on the DFE-580 920 * it is at 0 & 1. It is rev 0x12. 921 */ 922 if (pci_get_vendor(dev) == DL_VENDORID && 923 pci_get_device(dev) == DL_DEVICEID_550TX && 924 pci_get_revid(dev) == 0x12 ) 925 sc->ste_one_phy = 1; 926 927 /* 928 * Handle power management nonsense. 929 */ 930 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 931 if (command == 0x01) { 932 933 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 934 if (command & STE_PSTATE_MASK) { 935 u_int32_t iobase, membase, irq; 936 937 /* Save important PCI config data. */ 938 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 939 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 940 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 941 942 /* Reset the power state. */ 943 printf("ste%d: chip is in D%d power mode " 944 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 945 command &= 0xFFFFFFFC; 946 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 947 948 /* Restore PCI config data. */ 949 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 950 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 951 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 952 } 953 } 954 955 /* 956 * Map control/status registers. 957 */ 958 command = pci_read_config(dev, PCIR_COMMAND, 4); 959 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 960 pci_write_config(dev, PCIR_COMMAND, command, 4); 961 command = pci_read_config(dev, PCIR_COMMAND, 4); 962 963 #ifdef STE_USEIOSPACE 964 if (!(command & PCIM_CMD_PORTEN)) { 965 printf("ste%d: failed to enable I/O ports!\n", unit); 966 error = ENXIO; 967 goto fail; 968 } 969 #else 970 if (!(command & PCIM_CMD_MEMEN)) { 971 printf("ste%d: failed to enable memory mapping!\n", unit); 972 error = ENXIO; 973 goto fail; 974 } 975 #endif 976 977 rid = STE_RID; 978 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 979 0, ~0, 1, RF_ACTIVE); 980 981 if (sc->ste_res == NULL) { 982 printf ("ste%d: couldn't map ports/memory\n", unit); 983 error = ENXIO; 984 goto fail; 985 } 986 987 sc->ste_btag = rman_get_bustag(sc->ste_res); 988 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 989 990 rid = 0; 991 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 992 RF_SHAREABLE | RF_ACTIVE); 993 994 if (sc->ste_irq == NULL) { 995 printf("ste%d: couldn't map interrupt\n", unit); 996 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 997 error = ENXIO; 998 goto fail; 999 } 1000 1001 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1002 ste_intr, sc, &sc->ste_intrhand); 1003 1004 if (error) { 1005 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1006 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1007 printf("ste%d: couldn't set up irq\n", unit); 1008 goto fail; 1009 } 1010 1011 callout_handle_init(&sc->ste_stat_ch); 1012 1013 /* Reset the adapter. */ 1014 ste_reset(sc); 1015 1016 /* 1017 * Get station address from the EEPROM. 1018 */ 1019 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1020 STE_EEADDR_NODE0, 3, 0)) { 1021 printf("ste%d: failed to read station address\n", unit); 1022 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1023 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1024 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1025 error = ENXIO;; 1026 goto fail; 1027 } 1028 1029 /* 1030 * A Sundance chip was detected. Inform the world. 1031 */ 1032 printf("ste%d: Ethernet address: %6D\n", unit, 1033 sc->arpcom.ac_enaddr, ":"); 1034 1035 sc->ste_unit = unit; 1036 1037 /* Allocate the descriptor queues. */ 1038 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1039 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1040 1041 if (sc->ste_ldata == NULL) { 1042 printf("ste%d: no memory for list buffers!\n", unit); 1043 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1044 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1045 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1046 error = ENXIO; 1047 goto fail; 1048 } 1049 1050 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1051 1052 /* Do MII setup. */ 1053 if (mii_phy_probe(dev, &sc->ste_miibus, 1054 ste_ifmedia_upd, ste_ifmedia_sts)) { 1055 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1056 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1057 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1058 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1059 contigfree(sc->ste_ldata, 1060 sizeof(struct ste_list_data), M_DEVBUF); 1061 error = ENXIO; 1062 goto fail; 1063 } 1064 1065 ifp = &sc->arpcom.ac_if; 1066 ifp->if_softc = sc; 1067 ifp->if_unit = unit; 1068 ifp->if_name = "ste"; 1069 ifp->if_mtu = ETHERMTU; 1070 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1071 ifp->if_ioctl = ste_ioctl; 1072 ifp->if_output = ether_output; 1073 ifp->if_start = ste_start; 1074 ifp->if_watchdog = ste_watchdog; 1075 ifp->if_init = ste_init; 1076 ifp->if_baudrate = 10000000; 1077 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1078 1079 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1080 1081 /* 1082 * Call MI attach routine. 1083 */ 1084 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1085 1086 /* 1087 * Tell the upper layer(s) we support long frames. 1088 */ 1089 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1090 1091 fail: 1092 splx(s); 1093 return(error); 1094 } 1095 1096 static int ste_detach(dev) 1097 device_t dev; 1098 { 1099 struct ste_softc *sc; 1100 struct ifnet *ifp; 1101 int s; 1102 1103 s = splimp(); 1104 1105 sc = device_get_softc(dev); 1106 ifp = &sc->arpcom.ac_if; 1107 1108 ste_stop(sc); 1109 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1110 1111 bus_generic_detach(dev); 1112 device_delete_child(dev, sc->ste_miibus); 1113 1114 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1115 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1116 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1117 1118 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1119 1120 splx(s); 1121 1122 return(0); 1123 } 1124 1125 static int ste_newbuf(sc, c, m) 1126 struct ste_softc *sc; 1127 struct ste_chain_onefrag *c; 1128 struct mbuf *m; 1129 { 1130 struct mbuf *m_new = NULL; 1131 1132 if (m == NULL) { 1133 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1134 if (m_new == NULL) 1135 return(ENOBUFS); 1136 MCLGET(m_new, M_DONTWAIT); 1137 if (!(m_new->m_flags & M_EXT)) { 1138 m_freem(m_new); 1139 return(ENOBUFS); 1140 } 1141 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1142 } else { 1143 m_new = m; 1144 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1145 m_new->m_data = m_new->m_ext.ext_buf; 1146 } 1147 1148 m_adj(m_new, ETHER_ALIGN); 1149 1150 c->ste_mbuf = m_new; 1151 c->ste_ptr->ste_status = 0; 1152 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1153 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1154 1155 return(0); 1156 } 1157 1158 static int ste_init_rx_list(sc) 1159 struct ste_softc *sc; 1160 { 1161 struct ste_chain_data *cd; 1162 struct ste_list_data *ld; 1163 int i; 1164 1165 cd = &sc->ste_cdata; 1166 ld = sc->ste_ldata; 1167 1168 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1169 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1170 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1171 return(ENOBUFS); 1172 if (i == (STE_RX_LIST_CNT - 1)) { 1173 cd->ste_rx_chain[i].ste_next = 1174 &cd->ste_rx_chain[0]; 1175 ld->ste_rx_list[i].ste_next = 1176 vtophys(&ld->ste_rx_list[0]); 1177 } else { 1178 cd->ste_rx_chain[i].ste_next = 1179 &cd->ste_rx_chain[i + 1]; 1180 ld->ste_rx_list[i].ste_next = 1181 vtophys(&ld->ste_rx_list[i + 1]); 1182 } 1183 ld->ste_rx_list[i].ste_status = 0; 1184 } 1185 1186 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1187 1188 return(0); 1189 } 1190 1191 static void ste_init_tx_list(sc) 1192 struct ste_softc *sc; 1193 { 1194 struct ste_chain_data *cd; 1195 struct ste_list_data *ld; 1196 int i; 1197 1198 cd = &sc->ste_cdata; 1199 ld = sc->ste_ldata; 1200 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1201 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1202 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1203 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1204 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1205 if (i == (STE_TX_LIST_CNT - 1)) 1206 cd->ste_tx_chain[i].ste_next = 1207 &cd->ste_tx_chain[0]; 1208 else 1209 cd->ste_tx_chain[i].ste_next = 1210 &cd->ste_tx_chain[i + 1]; 1211 if (i == 0) 1212 cd->ste_tx_chain[i].ste_prev = 1213 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1214 else 1215 cd->ste_tx_chain[i].ste_prev = 1216 &cd->ste_tx_chain[i - 1]; 1217 } 1218 1219 cd->ste_tx_prod = 0; 1220 cd->ste_tx_cons = 0; 1221 cd->ste_tx_cnt = 0; 1222 1223 return; 1224 } 1225 1226 static void ste_init(xsc) 1227 void *xsc; 1228 { 1229 struct ste_softc *sc; 1230 int i, s; 1231 struct ifnet *ifp; 1232 struct mii_data *mii; 1233 1234 s = splimp(); 1235 1236 sc = xsc; 1237 ifp = &sc->arpcom.ac_if; 1238 mii = device_get_softc(sc->ste_miibus); 1239 1240 ste_stop(sc); 1241 1242 /* Init our MAC address */ 1243 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1244 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1245 } 1246 1247 /* Init RX list */ 1248 if (ste_init_rx_list(sc) == ENOBUFS) { 1249 printf("ste%d: initialization failed: no " 1250 "memory for RX buffers\n", sc->ste_unit); 1251 ste_stop(sc); 1252 splx(s); 1253 return; 1254 } 1255 1256 /* Set RX polling interval */ 1257 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1258 1259 /* Init TX descriptors */ 1260 ste_init_tx_list(sc); 1261 1262 /* Set the TX freethresh value */ 1263 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1264 1265 /* Set the TX start threshold for best performance. */ 1266 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1267 1268 /* Set the TX reclaim threshold. */ 1269 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1270 1271 /* Set up the RX filter. */ 1272 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1273 1274 /* If we want promiscuous mode, set the allframes bit. */ 1275 if (ifp->if_flags & IFF_PROMISC) { 1276 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1277 } else { 1278 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1279 } 1280 1281 /* Set capture broadcast bit to accept broadcast frames. */ 1282 if (ifp->if_flags & IFF_BROADCAST) { 1283 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1284 } else { 1285 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1286 } 1287 1288 ste_setmulti(sc); 1289 1290 /* Load the address of the RX list. */ 1291 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1292 ste_wait(sc); 1293 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1294 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1296 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1297 1298 /* Set TX polling interval (defer until we TX first packet */ 1299 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1300 1301 /* Load address of the TX list */ 1302 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1303 ste_wait(sc); 1304 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1305 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1306 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1307 ste_wait(sc); 1308 sc->ste_tx_prev_idx=-1; 1309 1310 /* Enable receiver and transmitter */ 1311 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1312 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1313 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1314 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1315 1316 /* Enable stats counters. */ 1317 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1318 1319 /* Enable interrupts. */ 1320 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1321 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1322 1323 /* Accept VLAN length packets */ 1324 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1325 1326 ste_ifmedia_upd(ifp); 1327 1328 ifp->if_flags |= IFF_RUNNING; 1329 ifp->if_flags &= ~IFF_OACTIVE; 1330 1331 splx(s); 1332 1333 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1334 1335 return; 1336 } 1337 1338 static void ste_stop(sc) 1339 struct ste_softc *sc; 1340 { 1341 int i; 1342 struct ifnet *ifp; 1343 1344 ifp = &sc->arpcom.ac_if; 1345 1346 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1347 1348 CSR_WRITE_2(sc, STE_IMR, 0); 1349 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1350 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1351 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1352 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1353 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1354 ste_wait(sc); 1355 /* 1356 * Try really hard to stop the RX engine or under heavy RX 1357 * data chip will write into de-allocated memory. 1358 */ 1359 ste_reset(sc); 1360 1361 sc->ste_link = 0; 1362 1363 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1364 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1365 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1366 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1367 } 1368 } 1369 1370 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1371 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1372 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1373 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1374 } 1375 } 1376 1377 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1378 1379 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1380 1381 return; 1382 } 1383 1384 static void ste_reset(sc) 1385 struct ste_softc *sc; 1386 { 1387 int i; 1388 1389 STE_SETBIT4(sc, STE_ASICCTL, 1390 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1391 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1392 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1393 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1394 STE_ASICCTL_EXTRESET_RESET); 1395 1396 DELAY(100000); 1397 1398 for (i = 0; i < STE_TIMEOUT; i++) { 1399 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1400 break; 1401 } 1402 1403 if (i == STE_TIMEOUT) 1404 printf("ste%d: global reset never completed\n", sc->ste_unit); 1405 1406 return; 1407 } 1408 1409 static int ste_ioctl(ifp, command, data) 1410 struct ifnet *ifp; 1411 u_long command; 1412 caddr_t data; 1413 { 1414 struct ste_softc *sc; 1415 struct ifreq *ifr; 1416 struct mii_data *mii; 1417 int error = 0, s; 1418 1419 s = splimp(); 1420 1421 sc = ifp->if_softc; 1422 ifr = (struct ifreq *)data; 1423 1424 switch(command) { 1425 case SIOCSIFADDR: 1426 case SIOCGIFADDR: 1427 case SIOCSIFMTU: 1428 error = ether_ioctl(ifp, command, data); 1429 break; 1430 case SIOCSIFFLAGS: 1431 if (ifp->if_flags & IFF_UP) { 1432 if (ifp->if_flags & IFF_RUNNING && 1433 ifp->if_flags & IFF_PROMISC && 1434 !(sc->ste_if_flags & IFF_PROMISC)) { 1435 STE_SETBIT1(sc, STE_RX_MODE, 1436 STE_RXMODE_PROMISC); 1437 } else if (ifp->if_flags & IFF_RUNNING && 1438 !(ifp->if_flags & IFF_PROMISC) && 1439 sc->ste_if_flags & IFF_PROMISC) { 1440 STE_CLRBIT1(sc, STE_RX_MODE, 1441 STE_RXMODE_PROMISC); 1442 } 1443 if (!(ifp->if_flags & IFF_RUNNING)) { 1444 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1445 ste_init(sc); 1446 } 1447 } else { 1448 if (ifp->if_flags & IFF_RUNNING) 1449 ste_stop(sc); 1450 } 1451 sc->ste_if_flags = ifp->if_flags; 1452 error = 0; 1453 break; 1454 case SIOCADDMULTI: 1455 case SIOCDELMULTI: 1456 ste_setmulti(sc); 1457 error = 0; 1458 break; 1459 case SIOCGIFMEDIA: 1460 case SIOCSIFMEDIA: 1461 mii = device_get_softc(sc->ste_miibus); 1462 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1463 break; 1464 default: 1465 error = EINVAL; 1466 break; 1467 } 1468 1469 splx(s); 1470 1471 return(error); 1472 } 1473 1474 static int ste_encap(sc, c, m_head) 1475 struct ste_softc *sc; 1476 struct ste_chain *c; 1477 struct mbuf *m_head; 1478 { 1479 int frag = 0; 1480 struct ste_frag *f = NULL; 1481 struct mbuf *m; 1482 struct ste_desc *d; 1483 int total_len = 0; 1484 1485 d = c->ste_ptr; 1486 d->ste_ctl = 0; 1487 1488 encap_retry: 1489 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1490 if (m->m_len != 0) { 1491 if (frag == STE_MAXFRAGS) 1492 break; 1493 total_len += m->m_len; 1494 f = &d->ste_frags[frag]; 1495 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1496 f->ste_len = m->m_len; 1497 frag++; 1498 } 1499 } 1500 1501 if (m != NULL) { 1502 struct mbuf *mn; 1503 1504 /* 1505 * We ran out of segments. We have to recopy this 1506 * mbuf chain first. Bail out if we can't get the 1507 * new buffers. Code borrowed from if_fxp.c. 1508 */ 1509 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1510 if (mn == NULL) { 1511 m_freem(m_head); 1512 return ENOMEM; 1513 } 1514 if (m_head->m_pkthdr.len > MHLEN) { 1515 MCLGET(mn, M_DONTWAIT); 1516 if ((mn->m_flags & M_EXT) == 0) { 1517 m_freem(mn); 1518 m_freem(m_head); 1519 return ENOMEM; 1520 } 1521 } 1522 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1523 mtod(mn, caddr_t)); 1524 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1525 m_freem(m_head); 1526 m_head = mn; 1527 goto encap_retry; 1528 } 1529 1530 c->ste_mbuf = m_head; 1531 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1532 d->ste_ctl = 1; 1533 1534 return(0); 1535 } 1536 1537 static void ste_start(ifp) 1538 struct ifnet *ifp; 1539 { 1540 struct ste_softc *sc; 1541 struct mbuf *m_head = NULL; 1542 struct ste_chain *cur_tx = NULL; 1543 int idx; 1544 1545 sc = ifp->if_softc; 1546 1547 if (!sc->ste_link) 1548 return; 1549 1550 if (ifp->if_flags & IFF_OACTIVE) 1551 return; 1552 1553 idx = sc->ste_cdata.ste_tx_prod; 1554 1555 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1556 1557 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1558 ifp->if_flags |= IFF_OACTIVE; 1559 break; 1560 } 1561 1562 IF_DEQUEUE(&ifp->if_snd, m_head); 1563 if (m_head == NULL) 1564 break; 1565 1566 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1567 1568 if (ste_encap(sc, cur_tx, m_head) != 0) 1569 break; 1570 1571 cur_tx->ste_ptr->ste_next = 0; 1572 1573 if(sc->ste_tx_prev_idx < 0){ 1574 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1575 /* Load address of the TX list */ 1576 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1577 ste_wait(sc); 1578 1579 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1580 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1581 1582 /* Set TX polling interval to start TX engine */ 1583 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1584 1585 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1586 ste_wait(sc); 1587 }else{ 1588 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1589 sc->ste_cdata.ste_tx_chain[ 1590 sc->ste_tx_prev_idx].ste_ptr->ste_next 1591 = cur_tx->ste_phys; 1592 } 1593 1594 sc->ste_tx_prev_idx=idx; 1595 1596 /* 1597 * If there's a BPF listener, bounce a copy of this frame 1598 * to him. 1599 */ 1600 if (ifp->if_bpf) 1601 bpf_mtap(ifp, cur_tx->ste_mbuf); 1602 1603 STE_INC(idx, STE_TX_LIST_CNT); 1604 sc->ste_cdata.ste_tx_cnt++; 1605 ifp->if_timer = 5; 1606 sc->ste_cdata.ste_tx_prod = idx; 1607 } 1608 1609 return; 1610 } 1611 1612 static void ste_watchdog(ifp) 1613 struct ifnet *ifp; 1614 { 1615 struct ste_softc *sc; 1616 1617 sc = ifp->if_softc; 1618 1619 ifp->if_oerrors++; 1620 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1621 1622 ste_txeoc(sc); 1623 ste_txeof(sc); 1624 ste_rxeof(sc); 1625 ste_reset(sc); 1626 ste_init(sc); 1627 1628 if (ifp->if_snd.ifq_head != NULL) 1629 ste_start(ifp); 1630 1631 return; 1632 } 1633 1634 static void ste_shutdown(dev) 1635 device_t dev; 1636 { 1637 struct ste_softc *sc; 1638 1639 sc = device_get_softc(dev); 1640 1641 ste_stop(sc); 1642 1643 return; 1644 } 1645