1 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $ 35 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.35 2005/05/31 14:11:42 joerg Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 /* 55 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 56 * the SK-984x series adapters, both single port and dual port. 57 * References: 58 * The XaQti XMAC II datasheet, 59 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 60 * The SysKonnect GEnesis manual, http://www.syskonnect.com 61 * 62 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 63 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 64 * convenience to others until Vitesse corrects this problem: 65 * 66 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 67 * 68 * Written by Bill Paul <wpaul@ee.columbia.edu> 69 * Department of Electrical Engineering 70 * Columbia University, New York City 71 */ 72 73 /* 74 * The SysKonnect gigabit ethernet adapters consist of two main 75 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 76 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 77 * components and a PHY while the GEnesis controller provides a PCI 78 * interface with DMA support. Each card may have between 512K and 79 * 2MB of SRAM on board depending on the configuration. 80 * 81 * The SysKonnect GEnesis controller can have either one or two XMAC 82 * chips connected to it, allowing single or dual port NIC configurations. 83 * SysKonnect has the distinction of being the only vendor on the market 84 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 85 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 86 * XMAC registers. This driver takes advantage of these features to allow 87 * both XMACs to operate as independent interfaces. 88 */ 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 99 #include <net/if.h> 100 #include <net/ifq_var.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 106 #include <net/bpf.h> 107 108 #include <vm/vm.h> /* for vtophys */ 109 #include <vm/pmap.h> /* for vtophys */ 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <dev/netif/mii_layer/mii.h> 116 #include <dev/netif/mii_layer/miivar.h> 117 #include <dev/netif/mii_layer/brgphyreg.h> 118 119 #include <bus/pci/pcireg.h> 120 #include <bus/pci/pcivar.h> 121 122 #if 0 123 #define SK_USEIOSPACE 124 #endif 125 126 #include "if_skreg.h" 127 #include "xmaciireg.h" 128 #include "yukonreg.h" 129 130 /* "controller miibus0" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 static struct sk_type sk_devs[] = { 134 { VENDORID_SK, DEVICEID_SK_V1, 135 "SysKonnect Gigabit Ethernet (V1.0)" }, 136 { VENDORID_SK, DEVICEID_SK_V2, 137 "SysKonnect Gigabit Ethernet (V2.0)" }, 138 { VENDORID_MARVELL, DEVICEID_SK_V2, 139 "Marvell Gigabit Ethernet" }, 140 { VENDORID_3COM, DEVICEID_3COM_3C940, 141 "3Com 3C940 Gigabit Ethernet" }, 142 { VENDORID_LINKSYS, DEVICEID_LINKSYS_EG1032, 143 "Linksys EG1032 Gigabit Ethernet" }, 144 { VENDORID_DLINK, DEVICEID_DLINK_DGE530T, 145 "D-Link DGE-530T Gigabit Ethernet" }, 146 { 0, 0, NULL } 147 }; 148 149 static int skc_probe(device_t); 150 static int skc_attach(device_t); 151 static int skc_detach(device_t); 152 static void skc_shutdown(device_t); 153 static int sk_probe(device_t); 154 static int sk_attach(device_t); 155 static int sk_detach(device_t); 156 static void sk_tick(void *); 157 static void sk_intr(void *); 158 static void sk_intr_bcom(struct sk_if_softc *); 159 static void sk_intr_xmac(struct sk_if_softc *); 160 static void sk_intr_yukon(struct sk_if_softc *); 161 static void sk_rxeof(struct sk_if_softc *); 162 static void sk_txeof(struct sk_if_softc *); 163 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 164 static void sk_start(struct ifnet *); 165 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 166 static void sk_init(void *); 167 static void sk_init_xmac(struct sk_if_softc *); 168 static void sk_init_yukon(struct sk_if_softc *); 169 static void sk_stop(struct sk_if_softc *); 170 static void sk_watchdog(struct ifnet *); 171 static int sk_ifmedia_upd(struct ifnet *); 172 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 173 static void sk_reset(struct sk_softc *); 174 static int sk_newbuf(struct sk_if_softc *, struct sk_chain *, 175 struct mbuf *); 176 static int sk_alloc_jumbo_mem(struct sk_if_softc *); 177 static struct sk_jslot 178 *sk_jalloc(struct sk_if_softc *); 179 static void sk_jfree(void *); 180 static void sk_jref(void *); 181 static int sk_init_rx_ring(struct sk_if_softc *); 182 static void sk_init_tx_ring(struct sk_if_softc *); 183 static uint32_t sk_win_read_4(struct sk_softc *, int); 184 static uint16_t sk_win_read_2(struct sk_softc *, int); 185 static uint8_t sk_win_read_1(struct sk_softc *, int); 186 static void sk_win_write_4(struct sk_softc *, int, uint32_t); 187 static void sk_win_write_2(struct sk_softc *, int, uint32_t); 188 static void sk_win_write_1(struct sk_softc *, int, uint32_t); 189 static uint8_t sk_vpd_readbyte(struct sk_softc *, int); 190 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 191 static void sk_vpd_read(struct sk_softc *); 192 193 static int sk_miibus_readreg(device_t, int, int); 194 static int sk_miibus_writereg(device_t, int, int, int); 195 static void sk_miibus_statchg(device_t); 196 197 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 198 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int); 199 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 200 201 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 202 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int); 203 static void sk_marv_miibus_statchg(struct sk_if_softc *); 204 205 static void sk_setfilt(struct sk_if_softc *, caddr_t, int); 206 static void sk_setmulti(struct sk_if_softc *); 207 static void sk_setpromisc(struct sk_if_softc *); 208 209 #ifdef SK_USEIOSPACE 210 #define SK_RES SYS_RES_IOPORT 211 #define SK_RID SK_PCI_LOIO 212 #else 213 #define SK_RES SYS_RES_MEMORY 214 #define SK_RID SK_PCI_LOMEM 215 #endif 216 217 /* 218 * Note that we have newbus methods for both the GEnesis controller 219 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 220 * the miibus code is a child of the XMACs. We need to do it this way 221 * so that the miibus drivers can access the PHY registers on the 222 * right PHY. It's not quite what I had in mind, but it's the only 223 * design that achieves the desired effect. 224 */ 225 static device_method_t skc_methods[] = { 226 /* Device interface */ 227 DEVMETHOD(device_probe, skc_probe), 228 DEVMETHOD(device_attach, skc_attach), 229 DEVMETHOD(device_detach, skc_detach), 230 DEVMETHOD(device_shutdown, skc_shutdown), 231 232 /* bus interface */ 233 DEVMETHOD(bus_print_child, bus_generic_print_child), 234 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 235 236 { 0, 0 } 237 }; 238 239 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc)); 240 static devclass_t skc_devclass; 241 242 static device_method_t sk_methods[] = { 243 /* Device interface */ 244 DEVMETHOD(device_probe, sk_probe), 245 DEVMETHOD(device_attach, sk_attach), 246 DEVMETHOD(device_detach, sk_detach), 247 DEVMETHOD(device_shutdown, bus_generic_shutdown), 248 249 /* bus interface */ 250 DEVMETHOD(bus_print_child, bus_generic_print_child), 251 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 252 253 /* MII interface */ 254 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 255 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 256 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 257 258 { 0, 0 } 259 }; 260 261 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc)); 262 static devclass_t sk_devclass; 263 264 DECLARE_DUMMY_MODULE(if_sk); 265 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 266 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0); 267 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 268 269 #define SK_SETBIT(sc, reg, x) \ 270 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 271 272 #define SK_CLRBIT(sc, reg, x) \ 273 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 274 275 #define SK_WIN_SETBIT_4(sc, reg, x) \ 276 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 277 278 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 279 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 280 281 #define SK_WIN_SETBIT_2(sc, reg, x) \ 282 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 283 284 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 285 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 286 287 static uint32_t 288 sk_win_read_4(struct sk_softc *sc, int reg) 289 { 290 #ifdef SK_USEIOSPACE 291 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 292 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 293 #else 294 return(CSR_READ_4(sc, reg)); 295 #endif 296 } 297 298 static uint16_t 299 sk_win_read_2(struct sk_softc *sc, int reg) 300 { 301 #ifdef SK_USEIOSPACE 302 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 303 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 304 #else 305 return(CSR_READ_2(sc, reg)); 306 #endif 307 } 308 309 static uint8_t 310 sk_win_read_1(struct sk_softc *sc, int reg) 311 { 312 #ifdef SK_USEIOSPACE 313 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 314 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 315 #else 316 return(CSR_READ_1(sc, reg)); 317 #endif 318 } 319 320 static void 321 sk_win_write_4(struct sk_softc *sc, int reg, uint32_t val) 322 { 323 #ifdef SK_USEIOSPACE 324 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 325 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 326 #else 327 CSR_WRITE_4(sc, reg, val); 328 #endif 329 } 330 331 static void 332 sk_win_write_2(struct sk_softc *sc, int reg, uint32_t val) 333 { 334 #ifdef SK_USEIOSPACE 335 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 336 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 337 #else 338 CSR_WRITE_2(sc, reg, val); 339 #endif 340 } 341 342 static void 343 sk_win_write_1(struct sk_softc *sc, int reg, uint32_t val) 344 { 345 #ifdef SK_USEIOSPACE 346 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 347 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 348 #else 349 CSR_WRITE_1(sc, reg, val); 350 #endif 351 } 352 353 /* 354 * The VPD EEPROM contains Vital Product Data, as suggested in 355 * the PCI 2.1 specification. The VPD data is separared into areas 356 * denoted by resource IDs. The SysKonnect VPD contains an ID string 357 * resource (the name of the adapter), a read-only area resource 358 * containing various key/data fields and a read/write area which 359 * can be used to store asset management information or log messages. 360 * We read the ID string and read-only into buffers attached to 361 * the controller softc structure for later use. At the moment, 362 * we only use the ID string during sk_attach(). 363 */ 364 static uint8_t 365 sk_vpd_readbyte(struct sk_softc *sc, int addr) 366 { 367 int i; 368 369 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 370 for (i = 0; i < SK_TIMEOUT; i++) { 371 DELAY(1); 372 if (sk_win_read_2(sc, 373 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 374 break; 375 } 376 377 if (i == SK_TIMEOUT) 378 return(0); 379 380 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 381 } 382 383 static void 384 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 385 { 386 int i; 387 uint8_t *ptr; 388 389 ptr = (uint8_t *)res; 390 for (i = 0; i < sizeof(struct vpd_res); i++) 391 ptr[i] = sk_vpd_readbyte(sc, i + addr); 392 } 393 394 static void 395 sk_vpd_read(struct sk_softc *sc) 396 { 397 struct vpd_res res; 398 int i, pos = 0; 399 400 if (sc->sk_vpd_prodname != NULL) 401 free(sc->sk_vpd_prodname, M_DEVBUF); 402 if (sc->sk_vpd_readonly != NULL) 403 free(sc->sk_vpd_readonly, M_DEVBUF); 404 sc->sk_vpd_prodname = NULL; 405 sc->sk_vpd_readonly = NULL; 406 407 sk_vpd_read_res(sc, &res, pos); 408 409 if (res.vr_id != VPD_RES_ID) { 410 printf("skc%d: bad VPD resource id: expected %x got %x\n", 411 sc->sk_unit, VPD_RES_ID, res.vr_id); 412 return; 413 } 414 415 pos += sizeof(res); 416 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT); 417 for (i = 0; i < res.vr_len; i++) 418 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 419 sc->sk_vpd_prodname[i] = '\0'; 420 pos += i; 421 422 sk_vpd_read_res(sc, &res, pos); 423 424 if (res.vr_id != VPD_RES_READ) { 425 printf("skc%d: bad VPD resource id: expected %x got %x\n", 426 sc->sk_unit, VPD_RES_READ, res.vr_id); 427 return; 428 } 429 430 pos += sizeof(res); 431 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT); 432 for (i = 0; i < res.vr_len + 1; i++) 433 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 434 } 435 436 static int 437 sk_miibus_readreg(device_t dev, int phy, int reg) 438 { 439 struct sk_if_softc *sc_if = device_get_softc(dev); 440 441 switch(sc_if->sk_softc->sk_type) { 442 case SK_GENESIS: 443 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 444 case SK_YUKON: 445 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 446 } 447 448 return(0); 449 } 450 451 static int 452 sk_miibus_writereg(device_t dev, int phy, int reg, int val) 453 { 454 struct sk_if_softc *sc_if = device_get_softc(dev); 455 456 switch(sc_if->sk_softc->sk_type) { 457 case SK_GENESIS: 458 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 459 case SK_YUKON: 460 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 461 } 462 463 return(0); 464 } 465 466 static void 467 sk_miibus_statchg(device_t dev) 468 { 469 struct sk_if_softc *sc_if = device_get_softc(dev); 470 471 switch(sc_if->sk_softc->sk_type) { 472 case SK_GENESIS: 473 sk_xmac_miibus_statchg(sc_if); 474 break; 475 case SK_YUKON: 476 sk_marv_miibus_statchg(sc_if); 477 break; 478 } 479 } 480 481 static int 482 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 483 { 484 int i; 485 486 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 487 return(0); 488 489 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 490 SK_XM_READ_2(sc_if, XM_PHY_DATA); 491 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 492 for (i = 0; i < SK_TIMEOUT; i++) { 493 DELAY(1); 494 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 495 XM_MMUCMD_PHYDATARDY) 496 break; 497 } 498 499 if (i == SK_TIMEOUT) { 500 printf("sk%d: phy failed to come ready\n", 501 sc_if->sk_unit); 502 return(0); 503 } 504 } 505 DELAY(1); 506 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 507 } 508 509 static int 510 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 511 { 512 int i; 513 514 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 515 for (i = 0; i < SK_TIMEOUT; i++) { 516 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 517 break; 518 } 519 520 if (i == SK_TIMEOUT) { 521 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 522 return(ETIMEDOUT); 523 } 524 525 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 526 for (i = 0; i < SK_TIMEOUT; i++) { 527 DELAY(1); 528 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 529 break; 530 } 531 532 if (i == SK_TIMEOUT) 533 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 534 535 return(0); 536 } 537 538 static void 539 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if) 540 { 541 struct mii_data *mii; 542 543 mii = device_get_softc(sc_if->sk_miibus); 544 545 /* 546 * If this is a GMII PHY, manually set the XMAC's 547 * duplex mode accordingly. 548 */ 549 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 550 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 551 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 552 else 553 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 554 } 555 } 556 557 static int 558 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 559 { 560 uint16_t val; 561 int i; 562 563 if (phy != 0 || 564 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 565 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 566 return(0); 567 } 568 569 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 570 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 571 572 for (i = 0; i < SK_TIMEOUT; i++) { 573 DELAY(1); 574 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 575 if (val & YU_SMICR_READ_VALID) 576 break; 577 } 578 579 if (i == SK_TIMEOUT) { 580 printf("sk%d: phy failed to come ready\n", 581 sc_if->sk_unit); 582 return(0); 583 } 584 585 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 586 587 return(val); 588 } 589 590 static int 591 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 592 { 593 int i; 594 595 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 596 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 597 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 598 599 for (i = 0; i < SK_TIMEOUT; i++) { 600 DELAY(1); 601 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 602 break; 603 } 604 605 return(0); 606 } 607 608 static void 609 sk_marv_miibus_statchg(struct sk_if_softc *sc_if) 610 { 611 } 612 613 #define HASH_BITS 6 614 615 static void sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 616 { 617 int base; 618 619 base = XM_RXFILT_ENTRY(slot); 620 621 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 622 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 623 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 624 } 625 626 static void 627 sk_setmulti(struct sk_if_softc *sc_if) 628 { 629 struct sk_softc *sc = sc_if->sk_softc; 630 struct ifnet *ifp = &sc_if->arpcom.ac_if; 631 uint32_t hashes[2] = { 0, 0 }; 632 int h, i; 633 struct ifmultiaddr *ifma; 634 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 635 636 /* First, zot all the existing filters. */ 637 switch(sc->sk_type) { 638 case SK_GENESIS: 639 for (i = 1; i < XM_RXFILT_MAX; i++) 640 sk_setfilt(sc_if, (caddr_t)&dummy, i); 641 642 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 643 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 644 break; 645 case SK_YUKON: 646 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 647 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 648 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 649 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 650 break; 651 } 652 653 /* Now program new ones. */ 654 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 655 hashes[0] = 0xFFFFFFFF; 656 hashes[1] = 0xFFFFFFFF; 657 } else { 658 i = 1; 659 /* First find the tail of the list. */ 660 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 661 if (ifma->ifma_link.le_next == NULL) 662 break; 663 } 664 /* Now traverse the list backwards. */ 665 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 666 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 667 if (ifma->ifma_addr->sa_family != AF_LINK) 668 continue; 669 /* 670 * Program the first XM_RXFILT_MAX multicast groups 671 * into the perfect filter. For all others, 672 * use the hash table. 673 */ 674 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 675 sk_setfilt(sc_if, 676 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 677 i++; 678 continue; 679 } 680 681 switch(sc->sk_type) { 682 case SK_GENESIS: 683 h = ~ether_crc32_le(LLADDR((struct sockaddr_dl *) 684 ifma->ifma_addr), ETHER_ADDR_LEN) & 685 ((1 << HASH_BITS) -1 ); 686 if (h < 32) 687 hashes[0] |= (1 << h); 688 else 689 hashes[1] |= (1 << (h - 32)); 690 break; 691 692 case SK_YUKON: 693 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 694 ifma->ifma_addr), ETHER_ADDR_LEN) & 695 ((1 << HASH_BITS) -1 ); 696 if (h < 32) 697 hashes[0] |= (1 << h); 698 else 699 hashes[1] |= (1 << (h - 32)); 700 break; 701 } 702 } 703 } 704 705 switch(sc->sk_type) { 706 case SK_GENESIS: 707 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 708 XM_MODE_RX_USE_PERFECT); 709 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 710 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 711 break; 712 case SK_YUKON: 713 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 714 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 715 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 716 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 717 break; 718 } 719 } 720 721 static void 722 sk_setpromisc(struct sk_if_softc *sc_if) 723 { 724 struct sk_softc *sc = sc_if->sk_softc; 725 struct ifnet *ifp = &sc_if->arpcom.ac_if; 726 727 switch(sc->sk_type) { 728 case SK_GENESIS: 729 if (ifp->if_flags & IFF_PROMISC) { 730 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 731 } else { 732 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 733 } 734 break; 735 case SK_YUKON: 736 if (ifp->if_flags & IFF_PROMISC) { 737 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 738 YU_RCR_UFLEN | YU_RCR_MUFLEN); 739 } else { 740 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 741 YU_RCR_UFLEN | YU_RCR_MUFLEN); 742 } 743 break; 744 } 745 } 746 747 static int 748 sk_init_rx_ring(struct sk_if_softc *sc_if) 749 { 750 struct sk_chain_data *cd = &sc_if->sk_cdata; 751 struct sk_ring_data *rd = sc_if->sk_rdata; 752 int i; 753 754 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 755 756 for (i = 0; i < SK_RX_RING_CNT; i++) { 757 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 758 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 759 return(ENOBUFS); 760 if (i == (SK_RX_RING_CNT - 1)) { 761 cd->sk_rx_chain[i].sk_next = 762 &cd->sk_rx_chain[0]; 763 rd->sk_rx_ring[i].sk_next = 764 vtophys(&rd->sk_rx_ring[0]); 765 } else { 766 cd->sk_rx_chain[i].sk_next = 767 &cd->sk_rx_chain[i + 1]; 768 rd->sk_rx_ring[i].sk_next = 769 vtophys(&rd->sk_rx_ring[i + 1]); 770 } 771 } 772 773 sc_if->sk_cdata.sk_rx_prod = 0; 774 sc_if->sk_cdata.sk_rx_cons = 0; 775 776 return(0); 777 } 778 779 static void 780 sk_init_tx_ring(struct sk_if_softc *sc_if) 781 { 782 struct sk_chain_data *cd = &sc_if->sk_cdata; 783 struct sk_ring_data *rd = sc_if->sk_rdata; 784 int i, nexti; 785 786 bzero(sc_if->sk_rdata->sk_tx_ring, 787 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 788 789 for (i = 0; i < SK_TX_RING_CNT; i++) { 790 nexti = (i == (SK_TX_RING_CNT - 1)) ? 0 : i + 1; 791 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 792 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 793 rd->sk_tx_ring[i].sk_next = vtophys(&rd->sk_tx_ring[nexti]); 794 } 795 796 sc_if->sk_cdata.sk_tx_prod = 0; 797 sc_if->sk_cdata.sk_tx_cons = 0; 798 sc_if->sk_cdata.sk_tx_cnt = 0; 799 } 800 801 static int 802 sk_newbuf(struct sk_if_softc *sc_if, struct sk_chain *c, struct mbuf *m) 803 { 804 struct mbuf *m_new = NULL; 805 struct sk_rx_desc *r; 806 struct sk_jslot *buf; 807 808 if (m == NULL) { 809 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 810 if (m_new == NULL) 811 return(ENOBUFS); 812 813 /* Allocate the jumbo buffer */ 814 buf = sk_jalloc(sc_if); 815 if (buf == NULL) { 816 m_freem(m_new); 817 #ifdef SK_VERBOSE 818 printf("sk%d: jumbo allocation failed " 819 "-- packet dropped!\n", sc_if->sk_unit); 820 #endif 821 return(ENOBUFS); 822 } 823 824 /* Attach the buffer to the mbuf */ 825 m_new->m_ext.ext_arg = buf; 826 m_new->m_ext.ext_buf = buf->sk_buf; 827 m_new->m_ext.ext_free = sk_jfree; 828 m_new->m_ext.ext_ref = sk_jref; 829 m_new->m_ext.ext_size = SK_JUMBO_FRAMELEN; 830 831 m_new->m_data = m_new->m_ext.ext_buf; 832 m_new->m_flags |= M_EXT; 833 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 834 } else { 835 /* 836 * We're re-using a previously allocated mbuf; 837 * be sure to re-init pointers and lengths to 838 * default values. 839 */ 840 m_new = m; 841 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 842 m_new->m_data = m_new->m_ext.ext_buf; 843 } 844 845 /* 846 * Adjust alignment so packet payload begins on a 847 * longword boundary. Mandatory for Alpha, useful on 848 * x86 too. 849 */ 850 m_adj(m_new, ETHER_ALIGN); 851 852 r = c->sk_desc; 853 c->sk_mbuf = m_new; 854 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 855 r->sk_ctl = m_new->m_len | SK_RXSTAT; 856 857 return(0); 858 } 859 860 /* 861 * Allocate jumbo buffer storage. The SysKonnect adapters support 862 * "jumbograms" (9K frames), although SysKonnect doesn't currently 863 * use them in their drivers. In order for us to use them, we need 864 * large 9K receive buffers, however standard mbuf clusters are only 865 * 2048 bytes in size. Consequently, we need to allocate and manage 866 * our own jumbo buffer pool. Fortunately, this does not require an 867 * excessive amount of additional code. 868 */ 869 static int 870 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 871 { 872 caddr_t ptr; 873 int i; 874 struct sk_jslot *entry; 875 876 /* Grab a big chunk o' storage. */ 877 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 878 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 879 880 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 881 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 882 return(ENOBUFS); 883 } 884 885 SLIST_INIT(&sc_if->sk_jfree_listhead); 886 887 /* 888 * Now divide it up into 9K pieces and save the addresses 889 * in an array. Note that we play an evil trick here by using 890 * the first few bytes in the buffer to hold the the address 891 * of the softc structure for this interface. This is because 892 * sk_jfree() needs it, but it is called by the mbuf management 893 * code which will not pass it to us explicitly. 894 */ 895 ptr = sc_if->sk_cdata.sk_jumbo_buf; 896 for (i = 0; i < SK_JSLOTS; i++) { 897 entry = &sc_if->sk_cdata.sk_jslots[i]; 898 entry->sk_sc = sc_if; 899 entry->sk_buf = ptr; 900 entry->sk_inuse = 0; 901 entry->sk_slot = i; 902 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jslot_link); 903 ptr += SK_JLEN; 904 } 905 906 return(0); 907 } 908 909 /* 910 * Allocate a jumbo buffer. 911 */ 912 static struct sk_jslot * 913 sk_jalloc(struct sk_if_softc *sc_if) 914 { 915 struct sk_jslot *entry; 916 917 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 918 919 if (entry == NULL) { 920 #ifdef SK_VERBOSE 921 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 922 #endif 923 return(NULL); 924 } 925 926 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jslot_link); 927 entry->sk_inuse = 1; 928 929 return(entry); 930 } 931 932 /* 933 * Adjust usage count on a jumbo buffer. In general this doesn't 934 * get used much because our jumbo buffers don't get passed around 935 * a lot, but it's implemented for correctness. 936 */ 937 static void 938 sk_jref(void *arg) 939 { 940 struct sk_jslot *entry = (struct sk_jslot *)arg; 941 struct sk_if_softc *sc = entry->sk_sc; 942 943 if (sc == NULL) 944 panic("sk_jref: can't find softc pointer!"); 945 946 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry) 947 panic("sk_jref: asked to reference buffer " 948 "that we don't manage!"); 949 if (entry->sk_inuse == 0) 950 panic("sk_jref: buffer already free!"); 951 entry->sk_inuse++; 952 } 953 954 /* 955 * Release a jumbo buffer. 956 */ 957 static void 958 sk_jfree(void *arg) 959 { 960 struct sk_jslot *entry = (struct sk_jslot *)arg; 961 struct sk_if_softc *sc = entry->sk_sc; 962 963 if (sc == NULL) 964 panic("sk_jref: can't find softc pointer!"); 965 966 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry) 967 panic("sk_jref: asked to reference buffer " 968 "that we don't manage!"); 969 if (entry->sk_inuse == 0) 970 panic("sk_jref: buffer already free!"); 971 if (--entry->sk_inuse == 0) 972 SLIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jslot_link); 973 } 974 975 /* 976 * Set media options. 977 */ 978 static int 979 sk_ifmedia_upd(struct ifnet *ifp) 980 { 981 struct sk_if_softc *sc_if = ifp->if_softc; 982 struct mii_data *mii; 983 984 mii = device_get_softc(sc_if->sk_miibus); 985 sk_init(sc_if); 986 mii_mediachg(mii); 987 988 return(0); 989 } 990 991 /* 992 * Report current media status. 993 */ 994 static void 995 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 996 { 997 struct sk_if_softc *sc_if; 998 struct mii_data *mii; 999 1000 sc_if = ifp->if_softc; 1001 mii = device_get_softc(sc_if->sk_miibus); 1002 1003 mii_pollstat(mii); 1004 ifmr->ifm_active = mii->mii_media_active; 1005 ifmr->ifm_status = mii->mii_media_status; 1006 } 1007 1008 static int 1009 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1010 { 1011 struct sk_if_softc *sc_if = ifp->if_softc; 1012 struct ifreq *ifr = (struct ifreq *)data; 1013 struct mii_data *mii; 1014 int error = 0, s; 1015 1016 s = splimp(); 1017 1018 switch(command) { 1019 case SIOCSIFMTU: 1020 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1021 error = EINVAL; 1022 else { 1023 ifp->if_mtu = ifr->ifr_mtu; 1024 sk_init(sc_if); 1025 } 1026 break; 1027 case SIOCSIFFLAGS: 1028 if (ifp->if_flags & IFF_UP) { 1029 if (ifp->if_flags & IFF_RUNNING) { 1030 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1031 & IFF_PROMISC) { 1032 sk_setpromisc(sc_if); 1033 sk_setmulti(sc_if); 1034 } 1035 } else 1036 sk_init(sc_if); 1037 } else { 1038 if (ifp->if_flags & IFF_RUNNING) 1039 sk_stop(sc_if); 1040 } 1041 sc_if->sk_if_flags = ifp->if_flags; 1042 error = 0; 1043 break; 1044 case SIOCADDMULTI: 1045 case SIOCDELMULTI: 1046 sk_setmulti(sc_if); 1047 error = 0; 1048 break; 1049 case SIOCGIFMEDIA: 1050 case SIOCSIFMEDIA: 1051 mii = device_get_softc(sc_if->sk_miibus); 1052 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1053 break; 1054 default: 1055 error = ether_ioctl(ifp, command, data); 1056 break; 1057 } 1058 1059 splx(s); 1060 1061 return(error); 1062 } 1063 1064 /* 1065 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1066 * IDs against our list and return a device name if we find a match. 1067 */ 1068 static int 1069 skc_probe(device_t dev) 1070 { 1071 struct sk_type *t; 1072 uint16_t vendor, product; 1073 1074 vendor = pci_get_vendor(dev); 1075 product = pci_get_device(dev); 1076 1077 for (t = sk_devs; t->sk_name != NULL; t++) { 1078 if (vendor == t->sk_vid && product == t->sk_did) { 1079 device_set_desc(dev, t->sk_name); 1080 return(0); 1081 } 1082 } 1083 1084 return(ENXIO); 1085 } 1086 1087 /* 1088 * Force the GEnesis into reset, then bring it out of reset. 1089 */ 1090 static void 1091 sk_reset(struct sk_softc *sc) 1092 { 1093 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1094 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1095 if (sc->sk_type == SK_YUKON) 1096 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1097 1098 DELAY(1000); 1099 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1100 DELAY(2); 1101 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1102 if (sc->sk_type == SK_YUKON) 1103 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1104 1105 if (sc->sk_type == SK_GENESIS) { 1106 /* Configure packet arbiter */ 1107 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1108 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1109 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1110 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1111 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1112 } 1113 1114 /* Enable RAM interface */ 1115 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1116 1117 /* 1118 * Configure interrupt moderation. The moderation timer 1119 * defers interrupts specified in the interrupt moderation 1120 * timer mask based on the timeout specified in the interrupt 1121 * moderation timer init register. Each bit in the timer 1122 * register represents 18.825ns, so to specify a timeout in 1123 * microseconds, we have to multiply by 54. 1124 */ 1125 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1126 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1127 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1128 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1129 } 1130 1131 static int 1132 sk_probe(device_t dev) 1133 { 1134 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1135 1136 /* 1137 * Not much to do here. We always know there will be 1138 * at least one XMAC present, and if there are two, 1139 * skc_attach() will create a second device instance 1140 * for us. 1141 */ 1142 switch (sc->sk_type) { 1143 case SK_GENESIS: 1144 device_set_desc(dev, "XaQti Corp. XMAC II"); 1145 break; 1146 case SK_YUKON: 1147 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1148 break; 1149 } 1150 1151 return(0); 1152 } 1153 1154 /* 1155 * Each XMAC chip is attached as a separate logical IP interface. 1156 * Single port cards will have only one logical interface of course. 1157 */ 1158 static int 1159 sk_attach(device_t dev) 1160 { 1161 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1162 struct sk_if_softc *sc_if = device_get_softc(dev); 1163 struct ifnet *ifp; 1164 int i, port; 1165 1166 port = *(int *)device_get_ivars(dev); 1167 free(device_get_ivars(dev), M_DEVBUF); 1168 device_set_ivars(dev, NULL); 1169 sc_if->sk_dev = dev; 1170 callout_init(&sc_if->sk_tick_timer); 1171 1172 sc_if->sk_dev = dev; 1173 sc_if->sk_unit = device_get_unit(dev); 1174 sc_if->sk_port = port; 1175 sc_if->sk_softc = sc; 1176 sc->sk_if[port] = sc_if; 1177 if (port == SK_PORT_A) 1178 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1179 if (port == SK_PORT_B) 1180 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1181 1182 /* 1183 * Get station address for this interface. Note that 1184 * dual port cards actually come with three station 1185 * addresses: one for each port, plus an extra. The 1186 * extra one is used by the SysKonnect driver software 1187 * as a 'virtual' station address for when both ports 1188 * are operating in failover mode. Currently we don't 1189 * use this extra address. 1190 */ 1191 for (i = 0; i < ETHER_ADDR_LEN; i++) 1192 sc_if->arpcom.ac_enaddr[i] = 1193 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1194 1195 /* 1196 * Set up RAM buffer addresses. The NIC will have a certain 1197 * amount of SRAM on it, somewhere between 512K and 2MB. We 1198 * need to divide this up a) between the transmitter and 1199 * receiver and b) between the two XMACs, if this is a 1200 * dual port NIC. Our algotithm is to divide up the memory 1201 * evenly so that everyone gets a fair share. 1202 */ 1203 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1204 uint32_t chunk, val; 1205 1206 chunk = sc->sk_ramsize / 2; 1207 val = sc->sk_rboff / sizeof(uint64_t); 1208 sc_if->sk_rx_ramstart = val; 1209 val += (chunk / sizeof(uint64_t)); 1210 sc_if->sk_rx_ramend = val - 1; 1211 sc_if->sk_tx_ramstart = val; 1212 val += (chunk / sizeof(uint64_t)); 1213 sc_if->sk_tx_ramend = val - 1; 1214 } else { 1215 uint32_t chunk, val; 1216 1217 chunk = sc->sk_ramsize / 4; 1218 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1219 sizeof(uint64_t); 1220 sc_if->sk_rx_ramstart = val; 1221 val += (chunk / sizeof(uint64_t)); 1222 sc_if->sk_rx_ramend = val - 1; 1223 sc_if->sk_tx_ramstart = val; 1224 val += (chunk / sizeof(uint64_t)); 1225 sc_if->sk_tx_ramend = val - 1; 1226 } 1227 1228 /* Read and save PHY type and set PHY address */ 1229 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1230 switch(sc_if->sk_phytype) { 1231 case SK_PHYTYPE_XMAC: 1232 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1233 break; 1234 case SK_PHYTYPE_BCOM: 1235 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1236 break; 1237 case SK_PHYTYPE_MARV_COPPER: 1238 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1239 break; 1240 default: 1241 printf("skc%d: unsupported PHY type: %d\n", 1242 sc->sk_unit, sc_if->sk_phytype); 1243 return(ENODEV); 1244 } 1245 1246 /* Allocate the descriptor queues. */ 1247 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1248 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1249 1250 if (sc_if->sk_rdata == NULL) { 1251 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1252 sc->sk_if[port] = NULL; 1253 return(ENOMEM); 1254 } 1255 1256 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1257 1258 /* Try to allocate memory for jumbo buffers. */ 1259 if (sk_alloc_jumbo_mem(sc_if)) { 1260 printf("sk%d: jumbo buffer allocation failed\n", 1261 sc_if->sk_unit); 1262 contigfree(sc_if->sk_rdata, 1263 sizeof(struct sk_ring_data), M_DEVBUF); 1264 sc->sk_if[port] = NULL; 1265 return(ENOMEM); 1266 } 1267 1268 ifp = &sc_if->arpcom.ac_if; 1269 ifp->if_softc = sc_if; 1270 if_initname(ifp, "sk", sc_if->sk_unit); 1271 ifp->if_mtu = ETHERMTU; 1272 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1273 ifp->if_ioctl = sk_ioctl; 1274 ifp->if_start = sk_start; 1275 ifp->if_watchdog = sk_watchdog; 1276 ifp->if_init = sk_init; 1277 ifp->if_baudrate = 1000000000; 1278 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1); 1279 ifq_set_ready(&ifp->if_snd); 1280 1281 /* 1282 * Do miibus setup. 1283 */ 1284 switch (sc->sk_type) { 1285 case SK_GENESIS: 1286 sk_init_xmac(sc_if); 1287 break; 1288 case SK_YUKON: 1289 sk_init_yukon(sc_if); 1290 break; 1291 } 1292 1293 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1294 sk_ifmedia_upd, sk_ifmedia_sts)) { 1295 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1296 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, 1297 M_DEVBUF); 1298 contigfree(sc_if->sk_rdata, 1299 sizeof(struct sk_ring_data), M_DEVBUF); 1300 return(ENXIO); 1301 } 1302 1303 /* 1304 * Call MI attach routine. 1305 */ 1306 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1307 callout_init(&sc_if->sk_tick_timer); 1308 1309 return(0); 1310 } 1311 1312 /* 1313 * Attach the interface. Allocate softc structures, do ifmedia 1314 * setup and ethernet/BPF attach. 1315 */ 1316 static int 1317 skc_attach(device_t dev) 1318 { 1319 struct sk_softc *sc; 1320 int error = 0, *port, rid, s, unit; 1321 uint32_t command; 1322 uint8_t skrs; 1323 1324 s = splimp(); 1325 1326 sc = device_get_softc(dev); 1327 unit = device_get_unit(dev); 1328 switch (pci_get_device(dev)) { 1329 case DEVICEID_SK_V1: 1330 sc->sk_type = SK_GENESIS; 1331 break; 1332 case DEVICEID_SK_V2: 1333 case DEVICEID_3COM_3C940: 1334 case DEVICEID_LINKSYS_EG1032: 1335 case DEVICEID_DLINK_DGE530T: 1336 sc->sk_type = SK_YUKON; 1337 break; 1338 } 1339 1340 /* 1341 * Handle power management nonsense. 1342 */ 1343 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF; 1344 if (command == 0x01) { 1345 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4); 1346 if (command & SK_PSTATE_MASK) { 1347 uint32_t iobase, membase, irq; 1348 1349 /* Save important PCI config data. */ 1350 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1351 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1352 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1353 1354 /* Reset the power state. */ 1355 printf("skc%d: chip is in D%d power mode " 1356 "-- setting to D0\n", unit, command & SK_PSTATE_MASK); 1357 command &= 0xFFFFFFFC; 1358 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4); 1359 1360 /* Restore PCI config data. */ 1361 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1362 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1363 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1364 } 1365 } 1366 1367 /* 1368 * Map control/status registers. 1369 */ 1370 command = pci_read_config(dev, PCIR_COMMAND, 4); 1371 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1372 pci_write_config(dev, PCIR_COMMAND, command, 4); 1373 command = pci_read_config(dev, PCIR_COMMAND, 4); 1374 1375 #ifdef SK_USEIOSPACE 1376 if ((command & PCIM_CMD_PORTEN) == 0) { 1377 printf("skc%d: failed to enable I/O ports!\n", unit); 1378 error = ENXIO; 1379 goto fail; 1380 } 1381 #else 1382 if ((command & PCIM_CMD_MEMEN) == 0) { 1383 printf("skc%d: failed to enable memory mapping!\n", unit); 1384 error = ENXIO; 1385 goto fail; 1386 } 1387 #endif 1388 1389 rid = SK_RID; 1390 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1391 1392 if (sc->sk_res == NULL) { 1393 printf("sk%d: couldn't map ports/memory\n", unit); 1394 error = ENXIO; 1395 goto fail; 1396 } 1397 1398 sc->sk_btag = rman_get_bustag(sc->sk_res); 1399 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1400 1401 /* Allocate interrupt */ 1402 rid = 0; 1403 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1404 RF_SHAREABLE | RF_ACTIVE); 1405 1406 if (sc->sk_irq == NULL) { 1407 printf("skc%d: couldn't map interrupt\n", unit); 1408 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1409 error = ENXIO; 1410 goto fail; 1411 } 1412 1413 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1414 sk_intr, sc, 1415 &sc->sk_intrhand, NULL); 1416 1417 if (error) { 1418 printf("skc%d: couldn't set up irq\n", unit); 1419 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1420 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1421 goto fail; 1422 } 1423 1424 /* Reset the adapter. */ 1425 sk_reset(sc); 1426 1427 sc->sk_unit = unit; 1428 1429 /* Read and save vital product data from EEPROM. */ 1430 sk_vpd_read(sc); 1431 1432 skrs = sk_win_read_1(sc, SK_EPROM0); 1433 if (sc->sk_type == SK_GENESIS) { 1434 /* Read and save RAM size and RAMbuffer offset */ 1435 switch(skrs) { 1436 case SK_RAMSIZE_512K_64: 1437 sc->sk_ramsize = 0x80000; 1438 sc->sk_rboff = SK_RBOFF_0; 1439 break; 1440 case SK_RAMSIZE_1024K_64: 1441 sc->sk_ramsize = 0x100000; 1442 sc->sk_rboff = SK_RBOFF_80000; 1443 break; 1444 case SK_RAMSIZE_1024K_128: 1445 sc->sk_ramsize = 0x100000; 1446 sc->sk_rboff = SK_RBOFF_0; 1447 break; 1448 case SK_RAMSIZE_2048K_128: 1449 sc->sk_ramsize = 0x200000; 1450 sc->sk_rboff = SK_RBOFF_0; 1451 break; 1452 default: 1453 printf("skc%d: unknown ram size: %d\n", 1454 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1455 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1456 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1457 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1458 error = ENXIO; 1459 goto fail; 1460 break; 1461 } 1462 } else { /* SK_YUKON */ 1463 if (skrs == 0x00) { 1464 sc->sk_ramsize = 0x20000; 1465 } else { 1466 sc->sk_ramsize = skrs * (1<<12); 1467 } 1468 sc->sk_rboff = SK_RBOFF_0; 1469 } 1470 1471 /* Read and save physical media type */ 1472 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1473 case SK_PMD_1000BASESX: 1474 sc->sk_pmd = IFM_1000_SX; 1475 break; 1476 case SK_PMD_1000BASELX: 1477 sc->sk_pmd = IFM_1000_LX; 1478 break; 1479 case SK_PMD_1000BASECX: 1480 sc->sk_pmd = IFM_1000_CX; 1481 break; 1482 case SK_PMD_1000BASETX: 1483 sc->sk_pmd = IFM_1000_T; 1484 break; 1485 default: 1486 printf("skc%d: unknown media type: 0x%x\n", 1487 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1488 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1489 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1490 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1491 error = ENXIO; 1492 goto fail; 1493 } 1494 1495 /* Announce the product name. */ 1496 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1497 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1498 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1499 *port = SK_PORT_A; 1500 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1501 1502 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1503 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1504 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1505 *port = SK_PORT_B; 1506 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1507 } 1508 1509 /* Turn on the 'driver is loaded' LED. */ 1510 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1511 1512 bus_generic_attach(dev); 1513 1514 fail: 1515 splx(s); 1516 return(error); 1517 } 1518 1519 static int 1520 sk_detach(device_t dev) 1521 { 1522 struct sk_if_softc *sc_if = device_get_softc(dev); 1523 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1524 int s; 1525 1526 s = splimp(); 1527 1528 sk_stop(sc_if); 1529 ether_ifdetach(ifp); 1530 bus_generic_detach(dev); 1531 if (sc_if->sk_miibus != NULL) 1532 device_delete_child(dev, sc_if->sk_miibus); 1533 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1534 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF); 1535 1536 splx(s); 1537 1538 return(0); 1539 } 1540 1541 static int 1542 skc_detach(device_t dev) 1543 { 1544 struct sk_softc *sc; 1545 int s; 1546 1547 s = splimp(); 1548 1549 sc = device_get_softc(dev); 1550 1551 bus_generic_detach(dev); 1552 if (sc->sk_devs[SK_PORT_A] != NULL) 1553 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1554 if (sc->sk_devs[SK_PORT_B] != NULL) 1555 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1556 1557 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1558 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1559 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1560 1561 splx(s); 1562 1563 return(0); 1564 } 1565 1566 static int 1567 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1568 { 1569 struct sk_tx_desc *f = NULL; 1570 struct mbuf *m; 1571 uint32_t cnt = 0, cur, frag; 1572 1573 m = m_head; 1574 cur = frag = *txidx; 1575 1576 /* 1577 * Start packing the mbufs in this chain into 1578 * the fragment pointers. Stop when we run out 1579 * of fragments or hit the end of the mbuf chain. 1580 */ 1581 for (m = m_head; m != NULL; m = m->m_next) { 1582 if (m->m_len != 0) { 1583 if ((SK_TX_RING_CNT - 1584 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1585 return(ENOBUFS); 1586 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1587 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1588 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1589 if (cnt == 0) 1590 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1591 else 1592 f->sk_ctl |= SK_TXCTL_OWN; 1593 cur = frag; 1594 SK_INC(frag, SK_TX_RING_CNT); 1595 cnt++; 1596 } 1597 } 1598 1599 if (m != NULL) 1600 return(ENOBUFS); 1601 1602 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1603 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1604 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1605 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1606 sc_if->sk_cdata.sk_tx_cnt += cnt; 1607 1608 *txidx = frag; 1609 1610 return(0); 1611 } 1612 1613 static void 1614 sk_start(struct ifnet *ifp) 1615 { 1616 struct sk_if_softc *sc_if = ifp->if_softc; 1617 struct sk_softc *sc = sc_if->sk_softc; 1618 struct mbuf *m_head = NULL; 1619 uint32_t idx; 1620 1621 idx = sc_if->sk_cdata.sk_tx_prod; 1622 1623 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1624 m_head = ifq_poll(&ifp->if_snd); 1625 if (m_head == NULL) 1626 break; 1627 1628 /* 1629 * Pack the data into the transmit ring. If we 1630 * don't have room, set the OACTIVE flag and wait 1631 * for the NIC to drain the ring. 1632 */ 1633 if (sk_encap(sc_if, m_head, &idx)) { 1634 ifp->if_flags |= IFF_OACTIVE; 1635 break; 1636 } 1637 m_head = ifq_dequeue(&ifp->if_snd); 1638 1639 BPF_MTAP(ifp, m_head); 1640 } 1641 1642 /* Transmit */ 1643 sc_if->sk_cdata.sk_tx_prod = idx; 1644 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1645 1646 /* Set a timeout in case the chip goes out to lunch. */ 1647 ifp->if_timer = 5; 1648 } 1649 1650 1651 static void 1652 sk_watchdog(struct ifnet *ifp) 1653 { 1654 struct sk_if_softc *sc_if; 1655 1656 sc_if = ifp->if_softc; 1657 1658 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1659 sk_init(sc_if); 1660 } 1661 1662 static void 1663 skc_shutdown(device_t dev) 1664 { 1665 struct sk_softc *sc = device_get_softc(dev); 1666 1667 /* Turn off the 'driver is loaded' LED. */ 1668 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1669 1670 /* 1671 * Reset the GEnesis controller. Doing this should also 1672 * assert the resets on the attached XMAC(s). 1673 */ 1674 sk_reset(sc); 1675 } 1676 1677 static void 1678 sk_rxeof(struct sk_if_softc *sc_if) 1679 { 1680 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1681 struct mbuf *m; 1682 struct sk_chain *cur_rx; 1683 int i, total_len = 0; 1684 uint32_t rxstat; 1685 1686 i = sc_if->sk_cdata.sk_rx_prod; 1687 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1688 1689 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1690 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1691 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1692 m = cur_rx->sk_mbuf; 1693 cur_rx->sk_mbuf = NULL; 1694 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1695 SK_INC(i, SK_RX_RING_CNT); 1696 1697 if (rxstat & XM_RXSTAT_ERRFRAME) { 1698 ifp->if_ierrors++; 1699 sk_newbuf(sc_if, cur_rx, m); 1700 continue; 1701 } 1702 1703 /* 1704 * Try to allocate a new jumbo buffer. If that 1705 * fails, copy the packet to mbufs and put the 1706 * jumbo buffer back in the ring so it can be 1707 * re-used. If allocating mbufs fails, then we 1708 * have to drop the packet. 1709 */ 1710 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1711 struct mbuf *m0; 1712 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1713 total_len + ETHER_ALIGN, 0, ifp, NULL); 1714 sk_newbuf(sc_if, cur_rx, m); 1715 if (m0 == NULL) { 1716 printf("sk%d: no receive buffers " 1717 "available -- packet dropped!\n", 1718 sc_if->sk_unit); 1719 ifp->if_ierrors++; 1720 continue; 1721 } 1722 m_adj(m0, ETHER_ALIGN); 1723 m = m0; 1724 } else { 1725 m->m_pkthdr.rcvif = ifp; 1726 m->m_pkthdr.len = m->m_len = total_len; 1727 } 1728 1729 ifp->if_ipackets++; 1730 (*ifp->if_input)(ifp, m); 1731 } 1732 1733 sc_if->sk_cdata.sk_rx_prod = i; 1734 } 1735 1736 static void 1737 sk_txeof(struct sk_if_softc *sc_if) 1738 { 1739 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1740 struct sk_tx_desc *cur_tx = NULL; 1741 uint32_t idx; 1742 1743 /* 1744 * Go through our tx ring and free mbufs for those 1745 * frames that have been sent. 1746 */ 1747 idx = sc_if->sk_cdata.sk_tx_cons; 1748 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1749 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1750 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1751 break; 1752 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1753 ifp->if_opackets++; 1754 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1755 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1756 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1757 } 1758 sc_if->sk_cdata.sk_tx_cnt--; 1759 SK_INC(idx, SK_TX_RING_CNT); 1760 ifp->if_timer = 0; 1761 } 1762 1763 sc_if->sk_cdata.sk_tx_cons = idx; 1764 1765 if (cur_tx != NULL) 1766 ifp->if_flags &= ~IFF_OACTIVE; 1767 } 1768 1769 static void 1770 sk_tick(void *xsc_if) 1771 { 1772 struct sk_if_softc *sc_if = xsc_if; 1773 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1774 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 1775 int i; 1776 1777 if ((ifp->if_flags & IFF_UP) == 0) 1778 return; 1779 1780 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1781 sk_intr_bcom(sc_if); 1782 return; 1783 } 1784 1785 /* 1786 * According to SysKonnect, the correct way to verify that 1787 * the link has come back up is to poll bit 0 of the GPIO 1788 * register three times. This pin has the signal from the 1789 * link_sync pin connected to it; if we read the same link 1790 * state 3 times in a row, we know the link is up. 1791 */ 1792 for (i = 0; i < 3; i++) { 1793 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1794 break; 1795 } 1796 1797 if (i != 3) { 1798 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if); 1799 return; 1800 } 1801 1802 /* Turn the GP0 interrupt back on. */ 1803 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1804 SK_XM_READ_2(sc_if, XM_ISR); 1805 mii_tick(mii); 1806 mii_pollstat(mii); 1807 callout_stop(&sc_if->sk_tick_timer); 1808 } 1809 1810 static void 1811 sk_intr_bcom(struct sk_if_softc *sc_if) 1812 { 1813 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1814 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 1815 int status; 1816 1817 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1818 1819 /* 1820 * Read the PHY interrupt register to make sure 1821 * we clear any pending interrupts. 1822 */ 1823 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1824 1825 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1826 sk_init_xmac(sc_if); 1827 return; 1828 } 1829 1830 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1831 int lstat; 1832 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 1833 BRGPHY_MII_AUXSTS); 1834 1835 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1836 mii_mediachg(mii); 1837 /* Turn off the link LED. */ 1838 SK_IF_WRITE_1(sc_if, 0, 1839 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1840 sc_if->sk_link = 0; 1841 } else if (status & BRGPHY_ISR_LNK_CHG) { 1842 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 1843 BRGPHY_MII_IMR, 0xFF00); 1844 mii_tick(mii); 1845 sc_if->sk_link = 1; 1846 /* Turn on the link LED. */ 1847 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1848 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1849 SK_LINKLED_BLINK_OFF); 1850 mii_pollstat(mii); 1851 } else { 1852 mii_tick(mii); 1853 callout_reset(&sc_if->sk_tick_timer, hz, 1854 sk_tick, sc_if); 1855 } 1856 } 1857 1858 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1859 } 1860 1861 static void 1862 sk_intr_xmac(struct sk_if_softc *sc_if) 1863 { 1864 uint16_t status; 1865 1866 status = SK_XM_READ_2(sc_if, XM_ISR); 1867 1868 /* 1869 * Link has gone down. Start MII tick timeout to 1870 * watch for link resync. 1871 */ 1872 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1873 if (status & XM_ISR_GP0_SET) { 1874 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1875 callout_reset(&sc_if->sk_tick_timer, hz, 1876 sk_tick, sc_if); 1877 } 1878 1879 if (status & XM_ISR_AUTONEG_DONE) { 1880 callout_reset(&sc_if->sk_tick_timer, hz, 1881 sk_tick, sc_if); 1882 } 1883 } 1884 1885 if (status & XM_IMR_TX_UNDERRUN) 1886 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1887 1888 if (status & XM_IMR_RX_OVERRUN) 1889 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1890 1891 status = SK_XM_READ_2(sc_if, XM_ISR); 1892 } 1893 1894 static void 1895 sk_intr_yukon(struct sk_if_softc *sc_if) 1896 { 1897 int status; 1898 1899 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1900 } 1901 1902 static void 1903 sk_intr(void *xsc) 1904 { 1905 struct sk_softc *sc = xsc; 1906 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1907 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_A]; 1908 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1909 uint32_t status; 1910 1911 if (sc_if0 != NULL) 1912 ifp0 = &sc_if0->arpcom.ac_if; 1913 if (sc_if1 != NULL) 1914 ifp1 = &sc_if1->arpcom.ac_if; 1915 1916 for (;;) { 1917 status = CSR_READ_4(sc, SK_ISSR); 1918 if ((status & sc->sk_intrmask) == 0) 1919 break; 1920 1921 /* Handle receive interrupts first. */ 1922 if (status & SK_ISR_RX1_EOF) { 1923 sk_rxeof(sc_if0); 1924 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1925 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1926 } 1927 if (status & SK_ISR_RX2_EOF) { 1928 sk_rxeof(sc_if1); 1929 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1930 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1931 } 1932 1933 /* Then transmit interrupts. */ 1934 if (status & SK_ISR_TX1_S_EOF) { 1935 sk_txeof(sc_if0); 1936 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1937 SK_TXBMU_CLR_IRQ_EOF); 1938 } 1939 if (status & SK_ISR_TX2_S_EOF) { 1940 sk_txeof(sc_if1); 1941 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1942 SK_TXBMU_CLR_IRQ_EOF); 1943 } 1944 1945 /* Then MAC interrupts. */ 1946 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 1947 if (sc->sk_type == SK_GENESIS) 1948 sk_intr_xmac(sc_if0); 1949 else 1950 sk_intr_yukon(sc_if0); 1951 } 1952 1953 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 1954 if (sc->sk_type == SK_GENESIS) 1955 sk_intr_xmac(sc_if1); 1956 else 1957 sk_intr_yukon(sc_if0); 1958 } 1959 1960 if (status & SK_ISR_EXTERNAL_REG) { 1961 if (ifp0 != NULL && 1962 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 1963 sk_intr_bcom(sc_if0); 1964 if (ifp1 != NULL && 1965 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 1966 sk_intr_bcom(sc_if1); 1967 } 1968 } 1969 1970 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1971 1972 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd)) 1973 sk_start(ifp0); 1974 if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd)) 1975 sk_start(ifp1); 1976 } 1977 1978 static void 1979 sk_init_xmac(struct sk_if_softc *sc_if) 1980 { 1981 struct sk_softc *sc = sc_if->sk_softc; 1982 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1983 struct sk_bcom_hack bhack[] = { 1984 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1985 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1986 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1987 { 0, 0 } }; 1988 1989 /* Unreset the XMAC. */ 1990 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1991 DELAY(1000); 1992 1993 /* Reset the XMAC's internal state. */ 1994 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1995 1996 /* Save the XMAC II revision */ 1997 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1998 1999 /* 2000 * Perform additional initialization for external PHYs, 2001 * namely for the 1000baseTX cards that use the XMAC's 2002 * GMII mode. 2003 */ 2004 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2005 int i = 0; 2006 uint32_t val; 2007 2008 /* Take PHY out of reset. */ 2009 val = sk_win_read_4(sc, SK_GPIO); 2010 if (sc_if->sk_port == SK_PORT_A) 2011 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2012 else 2013 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2014 sk_win_write_4(sc, SK_GPIO, val); 2015 2016 /* Enable GMII mode on the XMAC. */ 2017 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2018 2019 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2020 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2021 DELAY(10000); 2022 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2023 BRGPHY_MII_IMR, 0xFFF0); 2024 2025 /* 2026 * Early versions of the BCM5400 apparently have 2027 * a bug that requires them to have their reserved 2028 * registers initialized to some magic values. I don't 2029 * know what the numbers do, I'm just the messenger. 2030 */ 2031 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2032 == 0x6041) { 2033 while(bhack[i].reg) { 2034 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2035 bhack[i].reg, bhack[i].val); 2036 i++; 2037 } 2038 } 2039 } 2040 2041 /* Set station address */ 2042 SK_XM_WRITE_2(sc_if, XM_PAR0, 2043 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2044 SK_XM_WRITE_2(sc_if, XM_PAR1, 2045 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2046 SK_XM_WRITE_2(sc_if, XM_PAR2, 2047 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2048 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2049 2050 if (ifp->if_flags & IFF_BROADCAST) 2051 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2052 else 2053 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2054 2055 /* We don't need the FCS appended to the packet. */ 2056 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2057 2058 /* We want short frames padded to 60 bytes. */ 2059 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2060 2061 /* 2062 * Enable the reception of all error frames. This is is 2063 * a necessary evil due to the design of the XMAC. The 2064 * XMAC's receive FIFO is only 8K in size, however jumbo 2065 * frames can be up to 9000 bytes in length. When bad 2066 * frame filtering is enabled, the XMAC's RX FIFO operates 2067 * in 'store and forward' mode. For this to work, the 2068 * entire frame has to fit into the FIFO, but that means 2069 * that jumbo frames larger than 8192 bytes will be 2070 * truncated. Disabling all bad frame filtering causes 2071 * the RX FIFO to operate in streaming mode, in which 2072 * case the XMAC will start transfering frames out of the 2073 * RX FIFO as soon as the FIFO threshold is reached. 2074 */ 2075 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2076 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2077 XM_MODE_RX_INRANGELEN); 2078 2079 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2080 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2081 else 2082 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2083 2084 /* 2085 * Bump up the transmit threshold. This helps hold off transmit 2086 * underruns when we're blasting traffic from both ports at once. 2087 */ 2088 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2089 2090 /* Set promiscuous mode */ 2091 sk_setpromisc(sc_if); 2092 2093 /* Set multicast filter */ 2094 sk_setmulti(sc_if); 2095 2096 /* Clear and enable interrupts */ 2097 SK_XM_READ_2(sc_if, XM_ISR); 2098 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2099 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2100 else 2101 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2102 2103 /* Configure MAC arbiter */ 2104 switch(sc_if->sk_xmac_rev) { 2105 case XM_XMAC_REV_B2: 2106 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2107 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2108 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2109 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2110 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2111 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2112 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2113 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2114 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2115 break; 2116 case XM_XMAC_REV_C1: 2117 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2118 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2119 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2120 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2121 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2122 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2123 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2124 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2125 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2126 break; 2127 default: 2128 break; 2129 } 2130 sk_win_write_2(sc, SK_MACARB_CTL, 2131 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2132 2133 sc_if->sk_link = 1; 2134 } 2135 2136 static void 2137 sk_init_yukon(struct sk_if_softc *sc_if) 2138 { 2139 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2140 uint32_t phy; 2141 uint16_t reg; 2142 int i; 2143 2144 /* GMAC and GPHY Reset */ 2145 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2146 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2147 DELAY(1000); 2148 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2149 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2150 DELAY(1000); 2151 2152 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2153 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2154 2155 switch(sc_if->sk_softc->sk_pmd) { 2156 case IFM_1000_SX: 2157 case IFM_1000_LX: 2158 phy |= SK_GPHY_FIBER; 2159 break; 2160 2161 case IFM_1000_CX: 2162 case IFM_1000_T: 2163 phy |= SK_GPHY_COPPER; 2164 break; 2165 } 2166 2167 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2168 DELAY(1000); 2169 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2170 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2171 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2172 2173 /* unused read of the interrupt source register */ 2174 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2175 2176 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2177 2178 /* MIB Counter Clear Mode set */ 2179 reg |= YU_PAR_MIB_CLR; 2180 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2181 2182 /* MIB Counter Clear Mode clear */ 2183 reg &= ~YU_PAR_MIB_CLR; 2184 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2185 2186 /* receive control reg */ 2187 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2188 2189 /* transmit parameter register */ 2190 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2191 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2192 2193 /* serial mode register */ 2194 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 2195 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2196 reg |= YU_SMR_MFL_JUMBO; 2197 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2198 2199 /* Setup Yukon's address */ 2200 for (i = 0; i < 3; i++) { 2201 /* Write Source Address 1 (unicast filter) */ 2202 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2203 sc_if->arpcom.ac_enaddr[i * 2] | 2204 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2205 } 2206 2207 for (i = 0; i < 3; i++) { 2208 reg = sk_win_read_2(sc_if->sk_softc, 2209 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2210 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2211 } 2212 2213 /* Set promiscuous mode */ 2214 sk_setpromisc(sc_if); 2215 2216 /* Set multicast filter */ 2217 sk_setmulti(sc_if); 2218 2219 /* enable interrupt mask for counter overflows */ 2220 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2221 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2222 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2223 2224 /* Configure RX MAC FIFO */ 2225 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2226 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2227 2228 /* Configure TX MAC FIFO */ 2229 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2230 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2231 } 2232 2233 /* 2234 * Note that to properly initialize any part of the GEnesis chip, 2235 * you first have to take it out of reset mode. 2236 */ 2237 static void 2238 sk_init(void *xsc) 2239 { 2240 struct sk_if_softc *sc_if = xsc; 2241 struct sk_softc *sc = sc_if->sk_softc; 2242 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2243 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2244 int s; 2245 uint16_t reg; 2246 2247 s = splimp(); 2248 2249 /* Cancel pending I/O and free all RX/TX buffers. */ 2250 sk_stop(sc_if); 2251 2252 if (sc->sk_type == SK_GENESIS) { 2253 /* Configure LINK_SYNC LED */ 2254 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2255 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2256 SK_LINKLED_LINKSYNC_ON); 2257 2258 /* Configure RX LED */ 2259 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2260 SK_RXLEDCTL_COUNTER_START); 2261 2262 /* Configure TX LED */ 2263 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2264 SK_TXLEDCTL_COUNTER_START); 2265 } 2266 2267 /* Configure I2C registers */ 2268 2269 /* Configure XMAC(s) */ 2270 switch (sc->sk_type) { 2271 case SK_GENESIS: 2272 sk_init_xmac(sc_if); 2273 break; 2274 case SK_YUKON: 2275 sk_init_yukon(sc_if); 2276 break; 2277 } 2278 mii_mediachg(mii); 2279 2280 if (sc->sk_type == SK_GENESIS) { 2281 /* Configure MAC FIFOs */ 2282 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2283 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2284 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2285 2286 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2287 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2288 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2289 } 2290 2291 /* Configure transmit arbiter(s) */ 2292 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2293 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2294 2295 /* Configure RAMbuffers */ 2296 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2297 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2298 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2299 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2300 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2301 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2302 2303 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2304 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2305 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2306 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2307 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2308 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2309 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2310 2311 /* Configure BMUs */ 2312 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2313 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2314 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2315 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2316 2317 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2318 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2319 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2320 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2321 2322 /* Init descriptors */ 2323 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2324 printf("sk%d: initialization failed: no " 2325 "memory for rx buffers\n", sc_if->sk_unit); 2326 sk_stop(sc_if); 2327 splx(s); 2328 return; 2329 } 2330 sk_init_tx_ring(sc_if); 2331 2332 /* Configure interrupt handling */ 2333 CSR_READ_4(sc, SK_ISSR); 2334 if (sc_if->sk_port == SK_PORT_A) 2335 sc->sk_intrmask |= SK_INTRS1; 2336 else 2337 sc->sk_intrmask |= SK_INTRS2; 2338 2339 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2340 2341 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2342 2343 /* Start BMUs. */ 2344 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2345 2346 switch(sc->sk_type) { 2347 case SK_GENESIS: 2348 /* Enable XMACs TX and RX state machines */ 2349 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2350 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2351 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2352 break; 2353 case SK_YUKON: 2354 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2355 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2356 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2357 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2358 } 2359 2360 ifp->if_flags |= IFF_RUNNING; 2361 ifp->if_flags &= ~IFF_OACTIVE; 2362 2363 splx(s); 2364 } 2365 2366 static void 2367 sk_stop(struct sk_if_softc *sc_if) 2368 { 2369 int i; 2370 struct sk_softc *sc = sc_if->sk_softc; 2371 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2372 2373 callout_stop(&sc_if->sk_tick_timer); 2374 2375 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2376 uint32_t val; 2377 2378 /* Put PHY back into reset. */ 2379 val = sk_win_read_4(sc, SK_GPIO); 2380 if (sc_if->sk_port == SK_PORT_A) { 2381 val |= SK_GPIO_DIR0; 2382 val &= ~SK_GPIO_DAT0; 2383 } else { 2384 val |= SK_GPIO_DIR2; 2385 val &= ~SK_GPIO_DAT2; 2386 } 2387 sk_win_write_4(sc, SK_GPIO, val); 2388 } 2389 2390 /* Turn off various components of this interface. */ 2391 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2392 switch (sc->sk_type) { 2393 case SK_GENESIS: 2394 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2395 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2396 break; 2397 case SK_YUKON: 2398 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2399 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2400 break; 2401 } 2402 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2403 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2404 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2405 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, 2406 SK_RBCTL_RESET | SK_RBCTL_OFF); 2407 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2408 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2409 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2410 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2411 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2412 2413 /* Disable interrupts */ 2414 if (sc_if->sk_port == SK_PORT_A) 2415 sc->sk_intrmask &= ~SK_INTRS1; 2416 else 2417 sc->sk_intrmask &= ~SK_INTRS2; 2418 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2419 2420 SK_XM_READ_2(sc_if, XM_ISR); 2421 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2422 2423 /* Free RX and TX mbufs still in the queues. */ 2424 for (i = 0; i < SK_RX_RING_CNT; i++) { 2425 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2426 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2427 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2428 } 2429 } 2430 2431 for (i = 0; i < SK_TX_RING_CNT; i++) { 2432 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2433 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2434 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2435 } 2436 } 2437 2438 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2439 } 2440