1 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $ 35 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.26 2005/02/21 18:40:37 joerg Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 /* 55 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 56 * the SK-984x series adapters, both single port and dual port. 57 * References: 58 * The XaQti XMAC II datasheet, 59 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 60 * The SysKonnect GEnesis manual, http://www.syskonnect.com 61 * 62 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 63 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 64 * convenience to others until Vitesse corrects this problem: 65 * 66 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 67 * 68 * Written by Bill Paul <wpaul@ee.columbia.edu> 69 * Department of Electrical Engineering 70 * Columbia University, New York City 71 */ 72 73 /* 74 * The SysKonnect gigabit ethernet adapters consist of two main 75 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 76 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 77 * components and a PHY while the GEnesis controller provides a PCI 78 * interface with DMA support. Each card may have between 512K and 79 * 2MB of SRAM on board depending on the configuration. 80 * 81 * The SysKonnect GEnesis controller can have either one or two XMAC 82 * chips connected to it, allowing single or dual port NIC configurations. 83 * SysKonnect has the distinction of being the only vendor on the market 84 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 85 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 86 * XMAC registers. This driver takes advantage of these features to allow 87 * both XMACs to operate as independent interfaces. 88 */ 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 99 #include <net/if.h> 100 #include <net/ifq_var.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 106 #include <net/bpf.h> 107 108 #include <vm/vm.h> /* for vtophys */ 109 #include <vm/pmap.h> /* for vtophys */ 110 #include <machine/clock.h> /* for DELAY */ 111 #include <machine/bus_pio.h> 112 #include <machine/bus_memio.h> 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #include "../mii_layer/mii.h" 119 #include "../mii_layer/miivar.h" 120 #include "../mii_layer/brgphyreg.h" 121 122 #include <bus/pci/pcireg.h> 123 #include <bus/pci/pcivar.h> 124 125 #if 0 126 #define SK_USEIOSPACE 127 #endif 128 129 #include "if_skreg.h" 130 #include "xmaciireg.h" 131 #include "yukonreg.h" 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 static struct sk_type sk_devs[] = { 137 { 138 VENDORID_SK, 139 DEVICEID_SK_V1, 140 "SysKonnect Gigabit Ethernet (V1.0)" 141 }, 142 { 143 VENDORID_SK, 144 DEVICEID_SK_V2, 145 "SysKonnect Gigabit Ethernet (V2.0)" 146 }, 147 { 148 VENDORID_MARVELL, 149 DEVICEID_SK_V2, 150 "Marvell Gigabit Ethernet" 151 }, 152 { 153 VENDORID_3COM, 154 DEVICEID_3COM_3C940, 155 "3Com 3C940 Gigabit Ethernet" 156 }, 157 { 158 VENDORID_LINKSYS, 159 DEVICEID_LINKSYS_EG1032, 160 "Linksys EG1032 Gigabit Ethernet" 161 }, 162 { 163 VENDORID_DLINK, 164 DEVICEID_DLINK_DGE530T, 165 "D-Link DGE-530T Gigabit Ethernet" 166 }, 167 { 0, 0, NULL } 168 }; 169 170 static int skc_probe (device_t); 171 static int skc_attach (device_t); 172 static int skc_detach (device_t); 173 static void skc_shutdown (device_t); 174 static int sk_probe (device_t); 175 static int sk_attach (device_t); 176 static int sk_detach (device_t); 177 static void sk_tick (void *); 178 static void sk_intr (void *); 179 static void sk_intr_bcom (struct sk_if_softc *); 180 static void sk_intr_xmac (struct sk_if_softc *); 181 static void sk_intr_yukon (struct sk_if_softc *); 182 static void sk_rxeof (struct sk_if_softc *); 183 static void sk_txeof (struct sk_if_softc *); 184 static int sk_encap (struct sk_if_softc *, struct mbuf *, 185 u_int32_t *); 186 static void sk_start (struct ifnet *); 187 static int sk_ioctl (struct ifnet *, u_long, caddr_t, 188 struct ucred *); 189 static void sk_init (void *); 190 static void sk_init_xmac (struct sk_if_softc *); 191 static void sk_init_yukon (struct sk_if_softc *); 192 static void sk_stop (struct sk_if_softc *); 193 static void sk_watchdog (struct ifnet *); 194 static int sk_ifmedia_upd (struct ifnet *); 195 static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *); 196 static void sk_reset (struct sk_softc *); 197 static int sk_newbuf (struct sk_if_softc *, 198 struct sk_chain *, struct mbuf *); 199 static int sk_alloc_jumbo_mem (struct sk_if_softc *); 200 static void *sk_jalloc (struct sk_if_softc *); 201 static void sk_jfree (caddr_t, u_int); 202 static void sk_jref (caddr_t, u_int); 203 static int sk_init_rx_ring (struct sk_if_softc *); 204 static void sk_init_tx_ring (struct sk_if_softc *); 205 static u_int32_t sk_win_read_4 (struct sk_softc *, int); 206 static u_int16_t sk_win_read_2 (struct sk_softc *, int); 207 static u_int8_t sk_win_read_1 (struct sk_softc *, int); 208 static void sk_win_write_4 (struct sk_softc *, int, u_int32_t); 209 static void sk_win_write_2 (struct sk_softc *, int, u_int32_t); 210 static void sk_win_write_1 (struct sk_softc *, int, u_int32_t); 211 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int); 212 static void sk_vpd_read_res (struct sk_softc *, 213 struct vpd_res *, int); 214 static void sk_vpd_read (struct sk_softc *); 215 216 static int sk_miibus_readreg (device_t, int, int); 217 static int sk_miibus_writereg (device_t, int, int, int); 218 static void sk_miibus_statchg (device_t); 219 220 static int sk_xmac_miibus_readreg (struct sk_if_softc *, int, int); 221 static int sk_xmac_miibus_writereg (struct sk_if_softc *, int, int, int); 222 static void sk_xmac_miibus_statchg (struct sk_if_softc *); 223 224 static int sk_marv_miibus_readreg (struct sk_if_softc *, int, int); 225 static int sk_marv_miibus_writereg (struct sk_if_softc *, int, int, int); 226 static void sk_marv_miibus_statchg (struct sk_if_softc *); 227 228 static u_int32_t xmac_calchash (caddr_t); 229 static u_int32_t gmac_calchash (caddr_t); 230 static void sk_setfilt (struct sk_if_softc *, caddr_t, int); 231 static void sk_setmulti (struct sk_if_softc *); 232 static void sk_setpromisc (struct sk_if_softc *); 233 234 #ifdef SK_USEIOSPACE 235 #define SK_RES SYS_RES_IOPORT 236 #define SK_RID SK_PCI_LOIO 237 #else 238 #define SK_RES SYS_RES_MEMORY 239 #define SK_RID SK_PCI_LOMEM 240 #endif 241 242 /* 243 * Note that we have newbus methods for both the GEnesis controller 244 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 245 * the miibus code is a child of the XMACs. We need to do it this way 246 * so that the miibus drivers can access the PHY registers on the 247 * right PHY. It's not quite what I had in mind, but it's the only 248 * design that achieves the desired effect. 249 */ 250 static device_method_t skc_methods[] = { 251 /* Device interface */ 252 DEVMETHOD(device_probe, skc_probe), 253 DEVMETHOD(device_attach, skc_attach), 254 DEVMETHOD(device_detach, skc_detach), 255 DEVMETHOD(device_shutdown, skc_shutdown), 256 257 /* bus interface */ 258 DEVMETHOD(bus_print_child, bus_generic_print_child), 259 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 260 261 { 0, 0 } 262 }; 263 264 static driver_t skc_driver = { 265 "skc", 266 skc_methods, 267 sizeof(struct sk_softc) 268 }; 269 270 static devclass_t skc_devclass; 271 272 static device_method_t sk_methods[] = { 273 /* Device interface */ 274 DEVMETHOD(device_probe, sk_probe), 275 DEVMETHOD(device_attach, sk_attach), 276 DEVMETHOD(device_detach, sk_detach), 277 DEVMETHOD(device_shutdown, bus_generic_shutdown), 278 279 /* bus interface */ 280 DEVMETHOD(bus_print_child, bus_generic_print_child), 281 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 282 283 /* MII interface */ 284 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 285 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 286 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 287 288 { 0, 0 } 289 }; 290 291 static driver_t sk_driver = { 292 "sk", 293 sk_methods, 294 sizeof(struct sk_if_softc) 295 }; 296 297 static devclass_t sk_devclass; 298 299 DECLARE_DUMMY_MODULE(if_sk); 300 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 301 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0); 302 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 303 304 #define SK_SETBIT(sc, reg, x) \ 305 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 306 307 #define SK_CLRBIT(sc, reg, x) \ 308 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 309 310 #define SK_WIN_SETBIT_4(sc, reg, x) \ 311 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 312 313 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 314 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 315 316 #define SK_WIN_SETBIT_2(sc, reg, x) \ 317 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 318 319 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 320 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 321 322 static u_int32_t sk_win_read_4(sc, reg) 323 struct sk_softc *sc; 324 int reg; 325 { 326 #ifdef SK_USEIOSPACE 327 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 328 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 329 #else 330 return(CSR_READ_4(sc, reg)); 331 #endif 332 } 333 334 static u_int16_t sk_win_read_2(sc, reg) 335 struct sk_softc *sc; 336 int reg; 337 { 338 #ifdef SK_USEIOSPACE 339 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 340 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 341 #else 342 return(CSR_READ_2(sc, reg)); 343 #endif 344 } 345 346 static u_int8_t sk_win_read_1(sc, reg) 347 struct sk_softc *sc; 348 int reg; 349 { 350 #ifdef SK_USEIOSPACE 351 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 352 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 353 #else 354 return(CSR_READ_1(sc, reg)); 355 #endif 356 } 357 358 static void sk_win_write_4(sc, reg, val) 359 struct sk_softc *sc; 360 int reg; 361 u_int32_t val; 362 { 363 #ifdef SK_USEIOSPACE 364 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 365 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 366 #else 367 CSR_WRITE_4(sc, reg, val); 368 #endif 369 return; 370 } 371 372 static void sk_win_write_2(sc, reg, val) 373 struct sk_softc *sc; 374 int reg; 375 u_int32_t val; 376 { 377 #ifdef SK_USEIOSPACE 378 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 379 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 380 #else 381 CSR_WRITE_2(sc, reg, val); 382 #endif 383 return; 384 } 385 386 static void sk_win_write_1(sc, reg, val) 387 struct sk_softc *sc; 388 int reg; 389 u_int32_t val; 390 { 391 #ifdef SK_USEIOSPACE 392 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 393 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 394 #else 395 CSR_WRITE_1(sc, reg, val); 396 #endif 397 return; 398 } 399 400 /* 401 * The VPD EEPROM contains Vital Product Data, as suggested in 402 * the PCI 2.1 specification. The VPD data is separared into areas 403 * denoted by resource IDs. The SysKonnect VPD contains an ID string 404 * resource (the name of the adapter), a read-only area resource 405 * containing various key/data fields and a read/write area which 406 * can be used to store asset management information or log messages. 407 * We read the ID string and read-only into buffers attached to 408 * the controller softc structure for later use. At the moment, 409 * we only use the ID string during sk_attach(). 410 */ 411 static u_int8_t sk_vpd_readbyte(sc, addr) 412 struct sk_softc *sc; 413 int addr; 414 { 415 int i; 416 417 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 418 for (i = 0; i < SK_TIMEOUT; i++) { 419 DELAY(1); 420 if (sk_win_read_2(sc, 421 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 422 break; 423 } 424 425 if (i == SK_TIMEOUT) 426 return(0); 427 428 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 429 } 430 431 static void sk_vpd_read_res(sc, res, addr) 432 struct sk_softc *sc; 433 struct vpd_res *res; 434 int addr; 435 { 436 int i; 437 u_int8_t *ptr; 438 439 ptr = (u_int8_t *)res; 440 for (i = 0; i < sizeof(struct vpd_res); i++) 441 ptr[i] = sk_vpd_readbyte(sc, i + addr); 442 443 return; 444 } 445 446 static void sk_vpd_read(sc) 447 struct sk_softc *sc; 448 { 449 int pos = 0, i; 450 struct vpd_res res; 451 452 if (sc->sk_vpd_prodname != NULL) 453 free(sc->sk_vpd_prodname, M_DEVBUF); 454 if (sc->sk_vpd_readonly != NULL) 455 free(sc->sk_vpd_readonly, M_DEVBUF); 456 sc->sk_vpd_prodname = NULL; 457 sc->sk_vpd_readonly = NULL; 458 459 sk_vpd_read_res(sc, &res, pos); 460 461 if (res.vr_id != VPD_RES_ID) { 462 printf("skc%d: bad VPD resource id: expected %x got %x\n", 463 sc->sk_unit, VPD_RES_ID, res.vr_id); 464 return; 465 } 466 467 pos += sizeof(res); 468 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT); 469 for (i = 0; i < res.vr_len; i++) 470 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 471 sc->sk_vpd_prodname[i] = '\0'; 472 pos += i; 473 474 sk_vpd_read_res(sc, &res, pos); 475 476 if (res.vr_id != VPD_RES_READ) { 477 printf("skc%d: bad VPD resource id: expected %x got %x\n", 478 sc->sk_unit, VPD_RES_READ, res.vr_id); 479 return; 480 } 481 482 pos += sizeof(res); 483 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT); 484 for (i = 0; i < res.vr_len + 1; i++) 485 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 486 487 return; 488 } 489 490 static int sk_miibus_readreg(dev, phy, reg) 491 device_t dev; 492 int phy, reg; 493 { 494 struct sk_if_softc *sc_if; 495 496 sc_if = device_get_softc(dev); 497 498 switch(sc_if->sk_softc->sk_type) { 499 case SK_GENESIS: 500 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 501 case SK_YUKON: 502 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 503 } 504 505 return(0); 506 } 507 508 static int sk_miibus_writereg(dev, phy, reg, val) 509 device_t dev; 510 int phy, reg, val; 511 { 512 struct sk_if_softc *sc_if; 513 514 sc_if = device_get_softc(dev); 515 516 switch(sc_if->sk_softc->sk_type) { 517 case SK_GENESIS: 518 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 519 case SK_YUKON: 520 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 521 } 522 523 return(0); 524 } 525 526 static void sk_miibus_statchg(dev) 527 device_t dev; 528 { 529 struct sk_if_softc *sc_if; 530 531 sc_if = device_get_softc(dev); 532 533 switch(sc_if->sk_softc->sk_type) { 534 case SK_GENESIS: 535 sk_xmac_miibus_statchg(sc_if); 536 break; 537 case SK_YUKON: 538 sk_marv_miibus_statchg(sc_if); 539 break; 540 } 541 542 return; 543 } 544 545 static int sk_xmac_miibus_readreg(sc_if, phy, reg) 546 struct sk_if_softc *sc_if; 547 int phy, reg; 548 { 549 int i; 550 551 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 552 return(0); 553 554 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 555 SK_XM_READ_2(sc_if, XM_PHY_DATA); 556 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 557 for (i = 0; i < SK_TIMEOUT; i++) { 558 DELAY(1); 559 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 560 XM_MMUCMD_PHYDATARDY) 561 break; 562 } 563 564 if (i == SK_TIMEOUT) { 565 printf("sk%d: phy failed to come ready\n", 566 sc_if->sk_unit); 567 return(0); 568 } 569 } 570 DELAY(1); 571 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 572 } 573 574 static int sk_xmac_miibus_writereg(sc_if, phy, reg, val) 575 struct sk_if_softc *sc_if; 576 int phy, reg, val; 577 { 578 int i; 579 580 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 581 for (i = 0; i < SK_TIMEOUT; i++) { 582 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 583 break; 584 } 585 586 if (i == SK_TIMEOUT) { 587 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 588 return(ETIMEDOUT); 589 } 590 591 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 592 for (i = 0; i < SK_TIMEOUT; i++) { 593 DELAY(1); 594 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 595 break; 596 } 597 598 if (i == SK_TIMEOUT) 599 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 600 601 return(0); 602 } 603 604 static void sk_xmac_miibus_statchg(sc_if) 605 struct sk_if_softc *sc_if; 606 { 607 struct mii_data *mii; 608 609 mii = device_get_softc(sc_if->sk_miibus); 610 611 /* 612 * If this is a GMII PHY, manually set the XMAC's 613 * duplex mode accordingly. 614 */ 615 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 616 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 617 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 618 } else { 619 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 620 } 621 } 622 623 return; 624 } 625 626 static int sk_marv_miibus_readreg(sc_if, phy, reg) 627 struct sk_if_softc *sc_if; 628 int phy, reg; 629 { 630 u_int16_t val; 631 int i; 632 633 if (phy != 0 || 634 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 635 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 636 return(0); 637 } 638 639 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 640 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 641 642 for (i = 0; i < SK_TIMEOUT; i++) { 643 DELAY(1); 644 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 645 if (val & YU_SMICR_READ_VALID) 646 break; 647 } 648 649 if (i == SK_TIMEOUT) { 650 printf("sk%d: phy failed to come ready\n", 651 sc_if->sk_unit); 652 return(0); 653 } 654 655 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 656 657 return(val); 658 } 659 660 static int sk_marv_miibus_writereg(sc_if, phy, reg, val) 661 struct sk_if_softc *sc_if; 662 int phy, reg, val; 663 { 664 int i; 665 666 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 667 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 668 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 669 670 for (i = 0; i < SK_TIMEOUT; i++) { 671 DELAY(1); 672 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 673 break; 674 } 675 676 return(0); 677 } 678 679 static void sk_marv_miibus_statchg(sc_if) 680 struct sk_if_softc *sc_if; 681 { 682 return; 683 } 684 685 #define XMAC_POLY 0xEDB88320 686 #define GMAC_POLY 0x04C11DB7L 687 #define HASH_BITS 6 688 689 static u_int32_t xmac_calchash(addr) 690 caddr_t addr; 691 { 692 u_int32_t idx, bit, data, crc; 693 694 /* Compute CRC for the address value. */ 695 crc = 0xFFFFFFFF; /* initial value */ 696 697 for (idx = 0; idx < 6; idx++) { 698 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 699 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? XMAC_POLY : 0); 700 } 701 702 return (~crc & ((1 << HASH_BITS) - 1)); 703 } 704 705 static u_int32_t gmac_calchash(addr) 706 caddr_t addr; 707 { 708 u_int32_t idx, bit, crc, tmpData, data; 709 710 /* Compute CRC for the address value. */ 711 crc = 0xFFFFFFFF; /* initial value */ 712 713 for (idx = 0; idx < 6; idx++) { 714 data = *addr++; 715 716 /* Change bit order in byte. */ 717 tmpData = data; 718 for (bit = 0; bit < 8; bit++) { 719 if (tmpData & 1) { 720 data |= 1 << (7 - bit); 721 } 722 else { 723 data &= ~(1 << (7 - bit)); 724 } 725 726 tmpData >>= 1; 727 } 728 729 crc ^= (data << 24); 730 for (bit = 0; bit < 8; bit++) { 731 if (crc & 0x80000000) { 732 crc = (crc << 1) ^ GMAC_POLY; 733 } else { 734 crc <<= 1; 735 } 736 } 737 } 738 739 return (crc & ((1 << HASH_BITS) - 1)); 740 } 741 742 static void sk_setfilt(sc_if, addr, slot) 743 struct sk_if_softc *sc_if; 744 caddr_t addr; 745 int slot; 746 { 747 int base; 748 749 base = XM_RXFILT_ENTRY(slot); 750 751 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 752 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 753 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 754 755 return; 756 } 757 758 static void sk_setmulti(sc_if) 759 struct sk_if_softc *sc_if; 760 { 761 struct sk_softc *sc = sc_if->sk_softc; 762 struct ifnet *ifp = &sc_if->arpcom.ac_if; 763 u_int32_t hashes[2] = { 0, 0 }; 764 int h, i; 765 struct ifmultiaddr *ifma; 766 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 767 768 769 /* First, zot all the existing filters. */ 770 switch(sc->sk_type) { 771 case SK_GENESIS: 772 for (i = 1; i < XM_RXFILT_MAX; i++) 773 sk_setfilt(sc_if, (caddr_t)&dummy, i); 774 775 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 776 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 777 break; 778 case SK_YUKON: 779 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 780 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 781 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 782 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 783 break; 784 } 785 786 /* Now program new ones. */ 787 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 788 hashes[0] = 0xFFFFFFFF; 789 hashes[1] = 0xFFFFFFFF; 790 } else { 791 i = 1; 792 /* First find the tail of the list. */ 793 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 794 ifma = ifma->ifma_link.le_next) { 795 if (ifma->ifma_link.le_next == NULL) 796 break; 797 } 798 /* Now traverse the list backwards. */ 799 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 800 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 801 if (ifma->ifma_addr->sa_family != AF_LINK) 802 continue; 803 /* 804 * Program the first XM_RXFILT_MAX multicast groups 805 * into the perfect filter. For all others, 806 * use the hash table. 807 */ 808 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 809 sk_setfilt(sc_if, 810 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 811 i++; 812 continue; 813 } 814 815 switch(sc->sk_type) { 816 case SK_GENESIS: 817 h = xmac_calchash( 818 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 819 if (h < 32) 820 hashes[0] |= (1 << h); 821 else 822 hashes[1] |= (1 << (h - 32)); 823 break; 824 825 case SK_YUKON: 826 h = gmac_calchash( 827 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 828 if (h < 32) 829 hashes[0] |= (1 << h); 830 else 831 hashes[1] |= (1 << (h - 32)); 832 break; 833 } 834 } 835 } 836 837 switch(sc->sk_type) { 838 case SK_GENESIS: 839 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 840 XM_MODE_RX_USE_PERFECT); 841 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 842 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 843 break; 844 case SK_YUKON: 845 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 846 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 847 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 848 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 849 break; 850 } 851 852 return; 853 } 854 855 static void sk_setpromisc(sc_if) 856 struct sk_if_softc *sc_if; 857 { 858 struct sk_softc *sc = sc_if->sk_softc; 859 struct ifnet *ifp = &sc_if->arpcom.ac_if; 860 861 switch(sc->sk_type) { 862 case SK_GENESIS: 863 if (ifp->if_flags & IFF_PROMISC) { 864 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 865 } else { 866 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 867 } 868 break; 869 case SK_YUKON: 870 if (ifp->if_flags & IFF_PROMISC) { 871 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 872 YU_RCR_UFLEN | YU_RCR_MUFLEN); 873 } else { 874 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 875 YU_RCR_UFLEN | YU_RCR_MUFLEN); 876 } 877 break; 878 } 879 880 return; 881 } 882 883 static int sk_init_rx_ring(sc_if) 884 struct sk_if_softc *sc_if; 885 { 886 struct sk_chain_data *cd = &sc_if->sk_cdata; 887 struct sk_ring_data *rd = sc_if->sk_rdata; 888 int i; 889 890 bzero((char *)rd->sk_rx_ring, 891 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 892 893 for (i = 0; i < SK_RX_RING_CNT; i++) { 894 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 895 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 896 return(ENOBUFS); 897 if (i == (SK_RX_RING_CNT - 1)) { 898 cd->sk_rx_chain[i].sk_next = 899 &cd->sk_rx_chain[0]; 900 rd->sk_rx_ring[i].sk_next = 901 vtophys(&rd->sk_rx_ring[0]); 902 } else { 903 cd->sk_rx_chain[i].sk_next = 904 &cd->sk_rx_chain[i + 1]; 905 rd->sk_rx_ring[i].sk_next = 906 vtophys(&rd->sk_rx_ring[i + 1]); 907 } 908 } 909 910 sc_if->sk_cdata.sk_rx_prod = 0; 911 sc_if->sk_cdata.sk_rx_cons = 0; 912 913 return(0); 914 } 915 916 static void sk_init_tx_ring(sc_if) 917 struct sk_if_softc *sc_if; 918 { 919 struct sk_chain_data *cd = &sc_if->sk_cdata; 920 struct sk_ring_data *rd = sc_if->sk_rdata; 921 int i; 922 923 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 924 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 925 926 for (i = 0; i < SK_TX_RING_CNT; i++) { 927 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 928 if (i == (SK_TX_RING_CNT - 1)) { 929 cd->sk_tx_chain[i].sk_next = 930 &cd->sk_tx_chain[0]; 931 rd->sk_tx_ring[i].sk_next = 932 vtophys(&rd->sk_tx_ring[0]); 933 } else { 934 cd->sk_tx_chain[i].sk_next = 935 &cd->sk_tx_chain[i + 1]; 936 rd->sk_tx_ring[i].sk_next = 937 vtophys(&rd->sk_tx_ring[i + 1]); 938 } 939 } 940 941 sc_if->sk_cdata.sk_tx_prod = 0; 942 sc_if->sk_cdata.sk_tx_cons = 0; 943 sc_if->sk_cdata.sk_tx_cnt = 0; 944 945 return; 946 } 947 948 static int sk_newbuf(sc_if, c, m) 949 struct sk_if_softc *sc_if; 950 struct sk_chain *c; 951 struct mbuf *m; 952 { 953 struct mbuf *m_new = NULL; 954 struct sk_rx_desc *r; 955 956 if (m == NULL) { 957 caddr_t *buf = NULL; 958 959 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 960 if (m_new == NULL) 961 return(ENOBUFS); 962 963 /* Allocate the jumbo buffer */ 964 buf = sk_jalloc(sc_if); 965 if (buf == NULL) { 966 m_freem(m_new); 967 #ifdef SK_VERBOSE 968 printf("sk%d: jumbo allocation failed " 969 "-- packet dropped!\n", sc_if->sk_unit); 970 #endif 971 return(ENOBUFS); 972 } 973 974 /* Attach the buffer to the mbuf */ 975 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 976 m_new->m_flags |= M_EXT | M_EXT_OLD; 977 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 978 m_new->m_len = SK_MCLBYTES; 979 m_new->m_ext.ext_nfree.old = sk_jfree; 980 m_new->m_ext.ext_nref.old = sk_jref; 981 } else { 982 /* 983 * We're re-using a previously allocated mbuf; 984 * be sure to re-init pointers and lengths to 985 * default values. 986 */ 987 m_new = m; 988 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES; 989 m_new->m_data = m_new->m_ext.ext_buf; 990 } 991 992 /* 993 * Adjust alignment so packet payload begins on a 994 * longword boundary. Mandatory for Alpha, useful on 995 * x86 too. 996 */ 997 m_adj(m_new, ETHER_ALIGN); 998 999 r = c->sk_desc; 1000 c->sk_mbuf = m_new; 1001 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 1002 r->sk_ctl = m_new->m_len | SK_RXSTAT; 1003 1004 return(0); 1005 } 1006 1007 /* 1008 * Allocate jumbo buffer storage. The SysKonnect adapters support 1009 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1010 * use them in their drivers. In order for us to use them, we need 1011 * large 9K receive buffers, however standard mbuf clusters are only 1012 * 2048 bytes in size. Consequently, we need to allocate and manage 1013 * our own jumbo buffer pool. Fortunately, this does not require an 1014 * excessive amount of additional code. 1015 */ 1016 static int sk_alloc_jumbo_mem(sc_if) 1017 struct sk_if_softc *sc_if; 1018 { 1019 caddr_t ptr; 1020 int i; 1021 struct sk_jpool_entry *entry; 1022 1023 /* Grab a big chunk o' storage. */ 1024 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 1025 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1026 1027 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 1028 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 1029 return(ENOBUFS); 1030 } 1031 1032 SLIST_INIT(&sc_if->sk_jfree_listhead); 1033 SLIST_INIT(&sc_if->sk_jinuse_listhead); 1034 1035 /* 1036 * Now divide it up into 9K pieces and save the addresses 1037 * in an array. Note that we play an evil trick here by using 1038 * the first few bytes in the buffer to hold the the address 1039 * of the softc structure for this interface. This is because 1040 * sk_jfree() needs it, but it is called by the mbuf management 1041 * code which will not pass it to us explicitly. 1042 */ 1043 ptr = sc_if->sk_cdata.sk_jumbo_buf; 1044 for (i = 0; i < SK_JSLOTS; i++) { 1045 u_int64_t **aptr; 1046 aptr = (u_int64_t **)ptr; 1047 aptr[0] = (u_int64_t *)sc_if; 1048 ptr += sizeof(u_int64_t); 1049 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr; 1050 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0; 1051 ptr += SK_MCLBYTES; 1052 entry = malloc(sizeof(struct sk_jpool_entry), 1053 M_DEVBUF, M_WAITOK); 1054 if (entry == NULL) { 1055 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 1056 sc_if->sk_cdata.sk_jumbo_buf = NULL; 1057 printf("sk%d: no memory for jumbo " 1058 "buffer queue!\n", sc_if->sk_unit); 1059 return(ENOBUFS); 1060 } 1061 entry->slot = i; 1062 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 1063 entry, jpool_entries); 1064 } 1065 1066 return(0); 1067 } 1068 1069 /* 1070 * Allocate a jumbo buffer. 1071 */ 1072 static void *sk_jalloc(sc_if) 1073 struct sk_if_softc *sc_if; 1074 { 1075 struct sk_jpool_entry *entry; 1076 1077 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 1078 1079 if (entry == NULL) { 1080 #ifdef SK_VERBOSE 1081 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 1082 #endif 1083 return(NULL); 1084 } 1085 1086 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 1087 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 1088 sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1; 1089 return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf); 1090 } 1091 1092 /* 1093 * Adjust usage count on a jumbo buffer. In general this doesn't 1094 * get used much because our jumbo buffers don't get passed around 1095 * a lot, but it's implemented for correctness. 1096 */ 1097 static void sk_jref(buf, size) 1098 caddr_t buf; 1099 u_int size; 1100 { 1101 struct sk_if_softc *sc_if; 1102 u_int64_t **aptr; 1103 int i; 1104 1105 /* Extract the softc struct pointer. */ 1106 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 1107 sc_if = (struct sk_if_softc *)(aptr[0]); 1108 1109 if (sc_if == NULL) 1110 panic("sk_jref: can't find softc pointer!"); 1111 1112 if (size != SK_MCLBYTES) 1113 panic("sk_jref: adjusting refcount of buf of wrong size!"); 1114 1115 /* calculate the slot this buffer belongs to */ 1116 1117 i = ((vm_offset_t)aptr 1118 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 1119 1120 if ((i < 0) || (i >= SK_JSLOTS)) 1121 panic("sk_jref: asked to reference buffer " 1122 "that we don't manage!"); 1123 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) 1124 panic("sk_jref: buffer already free!"); 1125 else 1126 sc_if->sk_cdata.sk_jslots[i].sk_inuse++; 1127 1128 return; 1129 } 1130 1131 /* 1132 * Release a jumbo buffer. 1133 */ 1134 static void sk_jfree(buf, size) 1135 caddr_t buf; 1136 u_int size; 1137 { 1138 struct sk_if_softc *sc_if; 1139 u_int64_t **aptr; 1140 int i; 1141 struct sk_jpool_entry *entry; 1142 1143 /* Extract the softc struct pointer. */ 1144 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 1145 sc_if = (struct sk_if_softc *)(aptr[0]); 1146 1147 if (sc_if == NULL) 1148 panic("sk_jfree: can't find softc pointer!"); 1149 1150 if (size != SK_MCLBYTES) 1151 panic("sk_jfree: freeing buffer of wrong size!"); 1152 1153 /* calculate the slot this buffer belongs to */ 1154 1155 i = ((vm_offset_t)aptr 1156 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 1157 1158 if ((i < 0) || (i >= SK_JSLOTS)) 1159 panic("sk_jfree: asked to free buffer that we don't manage!"); 1160 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) 1161 panic("sk_jfree: buffer already free!"); 1162 else { 1163 sc_if->sk_cdata.sk_jslots[i].sk_inuse--; 1164 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) { 1165 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 1166 if (entry == NULL) 1167 panic("sk_jfree: buffer not in use!"); 1168 entry->slot = i; 1169 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, 1170 jpool_entries); 1171 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 1172 entry, jpool_entries); 1173 } 1174 } 1175 1176 return; 1177 } 1178 1179 /* 1180 * Set media options. 1181 */ 1182 static int sk_ifmedia_upd(ifp) 1183 struct ifnet *ifp; 1184 { 1185 struct sk_if_softc *sc_if = ifp->if_softc; 1186 struct mii_data *mii; 1187 1188 mii = device_get_softc(sc_if->sk_miibus); 1189 sk_init(sc_if); 1190 mii_mediachg(mii); 1191 1192 return(0); 1193 } 1194 1195 /* 1196 * Report current media status. 1197 */ 1198 static void sk_ifmedia_sts(ifp, ifmr) 1199 struct ifnet *ifp; 1200 struct ifmediareq *ifmr; 1201 { 1202 struct sk_if_softc *sc_if; 1203 struct mii_data *mii; 1204 1205 sc_if = ifp->if_softc; 1206 mii = device_get_softc(sc_if->sk_miibus); 1207 1208 mii_pollstat(mii); 1209 ifmr->ifm_active = mii->mii_media_active; 1210 ifmr->ifm_status = mii->mii_media_status; 1211 1212 return; 1213 } 1214 1215 static int sk_ioctl(ifp, command, data, cr) 1216 struct ifnet *ifp; 1217 u_long command; 1218 caddr_t data; 1219 struct ucred *cr; 1220 { 1221 struct sk_if_softc *sc_if = ifp->if_softc; 1222 struct ifreq *ifr = (struct ifreq *) data; 1223 int s, error = 0; 1224 struct mii_data *mii; 1225 1226 s = splimp(); 1227 1228 switch(command) { 1229 case SIOCSIFADDR: 1230 case SIOCGIFADDR: 1231 error = ether_ioctl(ifp, command, data); 1232 break; 1233 case SIOCSIFMTU: 1234 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1235 error = EINVAL; 1236 else { 1237 ifp->if_mtu = ifr->ifr_mtu; 1238 sk_init(sc_if); 1239 } 1240 break; 1241 case SIOCSIFFLAGS: 1242 if (ifp->if_flags & IFF_UP) { 1243 if (ifp->if_flags & IFF_RUNNING) { 1244 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1245 & IFF_PROMISC) { 1246 sk_setpromisc(sc_if); 1247 sk_setmulti(sc_if); 1248 } 1249 } else 1250 sk_init(sc_if); 1251 } else { 1252 if (ifp->if_flags & IFF_RUNNING) 1253 sk_stop(sc_if); 1254 } 1255 sc_if->sk_if_flags = ifp->if_flags; 1256 error = 0; 1257 break; 1258 case SIOCADDMULTI: 1259 case SIOCDELMULTI: 1260 sk_setmulti(sc_if); 1261 error = 0; 1262 break; 1263 case SIOCGIFMEDIA: 1264 case SIOCSIFMEDIA: 1265 mii = device_get_softc(sc_if->sk_miibus); 1266 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1267 break; 1268 default: 1269 error = EINVAL; 1270 break; 1271 } 1272 1273 (void)splx(s); 1274 1275 return(error); 1276 } 1277 1278 /* 1279 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1280 * IDs against our list and return a device name if we find a match. 1281 */ 1282 static int skc_probe(dev) 1283 device_t dev; 1284 { 1285 struct sk_softc *sc; 1286 struct sk_type *t = sk_devs; 1287 1288 sc = device_get_softc(dev); 1289 1290 while(t->sk_name != NULL) { 1291 if ((pci_get_vendor(dev) == t->sk_vid) && 1292 (pci_get_device(dev) == t->sk_did)) { 1293 device_set_desc(dev, t->sk_name); 1294 return(0); 1295 } 1296 t++; 1297 } 1298 1299 return(ENXIO); 1300 } 1301 1302 /* 1303 * Force the GEnesis into reset, then bring it out of reset. 1304 */ 1305 static void sk_reset(sc) 1306 struct sk_softc *sc; 1307 { 1308 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1309 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1310 if (sc->sk_type == SK_YUKON) 1311 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1312 1313 DELAY(1000); 1314 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1315 DELAY(2); 1316 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1317 if (sc->sk_type == SK_YUKON) 1318 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1319 1320 if (sc->sk_type == SK_GENESIS) { 1321 /* Configure packet arbiter */ 1322 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1323 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1324 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1325 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1326 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1327 } 1328 1329 /* Enable RAM interface */ 1330 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1331 1332 /* 1333 * Configure interrupt moderation. The moderation timer 1334 * defers interrupts specified in the interrupt moderation 1335 * timer mask based on the timeout specified in the interrupt 1336 * moderation timer init register. Each bit in the timer 1337 * register represents 18.825ns, so to specify a timeout in 1338 * microseconds, we have to multiply by 54. 1339 */ 1340 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1341 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1342 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1343 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1344 1345 return; 1346 } 1347 1348 static int sk_probe(dev) 1349 device_t dev; 1350 { 1351 struct sk_softc *sc; 1352 1353 sc = device_get_softc(device_get_parent(dev)); 1354 1355 /* 1356 * Not much to do here. We always know there will be 1357 * at least one XMAC present, and if there are two, 1358 * skc_attach() will create a second device instance 1359 * for us. 1360 */ 1361 switch (sc->sk_type) { 1362 case SK_GENESIS: 1363 device_set_desc(dev, "XaQti Corp. XMAC II"); 1364 break; 1365 case SK_YUKON: 1366 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1367 break; 1368 } 1369 1370 return(0); 1371 } 1372 1373 /* 1374 * Each XMAC chip is attached as a separate logical IP interface. 1375 * Single port cards will have only one logical interface of course. 1376 */ 1377 static int sk_attach(dev) 1378 device_t dev; 1379 { 1380 struct sk_softc *sc; 1381 struct sk_if_softc *sc_if; 1382 struct ifnet *ifp; 1383 int i, port; 1384 1385 if (dev == NULL) 1386 return(EINVAL); 1387 1388 sc_if = device_get_softc(dev); 1389 sc = device_get_softc(device_get_parent(dev)); 1390 port = *(int *)device_get_ivars(dev); 1391 free(device_get_ivars(dev), M_DEVBUF); 1392 device_set_ivars(dev, NULL); 1393 sc_if->sk_dev = dev; 1394 callout_init(&sc_if->sk_tick_timer); 1395 1396 bzero((char *)sc_if, sizeof(struct sk_if_softc)); 1397 1398 sc_if->sk_dev = dev; 1399 sc_if->sk_unit = device_get_unit(dev); 1400 sc_if->sk_port = port; 1401 sc_if->sk_softc = sc; 1402 sc->sk_if[port] = sc_if; 1403 if (port == SK_PORT_A) 1404 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1405 if (port == SK_PORT_B) 1406 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1407 1408 /* 1409 * Get station address for this interface. Note that 1410 * dual port cards actually come with three station 1411 * addresses: one for each port, plus an extra. The 1412 * extra one is used by the SysKonnect driver software 1413 * as a 'virtual' station address for when both ports 1414 * are operating in failover mode. Currently we don't 1415 * use this extra address. 1416 */ 1417 for (i = 0; i < ETHER_ADDR_LEN; i++) 1418 sc_if->arpcom.ac_enaddr[i] = 1419 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1420 1421 /* 1422 * Set up RAM buffer addresses. The NIC will have a certain 1423 * amount of SRAM on it, somewhere between 512K and 2MB. We 1424 * need to divide this up a) between the transmitter and 1425 * receiver and b) between the two XMACs, if this is a 1426 * dual port NIC. Our algotithm is to divide up the memory 1427 * evenly so that everyone gets a fair share. 1428 */ 1429 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1430 u_int32_t chunk, val; 1431 1432 chunk = sc->sk_ramsize / 2; 1433 val = sc->sk_rboff / sizeof(u_int64_t); 1434 sc_if->sk_rx_ramstart = val; 1435 val += (chunk / sizeof(u_int64_t)); 1436 sc_if->sk_rx_ramend = val - 1; 1437 sc_if->sk_tx_ramstart = val; 1438 val += (chunk / sizeof(u_int64_t)); 1439 sc_if->sk_tx_ramend = val - 1; 1440 } else { 1441 u_int32_t chunk, val; 1442 1443 chunk = sc->sk_ramsize / 4; 1444 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1445 sizeof(u_int64_t); 1446 sc_if->sk_rx_ramstart = val; 1447 val += (chunk / sizeof(u_int64_t)); 1448 sc_if->sk_rx_ramend = val - 1; 1449 sc_if->sk_tx_ramstart = val; 1450 val += (chunk / sizeof(u_int64_t)); 1451 sc_if->sk_tx_ramend = val - 1; 1452 } 1453 1454 /* Read and save PHY type and set PHY address */ 1455 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1456 switch(sc_if->sk_phytype) { 1457 case SK_PHYTYPE_XMAC: 1458 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1459 break; 1460 case SK_PHYTYPE_BCOM: 1461 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1462 break; 1463 case SK_PHYTYPE_MARV_COPPER: 1464 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1465 break; 1466 default: 1467 printf("skc%d: unsupported PHY type: %d\n", 1468 sc->sk_unit, sc_if->sk_phytype); 1469 return(ENODEV); 1470 } 1471 1472 /* Allocate the descriptor queues. */ 1473 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1474 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1475 1476 if (sc_if->sk_rdata == NULL) { 1477 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1478 sc->sk_if[port] = NULL; 1479 return(ENOMEM); 1480 } 1481 1482 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1483 1484 /* Try to allocate memory for jumbo buffers. */ 1485 if (sk_alloc_jumbo_mem(sc_if)) { 1486 printf("sk%d: jumbo buffer allocation failed\n", 1487 sc_if->sk_unit); 1488 contigfree(sc_if->sk_rdata, 1489 sizeof(struct sk_ring_data), M_DEVBUF); 1490 sc->sk_if[port] = NULL; 1491 return(ENOMEM); 1492 } 1493 1494 ifp = &sc_if->arpcom.ac_if; 1495 ifp->if_softc = sc_if; 1496 if_initname(ifp, "sk", sc_if->sk_unit); 1497 ifp->if_mtu = ETHERMTU; 1498 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1499 ifp->if_ioctl = sk_ioctl; 1500 ifp->if_start = sk_start; 1501 ifp->if_watchdog = sk_watchdog; 1502 ifp->if_init = sk_init; 1503 ifp->if_baudrate = 1000000000; 1504 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1); 1505 ifq_set_ready(&ifp->if_snd); 1506 1507 /* 1508 * Do miibus setup. 1509 */ 1510 switch (sc->sk_type) { 1511 case SK_GENESIS: 1512 sk_init_xmac(sc_if); 1513 break; 1514 case SK_YUKON: 1515 sk_init_yukon(sc_if); 1516 break; 1517 } 1518 1519 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1520 sk_ifmedia_upd, sk_ifmedia_sts)) { 1521 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1522 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, 1523 M_DEVBUF); 1524 contigfree(sc_if->sk_rdata, 1525 sizeof(struct sk_ring_data), M_DEVBUF); 1526 return(ENXIO); 1527 } 1528 1529 /* 1530 * Call MI attach routine. 1531 */ 1532 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1533 callout_init(&sc_if->sk_tick_timer); 1534 1535 return(0); 1536 } 1537 1538 /* 1539 * Attach the interface. Allocate softc structures, do ifmedia 1540 * setup and ethernet/BPF attach. 1541 */ 1542 static int skc_attach(dev) 1543 device_t dev; 1544 { 1545 int s; 1546 u_int32_t command; 1547 struct sk_softc *sc; 1548 int unit, error = 0, rid, *port; 1549 uint8_t skrs; 1550 1551 s = splimp(); 1552 1553 sc = device_get_softc(dev); 1554 unit = device_get_unit(dev); 1555 bzero(sc, sizeof(struct sk_softc)); 1556 switch (pci_get_device(dev)) { 1557 case DEVICEID_SK_V1: 1558 sc->sk_type = SK_GENESIS; 1559 break; 1560 case DEVICEID_SK_V2: 1561 case DEVICEID_3COM_3C940: 1562 case DEVICEID_LINKSYS_EG1032: 1563 case DEVICEID_DLINK_DGE530T: 1564 sc->sk_type = SK_YUKON; 1565 break; 1566 } 1567 1568 /* 1569 * Handle power management nonsense. 1570 */ 1571 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF; 1572 if (command == 0x01) { 1573 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4); 1574 if (command & SK_PSTATE_MASK) { 1575 u_int32_t iobase, membase, irq; 1576 1577 /* Save important PCI config data. */ 1578 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1579 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1580 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1581 1582 /* Reset the power state. */ 1583 printf("skc%d: chip is in D%d power mode " 1584 "-- setting to D0\n", unit, command & SK_PSTATE_MASK); 1585 command &= 0xFFFFFFFC; 1586 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4); 1587 1588 /* Restore PCI config data. */ 1589 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1590 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1591 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1592 } 1593 } 1594 1595 /* 1596 * Map control/status registers. 1597 */ 1598 command = pci_read_config(dev, PCIR_COMMAND, 4); 1599 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1600 pci_write_config(dev, PCIR_COMMAND, command, 4); 1601 command = pci_read_config(dev, PCIR_COMMAND, 4); 1602 1603 #ifdef SK_USEIOSPACE 1604 if (!(command & PCIM_CMD_PORTEN)) { 1605 printf("skc%d: failed to enable I/O ports!\n", unit); 1606 error = ENXIO; 1607 goto fail; 1608 } 1609 #else 1610 if (!(command & PCIM_CMD_MEMEN)) { 1611 printf("skc%d: failed to enable memory mapping!\n", unit); 1612 error = ENXIO; 1613 goto fail; 1614 } 1615 #endif 1616 1617 rid = SK_RID; 1618 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid, 1619 0, ~0, 1, RF_ACTIVE); 1620 1621 if (sc->sk_res == NULL) { 1622 printf("sk%d: couldn't map ports/memory\n", unit); 1623 error = ENXIO; 1624 goto fail; 1625 } 1626 1627 sc->sk_btag = rman_get_bustag(sc->sk_res); 1628 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1629 1630 /* Allocate interrupt */ 1631 rid = 0; 1632 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1633 RF_SHAREABLE | RF_ACTIVE); 1634 1635 if (sc->sk_irq == NULL) { 1636 printf("skc%d: couldn't map interrupt\n", unit); 1637 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1638 error = ENXIO; 1639 goto fail; 1640 } 1641 1642 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1643 sk_intr, sc, &sc->sk_intrhand); 1644 1645 if (error) { 1646 printf("skc%d: couldn't set up irq\n", unit); 1647 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1648 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1649 goto fail; 1650 } 1651 1652 /* Reset the adapter. */ 1653 sk_reset(sc); 1654 1655 sc->sk_unit = unit; 1656 1657 /* Read and save vital product data from EEPROM. */ 1658 sk_vpd_read(sc); 1659 1660 skrs = sk_win_read_1(sc, SK_EPROM0); 1661 if (sc->sk_type == SK_GENESIS) { 1662 /* Read and save RAM size and RAMbuffer offset */ 1663 switch(skrs) { 1664 case SK_RAMSIZE_512K_64: 1665 sc->sk_ramsize = 0x80000; 1666 sc->sk_rboff = SK_RBOFF_0; 1667 break; 1668 case SK_RAMSIZE_1024K_64: 1669 sc->sk_ramsize = 0x100000; 1670 sc->sk_rboff = SK_RBOFF_80000; 1671 break; 1672 case SK_RAMSIZE_1024K_128: 1673 sc->sk_ramsize = 0x100000; 1674 sc->sk_rboff = SK_RBOFF_0; 1675 break; 1676 case SK_RAMSIZE_2048K_128: 1677 sc->sk_ramsize = 0x200000; 1678 sc->sk_rboff = SK_RBOFF_0; 1679 break; 1680 default: 1681 printf("skc%d: unknown ram size: %d\n", 1682 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1683 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1685 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1686 error = ENXIO; 1687 goto fail; 1688 break; 1689 } 1690 } else { /* SK_YUKON */ 1691 if (skrs == 0x00) { 1692 sc->sk_ramsize = 0x20000; 1693 } else { 1694 sc->sk_ramsize = skrs * (1<<12); 1695 } 1696 sc->sk_rboff = SK_RBOFF_0; 1697 } 1698 1699 /* Read and save physical media type */ 1700 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1701 case SK_PMD_1000BASESX: 1702 sc->sk_pmd = IFM_1000_SX; 1703 break; 1704 case SK_PMD_1000BASELX: 1705 sc->sk_pmd = IFM_1000_LX; 1706 break; 1707 case SK_PMD_1000BASECX: 1708 sc->sk_pmd = IFM_1000_CX; 1709 break; 1710 case SK_PMD_1000BASETX: 1711 sc->sk_pmd = IFM_1000_T; 1712 break; 1713 default: 1714 printf("skc%d: unknown media type: 0x%x\n", 1715 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1716 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1717 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1718 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1719 error = ENXIO; 1720 goto fail; 1721 } 1722 1723 /* Announce the product name. */ 1724 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1725 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1726 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1727 *port = SK_PORT_A; 1728 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1729 1730 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1731 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1732 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1733 *port = SK_PORT_B; 1734 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1735 } 1736 1737 /* Turn on the 'driver is loaded' LED. */ 1738 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1739 1740 bus_generic_attach(dev); 1741 1742 fail: 1743 splx(s); 1744 return(error); 1745 } 1746 1747 static int sk_detach(dev) 1748 device_t dev; 1749 { 1750 struct sk_softc *sc; 1751 struct sk_if_softc *sc_if; 1752 struct ifnet *ifp; 1753 int s; 1754 1755 s = splimp(); 1756 1757 sc = device_get_softc(device_get_parent(dev)); 1758 sc_if = device_get_softc(dev); 1759 ifp = &sc_if->arpcom.ac_if; 1760 sk_stop(sc_if); 1761 ether_ifdetach(ifp); 1762 bus_generic_detach(dev); 1763 if (sc_if->sk_miibus != NULL) 1764 device_delete_child(dev, sc_if->sk_miibus); 1765 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1766 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF); 1767 1768 return(0); 1769 } 1770 1771 static int skc_detach(dev) 1772 device_t dev; 1773 { 1774 struct sk_softc *sc; 1775 int s; 1776 1777 s = splimp(); 1778 1779 sc = device_get_softc(dev); 1780 1781 bus_generic_detach(dev); 1782 if (sc->sk_devs[SK_PORT_A] != NULL) 1783 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1784 if (sc->sk_devs[SK_PORT_B] != NULL) 1785 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1786 1787 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1788 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1789 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1790 1791 splx(s); 1792 1793 return(0); 1794 } 1795 1796 static int sk_encap(sc_if, m_head, txidx) 1797 struct sk_if_softc *sc_if; 1798 struct mbuf *m_head; 1799 u_int32_t *txidx; 1800 { 1801 struct sk_tx_desc *f = NULL; 1802 struct mbuf *m; 1803 u_int32_t frag, cur, cnt = 0; 1804 1805 m = m_head; 1806 cur = frag = *txidx; 1807 1808 /* 1809 * Start packing the mbufs in this chain into 1810 * the fragment pointers. Stop when we run out 1811 * of fragments or hit the end of the mbuf chain. 1812 */ 1813 for (m = m_head; m != NULL; m = m->m_next) { 1814 if (m->m_len != 0) { 1815 if ((SK_TX_RING_CNT - 1816 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1817 return(ENOBUFS); 1818 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1819 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1820 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1821 if (cnt == 0) 1822 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1823 else 1824 f->sk_ctl |= SK_TXCTL_OWN; 1825 cur = frag; 1826 SK_INC(frag, SK_TX_RING_CNT); 1827 cnt++; 1828 } 1829 } 1830 1831 if (m != NULL) 1832 return(ENOBUFS); 1833 1834 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1835 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1836 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1837 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1838 sc_if->sk_cdata.sk_tx_cnt += cnt; 1839 1840 *txidx = frag; 1841 1842 return(0); 1843 } 1844 1845 static void sk_start(ifp) 1846 struct ifnet *ifp; 1847 { 1848 struct sk_softc *sc; 1849 struct sk_if_softc *sc_if; 1850 struct mbuf *m_head = NULL; 1851 u_int32_t idx; 1852 1853 sc_if = ifp->if_softc; 1854 sc = sc_if->sk_softc; 1855 1856 idx = sc_if->sk_cdata.sk_tx_prod; 1857 1858 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1859 m_head = ifq_poll(&ifp->if_snd); 1860 if (m_head == NULL) 1861 break; 1862 1863 /* 1864 * Pack the data into the transmit ring. If we 1865 * don't have room, set the OACTIVE flag and wait 1866 * for the NIC to drain the ring. 1867 */ 1868 if (sk_encap(sc_if, m_head, &idx)) { 1869 ifp->if_flags |= IFF_OACTIVE; 1870 break; 1871 } 1872 m_head = ifq_dequeue(&ifp->if_snd); 1873 1874 BPF_MTAP(ifp, m_head); 1875 } 1876 1877 /* Transmit */ 1878 sc_if->sk_cdata.sk_tx_prod = idx; 1879 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1880 1881 /* Set a timeout in case the chip goes out to lunch. */ 1882 ifp->if_timer = 5; 1883 1884 return; 1885 } 1886 1887 1888 static void sk_watchdog(ifp) 1889 struct ifnet *ifp; 1890 { 1891 struct sk_if_softc *sc_if; 1892 1893 sc_if = ifp->if_softc; 1894 1895 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1896 sk_init(sc_if); 1897 1898 return; 1899 } 1900 1901 static void skc_shutdown(dev) 1902 device_t dev; 1903 { 1904 struct sk_softc *sc; 1905 1906 sc = device_get_softc(dev); 1907 1908 /* Turn off the 'driver is loaded' LED. */ 1909 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1910 1911 /* 1912 * Reset the GEnesis controller. Doing this should also 1913 * assert the resets on the attached XMAC(s). 1914 */ 1915 sk_reset(sc); 1916 1917 return; 1918 } 1919 1920 static void sk_rxeof(sc_if) 1921 struct sk_if_softc *sc_if; 1922 { 1923 struct mbuf *m; 1924 struct ifnet *ifp; 1925 struct sk_chain *cur_rx; 1926 int total_len = 0; 1927 int i; 1928 u_int32_t rxstat; 1929 1930 ifp = &sc_if->arpcom.ac_if; 1931 i = sc_if->sk_cdata.sk_rx_prod; 1932 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1933 1934 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1935 1936 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1937 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1938 m = cur_rx->sk_mbuf; 1939 cur_rx->sk_mbuf = NULL; 1940 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1941 SK_INC(i, SK_RX_RING_CNT); 1942 1943 if (rxstat & XM_RXSTAT_ERRFRAME) { 1944 ifp->if_ierrors++; 1945 sk_newbuf(sc_if, cur_rx, m); 1946 continue; 1947 } 1948 1949 /* 1950 * Try to allocate a new jumbo buffer. If that 1951 * fails, copy the packet to mbufs and put the 1952 * jumbo buffer back in the ring so it can be 1953 * re-used. If allocating mbufs fails, then we 1954 * have to drop the packet. 1955 */ 1956 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1957 struct mbuf *m0; 1958 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1959 total_len + ETHER_ALIGN, 0, ifp, NULL); 1960 sk_newbuf(sc_if, cur_rx, m); 1961 if (m0 == NULL) { 1962 printf("sk%d: no receive buffers " 1963 "available -- packet dropped!\n", 1964 sc_if->sk_unit); 1965 ifp->if_ierrors++; 1966 continue; 1967 } 1968 m_adj(m0, ETHER_ALIGN); 1969 m = m0; 1970 } else { 1971 m->m_pkthdr.rcvif = ifp; 1972 m->m_pkthdr.len = m->m_len = total_len; 1973 } 1974 1975 ifp->if_ipackets++; 1976 (*ifp->if_input)(ifp, m); 1977 } 1978 1979 sc_if->sk_cdata.sk_rx_prod = i; 1980 1981 return; 1982 } 1983 1984 static void sk_txeof(sc_if) 1985 struct sk_if_softc *sc_if; 1986 { 1987 struct sk_tx_desc *cur_tx = NULL; 1988 struct ifnet *ifp; 1989 u_int32_t idx; 1990 1991 ifp = &sc_if->arpcom.ac_if; 1992 1993 /* 1994 * Go through our tx ring and free mbufs for those 1995 * frames that have been sent. 1996 */ 1997 idx = sc_if->sk_cdata.sk_tx_cons; 1998 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1999 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2000 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 2001 break; 2002 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 2003 ifp->if_opackets++; 2004 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2005 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2006 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2007 } 2008 sc_if->sk_cdata.sk_tx_cnt--; 2009 SK_INC(idx, SK_TX_RING_CNT); 2010 ifp->if_timer = 0; 2011 } 2012 2013 sc_if->sk_cdata.sk_tx_cons = idx; 2014 2015 if (cur_tx != NULL) 2016 ifp->if_flags &= ~IFF_OACTIVE; 2017 2018 return; 2019 } 2020 2021 static void sk_tick(xsc_if) 2022 void *xsc_if; 2023 { 2024 struct sk_if_softc *sc_if; 2025 struct mii_data *mii; 2026 struct ifnet *ifp; 2027 int i; 2028 2029 sc_if = xsc_if; 2030 ifp = &sc_if->arpcom.ac_if; 2031 mii = device_get_softc(sc_if->sk_miibus); 2032 2033 if (!(ifp->if_flags & IFF_UP)) 2034 return; 2035 2036 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2037 sk_intr_bcom(sc_if); 2038 return; 2039 } 2040 2041 /* 2042 * According to SysKonnect, the correct way to verify that 2043 * the link has come back up is to poll bit 0 of the GPIO 2044 * register three times. This pin has the signal from the 2045 * link_sync pin connected to it; if we read the same link 2046 * state 3 times in a row, we know the link is up. 2047 */ 2048 for (i = 0; i < 3; i++) { 2049 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2050 break; 2051 } 2052 2053 if (i != 3) { 2054 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if); 2055 return; 2056 } 2057 2058 /* Turn the GP0 interrupt back on. */ 2059 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2060 SK_XM_READ_2(sc_if, XM_ISR); 2061 mii_tick(mii); 2062 mii_pollstat(mii); 2063 callout_stop(&sc_if->sk_tick_timer); 2064 2065 return; 2066 } 2067 2068 static void sk_intr_bcom(sc_if) 2069 struct sk_if_softc *sc_if; 2070 { 2071 struct sk_softc *sc; 2072 struct mii_data *mii; 2073 struct ifnet *ifp; 2074 int status; 2075 2076 sc = sc_if->sk_softc; 2077 mii = device_get_softc(sc_if->sk_miibus); 2078 ifp = &sc_if->arpcom.ac_if; 2079 2080 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2081 2082 /* 2083 * Read the PHY interrupt register to make sure 2084 * we clear any pending interrupts. 2085 */ 2086 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2087 2088 if (!(ifp->if_flags & IFF_RUNNING)) { 2089 sk_init_xmac(sc_if); 2090 return; 2091 } 2092 2093 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2094 int lstat; 2095 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2096 BRGPHY_MII_AUXSTS); 2097 2098 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2099 mii_mediachg(mii); 2100 /* Turn off the link LED. */ 2101 SK_IF_WRITE_1(sc_if, 0, 2102 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2103 sc_if->sk_link = 0; 2104 } else if (status & BRGPHY_ISR_LNK_CHG) { 2105 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2106 BRGPHY_MII_IMR, 0xFF00); 2107 mii_tick(mii); 2108 sc_if->sk_link = 1; 2109 /* Turn on the link LED. */ 2110 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2111 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2112 SK_LINKLED_BLINK_OFF); 2113 mii_pollstat(mii); 2114 } else { 2115 mii_tick(mii); 2116 callout_reset(&sc_if->sk_tick_timer, hz, 2117 sk_tick, sc_if); 2118 } 2119 } 2120 2121 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2122 2123 return; 2124 } 2125 2126 static void sk_intr_xmac(sc_if) 2127 struct sk_if_softc *sc_if; 2128 { 2129 struct sk_softc *sc; 2130 u_int16_t status; 2131 struct mii_data *mii; 2132 2133 sc = sc_if->sk_softc; 2134 mii = device_get_softc(sc_if->sk_miibus); 2135 status = SK_XM_READ_2(sc_if, XM_ISR); 2136 2137 /* 2138 * Link has gone down. Start MII tick timeout to 2139 * watch for link resync. 2140 */ 2141 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2142 if (status & XM_ISR_GP0_SET) { 2143 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2144 callout_reset(&sc_if->sk_tick_timer, hz, 2145 sk_tick, sc_if); 2146 } 2147 2148 if (status & XM_ISR_AUTONEG_DONE) { 2149 callout_reset(&sc_if->sk_tick_timer, hz, 2150 sk_tick, sc_if); 2151 } 2152 } 2153 2154 if (status & XM_IMR_TX_UNDERRUN) 2155 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2156 2157 if (status & XM_IMR_RX_OVERRUN) 2158 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2159 2160 status = SK_XM_READ_2(sc_if, XM_ISR); 2161 2162 return; 2163 } 2164 2165 static void sk_intr_yukon(sc_if) 2166 struct sk_if_softc *sc_if; 2167 { 2168 int status; 2169 2170 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2171 2172 return; 2173 } 2174 2175 static void sk_intr(xsc) 2176 void *xsc; 2177 { 2178 struct sk_softc *sc = xsc; 2179 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 2180 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2181 u_int32_t status; 2182 2183 sc_if0 = sc->sk_if[SK_PORT_A]; 2184 sc_if1 = sc->sk_if[SK_PORT_B]; 2185 2186 if (sc_if0 != NULL) 2187 ifp0 = &sc_if0->arpcom.ac_if; 2188 if (sc_if1 != NULL) 2189 ifp1 = &sc_if1->arpcom.ac_if; 2190 2191 for (;;) { 2192 status = CSR_READ_4(sc, SK_ISSR); 2193 if (!(status & sc->sk_intrmask)) 2194 break; 2195 2196 /* Handle receive interrupts first. */ 2197 if (status & SK_ISR_RX1_EOF) { 2198 sk_rxeof(sc_if0); 2199 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2200 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2201 } 2202 if (status & SK_ISR_RX2_EOF) { 2203 sk_rxeof(sc_if1); 2204 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2205 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2206 } 2207 2208 /* Then transmit interrupts. */ 2209 if (status & SK_ISR_TX1_S_EOF) { 2210 sk_txeof(sc_if0); 2211 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2212 SK_TXBMU_CLR_IRQ_EOF); 2213 } 2214 if (status & SK_ISR_TX2_S_EOF) { 2215 sk_txeof(sc_if1); 2216 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2217 SK_TXBMU_CLR_IRQ_EOF); 2218 } 2219 2220 /* Then MAC interrupts. */ 2221 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 2222 if (sc->sk_type == SK_GENESIS) 2223 sk_intr_xmac(sc_if0); 2224 else 2225 sk_intr_yukon(sc_if0); 2226 } 2227 2228 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 2229 if (sc->sk_type == SK_GENESIS) 2230 sk_intr_xmac(sc_if1); 2231 else 2232 sk_intr_yukon(sc_if0); 2233 } 2234 2235 if (status & SK_ISR_EXTERNAL_REG) { 2236 if (ifp0 != NULL && 2237 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2238 sk_intr_bcom(sc_if0); 2239 if (ifp1 != NULL && 2240 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2241 sk_intr_bcom(sc_if1); 2242 } 2243 } 2244 2245 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2246 2247 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd)) 2248 sk_start(ifp0); 2249 if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd)) 2250 sk_start(ifp1); 2251 2252 return; 2253 } 2254 2255 static void sk_init_xmac(sc_if) 2256 struct sk_if_softc *sc_if; 2257 { 2258 struct sk_softc *sc; 2259 struct ifnet *ifp; 2260 struct sk_bcom_hack bhack[] = { 2261 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2262 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2263 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2264 { 0, 0 } }; 2265 2266 sc = sc_if->sk_softc; 2267 ifp = &sc_if->arpcom.ac_if; 2268 2269 /* Unreset the XMAC. */ 2270 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2271 DELAY(1000); 2272 2273 /* Reset the XMAC's internal state. */ 2274 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2275 2276 /* Save the XMAC II revision */ 2277 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2278 2279 /* 2280 * Perform additional initialization for external PHYs, 2281 * namely for the 1000baseTX cards that use the XMAC's 2282 * GMII mode. 2283 */ 2284 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2285 int i = 0; 2286 u_int32_t val; 2287 2288 /* Take PHY out of reset. */ 2289 val = sk_win_read_4(sc, SK_GPIO); 2290 if (sc_if->sk_port == SK_PORT_A) 2291 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2292 else 2293 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2294 sk_win_write_4(sc, SK_GPIO, val); 2295 2296 /* Enable GMII mode on the XMAC. */ 2297 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2298 2299 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2300 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2301 DELAY(10000); 2302 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2303 BRGPHY_MII_IMR, 0xFFF0); 2304 2305 /* 2306 * Early versions of the BCM5400 apparently have 2307 * a bug that requires them to have their reserved 2308 * registers initialized to some magic values. I don't 2309 * know what the numbers do, I'm just the messenger. 2310 */ 2311 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2312 == 0x6041) { 2313 while(bhack[i].reg) { 2314 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2315 bhack[i].reg, bhack[i].val); 2316 i++; 2317 } 2318 } 2319 } 2320 2321 /* Set station address */ 2322 SK_XM_WRITE_2(sc_if, XM_PAR0, 2323 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2324 SK_XM_WRITE_2(sc_if, XM_PAR1, 2325 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2326 SK_XM_WRITE_2(sc_if, XM_PAR2, 2327 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2328 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2329 2330 if (ifp->if_flags & IFF_BROADCAST) { 2331 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2332 } else { 2333 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2334 } 2335 2336 /* We don't need the FCS appended to the packet. */ 2337 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2338 2339 /* We want short frames padded to 60 bytes. */ 2340 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2341 2342 /* 2343 * Enable the reception of all error frames. This is is 2344 * a necessary evil due to the design of the XMAC. The 2345 * XMAC's receive FIFO is only 8K in size, however jumbo 2346 * frames can be up to 9000 bytes in length. When bad 2347 * frame filtering is enabled, the XMAC's RX FIFO operates 2348 * in 'store and forward' mode. For this to work, the 2349 * entire frame has to fit into the FIFO, but that means 2350 * that jumbo frames larger than 8192 bytes will be 2351 * truncated. Disabling all bad frame filtering causes 2352 * the RX FIFO to operate in streaming mode, in which 2353 * case the XMAC will start transfering frames out of the 2354 * RX FIFO as soon as the FIFO threshold is reached. 2355 */ 2356 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2357 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2358 XM_MODE_RX_INRANGELEN); 2359 2360 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2361 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2362 else 2363 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2364 2365 /* 2366 * Bump up the transmit threshold. This helps hold off transmit 2367 * underruns when we're blasting traffic from both ports at once. 2368 */ 2369 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2370 2371 /* Set promiscuous mode */ 2372 sk_setpromisc(sc_if); 2373 2374 /* Set multicast filter */ 2375 sk_setmulti(sc_if); 2376 2377 /* Clear and enable interrupts */ 2378 SK_XM_READ_2(sc_if, XM_ISR); 2379 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2380 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2381 else 2382 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2383 2384 /* Configure MAC arbiter */ 2385 switch(sc_if->sk_xmac_rev) { 2386 case XM_XMAC_REV_B2: 2387 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2388 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2389 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2390 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2391 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2392 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2393 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2394 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2395 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2396 break; 2397 case XM_XMAC_REV_C1: 2398 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2399 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2400 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2401 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2402 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2403 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2404 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2405 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2406 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2407 break; 2408 default: 2409 break; 2410 } 2411 sk_win_write_2(sc, SK_MACARB_CTL, 2412 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2413 2414 sc_if->sk_link = 1; 2415 2416 return; 2417 } 2418 2419 static void sk_init_yukon(sc_if) 2420 struct sk_if_softc *sc_if; 2421 { 2422 u_int32_t phy; 2423 u_int16_t reg; 2424 struct sk_softc *sc; 2425 struct ifnet *ifp; 2426 int i; 2427 2428 sc = sc_if->sk_softc; 2429 ifp = &sc_if->arpcom.ac_if; 2430 2431 /* GMAC and GPHY Reset */ 2432 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2433 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2434 DELAY(1000); 2435 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2436 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2437 DELAY(1000); 2438 2439 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2440 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2441 2442 switch(sc_if->sk_softc->sk_pmd) { 2443 case IFM_1000_SX: 2444 case IFM_1000_LX: 2445 phy |= SK_GPHY_FIBER; 2446 break; 2447 2448 case IFM_1000_CX: 2449 case IFM_1000_T: 2450 phy |= SK_GPHY_COPPER; 2451 break; 2452 } 2453 2454 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2455 DELAY(1000); 2456 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2457 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2458 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2459 2460 /* unused read of the interrupt source register */ 2461 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2462 2463 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2464 2465 /* MIB Counter Clear Mode set */ 2466 reg |= YU_PAR_MIB_CLR; 2467 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2468 2469 /* MIB Counter Clear Mode clear */ 2470 reg &= ~YU_PAR_MIB_CLR; 2471 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2472 2473 /* receive control reg */ 2474 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2475 2476 /* transmit parameter register */ 2477 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2478 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2479 2480 /* serial mode register */ 2481 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 2482 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2483 reg |= YU_SMR_MFL_JUMBO; 2484 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2485 2486 /* Setup Yukon's address */ 2487 for (i = 0; i < 3; i++) { 2488 /* Write Source Address 1 (unicast filter) */ 2489 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2490 sc_if->arpcom.ac_enaddr[i * 2] | 2491 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2492 } 2493 2494 for (i = 0; i < 3; i++) { 2495 reg = sk_win_read_2(sc_if->sk_softc, 2496 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2497 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2498 } 2499 2500 /* Set promiscuous mode */ 2501 sk_setpromisc(sc_if); 2502 2503 /* Set multicast filter */ 2504 sk_setmulti(sc_if); 2505 2506 /* enable interrupt mask for counter overflows */ 2507 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2508 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2509 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2510 2511 /* Configure RX MAC FIFO */ 2512 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2513 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2514 2515 /* Configure TX MAC FIFO */ 2516 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2517 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2518 } 2519 2520 /* 2521 * Note that to properly initialize any part of the GEnesis chip, 2522 * you first have to take it out of reset mode. 2523 */ 2524 static void sk_init(xsc) 2525 void *xsc; 2526 { 2527 struct sk_if_softc *sc_if = xsc; 2528 struct sk_softc *sc; 2529 struct ifnet *ifp; 2530 struct mii_data *mii; 2531 int s; 2532 u_int16_t reg; 2533 2534 s = splimp(); 2535 2536 ifp = &sc_if->arpcom.ac_if; 2537 sc = sc_if->sk_softc; 2538 mii = device_get_softc(sc_if->sk_miibus); 2539 2540 /* Cancel pending I/O and free all RX/TX buffers. */ 2541 sk_stop(sc_if); 2542 2543 if (sc->sk_type == SK_GENESIS) { 2544 /* Configure LINK_SYNC LED */ 2545 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2546 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2547 SK_LINKLED_LINKSYNC_ON); 2548 2549 /* Configure RX LED */ 2550 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2551 SK_RXLEDCTL_COUNTER_START); 2552 2553 /* Configure TX LED */ 2554 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2555 SK_TXLEDCTL_COUNTER_START); 2556 } 2557 2558 /* Configure I2C registers */ 2559 2560 /* Configure XMAC(s) */ 2561 switch (sc->sk_type) { 2562 case SK_GENESIS: 2563 sk_init_xmac(sc_if); 2564 break; 2565 case SK_YUKON: 2566 sk_init_yukon(sc_if); 2567 break; 2568 } 2569 mii_mediachg(mii); 2570 2571 if (sc->sk_type == SK_GENESIS) { 2572 /* Configure MAC FIFOs */ 2573 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2574 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2575 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2576 2577 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2578 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2579 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2580 } 2581 2582 /* Configure transmit arbiter(s) */ 2583 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2584 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2585 2586 /* Configure RAMbuffers */ 2587 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2588 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2589 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2590 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2591 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2592 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2593 2594 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2595 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2596 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2597 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2598 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2599 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2600 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2601 2602 /* Configure BMUs */ 2603 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2604 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2605 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2606 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2607 2608 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2609 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2610 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2611 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2612 2613 /* Init descriptors */ 2614 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2615 printf("sk%d: initialization failed: no " 2616 "memory for rx buffers\n", sc_if->sk_unit); 2617 sk_stop(sc_if); 2618 (void)splx(s); 2619 return; 2620 } 2621 sk_init_tx_ring(sc_if); 2622 2623 /* Configure interrupt handling */ 2624 CSR_READ_4(sc, SK_ISSR); 2625 if (sc_if->sk_port == SK_PORT_A) 2626 sc->sk_intrmask |= SK_INTRS1; 2627 else 2628 sc->sk_intrmask |= SK_INTRS2; 2629 2630 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2631 2632 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2633 2634 /* Start BMUs. */ 2635 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2636 2637 switch(sc->sk_type) { 2638 case SK_GENESIS: 2639 /* Enable XMACs TX and RX state machines */ 2640 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2641 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2642 break; 2643 case SK_YUKON: 2644 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2645 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2646 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2647 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2648 } 2649 2650 ifp->if_flags |= IFF_RUNNING; 2651 ifp->if_flags &= ~IFF_OACTIVE; 2652 2653 splx(s); 2654 2655 return; 2656 } 2657 2658 static void sk_stop(sc_if) 2659 struct sk_if_softc *sc_if; 2660 { 2661 int i; 2662 struct sk_softc *sc; 2663 struct ifnet *ifp; 2664 2665 sc = sc_if->sk_softc; 2666 ifp = &sc_if->arpcom.ac_if; 2667 2668 callout_stop(&sc_if->sk_tick_timer); 2669 2670 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2671 u_int32_t val; 2672 2673 /* Put PHY back into reset. */ 2674 val = sk_win_read_4(sc, SK_GPIO); 2675 if (sc_if->sk_port == SK_PORT_A) { 2676 val |= SK_GPIO_DIR0; 2677 val &= ~SK_GPIO_DAT0; 2678 } else { 2679 val |= SK_GPIO_DIR2; 2680 val &= ~SK_GPIO_DAT2; 2681 } 2682 sk_win_write_4(sc, SK_GPIO, val); 2683 } 2684 2685 /* Turn off various components of this interface. */ 2686 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2687 switch (sc->sk_type) { 2688 case SK_GENESIS: 2689 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2690 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2691 break; 2692 case SK_YUKON: 2693 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2694 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2695 break; 2696 } 2697 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2698 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2699 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2700 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2701 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2702 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2703 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2704 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2705 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2706 2707 /* Disable interrupts */ 2708 if (sc_if->sk_port == SK_PORT_A) 2709 sc->sk_intrmask &= ~SK_INTRS1; 2710 else 2711 sc->sk_intrmask &= ~SK_INTRS2; 2712 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2713 2714 SK_XM_READ_2(sc_if, XM_ISR); 2715 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2716 2717 /* Free RX and TX mbufs still in the queues. */ 2718 for (i = 0; i < SK_RX_RING_CNT; i++) { 2719 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2720 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2721 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2722 } 2723 } 2724 2725 for (i = 0; i < SK_TX_RING_CNT; i++) { 2726 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2727 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2728 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2729 } 2730 } 2731 2732 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2733 2734 return; 2735 } 2736