1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.23 2005/05/25 01:44:29 dillon Exp $ 34 */ 35 36 /* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/sockio.h> 64 #include <sys/mbuf.h> 65 #include <sys/malloc.h> 66 #include <sys/kernel.h> 67 #include <sys/socket.h> 68 #include <sys/sysctl.h> 69 70 #include <net/if.h> 71 #include <net/ifq_var.h> 72 #include <net/if_arp.h> 73 #include <net/ethernet.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 #include <net/if_types.h> 77 #include <net/vlan/if_vlan_var.h> 78 79 #include <net/bpf.h> 80 81 #include <machine/bus_pio.h> 82 #include <machine/bus_memio.h> 83 #include <machine/bus.h> 84 #include <machine/resource.h> 85 #include <sys/bus.h> 86 #include <sys/rman.h> 87 88 #include <dev/netif/mii_layer/mii.h> 89 #include <dev/netif/mii_layer/miivar.h> 90 91 #include <bus/pci/pcireg.h> 92 #include <bus/pci/pcivar.h> 93 94 #define SIS_USEIOSPACE 95 96 #include "if_sisreg.h" 97 98 /* "controller miibus0" required. See GENERIC if you get errors here. */ 99 #include "miibus_if.h" 100 101 /* 102 * Various supported device vendors/types and their names. 103 */ 104 static struct sis_type sis_devs[] = { 105 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 106 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 107 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 108 { 0, 0, NULL } 109 }; 110 111 static int sis_probe(device_t); 112 static int sis_attach(device_t); 113 static int sis_detach(device_t); 114 115 static int sis_newbuf(struct sis_softc *, struct sis_desc *, 116 struct mbuf *); 117 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *); 118 static void sis_rxeof(struct sis_softc *); 119 static void sis_rxeoc(struct sis_softc *); 120 static void sis_txeof(struct sis_softc *); 121 static void sis_intr(void *); 122 static void sis_tick(void *); 123 static void sis_start(struct ifnet *); 124 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 125 static void sis_init(void *); 126 static void sis_stop(struct sis_softc *); 127 static void sis_watchdog(struct ifnet *); 128 static void sis_shutdown(device_t); 129 static int sis_ifmedia_upd(struct ifnet *); 130 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 131 132 static uint16_t sis_reverse(uint16_t); 133 static void sis_delay(struct sis_softc *); 134 static void sis_eeprom_idle(struct sis_softc *); 135 static void sis_eeprom_putbyte(struct sis_softc *, int); 136 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *); 137 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 138 #ifdef __i386__ 139 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int); 140 static void sis_read_mac(struct sis_softc *, device_t, caddr_t); 141 static device_t sis_find_bridge(device_t); 142 #endif 143 144 static void sis_mii_sync(struct sis_softc *); 145 static void sis_mii_send(struct sis_softc *, uint32_t, int); 146 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 147 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 148 static int sis_miibus_readreg(device_t, int, int); 149 static int sis_miibus_writereg(device_t, int, int, int); 150 static void sis_miibus_statchg(device_t); 151 152 static void sis_setmulti_sis(struct sis_softc *); 153 static void sis_setmulti_ns(struct sis_softc *); 154 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *); 155 static void sis_reset(struct sis_softc *); 156 static int sis_list_rx_init(struct sis_softc *); 157 static int sis_list_tx_init(struct sis_softc *); 158 159 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int); 160 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int); 161 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int); 162 #ifdef DEVICE_POLLING 163 static poll_handler_t sis_poll; 164 #endif 165 #ifdef SIS_USEIOSPACE 166 #define SIS_RES SYS_RES_IOPORT 167 #define SIS_RID SIS_PCI_LOIO 168 #else 169 #define SIS_RES SYS_RES_MEMORY 170 #define SIS_RID SIS_PCI_LOMEM 171 #endif 172 173 static device_method_t sis_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, sis_probe), 176 DEVMETHOD(device_attach, sis_attach), 177 DEVMETHOD(device_detach, sis_detach), 178 DEVMETHOD(device_shutdown, sis_shutdown), 179 180 /* bus interface */ 181 DEVMETHOD(bus_print_child, bus_generic_print_child), 182 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 186 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 187 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 188 189 { 0, 0 } 190 }; 191 192 static driver_t sis_driver = { 193 "sis", 194 sis_methods, 195 sizeof(struct sis_softc) 196 }; 197 198 static devclass_t sis_devclass; 199 200 DECLARE_DUMMY_MODULE(if_sis); 201 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 202 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 203 204 #define SIS_SETBIT(sc, reg, x) \ 205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 206 207 #define SIS_CLRBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 209 210 #define SIO_SET(x) \ 211 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 212 213 #define SIO_CLR(x) \ 214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 215 216 static void 217 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 218 { 219 struct sis_desc *r; 220 221 r = arg; 222 r->sis_next = segs->ds_addr; 223 } 224 225 static void 226 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 227 { 228 struct sis_desc *r; 229 230 r = arg; 231 r->sis_ptr = segs->ds_addr; 232 } 233 234 static void 235 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 236 { 237 uint32_t *p; 238 239 p = arg; 240 *p = segs->ds_addr; 241 } 242 243 /* 244 * Routine to reverse the bits in a word. Stolen almost 245 * verbatim from /usr/games/fortune. 246 */ 247 static uint16_t 248 sis_reverse(uint16_t n) 249 { 250 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 251 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 252 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 253 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 254 255 return(n); 256 } 257 258 static void 259 sis_delay(struct sis_softc *sc) 260 { 261 int idx; 262 263 for (idx = (300 / 33) + 1; idx > 0; idx--) 264 CSR_READ_4(sc, SIS_CSR); 265 } 266 267 static void 268 sis_eeprom_idle(struct sis_softc *sc) 269 { 270 int i; 271 272 SIO_SET(SIS_EECTL_CSEL); 273 sis_delay(sc); 274 SIO_SET(SIS_EECTL_CLK); 275 sis_delay(sc); 276 277 for (i = 0; i < 25; i++) { 278 SIO_CLR(SIS_EECTL_CLK); 279 sis_delay(sc); 280 SIO_SET(SIS_EECTL_CLK); 281 sis_delay(sc); 282 } 283 284 SIO_CLR(SIS_EECTL_CLK); 285 sis_delay(sc); 286 SIO_CLR(SIS_EECTL_CSEL); 287 sis_delay(sc); 288 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 289 } 290 291 /* 292 * Send a read command and address to the EEPROM, check for ACK. 293 */ 294 static void 295 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 296 { 297 int d, i; 298 299 d = addr | SIS_EECMD_READ; 300 301 /* 302 * Feed in each bit and stobe the clock. 303 */ 304 for (i = 0x400; i; i >>= 1) { 305 if (d & i) 306 SIO_SET(SIS_EECTL_DIN); 307 else 308 SIO_CLR(SIS_EECTL_DIN); 309 sis_delay(sc); 310 SIO_SET(SIS_EECTL_CLK); 311 sis_delay(sc); 312 SIO_CLR(SIS_EECTL_CLK); 313 sis_delay(sc); 314 } 315 } 316 317 /* 318 * Read a word of data stored in the EEPROM at address 'addr.' 319 */ 320 static void 321 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 322 { 323 int i; 324 uint16_t word = 0; 325 326 /* Force EEPROM to idle state. */ 327 sis_eeprom_idle(sc); 328 329 /* Enter EEPROM access mode. */ 330 sis_delay(sc); 331 SIO_CLR(SIS_EECTL_CLK); 332 sis_delay(sc); 333 SIO_SET(SIS_EECTL_CSEL); 334 sis_delay(sc); 335 336 /* 337 * Send address of word we want to read. 338 */ 339 sis_eeprom_putbyte(sc, addr); 340 341 /* 342 * Start reading bits from EEPROM. 343 */ 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_SET(SIS_EECTL_CLK); 346 sis_delay(sc); 347 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 348 word |= i; 349 sis_delay(sc); 350 SIO_CLR(SIS_EECTL_CLK); 351 sis_delay(sc); 352 } 353 354 /* Turn off EEPROM access mode. */ 355 sis_eeprom_idle(sc); 356 357 *dest = word; 358 } 359 360 /* 361 * Read a sequence of words from the EEPROM. 362 */ 363 static void 364 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 365 { 366 int i; 367 uint16_t word = 0, *ptr; 368 369 for (i = 0; i < cnt; i++) { 370 sis_eeprom_getword(sc, off + i, &word); 371 ptr = (uint16_t *)(dest + (i * 2)); 372 if (swap) 373 *ptr = ntohs(word); 374 else 375 *ptr = word; 376 } 377 } 378 379 #ifdef __i386__ 380 static device_t 381 sis_find_bridge(device_t dev) 382 { 383 devclass_t pci_devclass; 384 device_t *pci_devices; 385 int pci_count = 0; 386 device_t *pci_children; 387 int pci_childcount = 0; 388 device_t *busp, *childp; 389 device_t child = NULL; 390 int i, j; 391 392 if ((pci_devclass = devclass_find("pci")) == NULL) 393 return(NULL); 394 395 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 396 397 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 398 pci_childcount = 0; 399 device_get_children(*busp, &pci_children, &pci_childcount); 400 for (j = 0, childp = pci_children; j < pci_childcount; 401 j++, childp++) { 402 if (pci_get_vendor(*childp) == SIS_VENDORID && 403 pci_get_device(*childp) == 0x0008) { 404 child = *childp; 405 goto done; 406 } 407 } 408 } 409 410 done: 411 free(pci_devices, M_TEMP); 412 free(pci_children, M_TEMP); 413 return(child); 414 } 415 416 static void 417 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, 418 int cnt) 419 { 420 device_t bridge; 421 uint8_t reg; 422 int i; 423 bus_space_tag_t btag; 424 425 bridge = sis_find_bridge(dev); 426 if (bridge == NULL) 427 return; 428 reg = pci_read_config(bridge, 0x48, 1); 429 pci_write_config(bridge, 0x48, reg|0x40, 1); 430 431 /* XXX */ 432 btag = I386_BUS_SPACE_IO; 433 434 for (i = 0; i < cnt; i++) { 435 bus_space_write_1(btag, 0x0, 0x70, i + off); 436 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 437 } 438 439 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 440 } 441 442 static void 443 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 444 { 445 uint32_t filtsave, csrsave; 446 447 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 448 csrsave = CSR_READ_4(sc, SIS_CSR); 449 450 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 451 CSR_WRITE_4(sc, SIS_CSR, 0); 452 453 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 454 455 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 456 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 457 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 458 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 459 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 460 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 461 462 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 463 CSR_WRITE_4(sc, SIS_CSR, csrsave); 464 } 465 #endif 466 467 /* 468 * Sync the PHYs by setting data bit and strobing the clock 32 times. 469 */ 470 static void 471 sis_mii_sync(struct sis_softc *sc) 472 { 473 int i; 474 475 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 476 477 for (i = 0; i < 32; i++) { 478 SIO_SET(SIS_MII_CLK); 479 DELAY(1); 480 SIO_CLR(SIS_MII_CLK); 481 DELAY(1); 482 } 483 } 484 485 /* 486 * Clock a series of bits through the MII. 487 */ 488 static void 489 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 490 { 491 int i; 492 493 SIO_CLR(SIS_MII_CLK); 494 495 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 496 if (bits & i) 497 SIO_SET(SIS_MII_DATA); 498 else 499 SIO_CLR(SIS_MII_DATA); 500 DELAY(1); 501 SIO_CLR(SIS_MII_CLK); 502 DELAY(1); 503 SIO_SET(SIS_MII_CLK); 504 } 505 } 506 507 /* 508 * Read an PHY register through the MII. 509 */ 510 static int 511 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 512 { 513 int i, ack, s; 514 515 s = splimp(); 516 517 /* 518 * Set up frame for RX. 519 */ 520 frame->mii_stdelim = SIS_MII_STARTDELIM; 521 frame->mii_opcode = SIS_MII_READOP; 522 frame->mii_turnaround = 0; 523 frame->mii_data = 0; 524 525 /* 526 * Turn on data xmit. 527 */ 528 SIO_SET(SIS_MII_DIR); 529 530 sis_mii_sync(sc); 531 532 /* 533 * Send command/address info. 534 */ 535 sis_mii_send(sc, frame->mii_stdelim, 2); 536 sis_mii_send(sc, frame->mii_opcode, 2); 537 sis_mii_send(sc, frame->mii_phyaddr, 5); 538 sis_mii_send(sc, frame->mii_regaddr, 5); 539 540 /* Idle bit */ 541 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 542 DELAY(1); 543 SIO_SET(SIS_MII_CLK); 544 DELAY(1); 545 546 /* Turn off xmit. */ 547 SIO_CLR(SIS_MII_DIR); 548 549 /* Check for ack */ 550 SIO_CLR(SIS_MII_CLK); 551 DELAY(1); 552 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 553 SIO_SET(SIS_MII_CLK); 554 DELAY(1); 555 556 /* 557 * Now try reading data bits. If the ack failed, we still 558 * need to clock through 16 cycles to keep the PHY(s) in sync. 559 */ 560 if (ack) { 561 for(i = 0; i < 16; i++) { 562 SIO_CLR(SIS_MII_CLK); 563 DELAY(1); 564 SIO_SET(SIS_MII_CLK); 565 DELAY(1); 566 } 567 goto fail; 568 } 569 570 for (i = 0x8000; i; i >>= 1) { 571 SIO_CLR(SIS_MII_CLK); 572 DELAY(1); 573 if (!ack) { 574 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 575 frame->mii_data |= i; 576 DELAY(1); 577 } 578 SIO_SET(SIS_MII_CLK); 579 DELAY(1); 580 } 581 582 fail: 583 584 SIO_CLR(SIS_MII_CLK); 585 DELAY(1); 586 SIO_SET(SIS_MII_CLK); 587 DELAY(1); 588 589 splx(s); 590 591 if (ack) 592 return(1); 593 return(0); 594 } 595 596 /* 597 * Write to a PHY register through the MII. 598 */ 599 static int 600 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 601 { 602 int s; 603 604 s = splimp(); 605 /* 606 * Set up frame for TX. 607 */ 608 609 frame->mii_stdelim = SIS_MII_STARTDELIM; 610 frame->mii_opcode = SIS_MII_WRITEOP; 611 frame->mii_turnaround = SIS_MII_TURNAROUND; 612 613 /* 614 * Turn on data output. 615 */ 616 SIO_SET(SIS_MII_DIR); 617 618 sis_mii_sync(sc); 619 620 sis_mii_send(sc, frame->mii_stdelim, 2); 621 sis_mii_send(sc, frame->mii_opcode, 2); 622 sis_mii_send(sc, frame->mii_phyaddr, 5); 623 sis_mii_send(sc, frame->mii_regaddr, 5); 624 sis_mii_send(sc, frame->mii_turnaround, 2); 625 sis_mii_send(sc, frame->mii_data, 16); 626 627 /* Idle bit. */ 628 SIO_SET(SIS_MII_CLK); 629 DELAY(1); 630 SIO_CLR(SIS_MII_CLK); 631 DELAY(1); 632 633 /* 634 * Turn off xmit. 635 */ 636 SIO_CLR(SIS_MII_DIR); 637 638 splx(s); 639 640 return(0); 641 } 642 643 static int 644 sis_miibus_readreg(device_t dev, int phy, int reg) 645 { 646 struct sis_softc *sc; 647 struct sis_mii_frame frame; 648 649 sc = device_get_softc(dev); 650 651 if (sc->sis_type == SIS_TYPE_83815) { 652 if (phy != 0) 653 return(0); 654 /* 655 * The NatSemi chip can take a while after 656 * a reset to come ready, during which the BMSR 657 * returns a value of 0. This is *never* supposed 658 * to happen: some of the BMSR bits are meant to 659 * be hardwired in the on position, and this can 660 * confuse the miibus code a bit during the probe 661 * and attach phase. So we make an effort to check 662 * for this condition and wait for it to clear. 663 */ 664 if (!CSR_READ_4(sc, NS_BMSR)) 665 DELAY(1000); 666 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 667 } 668 /* 669 * Chipsets < SIS_635 seem not to be able to read/write 670 * through mdio. Use the enhanced PHY access register 671 * again for them. 672 */ 673 if (sc->sis_type == SIS_TYPE_900 && 674 sc->sis_rev < SIS_REV_635) { 675 int i, val = 0; 676 677 if (phy != 0) 678 return(0); 679 680 CSR_WRITE_4(sc, SIS_PHYCTL, 681 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 682 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 683 684 for (i = 0; i < SIS_TIMEOUT; i++) { 685 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 686 break; 687 } 688 689 if (i == SIS_TIMEOUT) { 690 device_printf(dev, "PHY failed to come ready\n"); 691 return(0); 692 } 693 694 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 695 696 if (val == 0xFFFF) 697 return(0); 698 699 return(val); 700 } else { 701 bzero((char *)&frame, sizeof(frame)); 702 703 frame.mii_phyaddr = phy; 704 frame.mii_regaddr = reg; 705 sis_mii_readreg(sc, &frame); 706 707 return(frame.mii_data); 708 } 709 } 710 711 static int 712 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 713 { 714 struct sis_softc *sc; 715 struct sis_mii_frame frame; 716 717 sc = device_get_softc(dev); 718 719 if (sc->sis_type == SIS_TYPE_83815) { 720 if (phy != 0) 721 return(0); 722 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 723 return(0); 724 } 725 726 if (sc->sis_type == SIS_TYPE_900 && 727 sc->sis_rev < SIS_REV_635) { 728 int i; 729 730 if (phy != 0) 731 return(0); 732 733 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 734 (reg << 6) | SIS_PHYOP_WRITE); 735 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 736 737 for (i = 0; i < SIS_TIMEOUT; i++) { 738 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 739 break; 740 } 741 742 if (i == SIS_TIMEOUT) 743 device_printf(dev, "PHY failed to come ready\n"); 744 } else { 745 bzero((char *)&frame, sizeof(frame)); 746 747 frame.mii_phyaddr = phy; 748 frame.mii_regaddr = reg; 749 frame.mii_data = data; 750 sis_mii_writereg(sc, &frame); 751 } 752 return(0); 753 } 754 755 static void sis_miibus_statchg(device_t dev) 756 { 757 struct sis_softc *sc; 758 759 sc = device_get_softc(dev); 760 sis_init(sc); 761 } 762 763 static uint32_t 764 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 765 { 766 uint32_t crc, carry; 767 int i, j; 768 uint8_t c; 769 770 /* Compute CRC for the address value. */ 771 crc = 0xFFFFFFFF; /* initial value */ 772 773 for (i = 0; i < 6; i++) { 774 c = *(addr + i); 775 for (j = 0; j < 8; j++) { 776 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 777 crc <<= 1; 778 c >>= 1; 779 if (carry) 780 crc = (crc ^ 0x04c11db6) | carry; 781 } 782 } 783 784 /* 785 * return the filter bit position 786 * 787 * The NatSemi chip has a 512-bit filter, which is 788 * different than the SiS, so we special-case it. 789 */ 790 if (sc->sis_type == SIS_TYPE_83815) 791 return (crc >> 23); 792 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 793 return (crc >> 24); 794 else 795 return (crc >> 25); 796 } 797 798 static void 799 sis_setmulti_ns(struct sis_softc *sc) 800 { 801 struct ifnet *ifp; 802 struct ifmultiaddr *ifma; 803 uint32_t h = 0, i, filtsave; 804 int bit, index; 805 806 ifp = &sc->arpcom.ac_if; 807 808 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 809 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 810 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 811 return; 812 } 813 814 /* 815 * We have to explicitly enable the multicast hash table 816 * on the NatSemi chip if we want to use it, which we do. 817 */ 818 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 819 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 820 821 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 822 823 /* first, zot all the existing hash bits */ 824 for (i = 0; i < 32; i++) { 825 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 826 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 827 } 828 829 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 830 if (ifma->ifma_addr->sa_family != AF_LINK) 831 continue; 832 h = sis_mchash(sc, 833 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 834 index = h >> 3; 835 bit = h & 0x1F; 836 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 837 if (bit > 0xF) 838 bit -= 0x10; 839 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 840 } 841 842 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 843 } 844 845 static void 846 sis_setmulti_sis(struct sis_softc *sc) 847 { 848 struct ifnet *ifp; 849 struct ifmultiaddr *ifma; 850 uint32_t h, i, n, ctl; 851 uint16_t hashes[16]; 852 853 ifp = &sc->arpcom.ac_if; 854 855 /* hash table size */ 856 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 857 n = 16; 858 else 859 n = 8; 860 861 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 862 863 if (ifp->if_flags & IFF_BROADCAST) 864 ctl |= SIS_RXFILTCTL_BROAD; 865 866 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 867 ctl |= SIS_RXFILTCTL_ALLMULTI; 868 if (ifp->if_flags & IFF_PROMISC) 869 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 870 for (i = 0; i < n; i++) 871 hashes[i] = ~0; 872 } else { 873 for (i = 0; i < n; i++) 874 hashes[i] = 0; 875 i = 0; 876 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 877 if (ifma->ifma_addr->sa_family != AF_LINK) 878 continue; 879 h = sis_mchash(sc, 880 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 881 hashes[h >> 4] |= 1 << (h & 0xf); 882 i++; 883 } 884 if (i > n) { 885 ctl |= SIS_RXFILTCTL_ALLMULTI; 886 for (i = 0; i < n; i++) 887 hashes[i] = ~0; 888 } 889 } 890 891 for (i = 0; i < n; i++) { 892 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 893 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 894 } 895 896 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 897 } 898 899 static void 900 sis_reset(struct sis_softc *sc) 901 { 902 struct ifnet *ifp = &sc->arpcom.ac_if; 903 int i; 904 905 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 906 907 for (i = 0; i < SIS_TIMEOUT; i++) { 908 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 909 break; 910 } 911 912 if (i == SIS_TIMEOUT) 913 if_printf(ifp, "reset never completed\n"); 914 915 /* Wait a little while for the chip to get its brains in order. */ 916 DELAY(1000); 917 918 /* 919 * If this is a NetSemi chip, make sure to clear 920 * PME mode. 921 */ 922 if (sc->sis_type == SIS_TYPE_83815) { 923 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 924 CSR_WRITE_4(sc, NS_CLKRUN, 0); 925 } 926 } 927 928 /* 929 * Probe for an SiS chip. Check the PCI vendor and device 930 * IDs against our list and return a device name if we find a match. 931 */ 932 static int 933 sis_probe(device_t dev) 934 { 935 struct sis_type *t; 936 937 t = sis_devs; 938 939 while(t->sis_name != NULL) { 940 if ((pci_get_vendor(dev) == t->sis_vid) && 941 (pci_get_device(dev) == t->sis_did)) { 942 device_set_desc(dev, t->sis_name); 943 return(0); 944 } 945 t++; 946 } 947 948 return(ENXIO); 949 } 950 951 /* 952 * Attach the interface. Allocate softc structures, do ifmedia 953 * setup and ethernet/BPF attach. 954 */ 955 static int 956 sis_attach(device_t dev) 957 { 958 uint8_t eaddr[ETHER_ADDR_LEN]; 959 uint32_t command; 960 struct sis_softc *sc; 961 struct ifnet *ifp; 962 int error, rid, waittime; 963 964 error = waittime = 0; 965 sc = device_get_softc(dev); 966 bzero(sc, sizeof(struct sis_softc)); 967 968 if (pci_get_device(dev) == SIS_DEVICEID_900) 969 sc->sis_type = SIS_TYPE_900; 970 if (pci_get_device(dev) == SIS_DEVICEID_7016) 971 sc->sis_type = SIS_TYPE_7016; 972 if (pci_get_vendor(dev) == NS_VENDORID) 973 sc->sis_type = SIS_TYPE_83815; 974 975 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 976 977 /* 978 * Handle power management nonsense. 979 */ 980 981 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 982 if (command == 0x01) { 983 984 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 985 if (command & SIS_PSTATE_MASK) { 986 uint32_t iobase, membase, irq; 987 988 /* Save important PCI config data. */ 989 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 990 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 991 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 992 993 /* Reset the power state. */ 994 device_printf(dev, "chip is in D%d power mode " 995 "-- setting to D0\n", command & SIS_PSTATE_MASK); 996 command &= 0xFFFFFFFC; 997 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 998 999 /* Restore PCI config data. */ 1000 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1001 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1002 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1003 } 1004 } 1005 1006 /* 1007 * Map control/status registers. 1008 */ 1009 command = pci_read_config(dev, PCIR_COMMAND, 4); 1010 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1011 pci_write_config(dev, PCIR_COMMAND, command, 4); 1012 command = pci_read_config(dev, PCIR_COMMAND, 4); 1013 1014 #ifdef SIS_USEIOSPACE 1015 if (!(command & PCIM_CMD_PORTEN)) { 1016 device_printf(dev, "failed to enable I/O ports!\n"); 1017 error = ENXIO;; 1018 goto fail; 1019 } 1020 #else 1021 if (!(command & PCIM_CMD_MEMEN)) { 1022 device_printf(dev, "failed to enable memory mapping!\n"); 1023 error = ENXIO;; 1024 goto fail; 1025 } 1026 #endif 1027 1028 rid = SIS_RID; 1029 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 1030 1031 if (sc->sis_res == NULL) { 1032 device_printf(dev, "couldn't map ports/memory\n"); 1033 error = ENXIO; 1034 goto fail; 1035 } 1036 1037 sc->sis_btag = rman_get_bustag(sc->sis_res); 1038 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1039 1040 /* Allocate interrupt */ 1041 rid = 0; 1042 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1043 RF_SHAREABLE | RF_ACTIVE); 1044 1045 if (sc->sis_irq == NULL) { 1046 device_printf(dev, "couldn't map interrupt\n"); 1047 error = ENXIO; 1048 goto fail; 1049 } 1050 1051 /* Reset the adapter. */ 1052 sis_reset(sc); 1053 1054 if (sc->sis_type == SIS_TYPE_900 && 1055 (sc->sis_rev == SIS_REV_635 || 1056 sc->sis_rev == SIS_REV_900B)) { 1057 SIO_SET(SIS_CFG_RND_CNT); 1058 SIO_SET(SIS_CFG_PERR_DETECT); 1059 } 1060 1061 /* 1062 * Get station address from the EEPROM. 1063 */ 1064 switch (pci_get_vendor(dev)) { 1065 case NS_VENDORID: 1066 /* 1067 * Reading the MAC address out of the EEPROM on 1068 * the NatSemi chip takes a bit more work than 1069 * you'd expect. The address spans 4 16-bit words, 1070 * with the first word containing only a single bit. 1071 * You have to shift everything over one bit to 1072 * get it aligned properly. Also, the bits are 1073 * stored backwards (the LSB is really the MSB, 1074 * and so on) so you have to reverse them in order 1075 * to get the MAC address into the form we want. 1076 * Why? Who the hell knows. 1077 */ 1078 { 1079 uint16_t tmp[4]; 1080 1081 sis_read_eeprom(sc, (caddr_t)&tmp, 1082 NS_EE_NODEADDR, 4, 0); 1083 1084 /* Shift everything over one bit. */ 1085 tmp[3] = tmp[3] >> 1; 1086 tmp[3] |= tmp[2] << 15; 1087 tmp[2] = tmp[2] >> 1; 1088 tmp[2] |= tmp[1] << 15; 1089 tmp[1] = tmp[1] >> 1; 1090 tmp[1] |= tmp[0] << 15; 1091 1092 /* Now reverse all the bits. */ 1093 tmp[3] = sis_reverse(tmp[3]); 1094 tmp[2] = sis_reverse(tmp[2]); 1095 tmp[1] = sis_reverse(tmp[1]); 1096 1097 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1098 } 1099 break; 1100 case SIS_VENDORID: 1101 default: 1102 #ifdef __i386__ 1103 /* 1104 * If this is a SiS 630E chipset with an embedded 1105 * SiS 900 controller, we have to read the MAC address 1106 * from the APC CMOS RAM. Our method for doing this 1107 * is very ugly since we have to reach out and grab 1108 * ahold of hardware for which we cannot properly 1109 * allocate resources. This code is only compiled on 1110 * the i386 architecture since the SiS 630E chipset 1111 * is for x86 motherboards only. Note that there are 1112 * a lot of magic numbers in this hack. These are 1113 * taken from SiS's Linux driver. I'd like to replace 1114 * them with proper symbolic definitions, but that 1115 * requires some datasheets that I don't have access 1116 * to at the moment. 1117 */ 1118 if (sc->sis_rev == SIS_REV_630S || 1119 sc->sis_rev == SIS_REV_630E || 1120 sc->sis_rev == SIS_REV_630EA1) 1121 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1122 1123 else if (sc->sis_rev == SIS_REV_635 || 1124 sc->sis_rev == SIS_REV_630ET) 1125 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1126 else if (sc->sis_rev == SIS_REV_96x) { 1127 /* 1128 * Allow to read EEPROM from LAN. It is shared 1129 * between a 1394 controller and the NIC and each 1130 * time we access it, we need to set SIS_EECMD_REQ. 1131 */ 1132 SIO_SET(SIS_EECMD_REQ); 1133 for (waittime = 0; waittime < SIS_TIMEOUT; 1134 waittime++) { 1135 /* Force EEPROM to idle state. */ 1136 sis_eeprom_idle(sc); 1137 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1138 sis_read_eeprom(sc, (caddr_t)&eaddr, 1139 SIS_EE_NODEADDR, 3, 0); 1140 break; 1141 } 1142 DELAY(1); 1143 } 1144 /* 1145 * Set SIS_EECTL_CLK to high, so a other master 1146 * can operate on the i2c bus. 1147 */ 1148 SIO_SET(SIS_EECTL_CLK); 1149 /* Refuse EEPROM access by LAN */ 1150 SIO_SET(SIS_EECMD_DONE); 1151 } else 1152 #endif 1153 sis_read_eeprom(sc, (caddr_t)&eaddr, 1154 SIS_EE_NODEADDR, 3, 0); 1155 break; 1156 } 1157 1158 callout_init(&sc->sis_timer); 1159 1160 /* 1161 * Allocate the parent bus DMA tag appropriate for PCI. 1162 */ 1163 #define SIS_NSEG_NEW 32 1164 error = bus_dma_tag_create(NULL, /* parent */ 1165 1, 0, /* alignment, boundary */ 1166 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1167 BUS_SPACE_MAXADDR, /* highaddr */ 1168 NULL, NULL, /* filter, filterarg */ 1169 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1170 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1171 BUS_DMA_ALLOCNOW, /* flags */ 1172 &sc->sis_parent_tag); 1173 if (error) 1174 goto fail; 1175 1176 /* 1177 * Now allocate a tag for the DMA descriptor lists and a chunk 1178 * of DMA-able memory based on the tag. Also obtain the physical 1179 * addresses of the RX and TX ring, which we'll need later. 1180 * All of our lists are allocated as a contiguous block of memory. 1181 */ 1182 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1183 1, 0, /* alignment, boundary */ 1184 BUS_SPACE_MAXADDR, /* lowaddr */ 1185 BUS_SPACE_MAXADDR, /* highaddr */ 1186 NULL, NULL, /* filter, filterarg */ 1187 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */ 1188 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1189 0, /* flags */ 1190 &sc->sis_ldata.sis_rx_tag); 1191 if (error) 1192 goto fail; 1193 1194 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1195 (void **)&sc->sis_ldata.sis_rx_list, 1196 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1197 &sc->sis_ldata.sis_rx_dmamap); 1198 1199 if (error) { 1200 device_printf(dev, "no memory for rx list buffers!\n"); 1201 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1202 sc->sis_ldata.sis_rx_tag = NULL; 1203 goto fail; 1204 } 1205 1206 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1207 sc->sis_ldata.sis_rx_dmamap, 1208 sc->sis_ldata.sis_rx_list, 1209 sizeof(struct sis_desc), sis_dma_map_ring, 1210 &sc->sis_cdata.sis_rx_paddr, 0); 1211 1212 if (error) { 1213 device_printf(dev, "cannot get address of the rx ring!\n"); 1214 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1215 sc->sis_ldata.sis_rx_list, 1216 sc->sis_ldata.sis_rx_dmamap); 1217 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1218 sc->sis_ldata.sis_rx_tag = NULL; 1219 goto fail; 1220 } 1221 1222 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1223 1, 0, /* alignment, boundary */ 1224 BUS_SPACE_MAXADDR, /* lowaddr */ 1225 BUS_SPACE_MAXADDR, /* highaddr */ 1226 NULL, NULL, /* filter, filterarg */ 1227 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */ 1228 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1229 0, /* flags */ 1230 &sc->sis_ldata.sis_tx_tag); 1231 if (error) 1232 goto fail; 1233 1234 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1235 (void **)&sc->sis_ldata.sis_tx_list, 1236 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1237 &sc->sis_ldata.sis_tx_dmamap); 1238 1239 if (error) { 1240 device_printf(dev, "no memory for tx list buffers!\n"); 1241 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1242 sc->sis_ldata.sis_tx_tag = NULL; 1243 goto fail; 1244 } 1245 1246 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1247 sc->sis_ldata.sis_tx_dmamap, 1248 sc->sis_ldata.sis_tx_list, 1249 sizeof(struct sis_desc), sis_dma_map_ring, 1250 &sc->sis_cdata.sis_tx_paddr, 0); 1251 1252 if (error) { 1253 device_printf(dev, "cannot get address of the tx ring!\n"); 1254 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1255 sc->sis_ldata.sis_tx_list, 1256 sc->sis_ldata.sis_tx_dmamap); 1257 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1258 sc->sis_ldata.sis_tx_tag = NULL; 1259 goto fail; 1260 } 1261 1262 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1263 1, 0, /* alignment, boundary */ 1264 BUS_SPACE_MAXADDR, /* lowaddr */ 1265 BUS_SPACE_MAXADDR, /* highaddr */ 1266 NULL, NULL, /* filter, filterarg */ 1267 MCLBYTES, 1, /* maxsize, nsegments */ 1268 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1269 0, /* flags */ 1270 &sc->sis_tag); 1271 if (error) 1272 goto fail; 1273 1274 ifp = &sc->arpcom.ac_if; 1275 ifp->if_softc = sc; 1276 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1277 ifp->if_mtu = ETHERMTU; 1278 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1279 ifp->if_ioctl = sis_ioctl; 1280 ifp->if_start = sis_start; 1281 ifp->if_watchdog = sis_watchdog; 1282 ifp->if_init = sis_init; 1283 ifp->if_baudrate = 10000000; 1284 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1285 ifq_set_ready(&ifp->if_snd); 1286 #ifdef DEVICE_POLLING 1287 ifp->if_poll = sis_poll; 1288 #endif 1289 ifp->if_capenable = ifp->if_capabilities; 1290 1291 /* 1292 * Do MII setup. 1293 */ 1294 if (mii_phy_probe(dev, &sc->sis_miibus, 1295 sis_ifmedia_upd, sis_ifmedia_sts)) { 1296 device_printf(dev, "MII without any PHY!\n"); 1297 error = ENXIO; 1298 goto fail; 1299 } 1300 1301 /* 1302 * Call MI attach routine. 1303 */ 1304 ether_ifattach(ifp, eaddr); 1305 1306 /* 1307 * Tell the upper layer(s) we support long frames. 1308 */ 1309 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1310 1311 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1312 sis_intr, sc, 1313 &sc->sis_intrhand, NULL); 1314 1315 if (error) { 1316 device_printf(dev, "couldn't set up irq\n"); 1317 ether_ifdetach(ifp); 1318 goto fail; 1319 } 1320 1321 fail: 1322 if (error) 1323 sis_detach(dev); 1324 1325 return(error); 1326 } 1327 1328 /* 1329 * Shutdown hardware and free up resources. It is called in both the error case 1330 * and the normal detach case so it needs to be careful about only freeing 1331 * resources that have actually been allocated. 1332 */ 1333 static int 1334 sis_detach(device_t dev) 1335 { 1336 struct sis_softc *sc; 1337 struct ifnet *ifp; 1338 int s; 1339 1340 s = splimp(); 1341 1342 sc = device_get_softc(dev); 1343 ifp = &sc->arpcom.ac_if; 1344 1345 if (device_is_attached(dev)) { 1346 sis_reset(sc); 1347 sis_stop(sc); 1348 ether_ifdetach(ifp); 1349 } 1350 if (sc->sis_miibus) 1351 device_delete_child(dev, sc->sis_miibus); 1352 bus_generic_detach(dev); 1353 1354 if (sc->sis_intrhand) 1355 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1356 if (sc->sis_irq) 1357 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1358 if (sc->sis_res) 1359 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1360 1361 if (sc->sis_ldata.sis_rx_tag) { 1362 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1363 sc->sis_ldata.sis_rx_dmamap); 1364 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1365 sc->sis_ldata.sis_rx_list, 1366 sc->sis_ldata.sis_rx_dmamap); 1367 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1368 } 1369 1370 if (sc->sis_ldata.sis_tx_tag) { 1371 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1372 sc->sis_ldata.sis_tx_dmamap); 1373 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1374 sc->sis_ldata.sis_tx_list, 1375 sc->sis_ldata.sis_tx_dmamap); 1376 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1377 } 1378 if (sc->sis_tag) 1379 bus_dma_tag_destroy(sc->sis_tag); 1380 if (sc->sis_parent_tag) 1381 bus_dma_tag_destroy(sc->sis_parent_tag); 1382 1383 splx(s); 1384 1385 return(0); 1386 } 1387 1388 /* 1389 * Initialize the transmit descriptors. 1390 */ 1391 static int 1392 sis_list_tx_init(struct sis_softc *sc) 1393 { 1394 struct sis_list_data *ld; 1395 struct sis_ring_data *cd; 1396 int i, nexti; 1397 1398 cd = &sc->sis_cdata; 1399 ld = &sc->sis_ldata; 1400 1401 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1402 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1403 ld->sis_tx_list[i].sis_nextdesc = 1404 &ld->sis_tx_list[nexti]; 1405 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1406 sc->sis_ldata.sis_tx_dmamap, 1407 &ld->sis_tx_list[nexti], 1408 sizeof(struct sis_desc), sis_dma_map_desc_next, 1409 &ld->sis_tx_list[i], 0); 1410 ld->sis_tx_list[i].sis_mbuf = NULL; 1411 ld->sis_tx_list[i].sis_ptr = 0; 1412 ld->sis_tx_list[i].sis_ctl = 0; 1413 } 1414 1415 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1416 1417 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap, 1418 BUS_DMASYNC_PREWRITE); 1419 1420 return(0); 1421 } 1422 1423 /* 1424 * Initialize the RX descriptors and allocate mbufs for them. Note that 1425 * we arrange the descriptors in a closed ring, so that the last descriptor 1426 * points back to the first. 1427 */ 1428 static int 1429 sis_list_rx_init(struct sis_softc *sc) 1430 { 1431 struct sis_list_data *ld; 1432 struct sis_ring_data *cd; 1433 int i, nexti; 1434 1435 ld = &sc->sis_ldata; 1436 cd = &sc->sis_cdata; 1437 1438 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1439 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1440 return(ENOBUFS); 1441 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1442 ld->sis_rx_list[i].sis_nextdesc = 1443 &ld->sis_rx_list[nexti]; 1444 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1445 sc->sis_ldata.sis_rx_dmamap, 1446 &ld->sis_rx_list[nexti], 1447 sizeof(struct sis_desc), sis_dma_map_desc_next, 1448 &ld->sis_rx_list[i], 0); 1449 } 1450 1451 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap, 1452 BUS_DMASYNC_PREWRITE); 1453 1454 cd->sis_rx_prod = 0; 1455 1456 return(0); 1457 } 1458 1459 /* 1460 * Initialize an RX descriptor and attach an MBUF cluster. 1461 */ 1462 static int 1463 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 1464 { 1465 if (m == NULL) { 1466 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1467 if (m == NULL) 1468 return(ENOBUFS); 1469 } else { 1470 m->m_data = m->m_ext.ext_buf; 1471 } 1472 1473 c->sis_mbuf = m; 1474 c->sis_ctl = SIS_RXLEN; 1475 1476 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1477 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES, 1478 sis_dma_map_desc_ptr, c, 0); 1479 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1480 1481 return(0); 1482 } 1483 1484 /* 1485 * A frame has been uploaded: pass the resulting mbuf chain up to 1486 * the higher level protocols. 1487 */ 1488 static void 1489 sis_rxeof(struct sis_softc *sc) 1490 { 1491 struct mbuf *m; 1492 struct ifnet *ifp; 1493 struct sis_desc *cur_rx; 1494 int i, total_len = 0; 1495 uint32_t rxstat; 1496 1497 ifp = &sc->arpcom.ac_if; 1498 i = sc->sis_cdata.sis_rx_prod; 1499 1500 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1501 1502 #ifdef DEVICE_POLLING 1503 if (ifp->if_flags & IFF_POLLING) { 1504 if (sc->rxcycles <= 0) 1505 break; 1506 sc->rxcycles--; 1507 } 1508 #endif /* DEVICE_POLLING */ 1509 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1510 rxstat = cur_rx->sis_rxstat; 1511 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map, 1512 BUS_DMASYNC_POSTWRITE); 1513 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1514 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1515 m = cur_rx->sis_mbuf; 1516 cur_rx->sis_mbuf = NULL; 1517 total_len = SIS_RXBYTES(cur_rx); 1518 SIS_INC(i, SIS_RX_LIST_CNT); 1519 1520 /* 1521 * If an error occurs, update stats, clear the 1522 * status word and leave the mbuf cluster in place: 1523 * it should simply get re-used next time this descriptor 1524 * comes up in the ring. 1525 */ 1526 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1527 ifp->if_ierrors++; 1528 if (rxstat & SIS_RXSTAT_COLL) 1529 ifp->if_collisions++; 1530 sis_newbuf(sc, cur_rx, m); 1531 continue; 1532 } 1533 1534 /* No errors; receive the packet. */ 1535 #ifdef __i386__ 1536 /* 1537 * On the x86 we do not have alignment problems, so try to 1538 * allocate a new buffer for the receive ring, and pass up 1539 * the one where the packet is already, saving the expensive 1540 * copy done in m_devget(). 1541 * If we are on an architecture with alignment problems, or 1542 * if the allocation fails, then use m_devget and leave the 1543 * existing buffer in the receive ring. 1544 */ 1545 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1546 m->m_pkthdr.len = m->m_len = total_len; 1547 else 1548 #endif 1549 { 1550 struct mbuf *m0; 1551 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1552 total_len + ETHER_ALIGN, 0, ifp, NULL); 1553 sis_newbuf(sc, cur_rx, m); 1554 if (m0 == NULL) { 1555 ifp->if_ierrors++; 1556 continue; 1557 } 1558 m_adj(m0, ETHER_ALIGN); 1559 m = m0; 1560 } 1561 1562 ifp->if_ipackets++; 1563 (*ifp->if_input)(ifp, m); 1564 } 1565 1566 sc->sis_cdata.sis_rx_prod = i; 1567 } 1568 1569 static void 1570 sis_rxeoc(struct sis_softc *sc) 1571 { 1572 sis_rxeof(sc); 1573 sis_init(sc); 1574 } 1575 1576 /* 1577 * A frame was downloaded to the chip. It's safe for us to clean up 1578 * the list buffers. 1579 */ 1580 1581 static void 1582 sis_txeof(struct sis_softc *sc) 1583 { 1584 struct sis_desc *cur_tx; 1585 struct ifnet *ifp; 1586 uint32_t idx; 1587 1588 ifp = &sc->arpcom.ac_if; 1589 1590 /* 1591 * Go through our tx list and free mbufs for those 1592 * frames that have been transmitted. 1593 */ 1594 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1595 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1596 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1597 1598 if (SIS_OWNDESC(cur_tx)) 1599 break; 1600 1601 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1602 continue; 1603 1604 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1605 ifp->if_oerrors++; 1606 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1607 ifp->if_collisions++; 1608 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1609 ifp->if_collisions++; 1610 } 1611 1612 ifp->if_collisions += 1613 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1614 1615 ifp->if_opackets++; 1616 if (cur_tx->sis_mbuf != NULL) { 1617 m_freem(cur_tx->sis_mbuf); 1618 cur_tx->sis_mbuf = NULL; 1619 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1620 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1621 } 1622 } 1623 1624 if (idx != sc->sis_cdata.sis_tx_cons) { 1625 /* we freed up some buffers */ 1626 sc->sis_cdata.sis_tx_cons = idx; 1627 ifp->if_flags &= ~IFF_OACTIVE; 1628 } 1629 1630 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1631 } 1632 1633 static void 1634 sis_tick(void *xsc) 1635 { 1636 struct sis_softc *sc; 1637 struct mii_data *mii; 1638 struct ifnet *ifp; 1639 int s; 1640 1641 s = splimp(); 1642 1643 sc = xsc; 1644 ifp = &sc->arpcom.ac_if; 1645 1646 mii = device_get_softc(sc->sis_miibus); 1647 mii_tick(mii); 1648 1649 if (!sc->sis_link) { 1650 mii_pollstat(mii); 1651 if (mii->mii_media_status & IFM_ACTIVE && 1652 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1653 sc->sis_link++; 1654 if (!ifq_is_empty(&ifp->if_snd)) 1655 sis_start(ifp); 1656 } 1657 1658 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1659 1660 splx(s); 1661 } 1662 1663 #ifdef DEVICE_POLLING 1664 1665 static void 1666 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1667 { 1668 struct sis_softc *sc = ifp->if_softc; 1669 1670 switch(cmd) { 1671 case POLL_REGISTER: 1672 /* disable interrupts */ 1673 CSR_WRITE_4(sc, SIS_IER, 0); 1674 break; 1675 case POLL_DEREGISTER: 1676 /* enable interrupts */ 1677 CSR_WRITE_4(sc, SIS_IER, 1); 1678 break; 1679 default: 1680 /* 1681 * On the sis, reading the status register also clears it. 1682 * So before returning to intr mode we must make sure that all 1683 * possible pending sources of interrupts have been served. 1684 * In practice this means run to completion the *eof routines, 1685 * and then call the interrupt routine 1686 */ 1687 sc->rxcycles = count; 1688 sis_rxeof(sc); 1689 sis_txeof(sc); 1690 if (!ifq_is_empty(&ifp->if_snd)) 1691 sis_start(ifp); 1692 1693 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1694 uint32_t status; 1695 1696 /* Reading the ISR register clears all interrupts. */ 1697 status = CSR_READ_4(sc, SIS_ISR); 1698 1699 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1700 sis_rxeoc(sc); 1701 1702 if (status & (SIS_ISR_RX_IDLE)) 1703 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1704 1705 if (status & SIS_ISR_SYSERR) { 1706 sis_reset(sc); 1707 sis_init(sc); 1708 } 1709 } 1710 break; 1711 } 1712 } 1713 #endif /* DEVICE_POLLING */ 1714 1715 static void 1716 sis_intr(void *arg) 1717 { 1718 struct sis_softc *sc; 1719 struct ifnet *ifp; 1720 uint32_t status; 1721 1722 sc = arg; 1723 ifp = &sc->arpcom.ac_if; 1724 1725 /* Supress unwanted interrupts */ 1726 if (!(ifp->if_flags & IFF_UP)) { 1727 sis_stop(sc); 1728 return; 1729 } 1730 1731 /* Disable interrupts. */ 1732 CSR_WRITE_4(sc, SIS_IER, 0); 1733 1734 for (;;) { 1735 /* Reading the ISR register clears all interrupts. */ 1736 status = CSR_READ_4(sc, SIS_ISR); 1737 1738 if ((status & SIS_INTRS) == 0) 1739 break; 1740 1741 if (status & 1742 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | 1743 SIS_ISR_TX_IDLE) ) 1744 sis_txeof(sc); 1745 1746 if (status & 1747 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE)) 1748 sis_rxeof(sc); 1749 1750 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1751 sis_rxeoc(sc); 1752 1753 if (status & (SIS_ISR_RX_IDLE)) 1754 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1755 1756 if (status & SIS_ISR_SYSERR) { 1757 sis_reset(sc); 1758 sis_init(sc); 1759 } 1760 } 1761 1762 /* Re-enable interrupts. */ 1763 CSR_WRITE_4(sc, SIS_IER, 1); 1764 1765 if (!ifq_is_empty(&ifp->if_snd)) 1766 sis_start(ifp); 1767 } 1768 1769 /* 1770 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1771 * pointers to the fragment pointers. 1772 */ 1773 static int 1774 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1775 { 1776 struct sis_desc *f = NULL; 1777 struct mbuf *m; 1778 int frag, cur, cnt = 0; 1779 1780 /* 1781 * If there's no way we can send any packets, return now. 1782 */ 1783 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1784 return (ENOBUFS); 1785 1786 /* 1787 * Start packing the mbufs in this chain into 1788 * the fragment pointers. Stop when we run out 1789 * of fragments or hit the end of the mbuf chain. 1790 */ 1791 m = m_head; 1792 cur = frag = *txidx; 1793 1794 for (m = m_head; m != NULL; m = m->m_next) { 1795 if (m->m_len != 0) { 1796 if ((SIS_TX_LIST_CNT - 1797 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1798 return(ENOBUFS); 1799 f = &sc->sis_ldata.sis_tx_list[frag]; 1800 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1801 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1802 bus_dmamap_load(sc->sis_tag, f->sis_map, 1803 mtod(m, void *), m->m_len, 1804 sis_dma_map_desc_ptr, f, 0); 1805 bus_dmamap_sync(sc->sis_tag, f->sis_map, 1806 BUS_DMASYNC_PREREAD); 1807 if (cnt != 0) 1808 f->sis_ctl |= SIS_CMDSTS_OWN; 1809 cur = frag; 1810 SIS_INC(frag, SIS_TX_LIST_CNT); 1811 cnt++; 1812 } 1813 } 1814 1815 if (m != NULL) 1816 return(ENOBUFS); 1817 1818 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1819 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1820 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1821 sc->sis_cdata.sis_tx_cnt += cnt; 1822 *txidx = frag; 1823 1824 return(0); 1825 } 1826 1827 /* 1828 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1829 * to the mbuf data regions directly in the transmit lists. We also save a 1830 * copy of the pointers since the transmit list fragment pointers are 1831 * physical addresses. 1832 */ 1833 1834 static void 1835 sis_start(struct ifnet *ifp) 1836 { 1837 struct sis_softc *sc; 1838 struct mbuf *m_head = NULL; 1839 uint32_t idx; 1840 1841 sc = ifp->if_softc; 1842 1843 if (!sc->sis_link) 1844 return; 1845 1846 idx = sc->sis_cdata.sis_tx_prod; 1847 1848 if (ifp->if_flags & IFF_OACTIVE) 1849 return; 1850 1851 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1852 m_head = ifq_poll(&ifp->if_snd); 1853 if (m_head == NULL) 1854 break; 1855 1856 if (sis_encap(sc, m_head, &idx)) { 1857 ifp->if_flags |= IFF_OACTIVE; 1858 break; 1859 } 1860 m_head = ifq_dequeue(&ifp->if_snd); 1861 1862 /* 1863 * If there's a BPF listener, bounce a copy of this frame 1864 * to him. 1865 */ 1866 BPF_MTAP(ifp, m_head); 1867 } 1868 1869 /* Transmit */ 1870 sc->sis_cdata.sis_tx_prod = idx; 1871 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1872 1873 /* 1874 * Set a timeout in case the chip goes out to lunch. 1875 */ 1876 ifp->if_timer = 5; 1877 } 1878 1879 static void 1880 sis_init(void *xsc) 1881 { 1882 struct sis_softc *sc = xsc; 1883 struct ifnet *ifp = &sc->arpcom.ac_if; 1884 struct mii_data *mii; 1885 int s; 1886 1887 s = splimp(); 1888 1889 /* 1890 * Cancel pending I/O and free all RX/TX buffers. 1891 */ 1892 sis_stop(sc); 1893 1894 mii = device_get_softc(sc->sis_miibus); 1895 1896 /* Set MAC address */ 1897 if (sc->sis_type == SIS_TYPE_83815) { 1898 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1899 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1900 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1901 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1902 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1903 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1904 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1905 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1906 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1907 } else { 1908 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1909 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1910 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1911 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1912 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1913 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1914 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1915 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1916 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1917 } 1918 1919 /* Init circular RX list. */ 1920 if (sis_list_rx_init(sc) == ENOBUFS) { 1921 if_printf(ifp, "initialization failed: " 1922 "no memory for rx buffers\n"); 1923 sis_stop(sc); 1924 splx(s); 1925 return; 1926 } 1927 1928 /* 1929 * Init tx descriptors. 1930 */ 1931 sis_list_tx_init(sc); 1932 1933 /* 1934 * For the NatSemi chip, we have to explicitly enable the 1935 * reception of ARP frames, as well as turn on the 'perfect 1936 * match' filter where we store the station address, otherwise 1937 * we won't receive unicasts meant for this host. 1938 */ 1939 if (sc->sis_type == SIS_TYPE_83815) { 1940 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1941 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1942 } 1943 1944 /* If we want promiscuous mode, set the allframes bit. */ 1945 if (ifp->if_flags & IFF_PROMISC) 1946 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1947 else 1948 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1949 1950 /* 1951 * Set the capture broadcast bit to capture broadcast frames. 1952 */ 1953 if (ifp->if_flags & IFF_BROADCAST) 1954 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1955 else 1956 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1957 1958 /* 1959 * Load the multicast filter. 1960 */ 1961 if (sc->sis_type == SIS_TYPE_83815) 1962 sis_setmulti_ns(sc); 1963 else 1964 sis_setmulti_sis(sc); 1965 1966 /* Turn the receive filter on */ 1967 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1968 1969 /* 1970 * Load the address of the RX and TX lists. 1971 */ 1972 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1973 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1974 1975 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1976 * the PCI bus. When this bit is set, the Max DMA Burst Size 1977 * for TX/RX DMA should be no larger than 16 double words. 1978 */ 1979 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) 1980 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1981 else 1982 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1983 1984 /* Accept Long Packets for VLAN support */ 1985 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1986 1987 /* Set TX configuration */ 1988 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1989 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1990 else 1991 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1992 1993 /* Set full/half duplex mode. */ 1994 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1995 SIS_SETBIT(sc, SIS_TX_CFG, 1996 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1997 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1998 } else { 1999 SIS_CLRBIT(sc, SIS_TX_CFG, 2000 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2001 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2002 } 2003 2004 /* 2005 * Enable interrupts. 2006 */ 2007 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2008 #ifdef DEVICE_POLLING 2009 /* 2010 * ... only enable interrupts if we are not polling, make sure 2011 * they are off otherwise. 2012 */ 2013 if (ifp->if_flags & IFF_POLLING) 2014 CSR_WRITE_4(sc, SIS_IER, 0); 2015 else 2016 #endif /* DEVICE_POLLING */ 2017 CSR_WRITE_4(sc, SIS_IER, 1); 2018 2019 /* Enable receiver and transmitter. */ 2020 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2021 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2022 2023 #ifdef notdef 2024 mii_mediachg(mii); 2025 #endif 2026 2027 /* 2028 * Page 75 of the DP83815 manual recommends the 2029 * following register settings "for optimum 2030 * performance." Note however that at least three 2031 * of the registers are listed as "reserved" in 2032 * the register map, so who knows what they do. 2033 */ 2034 if (sc->sis_type == SIS_TYPE_83815) { 2035 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2036 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2037 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2038 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2039 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2040 } 2041 2042 ifp->if_flags |= IFF_RUNNING; 2043 ifp->if_flags &= ~IFF_OACTIVE; 2044 2045 splx(s); 2046 2047 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 2048 } 2049 2050 /* 2051 * Set media options. 2052 */ 2053 static int 2054 sis_ifmedia_upd(struct ifnet *ifp) 2055 { 2056 struct sis_softc *sc; 2057 struct mii_data *mii; 2058 2059 sc = ifp->if_softc; 2060 2061 mii = device_get_softc(sc->sis_miibus); 2062 sc->sis_link = 0; 2063 if (mii->mii_instance) { 2064 struct mii_softc *miisc; 2065 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2066 mii_phy_reset(miisc); 2067 } 2068 mii_mediachg(mii); 2069 2070 return(0); 2071 } 2072 2073 /* 2074 * Report current media status. 2075 */ 2076 static void 2077 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2078 { 2079 struct sis_softc *sc; 2080 struct mii_data *mii; 2081 2082 sc = ifp->if_softc; 2083 2084 mii = device_get_softc(sc->sis_miibus); 2085 mii_pollstat(mii); 2086 ifmr->ifm_active = mii->mii_media_active; 2087 ifmr->ifm_status = mii->mii_media_status; 2088 } 2089 2090 static int 2091 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2092 { 2093 struct sis_softc *sc = ifp->if_softc; 2094 struct ifreq *ifr = (struct ifreq *) data; 2095 struct mii_data *mii; 2096 int s, error = 0; 2097 2098 switch(command) { 2099 case SIOCSIFFLAGS: 2100 if (ifp->if_flags & IFF_UP) { 2101 sis_init(sc); 2102 } else { 2103 if (ifp->if_flags & IFF_RUNNING) 2104 sis_stop(sc); 2105 } 2106 error = 0; 2107 break; 2108 case SIOCADDMULTI: 2109 case SIOCDELMULTI: 2110 s = splimp(); 2111 if (sc->sis_type == SIS_TYPE_83815) 2112 sis_setmulti_ns(sc); 2113 else 2114 sis_setmulti_sis(sc); 2115 splx(s); 2116 error = 0; 2117 break; 2118 case SIOCGIFMEDIA: 2119 case SIOCSIFMEDIA: 2120 mii = device_get_softc(sc->sis_miibus); 2121 s = splimp(); 2122 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2123 splx(s); 2124 break; 2125 default: 2126 error = ether_ioctl(ifp, command, data); 2127 break; 2128 } 2129 2130 return(error); 2131 } 2132 2133 static void 2134 sis_watchdog(struct ifnet *ifp) 2135 { 2136 struct sis_softc *sc; 2137 2138 sc = ifp->if_softc; 2139 2140 ifp->if_oerrors++; 2141 if_printf(ifp, "watchdog timeout\n"); 2142 2143 sis_stop(sc); 2144 sis_reset(sc); 2145 sis_init(sc); 2146 2147 if (!ifq_is_empty(&ifp->if_snd)) 2148 sis_start(ifp); 2149 } 2150 2151 /* 2152 * Stop the adapter and free any mbufs allocated to the 2153 * RX and TX lists. 2154 */ 2155 static void 2156 sis_stop(struct sis_softc *sc) 2157 { 2158 int i; 2159 struct ifnet *ifp; 2160 2161 ifp = &sc->arpcom.ac_if; 2162 ifp->if_timer = 0; 2163 2164 callout_stop(&sc->sis_timer); 2165 2166 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2167 CSR_WRITE_4(sc, SIS_IER, 0); 2168 CSR_WRITE_4(sc, SIS_IMR, 0); 2169 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2170 DELAY(1000); 2171 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2172 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2173 2174 sc->sis_link = 0; 2175 2176 /* 2177 * Free data in the RX lists. 2178 */ 2179 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2180 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2181 bus_dmamap_unload(sc->sis_tag, 2182 sc->sis_ldata.sis_rx_list[i].sis_map); 2183 bus_dmamap_destroy(sc->sis_tag, 2184 sc->sis_ldata.sis_rx_list[i].sis_map); 2185 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2186 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2187 } 2188 } 2189 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list)); 2190 2191 /* 2192 * Free the TX list buffers. 2193 */ 2194 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2195 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2196 bus_dmamap_unload(sc->sis_tag, 2197 sc->sis_ldata.sis_tx_list[i].sis_map); 2198 bus_dmamap_destroy(sc->sis_tag, 2199 sc->sis_ldata.sis_tx_list[i].sis_map); 2200 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2201 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2202 } 2203 } 2204 2205 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list)); 2206 } 2207 2208 /* 2209 * Stop all chip I/O so that the kernel's probe routines don't 2210 * get confused by errant DMAs when rebooting. 2211 */ 2212 static void 2213 sis_shutdown(device_t dev) 2214 { 2215 struct sis_softc *sc; 2216 2217 sc = device_get_softc(dev); 2218 2219 sis_reset(sc); 2220 sis_stop(sc); 2221 } 2222