1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.34 2006/08/06 12:49:06 swildner Exp $ 34 */ 35 36 /* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #include "opt_polling.h" 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sysctl.h> 71 #include <sys/serialize.h> 72 #include <sys/thread2.h> 73 74 #include <net/if.h> 75 #include <net/ifq_var.h> 76 #include <net/if_arp.h> 77 #include <net/ethernet.h> 78 #include <net/if_dl.h> 79 #include <net/if_media.h> 80 #include <net/if_types.h> 81 #include <net/vlan/if_vlan_var.h> 82 83 #include <net/bpf.h> 84 85 #include <machine/bus_pio.h> 86 #include <machine/bus_memio.h> 87 #include <machine/bus.h> 88 #include <machine/resource.h> 89 #include <sys/bus.h> 90 #include <sys/rman.h> 91 92 #include <dev/netif/mii_layer/mii.h> 93 #include <dev/netif/mii_layer/miivar.h> 94 95 #include <bus/pci/pcidevs.h> 96 #include <bus/pci/pcireg.h> 97 #include <bus/pci/pcivar.h> 98 99 #define SIS_USEIOSPACE 100 101 #include "if_sisreg.h" 102 103 /* "controller miibus0" required. See GENERIC if you get errors here. */ 104 #include "miibus_if.h" 105 106 /* 107 * Various supported device vendors/types and their names. 108 */ 109 static struct sis_type sis_devs[] = { 110 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" }, 111 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" }, 112 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 113 { 0, 0, NULL } 114 }; 115 116 static int sis_probe(device_t); 117 static int sis_attach(device_t); 118 static int sis_detach(device_t); 119 120 static int sis_newbuf(struct sis_softc *, struct sis_desc *, 121 struct mbuf *); 122 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *); 123 static void sis_rxeof(struct sis_softc *); 124 static void sis_rxeoc(struct sis_softc *); 125 static void sis_txeof(struct sis_softc *); 126 static void sis_intr(void *); 127 static void sis_tick(void *); 128 static void sis_start(struct ifnet *); 129 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 130 static void sis_init(void *); 131 static void sis_stop(struct sis_softc *); 132 static void sis_watchdog(struct ifnet *); 133 static void sis_shutdown(device_t); 134 static int sis_ifmedia_upd(struct ifnet *); 135 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 136 137 static uint16_t sis_reverse(uint16_t); 138 static void sis_delay(struct sis_softc *); 139 static void sis_eeprom_idle(struct sis_softc *); 140 static void sis_eeprom_putbyte(struct sis_softc *, int); 141 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *); 142 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 143 #ifdef __i386__ 144 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int); 145 static void sis_read_mac(struct sis_softc *, device_t, caddr_t); 146 static device_t sis_find_bridge(device_t); 147 #endif 148 149 static void sis_mii_sync(struct sis_softc *); 150 static void sis_mii_send(struct sis_softc *, uint32_t, int); 151 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 152 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 153 static int sis_miibus_readreg(device_t, int, int); 154 static int sis_miibus_writereg(device_t, int, int, int); 155 static void sis_miibus_statchg(device_t); 156 157 static void sis_setmulti_sis(struct sis_softc *); 158 static void sis_setmulti_ns(struct sis_softc *); 159 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *); 160 static void sis_reset(struct sis_softc *); 161 static int sis_list_rx_init(struct sis_softc *); 162 static int sis_list_tx_init(struct sis_softc *); 163 164 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int); 165 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int); 166 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int); 167 #ifdef DEVICE_POLLING 168 static poll_handler_t sis_poll; 169 #endif 170 #ifdef SIS_USEIOSPACE 171 #define SIS_RES SYS_RES_IOPORT 172 #define SIS_RID SIS_PCI_LOIO 173 #else 174 #define SIS_RES SYS_RES_MEMORY 175 #define SIS_RID SIS_PCI_LOMEM 176 #endif 177 178 static device_method_t sis_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, sis_probe), 181 DEVMETHOD(device_attach, sis_attach), 182 DEVMETHOD(device_detach, sis_detach), 183 DEVMETHOD(device_shutdown, sis_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 191 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 192 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 193 194 { 0, 0 } 195 }; 196 197 static driver_t sis_driver = { 198 "sis", 199 sis_methods, 200 sizeof(struct sis_softc) 201 }; 202 203 static devclass_t sis_devclass; 204 205 DECLARE_DUMMY_MODULE(if_sis); 206 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 207 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 208 209 #define SIS_SETBIT(sc, reg, x) \ 210 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 211 212 #define SIS_CLRBIT(sc, reg, x) \ 213 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 214 215 #define SIO_SET(x) \ 216 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 217 218 #define SIO_CLR(x) \ 219 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 220 221 static void 222 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 223 { 224 struct sis_desc *r; 225 226 r = arg; 227 r->sis_next = segs->ds_addr; 228 } 229 230 static void 231 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 232 { 233 struct sis_desc *r; 234 235 r = arg; 236 r->sis_ptr = segs->ds_addr; 237 } 238 239 static void 240 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 241 { 242 uint32_t *p; 243 244 p = arg; 245 *p = segs->ds_addr; 246 } 247 248 /* 249 * Routine to reverse the bits in a word. Stolen almost 250 * verbatim from /usr/games/fortune. 251 */ 252 static uint16_t 253 sis_reverse(uint16_t n) 254 { 255 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 256 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 257 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 258 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 259 260 return(n); 261 } 262 263 static void 264 sis_delay(struct sis_softc *sc) 265 { 266 int idx; 267 268 for (idx = (300 / 33) + 1; idx > 0; idx--) 269 CSR_READ_4(sc, SIS_CSR); 270 } 271 272 static void 273 sis_eeprom_idle(struct sis_softc *sc) 274 { 275 int i; 276 277 SIO_SET(SIS_EECTL_CSEL); 278 sis_delay(sc); 279 SIO_SET(SIS_EECTL_CLK); 280 sis_delay(sc); 281 282 for (i = 0; i < 25; i++) { 283 SIO_CLR(SIS_EECTL_CLK); 284 sis_delay(sc); 285 SIO_SET(SIS_EECTL_CLK); 286 sis_delay(sc); 287 } 288 289 SIO_CLR(SIS_EECTL_CLK); 290 sis_delay(sc); 291 SIO_CLR(SIS_EECTL_CSEL); 292 sis_delay(sc); 293 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 294 } 295 296 /* 297 * Send a read command and address to the EEPROM, check for ACK. 298 */ 299 static void 300 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 301 { 302 int d, i; 303 304 d = addr | SIS_EECMD_READ; 305 306 /* 307 * Feed in each bit and stobe the clock. 308 */ 309 for (i = 0x400; i; i >>= 1) { 310 if (d & i) 311 SIO_SET(SIS_EECTL_DIN); 312 else 313 SIO_CLR(SIS_EECTL_DIN); 314 sis_delay(sc); 315 SIO_SET(SIS_EECTL_CLK); 316 sis_delay(sc); 317 SIO_CLR(SIS_EECTL_CLK); 318 sis_delay(sc); 319 } 320 } 321 322 /* 323 * Read a word of data stored in the EEPROM at address 'addr.' 324 */ 325 static void 326 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 327 { 328 int i; 329 uint16_t word = 0; 330 331 /* Force EEPROM to idle state. */ 332 sis_eeprom_idle(sc); 333 334 /* Enter EEPROM access mode. */ 335 sis_delay(sc); 336 SIO_CLR(SIS_EECTL_CLK); 337 sis_delay(sc); 338 SIO_SET(SIS_EECTL_CSEL); 339 sis_delay(sc); 340 341 /* 342 * Send address of word we want to read. 343 */ 344 sis_eeprom_putbyte(sc, addr); 345 346 /* 347 * Start reading bits from EEPROM. 348 */ 349 for (i = 0x8000; i; i >>= 1) { 350 SIO_SET(SIS_EECTL_CLK); 351 sis_delay(sc); 352 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 353 word |= i; 354 sis_delay(sc); 355 SIO_CLR(SIS_EECTL_CLK); 356 sis_delay(sc); 357 } 358 359 /* Turn off EEPROM access mode. */ 360 sis_eeprom_idle(sc); 361 362 *dest = word; 363 } 364 365 /* 366 * Read a sequence of words from the EEPROM. 367 */ 368 static void 369 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 370 { 371 int i; 372 uint16_t word = 0, *ptr; 373 374 for (i = 0; i < cnt; i++) { 375 sis_eeprom_getword(sc, off + i, &word); 376 ptr = (uint16_t *)(dest + (i * 2)); 377 if (swap) 378 *ptr = ntohs(word); 379 else 380 *ptr = word; 381 } 382 } 383 384 #ifdef __i386__ 385 static device_t 386 sis_find_bridge(device_t dev) 387 { 388 devclass_t pci_devclass; 389 device_t *pci_devices; 390 int pci_count = 0; 391 device_t *pci_children; 392 int pci_childcount = 0; 393 device_t *busp, *childp; 394 device_t child = NULL; 395 int i, j; 396 397 if ((pci_devclass = devclass_find("pci")) == NULL) 398 return(NULL); 399 400 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 401 402 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 403 pci_childcount = 0; 404 device_get_children(*busp, &pci_children, &pci_childcount); 405 for (j = 0, childp = pci_children; j < pci_childcount; 406 j++, childp++) { 407 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS && 408 pci_get_device(*childp) == 0x0008) { 409 child = *childp; 410 goto done; 411 } 412 } 413 } 414 415 done: 416 free(pci_devices, M_TEMP); 417 free(pci_children, M_TEMP); 418 return(child); 419 } 420 421 static void 422 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, 423 int cnt) 424 { 425 device_t bridge; 426 uint8_t reg; 427 int i; 428 bus_space_tag_t btag; 429 430 bridge = sis_find_bridge(dev); 431 if (bridge == NULL) 432 return; 433 reg = pci_read_config(bridge, 0x48, 1); 434 pci_write_config(bridge, 0x48, reg|0x40, 1); 435 436 /* XXX */ 437 btag = I386_BUS_SPACE_IO; 438 439 for (i = 0; i < cnt; i++) { 440 bus_space_write_1(btag, 0x0, 0x70, i + off); 441 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 442 } 443 444 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 445 } 446 447 static void 448 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 449 { 450 uint32_t filtsave, csrsave; 451 452 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 453 csrsave = CSR_READ_4(sc, SIS_CSR); 454 455 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 456 CSR_WRITE_4(sc, SIS_CSR, 0); 457 458 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 459 460 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 461 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 462 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 463 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 464 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 465 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 466 467 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 468 CSR_WRITE_4(sc, SIS_CSR, csrsave); 469 } 470 #endif 471 472 /* 473 * Sync the PHYs by setting data bit and strobing the clock 32 times. 474 */ 475 static void 476 sis_mii_sync(struct sis_softc *sc) 477 { 478 int i; 479 480 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 481 482 for (i = 0; i < 32; i++) { 483 SIO_SET(SIS_MII_CLK); 484 DELAY(1); 485 SIO_CLR(SIS_MII_CLK); 486 DELAY(1); 487 } 488 } 489 490 /* 491 * Clock a series of bits through the MII. 492 */ 493 static void 494 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 495 { 496 int i; 497 498 SIO_CLR(SIS_MII_CLK); 499 500 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 501 if (bits & i) 502 SIO_SET(SIS_MII_DATA); 503 else 504 SIO_CLR(SIS_MII_DATA); 505 DELAY(1); 506 SIO_CLR(SIS_MII_CLK); 507 DELAY(1); 508 SIO_SET(SIS_MII_CLK); 509 } 510 } 511 512 /* 513 * Read an PHY register through the MII. 514 */ 515 static int 516 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 517 { 518 int i, ack; 519 520 /* 521 * Set up frame for RX. 522 */ 523 frame->mii_stdelim = SIS_MII_STARTDELIM; 524 frame->mii_opcode = SIS_MII_READOP; 525 frame->mii_turnaround = 0; 526 frame->mii_data = 0; 527 528 /* 529 * Turn on data xmit. 530 */ 531 SIO_SET(SIS_MII_DIR); 532 533 sis_mii_sync(sc); 534 535 /* 536 * Send command/address info. 537 */ 538 sis_mii_send(sc, frame->mii_stdelim, 2); 539 sis_mii_send(sc, frame->mii_opcode, 2); 540 sis_mii_send(sc, frame->mii_phyaddr, 5); 541 sis_mii_send(sc, frame->mii_regaddr, 5); 542 543 /* Idle bit */ 544 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 545 DELAY(1); 546 SIO_SET(SIS_MII_CLK); 547 DELAY(1); 548 549 /* Turn off xmit. */ 550 SIO_CLR(SIS_MII_DIR); 551 552 /* Check for ack */ 553 SIO_CLR(SIS_MII_CLK); 554 DELAY(1); 555 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 556 SIO_SET(SIS_MII_CLK); 557 DELAY(1); 558 559 /* 560 * Now try reading data bits. If the ack failed, we still 561 * need to clock through 16 cycles to keep the PHY(s) in sync. 562 */ 563 if (ack) { 564 for(i = 0; i < 16; i++) { 565 SIO_CLR(SIS_MII_CLK); 566 DELAY(1); 567 SIO_SET(SIS_MII_CLK); 568 DELAY(1); 569 } 570 goto fail; 571 } 572 573 for (i = 0x8000; i; i >>= 1) { 574 SIO_CLR(SIS_MII_CLK); 575 DELAY(1); 576 if (!ack) { 577 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 578 frame->mii_data |= i; 579 DELAY(1); 580 } 581 SIO_SET(SIS_MII_CLK); 582 DELAY(1); 583 } 584 585 fail: 586 587 SIO_CLR(SIS_MII_CLK); 588 DELAY(1); 589 SIO_SET(SIS_MII_CLK); 590 DELAY(1); 591 592 if (ack) 593 return(1); 594 return(0); 595 } 596 597 /* 598 * Write to a PHY register through the MII. 599 */ 600 static int 601 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 602 { 603 /* 604 * Set up frame for TX. 605 */ 606 607 frame->mii_stdelim = SIS_MII_STARTDELIM; 608 frame->mii_opcode = SIS_MII_WRITEOP; 609 frame->mii_turnaround = SIS_MII_TURNAROUND; 610 611 /* 612 * Turn on data output. 613 */ 614 SIO_SET(SIS_MII_DIR); 615 616 sis_mii_sync(sc); 617 618 sis_mii_send(sc, frame->mii_stdelim, 2); 619 sis_mii_send(sc, frame->mii_opcode, 2); 620 sis_mii_send(sc, frame->mii_phyaddr, 5); 621 sis_mii_send(sc, frame->mii_regaddr, 5); 622 sis_mii_send(sc, frame->mii_turnaround, 2); 623 sis_mii_send(sc, frame->mii_data, 16); 624 625 /* Idle bit. */ 626 SIO_SET(SIS_MII_CLK); 627 DELAY(1); 628 SIO_CLR(SIS_MII_CLK); 629 DELAY(1); 630 631 /* 632 * Turn off xmit. 633 */ 634 SIO_CLR(SIS_MII_DIR); 635 636 return(0); 637 } 638 639 static int 640 sis_miibus_readreg(device_t dev, int phy, int reg) 641 { 642 struct sis_softc *sc; 643 struct sis_mii_frame frame; 644 645 sc = device_get_softc(dev); 646 647 if (sc->sis_type == SIS_TYPE_83815) { 648 if (phy != 0) 649 return(0); 650 /* 651 * The NatSemi chip can take a while after 652 * a reset to come ready, during which the BMSR 653 * returns a value of 0. This is *never* supposed 654 * to happen: some of the BMSR bits are meant to 655 * be hardwired in the on position, and this can 656 * confuse the miibus code a bit during the probe 657 * and attach phase. So we make an effort to check 658 * for this condition and wait for it to clear. 659 */ 660 if (!CSR_READ_4(sc, NS_BMSR)) 661 DELAY(1000); 662 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 663 } 664 /* 665 * Chipsets < SIS_635 seem not to be able to read/write 666 * through mdio. Use the enhanced PHY access register 667 * again for them. 668 */ 669 if (sc->sis_type == SIS_TYPE_900 && 670 sc->sis_rev < SIS_REV_635) { 671 int i, val = 0; 672 673 if (phy != 0) 674 return(0); 675 676 CSR_WRITE_4(sc, SIS_PHYCTL, 677 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 678 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 679 680 for (i = 0; i < SIS_TIMEOUT; i++) { 681 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 682 break; 683 } 684 685 if (i == SIS_TIMEOUT) { 686 device_printf(dev, "PHY failed to come ready\n"); 687 return(0); 688 } 689 690 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 691 692 if (val == 0xFFFF) 693 return(0); 694 695 return(val); 696 } else { 697 bzero((char *)&frame, sizeof(frame)); 698 699 frame.mii_phyaddr = phy; 700 frame.mii_regaddr = reg; 701 sis_mii_readreg(sc, &frame); 702 703 return(frame.mii_data); 704 } 705 } 706 707 static int 708 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 709 { 710 struct sis_softc *sc; 711 struct sis_mii_frame frame; 712 713 sc = device_get_softc(dev); 714 715 if (sc->sis_type == SIS_TYPE_83815) { 716 if (phy != 0) 717 return(0); 718 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 719 return(0); 720 } 721 722 if (sc->sis_type == SIS_TYPE_900 && 723 sc->sis_rev < SIS_REV_635) { 724 int i; 725 726 if (phy != 0) 727 return(0); 728 729 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 730 (reg << 6) | SIS_PHYOP_WRITE); 731 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 732 733 for (i = 0; i < SIS_TIMEOUT; i++) { 734 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 735 break; 736 } 737 738 if (i == SIS_TIMEOUT) 739 device_printf(dev, "PHY failed to come ready\n"); 740 } else { 741 bzero((char *)&frame, sizeof(frame)); 742 743 frame.mii_phyaddr = phy; 744 frame.mii_regaddr = reg; 745 frame.mii_data = data; 746 sis_mii_writereg(sc, &frame); 747 } 748 return(0); 749 } 750 751 static void 752 sis_miibus_statchg(device_t dev) 753 { 754 struct sis_softc *sc; 755 756 sc = device_get_softc(dev); 757 sis_init(sc); 758 } 759 760 static uint32_t 761 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 762 { 763 uint32_t crc, carry; 764 int i, j; 765 uint8_t c; 766 767 /* Compute CRC for the address value. */ 768 crc = 0xFFFFFFFF; /* initial value */ 769 770 for (i = 0; i < 6; i++) { 771 c = *(addr + i); 772 for (j = 0; j < 8; j++) { 773 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 774 crc <<= 1; 775 c >>= 1; 776 if (carry) 777 crc = (crc ^ 0x04c11db6) | carry; 778 } 779 } 780 781 /* 782 * return the filter bit position 783 * 784 * The NatSemi chip has a 512-bit filter, which is 785 * different than the SiS, so we special-case it. 786 */ 787 if (sc->sis_type == SIS_TYPE_83815) 788 return (crc >> 23); 789 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 790 return (crc >> 24); 791 else 792 return (crc >> 25); 793 } 794 795 static void 796 sis_setmulti_ns(struct sis_softc *sc) 797 { 798 struct ifnet *ifp; 799 struct ifmultiaddr *ifma; 800 uint32_t h = 0, i, filtsave; 801 int bit, index; 802 803 ifp = &sc->arpcom.ac_if; 804 805 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 806 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 807 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 808 return; 809 } 810 811 /* 812 * We have to explicitly enable the multicast hash table 813 * on the NatSemi chip if we want to use it, which we do. 814 */ 815 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 816 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 817 818 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 819 820 /* first, zot all the existing hash bits */ 821 for (i = 0; i < 32; i++) { 822 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 823 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 824 } 825 826 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 827 if (ifma->ifma_addr->sa_family != AF_LINK) 828 continue; 829 h = sis_mchash(sc, 830 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 831 index = h >> 3; 832 bit = h & 0x1F; 833 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 834 if (bit > 0xF) 835 bit -= 0x10; 836 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 837 } 838 839 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 840 } 841 842 static void 843 sis_setmulti_sis(struct sis_softc *sc) 844 { 845 struct ifnet *ifp; 846 struct ifmultiaddr *ifma; 847 uint32_t h, i, n, ctl; 848 uint16_t hashes[16]; 849 850 ifp = &sc->arpcom.ac_if; 851 852 /* hash table size */ 853 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 854 n = 16; 855 else 856 n = 8; 857 858 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 859 860 if (ifp->if_flags & IFF_BROADCAST) 861 ctl |= SIS_RXFILTCTL_BROAD; 862 863 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 864 ctl |= SIS_RXFILTCTL_ALLMULTI; 865 if (ifp->if_flags & IFF_PROMISC) 866 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 867 for (i = 0; i < n; i++) 868 hashes[i] = ~0; 869 } else { 870 for (i = 0; i < n; i++) 871 hashes[i] = 0; 872 i = 0; 873 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 874 if (ifma->ifma_addr->sa_family != AF_LINK) 875 continue; 876 h = sis_mchash(sc, 877 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 878 hashes[h >> 4] |= 1 << (h & 0xf); 879 i++; 880 } 881 if (i > n) { 882 ctl |= SIS_RXFILTCTL_ALLMULTI; 883 for (i = 0; i < n; i++) 884 hashes[i] = ~0; 885 } 886 } 887 888 for (i = 0; i < n; i++) { 889 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 890 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 891 } 892 893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 894 } 895 896 static void 897 sis_reset(struct sis_softc *sc) 898 { 899 struct ifnet *ifp = &sc->arpcom.ac_if; 900 int i; 901 902 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 903 904 for (i = 0; i < SIS_TIMEOUT; i++) { 905 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 906 break; 907 } 908 909 if (i == SIS_TIMEOUT) 910 if_printf(ifp, "reset never completed\n"); 911 912 /* Wait a little while for the chip to get its brains in order. */ 913 DELAY(1000); 914 915 /* 916 * If this is a NetSemi chip, make sure to clear 917 * PME mode. 918 */ 919 if (sc->sis_type == SIS_TYPE_83815) { 920 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 921 CSR_WRITE_4(sc, NS_CLKRUN, 0); 922 } 923 } 924 925 /* 926 * Probe for an SiS chip. Check the PCI vendor and device 927 * IDs against our list and return a device name if we find a match. 928 */ 929 static int 930 sis_probe(device_t dev) 931 { 932 struct sis_type *t; 933 934 t = sis_devs; 935 936 while(t->sis_name != NULL) { 937 if ((pci_get_vendor(dev) == t->sis_vid) && 938 (pci_get_device(dev) == t->sis_did)) { 939 device_set_desc(dev, t->sis_name); 940 return(0); 941 } 942 t++; 943 } 944 945 return(ENXIO); 946 } 947 948 /* 949 * Attach the interface. Allocate softc structures, do ifmedia 950 * setup and ethernet/BPF attach. 951 */ 952 static int 953 sis_attach(device_t dev) 954 { 955 uint8_t eaddr[ETHER_ADDR_LEN]; 956 uint32_t command; 957 struct sis_softc *sc; 958 struct ifnet *ifp; 959 int error, rid, waittime; 960 961 error = waittime = 0; 962 sc = device_get_softc(dev); 963 964 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900) 965 sc->sis_type = SIS_TYPE_900; 966 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016) 967 sc->sis_type = SIS_TYPE_7016; 968 if (pci_get_vendor(dev) == PCI_VENDOR_NS) 969 sc->sis_type = SIS_TYPE_83815; 970 971 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 972 973 /* 974 * Handle power management nonsense. 975 */ 976 977 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 978 if (command == 0x01) { 979 980 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 981 if (command & SIS_PSTATE_MASK) { 982 uint32_t iobase, membase, irq; 983 984 /* Save important PCI config data. */ 985 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 986 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 987 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 988 989 /* Reset the power state. */ 990 device_printf(dev, "chip is in D%d power mode " 991 "-- setting to D0\n", command & SIS_PSTATE_MASK); 992 command &= 0xFFFFFFFC; 993 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 994 995 /* Restore PCI config data. */ 996 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 997 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 998 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 999 } 1000 } 1001 1002 /* 1003 * Map control/status registers. 1004 */ 1005 command = pci_read_config(dev, PCIR_COMMAND, 4); 1006 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1007 pci_write_config(dev, PCIR_COMMAND, command, 4); 1008 command = pci_read_config(dev, PCIR_COMMAND, 4); 1009 1010 #ifdef SIS_USEIOSPACE 1011 if (!(command & PCIM_CMD_PORTEN)) { 1012 device_printf(dev, "failed to enable I/O ports!\n"); 1013 error = ENXIO; 1014 goto fail; 1015 } 1016 #else 1017 if (!(command & PCIM_CMD_MEMEN)) { 1018 device_printf(dev, "failed to enable memory mapping!\n"); 1019 error = ENXIO; 1020 goto fail; 1021 } 1022 #endif 1023 1024 rid = SIS_RID; 1025 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 1026 1027 if (sc->sis_res == NULL) { 1028 device_printf(dev, "couldn't map ports/memory\n"); 1029 error = ENXIO; 1030 goto fail; 1031 } 1032 1033 sc->sis_btag = rman_get_bustag(sc->sis_res); 1034 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1035 1036 /* Allocate interrupt */ 1037 rid = 0; 1038 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1039 RF_SHAREABLE | RF_ACTIVE); 1040 1041 if (sc->sis_irq == NULL) { 1042 device_printf(dev, "couldn't map interrupt\n"); 1043 error = ENXIO; 1044 goto fail; 1045 } 1046 1047 /* Reset the adapter. */ 1048 sis_reset(sc); 1049 1050 if (sc->sis_type == SIS_TYPE_900 && 1051 (sc->sis_rev == SIS_REV_635 || 1052 sc->sis_rev == SIS_REV_900B)) { 1053 SIO_SET(SIS_CFG_RND_CNT); 1054 SIO_SET(SIS_CFG_PERR_DETECT); 1055 } 1056 1057 /* 1058 * Get station address from the EEPROM. 1059 */ 1060 switch (pci_get_vendor(dev)) { 1061 case PCI_VENDOR_NS: 1062 /* 1063 * Reading the MAC address out of the EEPROM on 1064 * the NatSemi chip takes a bit more work than 1065 * you'd expect. The address spans 4 16-bit words, 1066 * with the first word containing only a single bit. 1067 * You have to shift everything over one bit to 1068 * get it aligned properly. Also, the bits are 1069 * stored backwards (the LSB is really the MSB, 1070 * and so on) so you have to reverse them in order 1071 * to get the MAC address into the form we want. 1072 * Why? Who the hell knows. 1073 */ 1074 { 1075 uint16_t tmp[4]; 1076 1077 sis_read_eeprom(sc, (caddr_t)&tmp, 1078 NS_EE_NODEADDR, 4, 0); 1079 1080 /* Shift everything over one bit. */ 1081 tmp[3] = tmp[3] >> 1; 1082 tmp[3] |= tmp[2] << 15; 1083 tmp[2] = tmp[2] >> 1; 1084 tmp[2] |= tmp[1] << 15; 1085 tmp[1] = tmp[1] >> 1; 1086 tmp[1] |= tmp[0] << 15; 1087 1088 /* Now reverse all the bits. */ 1089 tmp[3] = sis_reverse(tmp[3]); 1090 tmp[2] = sis_reverse(tmp[2]); 1091 tmp[1] = sis_reverse(tmp[1]); 1092 1093 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1094 } 1095 break; 1096 case PCI_VENDOR_SIS: 1097 default: 1098 #ifdef __i386__ 1099 /* 1100 * If this is a SiS 630E chipset with an embedded 1101 * SiS 900 controller, we have to read the MAC address 1102 * from the APC CMOS RAM. Our method for doing this 1103 * is very ugly since we have to reach out and grab 1104 * ahold of hardware for which we cannot properly 1105 * allocate resources. This code is only compiled on 1106 * the i386 architecture since the SiS 630E chipset 1107 * is for x86 motherboards only. Note that there are 1108 * a lot of magic numbers in this hack. These are 1109 * taken from SiS's Linux driver. I'd like to replace 1110 * them with proper symbolic definitions, but that 1111 * requires some datasheets that I don't have access 1112 * to at the moment. 1113 */ 1114 if (sc->sis_rev == SIS_REV_630S || 1115 sc->sis_rev == SIS_REV_630E || 1116 sc->sis_rev == SIS_REV_630EA1) 1117 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1118 1119 else if (sc->sis_rev == SIS_REV_635 || 1120 sc->sis_rev == SIS_REV_630ET) 1121 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1122 else if (sc->sis_rev == SIS_REV_96x) { 1123 /* 1124 * Allow to read EEPROM from LAN. It is shared 1125 * between a 1394 controller and the NIC and each 1126 * time we access it, we need to set SIS_EECMD_REQ. 1127 */ 1128 SIO_SET(SIS_EECMD_REQ); 1129 for (waittime = 0; waittime < SIS_TIMEOUT; 1130 waittime++) { 1131 /* Force EEPROM to idle state. */ 1132 sis_eeprom_idle(sc); 1133 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1134 sis_read_eeprom(sc, (caddr_t)&eaddr, 1135 SIS_EE_NODEADDR, 3, 0); 1136 break; 1137 } 1138 DELAY(1); 1139 } 1140 /* 1141 * Set SIS_EECTL_CLK to high, so a other master 1142 * can operate on the i2c bus. 1143 */ 1144 SIO_SET(SIS_EECTL_CLK); 1145 /* Refuse EEPROM access by LAN */ 1146 SIO_SET(SIS_EECMD_DONE); 1147 } else 1148 #endif 1149 sis_read_eeprom(sc, (caddr_t)&eaddr, 1150 SIS_EE_NODEADDR, 3, 0); 1151 break; 1152 } 1153 1154 callout_init(&sc->sis_timer); 1155 1156 /* 1157 * Allocate the parent bus DMA tag appropriate for PCI. 1158 */ 1159 #define SIS_NSEG_NEW 32 1160 error = bus_dma_tag_create(NULL, /* parent */ 1161 1, 0, /* alignment, boundary */ 1162 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1163 BUS_SPACE_MAXADDR, /* highaddr */ 1164 NULL, NULL, /* filter, filterarg */ 1165 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1166 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1167 BUS_DMA_ALLOCNOW, /* flags */ 1168 &sc->sis_parent_tag); 1169 if (error) 1170 goto fail; 1171 1172 /* 1173 * Now allocate a tag for the DMA descriptor lists and a chunk 1174 * of DMA-able memory based on the tag. Also obtain the physical 1175 * addresses of the RX and TX ring, which we'll need later. 1176 * All of our lists are allocated as a contiguous block of memory. 1177 */ 1178 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1179 1, 0, /* alignment, boundary */ 1180 BUS_SPACE_MAXADDR, /* lowaddr */ 1181 BUS_SPACE_MAXADDR, /* highaddr */ 1182 NULL, NULL, /* filter, filterarg */ 1183 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */ 1184 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1185 0, /* flags */ 1186 &sc->sis_ldata.sis_rx_tag); 1187 if (error) 1188 goto fail; 1189 1190 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1191 (void **)&sc->sis_ldata.sis_rx_list, 1192 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1193 &sc->sis_ldata.sis_rx_dmamap); 1194 1195 if (error) { 1196 device_printf(dev, "no memory for rx list buffers!\n"); 1197 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1198 sc->sis_ldata.sis_rx_tag = NULL; 1199 goto fail; 1200 } 1201 1202 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1203 sc->sis_ldata.sis_rx_dmamap, 1204 sc->sis_ldata.sis_rx_list, 1205 sizeof(struct sis_desc), sis_dma_map_ring, 1206 &sc->sis_cdata.sis_rx_paddr, 0); 1207 1208 if (error) { 1209 device_printf(dev, "cannot get address of the rx ring!\n"); 1210 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1211 sc->sis_ldata.sis_rx_list, 1212 sc->sis_ldata.sis_rx_dmamap); 1213 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1214 sc->sis_ldata.sis_rx_tag = NULL; 1215 goto fail; 1216 } 1217 1218 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1219 1, 0, /* alignment, boundary */ 1220 BUS_SPACE_MAXADDR, /* lowaddr */ 1221 BUS_SPACE_MAXADDR, /* highaddr */ 1222 NULL, NULL, /* filter, filterarg */ 1223 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */ 1224 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1225 0, /* flags */ 1226 &sc->sis_ldata.sis_tx_tag); 1227 if (error) 1228 goto fail; 1229 1230 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1231 (void **)&sc->sis_ldata.sis_tx_list, 1232 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1233 &sc->sis_ldata.sis_tx_dmamap); 1234 1235 if (error) { 1236 device_printf(dev, "no memory for tx list buffers!\n"); 1237 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1238 sc->sis_ldata.sis_tx_tag = NULL; 1239 goto fail; 1240 } 1241 1242 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1243 sc->sis_ldata.sis_tx_dmamap, 1244 sc->sis_ldata.sis_tx_list, 1245 sizeof(struct sis_desc), sis_dma_map_ring, 1246 &sc->sis_cdata.sis_tx_paddr, 0); 1247 1248 if (error) { 1249 device_printf(dev, "cannot get address of the tx ring!\n"); 1250 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1251 sc->sis_ldata.sis_tx_list, 1252 sc->sis_ldata.sis_tx_dmamap); 1253 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1254 sc->sis_ldata.sis_tx_tag = NULL; 1255 goto fail; 1256 } 1257 1258 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1259 1, 0, /* alignment, boundary */ 1260 BUS_SPACE_MAXADDR, /* lowaddr */ 1261 BUS_SPACE_MAXADDR, /* highaddr */ 1262 NULL, NULL, /* filter, filterarg */ 1263 MCLBYTES, 1, /* maxsize, nsegments */ 1264 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1265 0, /* flags */ 1266 &sc->sis_tag); 1267 if (error) 1268 goto fail; 1269 1270 ifp = &sc->arpcom.ac_if; 1271 ifp->if_softc = sc; 1272 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1273 ifp->if_mtu = ETHERMTU; 1274 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1275 ifp->if_ioctl = sis_ioctl; 1276 ifp->if_start = sis_start; 1277 ifp->if_watchdog = sis_watchdog; 1278 ifp->if_init = sis_init; 1279 ifp->if_baudrate = 10000000; 1280 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1281 ifq_set_ready(&ifp->if_snd); 1282 #ifdef DEVICE_POLLING 1283 ifp->if_poll = sis_poll; 1284 #endif 1285 ifp->if_capenable = ifp->if_capabilities; 1286 1287 /* 1288 * Do MII setup. 1289 */ 1290 if (mii_phy_probe(dev, &sc->sis_miibus, 1291 sis_ifmedia_upd, sis_ifmedia_sts)) { 1292 device_printf(dev, "MII without any PHY!\n"); 1293 error = ENXIO; 1294 goto fail; 1295 } 1296 1297 /* 1298 * Call MI attach routine. 1299 */ 1300 ether_ifattach(ifp, eaddr, NULL); 1301 1302 /* 1303 * Tell the upper layer(s) we support long frames. 1304 */ 1305 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1306 1307 error = bus_setup_intr(dev, sc->sis_irq, INTR_NETSAFE, 1308 sis_intr, sc, 1309 &sc->sis_intrhand, 1310 ifp->if_serializer); 1311 1312 if (error) { 1313 device_printf(dev, "couldn't set up irq\n"); 1314 ether_ifdetach(ifp); 1315 goto fail; 1316 } 1317 1318 fail: 1319 if (error) 1320 sis_detach(dev); 1321 1322 return(error); 1323 } 1324 1325 /* 1326 * Shutdown hardware and free up resources. It is called in both the error case 1327 * and the normal detach case so it needs to be careful about only freeing 1328 * resources that have actually been allocated. 1329 */ 1330 static int 1331 sis_detach(device_t dev) 1332 { 1333 struct sis_softc *sc = device_get_softc(dev); 1334 struct ifnet *ifp = &sc->arpcom.ac_if; 1335 1336 1337 if (device_is_attached(dev)) { 1338 lwkt_serialize_enter(ifp->if_serializer); 1339 sis_reset(sc); 1340 sis_stop(sc); 1341 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1342 lwkt_serialize_exit(ifp->if_serializer); 1343 1344 ether_ifdetach(ifp); 1345 } 1346 if (sc->sis_miibus) 1347 device_delete_child(dev, sc->sis_miibus); 1348 bus_generic_detach(dev); 1349 1350 if (sc->sis_irq) 1351 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1352 if (sc->sis_res) 1353 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1354 1355 if (sc->sis_ldata.sis_rx_tag) { 1356 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1357 sc->sis_ldata.sis_rx_dmamap); 1358 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1359 sc->sis_ldata.sis_rx_list, 1360 sc->sis_ldata.sis_rx_dmamap); 1361 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1362 } 1363 1364 if (sc->sis_ldata.sis_tx_tag) { 1365 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1366 sc->sis_ldata.sis_tx_dmamap); 1367 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1368 sc->sis_ldata.sis_tx_list, 1369 sc->sis_ldata.sis_tx_dmamap); 1370 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1371 } 1372 if (sc->sis_tag) 1373 bus_dma_tag_destroy(sc->sis_tag); 1374 if (sc->sis_parent_tag) 1375 bus_dma_tag_destroy(sc->sis_parent_tag); 1376 1377 return(0); 1378 } 1379 1380 /* 1381 * Initialize the transmit descriptors. 1382 */ 1383 static int 1384 sis_list_tx_init(struct sis_softc *sc) 1385 { 1386 struct sis_list_data *ld; 1387 struct sis_ring_data *cd; 1388 int i, nexti; 1389 1390 cd = &sc->sis_cdata; 1391 ld = &sc->sis_ldata; 1392 1393 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1394 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1395 ld->sis_tx_list[i].sis_nextdesc = 1396 &ld->sis_tx_list[nexti]; 1397 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1398 sc->sis_ldata.sis_tx_dmamap, 1399 &ld->sis_tx_list[nexti], 1400 sizeof(struct sis_desc), sis_dma_map_desc_next, 1401 &ld->sis_tx_list[i], 0); 1402 ld->sis_tx_list[i].sis_mbuf = NULL; 1403 ld->sis_tx_list[i].sis_ptr = 0; 1404 ld->sis_tx_list[i].sis_ctl = 0; 1405 } 1406 1407 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1408 1409 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap, 1410 BUS_DMASYNC_PREWRITE); 1411 1412 return(0); 1413 } 1414 1415 /* 1416 * Initialize the RX descriptors and allocate mbufs for them. Note that 1417 * we arrange the descriptors in a closed ring, so that the last descriptor 1418 * points back to the first. 1419 */ 1420 static int 1421 sis_list_rx_init(struct sis_softc *sc) 1422 { 1423 struct sis_list_data *ld; 1424 struct sis_ring_data *cd; 1425 int i, nexti; 1426 1427 ld = &sc->sis_ldata; 1428 cd = &sc->sis_cdata; 1429 1430 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1431 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1432 return(ENOBUFS); 1433 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1434 ld->sis_rx_list[i].sis_nextdesc = 1435 &ld->sis_rx_list[nexti]; 1436 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1437 sc->sis_ldata.sis_rx_dmamap, 1438 &ld->sis_rx_list[nexti], 1439 sizeof(struct sis_desc), sis_dma_map_desc_next, 1440 &ld->sis_rx_list[i], 0); 1441 } 1442 1443 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap, 1444 BUS_DMASYNC_PREWRITE); 1445 1446 cd->sis_rx_prod = 0; 1447 1448 return(0); 1449 } 1450 1451 /* 1452 * Initialize an RX descriptor and attach an MBUF cluster. 1453 */ 1454 static int 1455 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 1456 { 1457 if (m == NULL) { 1458 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1459 if (m == NULL) 1460 return(ENOBUFS); 1461 } else { 1462 m->m_data = m->m_ext.ext_buf; 1463 } 1464 1465 c->sis_mbuf = m; 1466 c->sis_ctl = SIS_RXLEN; 1467 1468 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1469 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES, 1470 sis_dma_map_desc_ptr, c, 0); 1471 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1472 1473 return(0); 1474 } 1475 1476 /* 1477 * A frame has been uploaded: pass the resulting mbuf chain up to 1478 * the higher level protocols. 1479 */ 1480 static void 1481 sis_rxeof(struct sis_softc *sc) 1482 { 1483 struct mbuf *m; 1484 struct ifnet *ifp; 1485 struct sis_desc *cur_rx; 1486 int i, total_len = 0; 1487 uint32_t rxstat; 1488 1489 ifp = &sc->arpcom.ac_if; 1490 i = sc->sis_cdata.sis_rx_prod; 1491 1492 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1493 1494 #ifdef DEVICE_POLLING 1495 if (ifp->if_flags & IFF_POLLING) { 1496 if (sc->rxcycles <= 0) 1497 break; 1498 sc->rxcycles--; 1499 } 1500 #endif /* DEVICE_POLLING */ 1501 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1502 rxstat = cur_rx->sis_rxstat; 1503 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map, 1504 BUS_DMASYNC_POSTWRITE); 1505 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1506 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1507 m = cur_rx->sis_mbuf; 1508 cur_rx->sis_mbuf = NULL; 1509 total_len = SIS_RXBYTES(cur_rx); 1510 SIS_INC(i, SIS_RX_LIST_CNT); 1511 1512 /* 1513 * If an error occurs, update stats, clear the 1514 * status word and leave the mbuf cluster in place: 1515 * it should simply get re-used next time this descriptor 1516 * comes up in the ring. 1517 */ 1518 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1519 ifp->if_ierrors++; 1520 if (rxstat & SIS_RXSTAT_COLL) 1521 ifp->if_collisions++; 1522 sis_newbuf(sc, cur_rx, m); 1523 continue; 1524 } 1525 1526 /* No errors; receive the packet. */ 1527 #ifdef __i386__ 1528 /* 1529 * On the x86 we do not have alignment problems, so try to 1530 * allocate a new buffer for the receive ring, and pass up 1531 * the one where the packet is already, saving the expensive 1532 * copy done in m_devget(). 1533 * If we are on an architecture with alignment problems, or 1534 * if the allocation fails, then use m_devget and leave the 1535 * existing buffer in the receive ring. 1536 */ 1537 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1538 m->m_pkthdr.len = m->m_len = total_len; 1539 else 1540 #endif 1541 { 1542 struct mbuf *m0; 1543 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1544 total_len + ETHER_ALIGN, 0, ifp, NULL); 1545 sis_newbuf(sc, cur_rx, m); 1546 if (m0 == NULL) { 1547 ifp->if_ierrors++; 1548 continue; 1549 } 1550 m_adj(m0, ETHER_ALIGN); 1551 m = m0; 1552 } 1553 1554 ifp->if_ipackets++; 1555 ifp->if_input(ifp, m); 1556 } 1557 1558 sc->sis_cdata.sis_rx_prod = i; 1559 } 1560 1561 static void 1562 sis_rxeoc(struct sis_softc *sc) 1563 { 1564 sis_rxeof(sc); 1565 sis_init(sc); 1566 } 1567 1568 /* 1569 * A frame was downloaded to the chip. It's safe for us to clean up 1570 * the list buffers. 1571 */ 1572 1573 static void 1574 sis_txeof(struct sis_softc *sc) 1575 { 1576 struct sis_desc *cur_tx; 1577 struct ifnet *ifp; 1578 uint32_t idx; 1579 1580 ifp = &sc->arpcom.ac_if; 1581 1582 /* 1583 * Go through our tx list and free mbufs for those 1584 * frames that have been transmitted. 1585 */ 1586 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1587 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1588 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1589 1590 if (SIS_OWNDESC(cur_tx)) 1591 break; 1592 1593 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1594 continue; 1595 1596 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1597 ifp->if_oerrors++; 1598 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1599 ifp->if_collisions++; 1600 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1601 ifp->if_collisions++; 1602 } 1603 1604 ifp->if_collisions += 1605 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1606 1607 ifp->if_opackets++; 1608 if (cur_tx->sis_mbuf != NULL) { 1609 m_freem(cur_tx->sis_mbuf); 1610 cur_tx->sis_mbuf = NULL; 1611 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1612 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1613 } 1614 } 1615 1616 if (idx != sc->sis_cdata.sis_tx_cons) { 1617 /* we freed up some buffers */ 1618 sc->sis_cdata.sis_tx_cons = idx; 1619 ifp->if_flags &= ~IFF_OACTIVE; 1620 } 1621 1622 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1623 } 1624 1625 static void 1626 sis_tick(void *xsc) 1627 { 1628 struct sis_softc *sc = xsc; 1629 struct mii_data *mii; 1630 struct ifnet *ifp = &sc->arpcom.ac_if; 1631 1632 lwkt_serialize_enter(ifp->if_serializer); 1633 1634 mii = device_get_softc(sc->sis_miibus); 1635 mii_tick(mii); 1636 1637 if (!sc->sis_link) { 1638 mii_pollstat(mii); 1639 if (mii->mii_media_status & IFM_ACTIVE && 1640 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1641 sc->sis_link++; 1642 if (!ifq_is_empty(&ifp->if_snd)) 1643 sis_start(ifp); 1644 } 1645 1646 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1647 lwkt_serialize_exit(ifp->if_serializer); 1648 } 1649 1650 #ifdef DEVICE_POLLING 1651 1652 static void 1653 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1654 { 1655 struct sis_softc *sc = ifp->if_softc; 1656 1657 switch(cmd) { 1658 case POLL_REGISTER: 1659 /* disable interrupts */ 1660 CSR_WRITE_4(sc, SIS_IER, 0); 1661 break; 1662 case POLL_DEREGISTER: 1663 /* enable interrupts */ 1664 CSR_WRITE_4(sc, SIS_IER, 1); 1665 break; 1666 default: 1667 /* 1668 * On the sis, reading the status register also clears it. 1669 * So before returning to intr mode we must make sure that all 1670 * possible pending sources of interrupts have been served. 1671 * In practice this means run to completion the *eof routines, 1672 * and then call the interrupt routine 1673 */ 1674 sc->rxcycles = count; 1675 sis_rxeof(sc); 1676 sis_txeof(sc); 1677 if (!ifq_is_empty(&ifp->if_snd)) 1678 sis_start(ifp); 1679 1680 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1681 uint32_t status; 1682 1683 /* Reading the ISR register clears all interrupts. */ 1684 status = CSR_READ_4(sc, SIS_ISR); 1685 1686 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1687 sis_rxeoc(sc); 1688 1689 if (status & (SIS_ISR_RX_IDLE)) 1690 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1691 1692 if (status & SIS_ISR_SYSERR) { 1693 sis_reset(sc); 1694 sis_init(sc); 1695 } 1696 } 1697 break; 1698 } 1699 } 1700 #endif /* DEVICE_POLLING */ 1701 1702 static void 1703 sis_intr(void *arg) 1704 { 1705 struct sis_softc *sc; 1706 struct ifnet *ifp; 1707 uint32_t status; 1708 1709 sc = arg; 1710 ifp = &sc->arpcom.ac_if; 1711 1712 /* Supress unwanted interrupts */ 1713 if (!(ifp->if_flags & IFF_UP)) { 1714 sis_stop(sc); 1715 return; 1716 } 1717 1718 /* Disable interrupts. */ 1719 CSR_WRITE_4(sc, SIS_IER, 0); 1720 1721 for (;;) { 1722 /* Reading the ISR register clears all interrupts. */ 1723 status = CSR_READ_4(sc, SIS_ISR); 1724 1725 if ((status & SIS_INTRS) == 0) 1726 break; 1727 1728 if (status & 1729 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | 1730 SIS_ISR_TX_IDLE) ) 1731 sis_txeof(sc); 1732 1733 if (status & 1734 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE)) 1735 sis_rxeof(sc); 1736 1737 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1738 sis_rxeoc(sc); 1739 1740 if (status & (SIS_ISR_RX_IDLE)) 1741 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1742 1743 if (status & SIS_ISR_SYSERR) { 1744 sis_reset(sc); 1745 sis_init(sc); 1746 } 1747 } 1748 1749 /* Re-enable interrupts. */ 1750 CSR_WRITE_4(sc, SIS_IER, 1); 1751 1752 if (!ifq_is_empty(&ifp->if_snd)) 1753 sis_start(ifp); 1754 } 1755 1756 /* 1757 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1758 * pointers to the fragment pointers. 1759 */ 1760 static int 1761 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1762 { 1763 struct sis_desc *f = NULL; 1764 struct mbuf *m; 1765 int frag, cur, cnt = 0; 1766 1767 /* 1768 * If there's no way we can send any packets, return now. 1769 */ 1770 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1771 return (ENOBUFS); 1772 1773 /* 1774 * Start packing the mbufs in this chain into 1775 * the fragment pointers. Stop when we run out 1776 * of fragments or hit the end of the mbuf chain. 1777 */ 1778 m = m_head; 1779 cur = frag = *txidx; 1780 1781 for (m = m_head; m != NULL; m = m->m_next) { 1782 if (m->m_len != 0) { 1783 if ((SIS_TX_LIST_CNT - 1784 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1785 return(ENOBUFS); 1786 f = &sc->sis_ldata.sis_tx_list[frag]; 1787 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1788 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1789 bus_dmamap_load(sc->sis_tag, f->sis_map, 1790 mtod(m, void *), m->m_len, 1791 sis_dma_map_desc_ptr, f, 0); 1792 bus_dmamap_sync(sc->sis_tag, f->sis_map, 1793 BUS_DMASYNC_PREREAD); 1794 if (cnt != 0) 1795 f->sis_ctl |= SIS_CMDSTS_OWN; 1796 cur = frag; 1797 SIS_INC(frag, SIS_TX_LIST_CNT); 1798 cnt++; 1799 } 1800 } 1801 1802 if (m != NULL) 1803 return(ENOBUFS); 1804 1805 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1806 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1807 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1808 sc->sis_cdata.sis_tx_cnt += cnt; 1809 *txidx = frag; 1810 1811 return(0); 1812 } 1813 1814 /* 1815 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1816 * to the mbuf data regions directly in the transmit lists. We also save a 1817 * copy of the pointers since the transmit list fragment pointers are 1818 * physical addresses. 1819 */ 1820 1821 static void 1822 sis_start(struct ifnet *ifp) 1823 { 1824 struct sis_softc *sc; 1825 struct mbuf *m_head = NULL; 1826 uint32_t idx; 1827 int need_trans; 1828 1829 sc = ifp->if_softc; 1830 1831 if (!sc->sis_link) 1832 return; 1833 1834 idx = sc->sis_cdata.sis_tx_prod; 1835 1836 if (ifp->if_flags & IFF_OACTIVE) 1837 return; 1838 1839 need_trans = 0; 1840 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1841 m_head = ifq_poll(&ifp->if_snd); 1842 if (m_head == NULL) 1843 break; 1844 1845 if (sis_encap(sc, m_head, &idx)) { 1846 ifp->if_flags |= IFF_OACTIVE; 1847 break; 1848 } 1849 ifq_dequeue(&ifp->if_snd, m_head); 1850 need_trans = 1; 1851 1852 /* 1853 * If there's a BPF listener, bounce a copy of this frame 1854 * to him. 1855 */ 1856 BPF_MTAP(ifp, m_head); 1857 } 1858 1859 if (!need_trans) 1860 return; 1861 1862 /* Transmit */ 1863 sc->sis_cdata.sis_tx_prod = idx; 1864 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1865 1866 /* 1867 * Set a timeout in case the chip goes out to lunch. 1868 */ 1869 ifp->if_timer = 5; 1870 } 1871 1872 static void 1873 sis_init(void *xsc) 1874 { 1875 struct sis_softc *sc = xsc; 1876 struct ifnet *ifp = &sc->arpcom.ac_if; 1877 struct mii_data *mii; 1878 1879 /* 1880 * Cancel pending I/O and free all RX/TX buffers. 1881 */ 1882 sis_stop(sc); 1883 1884 mii = device_get_softc(sc->sis_miibus); 1885 1886 /* Set MAC address */ 1887 if (sc->sis_type == SIS_TYPE_83815) { 1888 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1889 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1890 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1891 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1892 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1893 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1894 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1895 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1896 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1897 } else { 1898 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1899 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1900 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1901 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1902 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1903 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1904 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1905 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1906 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1907 } 1908 1909 /* Init circular RX list. */ 1910 if (sis_list_rx_init(sc) == ENOBUFS) { 1911 if_printf(ifp, "initialization failed: " 1912 "no memory for rx buffers\n"); 1913 sis_stop(sc); 1914 return; 1915 } 1916 1917 /* 1918 * Init tx descriptors. 1919 */ 1920 sis_list_tx_init(sc); 1921 1922 /* 1923 * For the NatSemi chip, we have to explicitly enable the 1924 * reception of ARP frames, as well as turn on the 'perfect 1925 * match' filter where we store the station address, otherwise 1926 * we won't receive unicasts meant for this host. 1927 */ 1928 if (sc->sis_type == SIS_TYPE_83815) { 1929 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1930 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1931 } 1932 1933 /* If we want promiscuous mode, set the allframes bit. */ 1934 if (ifp->if_flags & IFF_PROMISC) 1935 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1936 else 1937 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1938 1939 /* 1940 * Set the capture broadcast bit to capture broadcast frames. 1941 */ 1942 if (ifp->if_flags & IFF_BROADCAST) 1943 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1944 else 1945 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1946 1947 /* 1948 * Load the multicast filter. 1949 */ 1950 if (sc->sis_type == SIS_TYPE_83815) 1951 sis_setmulti_ns(sc); 1952 else 1953 sis_setmulti_sis(sc); 1954 1955 /* Turn the receive filter on */ 1956 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1957 1958 /* 1959 * Load the address of the RX and TX lists. 1960 */ 1961 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1962 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1963 1964 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1965 * the PCI bus. When this bit is set, the Max DMA Burst Size 1966 * for TX/RX DMA should be no larger than 16 double words. 1967 */ 1968 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) 1969 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1970 else 1971 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1972 1973 /* Accept Long Packets for VLAN support */ 1974 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1975 1976 /* Set TX configuration */ 1977 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1978 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1979 else 1980 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1981 1982 /* Set full/half duplex mode. */ 1983 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1984 SIS_SETBIT(sc, SIS_TX_CFG, 1985 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1986 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1987 } else { 1988 SIS_CLRBIT(sc, SIS_TX_CFG, 1989 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1990 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1991 } 1992 1993 /* 1994 * Enable interrupts. 1995 */ 1996 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1997 #ifdef DEVICE_POLLING 1998 /* 1999 * ... only enable interrupts if we are not polling, make sure 2000 * they are off otherwise. 2001 */ 2002 if (ifp->if_flags & IFF_POLLING) 2003 CSR_WRITE_4(sc, SIS_IER, 0); 2004 else 2005 #endif /* DEVICE_POLLING */ 2006 CSR_WRITE_4(sc, SIS_IER, 1); 2007 2008 /* Enable receiver and transmitter. */ 2009 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2010 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2011 2012 #ifdef notdef 2013 mii_mediachg(mii); 2014 #endif 2015 2016 /* 2017 * Page 75 of the DP83815 manual recommends the 2018 * following register settings "for optimum 2019 * performance." Note however that at least three 2020 * of the registers are listed as "reserved" in 2021 * the register map, so who knows what they do. 2022 */ 2023 if (sc->sis_type == SIS_TYPE_83815) { 2024 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2025 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2026 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2027 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2028 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2029 } 2030 2031 ifp->if_flags |= IFF_RUNNING; 2032 ifp->if_flags &= ~IFF_OACTIVE; 2033 2034 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 2035 } 2036 2037 /* 2038 * Set media options. 2039 */ 2040 static int 2041 sis_ifmedia_upd(struct ifnet *ifp) 2042 { 2043 struct sis_softc *sc; 2044 struct mii_data *mii; 2045 2046 sc = ifp->if_softc; 2047 2048 mii = device_get_softc(sc->sis_miibus); 2049 sc->sis_link = 0; 2050 if (mii->mii_instance) { 2051 struct mii_softc *miisc; 2052 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2053 mii_phy_reset(miisc); 2054 } 2055 mii_mediachg(mii); 2056 2057 return(0); 2058 } 2059 2060 /* 2061 * Report current media status. 2062 */ 2063 static void 2064 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2065 { 2066 struct sis_softc *sc; 2067 struct mii_data *mii; 2068 2069 sc = ifp->if_softc; 2070 2071 mii = device_get_softc(sc->sis_miibus); 2072 mii_pollstat(mii); 2073 ifmr->ifm_active = mii->mii_media_active; 2074 ifmr->ifm_status = mii->mii_media_status; 2075 } 2076 2077 static int 2078 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2079 { 2080 struct sis_softc *sc = ifp->if_softc; 2081 struct ifreq *ifr = (struct ifreq *) data; 2082 struct mii_data *mii; 2083 int error = 0; 2084 2085 switch(command) { 2086 case SIOCSIFFLAGS: 2087 if (ifp->if_flags & IFF_UP) { 2088 sis_init(sc); 2089 } else { 2090 if (ifp->if_flags & IFF_RUNNING) 2091 sis_stop(sc); 2092 } 2093 error = 0; 2094 break; 2095 case SIOCADDMULTI: 2096 case SIOCDELMULTI: 2097 if (sc->sis_type == SIS_TYPE_83815) 2098 sis_setmulti_ns(sc); 2099 else 2100 sis_setmulti_sis(sc); 2101 error = 0; 2102 break; 2103 case SIOCGIFMEDIA: 2104 case SIOCSIFMEDIA: 2105 mii = device_get_softc(sc->sis_miibus); 2106 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2107 break; 2108 default: 2109 error = ether_ioctl(ifp, command, data); 2110 break; 2111 } 2112 return(error); 2113 } 2114 2115 static void 2116 sis_watchdog(struct ifnet *ifp) 2117 { 2118 struct sis_softc *sc; 2119 2120 sc = ifp->if_softc; 2121 2122 ifp->if_oerrors++; 2123 if_printf(ifp, "watchdog timeout\n"); 2124 2125 sis_stop(sc); 2126 sis_reset(sc); 2127 sis_init(sc); 2128 2129 if (!ifq_is_empty(&ifp->if_snd)) 2130 sis_start(ifp); 2131 } 2132 2133 /* 2134 * Stop the adapter and free any mbufs allocated to the 2135 * RX and TX lists. 2136 */ 2137 static void 2138 sis_stop(struct sis_softc *sc) 2139 { 2140 int i; 2141 struct ifnet *ifp; 2142 2143 ifp = &sc->arpcom.ac_if; 2144 ifp->if_timer = 0; 2145 2146 callout_stop(&sc->sis_timer); 2147 2148 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2149 CSR_WRITE_4(sc, SIS_IER, 0); 2150 CSR_WRITE_4(sc, SIS_IMR, 0); 2151 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2152 DELAY(1000); 2153 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2154 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2155 2156 sc->sis_link = 0; 2157 2158 /* 2159 * Free data in the RX lists. 2160 */ 2161 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2162 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2163 bus_dmamap_unload(sc->sis_tag, 2164 sc->sis_ldata.sis_rx_list[i].sis_map); 2165 bus_dmamap_destroy(sc->sis_tag, 2166 sc->sis_ldata.sis_rx_list[i].sis_map); 2167 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2168 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2169 } 2170 } 2171 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list)); 2172 2173 /* 2174 * Free the TX list buffers. 2175 */ 2176 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2177 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2178 bus_dmamap_unload(sc->sis_tag, 2179 sc->sis_ldata.sis_tx_list[i].sis_map); 2180 bus_dmamap_destroy(sc->sis_tag, 2181 sc->sis_ldata.sis_tx_list[i].sis_map); 2182 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2183 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2184 } 2185 } 2186 2187 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list)); 2188 } 2189 2190 /* 2191 * Stop all chip I/O so that the kernel's probe routines don't 2192 * get confused by errant DMAs when rebooting. 2193 */ 2194 static void 2195 sis_shutdown(device_t dev) 2196 { 2197 struct sis_softc *sc; 2198 struct ifnet *ifp; 2199 2200 sc = device_get_softc(dev); 2201 ifp = &sc->arpcom.ac_if; 2202 lwkt_serialize_enter(ifp->if_serializer); 2203 sis_reset(sc); 2204 sis_stop(sc); 2205 lwkt_serialize_exit(ifp->if_serializer); 2206 } 2207 2208