1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.18 2005/05/24 20:59:02 dillon Exp $ 34 */ 35 36 /* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45 46 /* 47 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 48 * controller designed with flexibility and reducing CPU load in mind. 49 * The Starfire offers high and low priority buffer queues, a 50 * producer/consumer index mechanism and several different buffer 51 * queue and completion queue descriptor types. Any one of a number 52 * of different driver designs can be used, depending on system and 53 * OS requirements. This driver makes use of type0 transmit frame 54 * descriptors (since BSD fragments packets across an mbuf chain) 55 * and two RX buffer queues prioritized on size (one queue for small 56 * frames that will fit into a single mbuf, another with full size 57 * mbuf clusters for everything else). The producer/consumer indexes 58 * and completion queues are also used. 59 * 60 * One downside to the Starfire has to do with alignment: buffer 61 * queues must be aligned on 256-byte boundaries, and receive buffers 62 * must be aligned on longword boundaries. The receive buffer alignment 63 * causes problems on the Alpha platform, where the packet payload 64 * should be longword aligned. There is no simple way around this. 65 * 66 * For receive filtering, the Starfire offers 16 perfect filter slots 67 * and a 512-bit hash table. 68 * 69 * The Starfire has no internal transceiver, relying instead on an 70 * external MII-based transceiver. Accessing registers on external 71 * PHYs is done through a special register map rather than with the 72 * usual bitbang MDIO method. 73 * 74 * Acesssing the registers on the Starfire is a little tricky. The 75 * Starfire has a 512K internal register space. When programmed for 76 * PCI memory mapped mode, the entire register space can be accessed 77 * directly. However in I/O space mode, only 256 bytes are directly 78 * mapped into PCI I/O space. The other registers can be accessed 79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 80 * registers inside the 256-byte I/O window. 81 */ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/socket.h> 90 91 #include <net/if.h> 92 #include <net/ifq_var.h> 93 #include <net/if_arp.h> 94 #include <net/ethernet.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 98 #include <net/bpf.h> 99 100 #include <vm/vm.h> /* for vtophys */ 101 #include <vm/pmap.h> /* for vtophys */ 102 #include <machine/clock.h> /* for DELAY */ 103 #include <machine/bus_pio.h> 104 #include <machine/bus_memio.h> 105 #include <machine/bus.h> 106 #include <machine/resource.h> 107 #include <sys/bus.h> 108 #include <sys/rman.h> 109 110 #include "../mii_layer/mii.h" 111 #include "../mii_layer/miivar.h" 112 113 /* "controller miibus0" required. See GENERIC if you get errors here. */ 114 #include "miibus_if.h" 115 116 #include <bus/pci/pcireg.h> 117 #include <bus/pci/pcivar.h> 118 119 #define SF_USEIOSPACE 120 121 #include "if_sfreg.h" 122 123 static struct sf_type sf_devs[] = { 124 { AD_VENDORID, AD_DEVICEID_STARFIRE, 125 "Adaptec AIC-6915 10/100BaseTX" }, 126 { 0, 0, NULL } 127 }; 128 129 static int sf_probe (device_t); 130 static int sf_attach (device_t); 131 static int sf_detach (device_t); 132 static void sf_intr (void *); 133 static void sf_stats_update (void *); 134 static void sf_rxeof (struct sf_softc *); 135 static void sf_txeof (struct sf_softc *); 136 static int sf_encap (struct sf_softc *, 137 struct sf_tx_bufdesc_type0 *, 138 struct mbuf *); 139 static void sf_start (struct ifnet *); 140 static int sf_ioctl (struct ifnet *, u_long, caddr_t, 141 struct ucred *); 142 static void sf_init (void *); 143 static void sf_stop (struct sf_softc *); 144 static void sf_watchdog (struct ifnet *); 145 static void sf_shutdown (device_t); 146 static int sf_ifmedia_upd (struct ifnet *); 147 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148 static void sf_reset (struct sf_softc *); 149 static int sf_init_rx_ring (struct sf_softc *); 150 static void sf_init_tx_ring (struct sf_softc *); 151 static int sf_newbuf (struct sf_softc *, 152 struct sf_rx_bufdesc_type0 *, 153 struct mbuf *); 154 static void sf_setmulti (struct sf_softc *); 155 static int sf_setperf (struct sf_softc *, int, caddr_t); 156 static int sf_sethash (struct sf_softc *, caddr_t, int); 157 #ifdef notdef 158 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 159 #endif 160 161 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 162 static u_int32_t sf_calchash (caddr_t); 163 164 static int sf_miibus_readreg (device_t, int, int); 165 static int sf_miibus_writereg (device_t, int, int, int); 166 static void sf_miibus_statchg (device_t); 167 168 static u_int32_t csr_read_4 (struct sf_softc *, int); 169 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 170 static void sf_txthresh_adjust (struct sf_softc *); 171 172 #ifdef SF_USEIOSPACE 173 #define SF_RES SYS_RES_IOPORT 174 #define SF_RID SF_PCI_LOIO 175 #else 176 #define SF_RES SYS_RES_MEMORY 177 #define SF_RID SF_PCI_LOMEM 178 #endif 179 180 static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197 }; 198 199 static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203 }; 204 205 static devclass_t sf_devclass; 206 207 DECLARE_DUMMY_MODULE(if_sf); 208 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 209 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 210 211 #define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 213 214 #define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 216 217 static u_int32_t csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220 { 221 u_int32_t val; 222 223 #ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226 #else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228 #endif 229 230 return(val); 231 } 232 233 static u_int8_t sf_read_eeprom(sc, reg) 234 struct sf_softc *sc; 235 int reg; 236 { 237 u_int8_t val; 238 239 val = (csr_read_4(sc, SF_EEADDR_BASE + 240 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 241 242 return(val); 243 } 244 245 static void csr_write_4(sc, reg, val) 246 struct sf_softc *sc; 247 int reg; 248 u_int32_t val; 249 { 250 #ifdef SF_USEIOSPACE 251 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 252 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 253 #else 254 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 255 #endif 256 return; 257 } 258 259 static u_int32_t sf_calchash(addr) 260 caddr_t addr; 261 { 262 u_int32_t crc, carry; 263 int i, j; 264 u_int8_t c; 265 266 /* Compute CRC for the address value. */ 267 crc = 0xFFFFFFFF; /* initial value */ 268 269 for (i = 0; i < 6; i++) { 270 c = *(addr + i); 271 for (j = 0; j < 8; j++) { 272 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 273 crc <<= 1; 274 c >>= 1; 275 if (carry) 276 crc = (crc ^ 0x04c11db6) | carry; 277 } 278 } 279 280 /* return the filter bit position */ 281 return(crc >> 23 & 0x1FF); 282 } 283 284 /* 285 * Copy the address 'mac' into the perfect RX filter entry at 286 * offset 'idx.' The perfect filter only has 16 entries so do 287 * some sanity tests. 288 */ 289 static int sf_setperf(sc, idx, mac) 290 struct sf_softc *sc; 291 int idx; 292 caddr_t mac; 293 { 294 u_int16_t *p; 295 296 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 297 return(EINVAL); 298 299 if (mac == NULL) 300 return(EINVAL); 301 302 p = (u_int16_t *)mac; 303 304 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 305 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 310 311 return(0); 312 } 313 314 /* 315 * Set the bit in the 512-bit hash table that corresponds to the 316 * specified mac address 'mac.' If 'prio' is nonzero, update the 317 * priority hash table instead of the filter hash table. 318 */ 319 static int sf_sethash(sc, mac, prio) 320 struct sf_softc *sc; 321 caddr_t mac; 322 int prio; 323 { 324 u_int32_t h = 0; 325 326 if (mac == NULL) 327 return(EINVAL); 328 329 h = sf_calchash(mac); 330 331 if (prio) { 332 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 333 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 334 } else { 335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 337 } 338 339 return(0); 340 } 341 342 #ifdef notdef 343 /* 344 * Set a VLAN tag in the receive filter. 345 */ 346 static int sf_setvlan(sc, idx, vlan) 347 struct sf_softc *sc; 348 int idx; 349 u_int32_t vlan; 350 { 351 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 352 return(EINVAL); 353 354 csr_write_4(sc, SF_RXFILT_HASH_BASE + 355 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 356 357 return(0); 358 } 359 #endif 360 361 static int sf_miibus_readreg(dev, phy, reg) 362 device_t dev; 363 int phy, reg; 364 { 365 struct sf_softc *sc; 366 int i; 367 u_int32_t val = 0; 368 369 sc = device_get_softc(dev); 370 371 for (i = 0; i < SF_TIMEOUT; i++) { 372 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 373 if (val & SF_MII_DATAVALID) 374 break; 375 } 376 377 if (i == SF_TIMEOUT) 378 return(0); 379 380 if ((val & 0x0000FFFF) == 0xFFFF) 381 return(0); 382 383 return(val & 0x0000FFFF); 384 } 385 386 static int sf_miibus_writereg(dev, phy, reg, val) 387 device_t dev; 388 int phy, reg, val; 389 { 390 struct sf_softc *sc; 391 int i; 392 int busy; 393 394 sc = device_get_softc(dev); 395 396 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 397 398 for (i = 0; i < SF_TIMEOUT; i++) { 399 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 400 if (!(busy & SF_MII_BUSY)) 401 break; 402 } 403 404 return(0); 405 } 406 407 static void sf_miibus_statchg(dev) 408 device_t dev; 409 { 410 struct sf_softc *sc; 411 struct mii_data *mii; 412 413 sc = device_get_softc(dev); 414 mii = device_get_softc(sc->sf_miibus); 415 416 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 417 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 418 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 419 } else { 420 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 421 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 422 } 423 424 return; 425 } 426 427 static void sf_setmulti(sc) 428 struct sf_softc *sc; 429 { 430 struct ifnet *ifp; 431 int i; 432 struct ifmultiaddr *ifma; 433 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 434 435 ifp = &sc->arpcom.ac_if; 436 437 /* First zot all the existing filters. */ 438 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 439 sf_setperf(sc, i, (char *)&dummy); 440 for (i = SF_RXFILT_HASH_BASE; 441 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 442 csr_write_4(sc, i, 0); 443 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 444 445 /* Now program new ones. */ 446 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 447 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 448 } else { 449 i = 1; 450 /* First find the tail of the list. */ 451 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 452 ifma = ifma->ifma_link.le_next) { 453 if (ifma->ifma_link.le_next == NULL) 454 break; 455 } 456 /* Now traverse the list backwards. */ 457 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 458 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 459 if (ifma->ifma_addr->sa_family != AF_LINK) 460 continue; 461 /* 462 * Program the first 15 multicast groups 463 * into the perfect filter. For all others, 464 * use the hash table. 465 */ 466 if (i < SF_RXFILT_PERFECT_CNT) { 467 sf_setperf(sc, i, 468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 469 i++; 470 continue; 471 } 472 473 sf_sethash(sc, 474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 475 } 476 } 477 478 return; 479 } 480 481 /* 482 * Set media options. 483 */ 484 static int sf_ifmedia_upd(ifp) 485 struct ifnet *ifp; 486 { 487 struct sf_softc *sc; 488 struct mii_data *mii; 489 490 sc = ifp->if_softc; 491 mii = device_get_softc(sc->sf_miibus); 492 sc->sf_link = 0; 493 if (mii->mii_instance) { 494 struct mii_softc *miisc; 495 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 496 miisc = LIST_NEXT(miisc, mii_list)) 497 mii_phy_reset(miisc); 498 } 499 mii_mediachg(mii); 500 501 return(0); 502 } 503 504 /* 505 * Report current media status. 506 */ 507 static void sf_ifmedia_sts(ifp, ifmr) 508 struct ifnet *ifp; 509 struct ifmediareq *ifmr; 510 { 511 struct sf_softc *sc; 512 struct mii_data *mii; 513 514 sc = ifp->if_softc; 515 mii = device_get_softc(sc->sf_miibus); 516 517 mii_pollstat(mii); 518 ifmr->ifm_active = mii->mii_media_active; 519 ifmr->ifm_status = mii->mii_media_status; 520 521 return; 522 } 523 524 static int sf_ioctl(ifp, command, data, cr) 525 struct ifnet *ifp; 526 u_long command; 527 caddr_t data; 528 struct ucred *cr; 529 { 530 struct sf_softc *sc = ifp->if_softc; 531 struct ifreq *ifr = (struct ifreq *) data; 532 struct mii_data *mii; 533 int s, error = 0; 534 535 s = splimp(); 536 537 switch(command) { 538 case SIOCSIFADDR: 539 case SIOCGIFADDR: 540 case SIOCSIFMTU: 541 error = ether_ioctl(ifp, command, data); 542 break; 543 case SIOCSIFFLAGS: 544 if (ifp->if_flags & IFF_UP) { 545 if (ifp->if_flags & IFF_RUNNING && 546 ifp->if_flags & IFF_PROMISC && 547 !(sc->sf_if_flags & IFF_PROMISC)) { 548 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 549 } else if (ifp->if_flags & IFF_RUNNING && 550 !(ifp->if_flags & IFF_PROMISC) && 551 sc->sf_if_flags & IFF_PROMISC) { 552 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 553 } else if (!(ifp->if_flags & IFF_RUNNING)) 554 sf_init(sc); 555 } else { 556 if (ifp->if_flags & IFF_RUNNING) 557 sf_stop(sc); 558 } 559 sc->sf_if_flags = ifp->if_flags; 560 error = 0; 561 break; 562 case SIOCADDMULTI: 563 case SIOCDELMULTI: 564 sf_setmulti(sc); 565 error = 0; 566 break; 567 case SIOCGIFMEDIA: 568 case SIOCSIFMEDIA: 569 mii = device_get_softc(sc->sf_miibus); 570 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 571 break; 572 default: 573 error = EINVAL; 574 break; 575 } 576 577 (void)splx(s); 578 579 return(error); 580 } 581 582 static void sf_reset(sc) 583 struct sf_softc *sc; 584 { 585 int i; 586 587 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 588 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 589 DELAY(1000); 590 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 591 592 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 593 594 for (i = 0; i < SF_TIMEOUT; i++) { 595 DELAY(10); 596 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 597 break; 598 } 599 600 if (i == SF_TIMEOUT) 601 printf("sf%d: reset never completed!\n", sc->sf_unit); 602 603 /* Wait a little while for the chip to get its brains in order. */ 604 DELAY(1000); 605 return; 606 } 607 608 /* 609 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 610 * IDs against our list and return a device name if we find a match. 611 * We also check the subsystem ID so that we can identify exactly which 612 * NIC has been found, if possible. 613 */ 614 static int sf_probe(dev) 615 device_t dev; 616 { 617 struct sf_type *t; 618 619 t = sf_devs; 620 621 while(t->sf_name != NULL) { 622 if ((pci_get_vendor(dev) == t->sf_vid) && 623 (pci_get_device(dev) == t->sf_did)) { 624 switch((pci_read_config(dev, 625 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 626 case AD_SUBSYSID_62011_REV0: 627 case AD_SUBSYSID_62011_REV1: 628 device_set_desc(dev, 629 "Adaptec ANA-62011 10/100BaseTX"); 630 return(0); 631 break; 632 case AD_SUBSYSID_62022: 633 device_set_desc(dev, 634 "Adaptec ANA-62022 10/100BaseTX"); 635 return(0); 636 break; 637 case AD_SUBSYSID_62044_REV0: 638 case AD_SUBSYSID_62044_REV1: 639 device_set_desc(dev, 640 "Adaptec ANA-62044 10/100BaseTX"); 641 return(0); 642 break; 643 case AD_SUBSYSID_62020: 644 device_set_desc(dev, 645 "Adaptec ANA-62020 10/100BaseFX"); 646 return(0); 647 break; 648 case AD_SUBSYSID_69011: 649 device_set_desc(dev, 650 "Adaptec ANA-69011 10/100BaseTX"); 651 return(0); 652 break; 653 default: 654 device_set_desc(dev, t->sf_name); 655 return(0); 656 break; 657 } 658 } 659 t++; 660 } 661 662 return(ENXIO); 663 } 664 665 /* 666 * Attach the interface. Allocate softc structures, do ifmedia 667 * setup and ethernet/BPF attach. 668 */ 669 static int sf_attach(dev) 670 device_t dev; 671 { 672 int s, i; 673 u_int32_t command; 674 struct sf_softc *sc; 675 struct ifnet *ifp; 676 int unit, rid, error = 0; 677 678 s = splimp(); 679 680 sc = device_get_softc(dev); 681 unit = device_get_unit(dev); 682 bzero(sc, sizeof(struct sf_softc)); 683 684 /* 685 * Handle power management nonsense. 686 */ 687 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 688 if (command == 0x01) { 689 690 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 691 if (command & SF_PSTATE_MASK) { 692 u_int32_t iobase, membase, irq; 693 694 /* Save important PCI config data. */ 695 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 696 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 697 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 698 699 /* Reset the power state. */ 700 printf("sf%d: chip is in D%d power mode " 701 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 702 command &= 0xFFFFFFFC; 703 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 704 705 /* Restore PCI config data. */ 706 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 707 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 708 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 709 } 710 } 711 712 /* 713 * Map control/status registers. 714 */ 715 command = pci_read_config(dev, PCIR_COMMAND, 4); 716 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 717 pci_write_config(dev, PCIR_COMMAND, command, 4); 718 command = pci_read_config(dev, PCIR_COMMAND, 4); 719 720 #ifdef SF_USEIOSPACE 721 if (!(command & PCIM_CMD_PORTEN)) { 722 printf("sf%d: failed to enable I/O ports!\n", unit); 723 error = ENXIO; 724 goto fail; 725 } 726 #else 727 if (!(command & PCIM_CMD_MEMEN)) { 728 printf("sf%d: failed to enable memory mapping!\n", unit); 729 error = ENXIO; 730 goto fail; 731 } 732 #endif 733 734 rid = SF_RID; 735 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 736 737 if (sc->sf_res == NULL) { 738 printf ("sf%d: couldn't map ports\n", unit); 739 error = ENXIO; 740 goto fail; 741 } 742 743 sc->sf_btag = rman_get_bustag(sc->sf_res); 744 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 745 746 /* Allocate interrupt */ 747 rid = 0; 748 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 749 RF_SHAREABLE | RF_ACTIVE); 750 751 if (sc->sf_irq == NULL) { 752 printf("sf%d: couldn't map interrupt\n", unit); 753 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 754 error = ENXIO; 755 goto fail; 756 } 757 758 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 759 sf_intr, sc, &sc->sf_intrhand, NULL); 760 761 if (error) { 762 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 763 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 764 printf("sf%d: couldn't set up irq\n", unit); 765 goto fail; 766 } 767 768 callout_init(&sc->sf_stat_timer); 769 770 /* Reset the adapter. */ 771 sf_reset(sc); 772 773 /* 774 * Get station address from the EEPROM. 775 */ 776 for (i = 0; i < ETHER_ADDR_LEN; i++) 777 sc->arpcom.ac_enaddr[i] = 778 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 779 780 sc->sf_unit = unit; 781 782 /* Allocate the descriptor queues. */ 783 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 784 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 785 786 if (sc->sf_ldata == NULL) { 787 printf("sf%d: no memory for list buffers!\n", unit); 788 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 789 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 790 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 791 error = ENXIO; 792 goto fail; 793 } 794 795 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 796 797 /* Do MII setup. */ 798 if (mii_phy_probe(dev, &sc->sf_miibus, 799 sf_ifmedia_upd, sf_ifmedia_sts)) { 800 printf("sf%d: MII without any phy!\n", sc->sf_unit); 801 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 802 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 803 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 804 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 805 error = ENXIO; 806 goto fail; 807 } 808 809 ifp = &sc->arpcom.ac_if; 810 ifp->if_softc = sc; 811 if_initname(ifp, "sf", unit); 812 ifp->if_mtu = ETHERMTU; 813 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 814 ifp->if_ioctl = sf_ioctl; 815 ifp->if_start = sf_start; 816 ifp->if_watchdog = sf_watchdog; 817 ifp->if_init = sf_init; 818 ifp->if_baudrate = 10000000; 819 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 820 ifq_set_ready(&ifp->if_snd); 821 822 /* 823 * Call MI attach routine. 824 */ 825 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 826 827 fail: 828 splx(s); 829 return(error); 830 } 831 832 static int sf_detach(dev) 833 device_t dev; 834 { 835 struct sf_softc *sc; 836 struct ifnet *ifp; 837 int s; 838 839 s = splimp(); 840 841 sc = device_get_softc(dev); 842 ifp = &sc->arpcom.ac_if; 843 844 ether_ifdetach(ifp); 845 sf_stop(sc); 846 847 bus_generic_detach(dev); 848 device_delete_child(dev, sc->sf_miibus); 849 850 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 851 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 852 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 853 854 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 855 856 splx(s); 857 858 return(0); 859 } 860 861 static int sf_init_rx_ring(sc) 862 struct sf_softc *sc; 863 { 864 struct sf_list_data *ld; 865 int i; 866 867 ld = sc->sf_ldata; 868 869 bzero((char *)ld->sf_rx_dlist_big, 870 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 871 bzero((char *)ld->sf_rx_clist, 872 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 873 874 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 875 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 876 return(ENOBUFS); 877 } 878 879 return(0); 880 } 881 882 static void sf_init_tx_ring(sc) 883 struct sf_softc *sc; 884 { 885 struct sf_list_data *ld; 886 int i; 887 888 ld = sc->sf_ldata; 889 890 bzero((char *)ld->sf_tx_dlist, 891 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 892 bzero((char *)ld->sf_tx_clist, 893 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 894 895 for (i = 0; i < SF_TX_DLIST_CNT; i++) 896 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 897 for (i = 0; i < SF_TX_CLIST_CNT; i++) 898 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 899 900 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 901 sc->sf_tx_cnt = 0; 902 903 return; 904 } 905 906 static int sf_newbuf(sc, c, m) 907 struct sf_softc *sc; 908 struct sf_rx_bufdesc_type0 *c; 909 struct mbuf *m; 910 { 911 struct mbuf *m_new = NULL; 912 913 if (m == NULL) { 914 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 915 if (m_new == NULL) 916 return(ENOBUFS); 917 918 MCLGET(m_new, MB_DONTWAIT); 919 if (!(m_new->m_flags & M_EXT)) { 920 m_freem(m_new); 921 return(ENOBUFS); 922 } 923 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 924 } else { 925 m_new = m; 926 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 927 m_new->m_data = m_new->m_ext.ext_buf; 928 } 929 930 m_adj(m_new, sizeof(u_int64_t)); 931 932 c->sf_mbuf = m_new; 933 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 934 c->sf_valid = 1; 935 936 return(0); 937 } 938 939 /* 940 * The starfire is programmed to use 'normal' mode for packet reception, 941 * which means we use the consumer/producer model for both the buffer 942 * descriptor queue and the completion descriptor queue. The only problem 943 * with this is that it involves a lot of register accesses: we have to 944 * read the RX completion consumer and producer indexes and the RX buffer 945 * producer index, plus the RX completion consumer and RX buffer producer 946 * indexes have to be updated. It would have been easier if Adaptec had 947 * put each index in a separate register, especially given that the damn 948 * NIC has a 512K register space. 949 * 950 * In spite of all the lovely features that Adaptec crammed into the 6915, 951 * it is marred by one truly stupid design flaw, which is that receive 952 * buffer addresses must be aligned on a longword boundary. This forces 953 * the packet payload to be unaligned, which is suboptimal on the x86 and 954 * completely unuseable on the Alpha. Our only recourse is to copy received 955 * packets into properly aligned buffers before handing them off. 956 */ 957 958 static void sf_rxeof(sc) 959 struct sf_softc *sc; 960 { 961 struct mbuf *m; 962 struct ifnet *ifp; 963 struct sf_rx_bufdesc_type0 *desc; 964 struct sf_rx_cmpdesc_type3 *cur_rx; 965 u_int32_t rxcons, rxprod; 966 int cmpprodidx, cmpconsidx, bufprodidx; 967 968 ifp = &sc->arpcom.ac_if; 969 970 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 971 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 972 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 973 cmpconsidx = SF_IDX_LO(rxcons); 974 bufprodidx = SF_IDX_LO(rxprod); 975 976 while (cmpconsidx != cmpprodidx) { 977 struct mbuf *m0; 978 979 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 980 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 981 m = desc->sf_mbuf; 982 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 983 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 984 985 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 986 ifp->if_ierrors++; 987 sf_newbuf(sc, desc, m); 988 continue; 989 } 990 991 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 992 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 993 sf_newbuf(sc, desc, m); 994 if (m0 == NULL) { 995 ifp->if_ierrors++; 996 continue; 997 } 998 m_adj(m0, ETHER_ALIGN); 999 m = m0; 1000 1001 ifp->if_ipackets++; 1002 1003 (*ifp->if_input)(ifp, m); 1004 } 1005 1006 csr_write_4(sc, SF_CQ_CONSIDX, 1007 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1008 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1009 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1010 1011 return; 1012 } 1013 1014 /* 1015 * Read the transmit status from the completion queue and release 1016 * mbufs. Note that the buffer descriptor index in the completion 1017 * descriptor is an offset from the start of the transmit buffer 1018 * descriptor list in bytes. This is important because the manual 1019 * gives the impression that it should match the producer/consumer 1020 * index, which is the offset in 8 byte blocks. 1021 */ 1022 static void sf_txeof(sc) 1023 struct sf_softc *sc; 1024 { 1025 int txcons, cmpprodidx, cmpconsidx; 1026 struct sf_tx_cmpdesc_type1 *cur_cmp; 1027 struct sf_tx_bufdesc_type0 *cur_tx; 1028 struct ifnet *ifp; 1029 1030 ifp = &sc->arpcom.ac_if; 1031 1032 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1033 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1034 cmpconsidx = SF_IDX_HI(txcons); 1035 1036 while (cmpconsidx != cmpprodidx) { 1037 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1038 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1039 1040 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1041 ifp->if_opackets++; 1042 else { 1043 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1044 sf_txthresh_adjust(sc); 1045 ifp->if_oerrors++; 1046 } 1047 1048 sc->sf_tx_cnt--; 1049 if (cur_tx->sf_mbuf != NULL) { 1050 m_freem(cur_tx->sf_mbuf); 1051 cur_tx->sf_mbuf = NULL; 1052 } else 1053 break; 1054 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1055 } 1056 1057 ifp->if_timer = 0; 1058 ifp->if_flags &= ~IFF_OACTIVE; 1059 1060 csr_write_4(sc, SF_CQ_CONSIDX, 1061 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1062 ((cmpconsidx << 16) & 0xFFFF0000)); 1063 1064 return; 1065 } 1066 1067 static void sf_txthresh_adjust(sc) 1068 struct sf_softc *sc; 1069 { 1070 u_int32_t txfctl; 1071 u_int8_t txthresh; 1072 1073 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1074 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1075 if (txthresh < 0xFF) { 1076 txthresh++; 1077 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1078 txfctl |= txthresh; 1079 #ifdef DIAGNOSTIC 1080 printf("sf%d: tx underrun, increasing " 1081 "tx threshold to %d bytes\n", 1082 sc->sf_unit, txthresh * 4); 1083 #endif 1084 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1085 } 1086 1087 return; 1088 } 1089 1090 static void sf_intr(arg) 1091 void *arg; 1092 { 1093 struct sf_softc *sc; 1094 struct ifnet *ifp; 1095 u_int32_t status; 1096 1097 sc = arg; 1098 ifp = &sc->arpcom.ac_if; 1099 1100 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1101 return; 1102 1103 /* Disable interrupts. */ 1104 csr_write_4(sc, SF_IMR, 0x00000000); 1105 1106 for (;;) { 1107 status = csr_read_4(sc, SF_ISR); 1108 if (status) 1109 csr_write_4(sc, SF_ISR, status); 1110 1111 if (!(status & SF_INTRS)) 1112 break; 1113 1114 if (status & SF_ISR_RXDQ1_DMADONE) 1115 sf_rxeof(sc); 1116 1117 if (status & SF_ISR_TX_TXDONE || 1118 status & SF_ISR_TX_DMADONE || 1119 status & SF_ISR_TX_QUEUEDONE) 1120 sf_txeof(sc); 1121 1122 if (status & SF_ISR_TX_LOFIFO) 1123 sf_txthresh_adjust(sc); 1124 1125 if (status & SF_ISR_ABNORMALINTR) { 1126 if (status & SF_ISR_STATSOFLOW) { 1127 callout_stop(&sc->sf_stat_timer); 1128 sf_stats_update(sc); 1129 } else 1130 sf_init(sc); 1131 } 1132 } 1133 1134 /* Re-enable interrupts. */ 1135 csr_write_4(sc, SF_IMR, SF_INTRS); 1136 1137 if (!ifq_is_empty(&ifp->if_snd)) 1138 sf_start(ifp); 1139 1140 return; 1141 } 1142 1143 static void sf_init(xsc) 1144 void *xsc; 1145 { 1146 struct sf_softc *sc; 1147 struct ifnet *ifp; 1148 struct mii_data *mii; 1149 int i, s; 1150 1151 s = splimp(); 1152 1153 sc = xsc; 1154 ifp = &sc->arpcom.ac_if; 1155 mii = device_get_softc(sc->sf_miibus); 1156 1157 sf_stop(sc); 1158 sf_reset(sc); 1159 1160 /* Init all the receive filter registers */ 1161 for (i = SF_RXFILT_PERFECT_BASE; 1162 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1163 csr_write_4(sc, i, 0); 1164 1165 /* Empty stats counter registers. */ 1166 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1167 csr_write_4(sc, SF_STATS_BASE + 1168 (i + sizeof(u_int32_t)), 0); 1169 1170 /* Init our MAC address */ 1171 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1172 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1173 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1174 1175 if (sf_init_rx_ring(sc) == ENOBUFS) { 1176 printf("sf%d: initialization failed: no " 1177 "memory for rx buffers\n", sc->sf_unit); 1178 (void)splx(s); 1179 return; 1180 } 1181 1182 sf_init_tx_ring(sc); 1183 1184 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1185 1186 /* If we want promiscuous mode, set the allframes bit. */ 1187 if (ifp->if_flags & IFF_PROMISC) { 1188 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1189 } else { 1190 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1191 } 1192 1193 if (ifp->if_flags & IFF_BROADCAST) { 1194 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1195 } else { 1196 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1197 } 1198 1199 /* 1200 * Load the multicast filter. 1201 */ 1202 sf_setmulti(sc); 1203 1204 /* Init the completion queue indexes */ 1205 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1206 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1207 1208 /* Init the RX completion queue */ 1209 csr_write_4(sc, SF_RXCQ_CTL_1, 1210 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1211 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1212 1213 /* Init RX DMA control. */ 1214 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1215 1216 /* Init the RX buffer descriptor queue. */ 1217 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1218 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1219 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1220 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1221 1222 /* Init the TX completion queue */ 1223 csr_write_4(sc, SF_TXCQ_CTL, 1224 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1225 1226 /* Init the TX buffer descriptor queue. */ 1227 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1228 vtophys(sc->sf_ldata->sf_tx_dlist)); 1229 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1230 csr_write_4(sc, SF_TXDQ_CTL, 1231 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1232 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1233 1234 /* Enable autopadding of short TX frames. */ 1235 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1236 1237 /* Enable interrupts. */ 1238 csr_write_4(sc, SF_IMR, SF_INTRS); 1239 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1240 1241 /* Enable the RX and TX engines. */ 1242 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1243 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1244 1245 /*mii_mediachg(mii);*/ 1246 sf_ifmedia_upd(ifp); 1247 1248 ifp->if_flags |= IFF_RUNNING; 1249 ifp->if_flags &= ~IFF_OACTIVE; 1250 1251 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1252 1253 splx(s); 1254 1255 return; 1256 } 1257 1258 static int sf_encap(sc, c, m_head) 1259 struct sf_softc *sc; 1260 struct sf_tx_bufdesc_type0 *c; 1261 struct mbuf *m_head; 1262 { 1263 int frag = 0; 1264 struct sf_frag *f = NULL; 1265 struct mbuf *m; 1266 1267 m = m_head; 1268 1269 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1270 if (m->m_len != 0) { 1271 if (frag == SF_MAXFRAGS) 1272 break; 1273 f = &c->sf_frags[frag]; 1274 if (frag == 0) 1275 f->sf_pktlen = m_head->m_pkthdr.len; 1276 f->sf_fraglen = m->m_len; 1277 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1278 frag++; 1279 } 1280 } 1281 1282 if (m != NULL) { 1283 struct mbuf *m_new = NULL; 1284 1285 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1286 if (m_new == NULL) { 1287 printf("sf%d: no memory for tx list", sc->sf_unit); 1288 return(1); 1289 } 1290 1291 if (m_head->m_pkthdr.len > MHLEN) { 1292 MCLGET(m_new, MB_DONTWAIT); 1293 if (!(m_new->m_flags & M_EXT)) { 1294 m_freem(m_new); 1295 printf("sf%d: no memory for tx list", 1296 sc->sf_unit); 1297 return(1); 1298 } 1299 } 1300 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1301 mtod(m_new, caddr_t)); 1302 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1303 m_freem(m_head); 1304 m_head = m_new; 1305 f = &c->sf_frags[0]; 1306 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1307 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1308 frag = 1; 1309 } 1310 1311 c->sf_mbuf = m_head; 1312 c->sf_id = SF_TX_BUFDESC_ID; 1313 c->sf_fragcnt = frag; 1314 c->sf_intr = 1; 1315 c->sf_caltcp = 0; 1316 c->sf_crcen = 1; 1317 1318 return(0); 1319 } 1320 1321 static void sf_start(ifp) 1322 struct ifnet *ifp; 1323 { 1324 struct sf_softc *sc; 1325 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1326 struct mbuf *m_head = NULL; 1327 int i, txprod; 1328 1329 sc = ifp->if_softc; 1330 1331 if (!sc->sf_link) 1332 return; 1333 1334 if (ifp->if_flags & IFF_OACTIVE) 1335 return; 1336 1337 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1338 i = SF_IDX_HI(txprod) >> 4; 1339 1340 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1341 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1342 sf_init(sc); 1343 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1344 i = SF_IDX_HI(txprod) >> 4; 1345 } 1346 1347 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1348 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1349 ifp->if_flags |= IFF_OACTIVE; 1350 cur_tx = NULL; 1351 break; 1352 } 1353 m_head = ifq_poll(&ifp->if_snd); 1354 if (m_head == NULL) 1355 break; 1356 1357 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1358 if (sf_encap(sc, cur_tx, m_head)) { 1359 ifp->if_flags |= IFF_OACTIVE; 1360 cur_tx = NULL; 1361 break; 1362 } 1363 ifq_dequeue(&ifp->if_snd); 1364 BPF_MTAP(ifp, cur_tx->sf_mbuf); 1365 1366 SF_INC(i, SF_TX_DLIST_CNT); 1367 sc->sf_tx_cnt++; 1368 /* 1369 * Don't get the TX DMA queue get too full. 1370 */ 1371 if (sc->sf_tx_cnt > 64) 1372 break; 1373 } 1374 1375 if (cur_tx == NULL) 1376 return; 1377 1378 /* Transmit */ 1379 csr_write_4(sc, SF_TXDQ_PRODIDX, 1380 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1381 ((i << 20) & 0xFFFF0000)); 1382 1383 ifp->if_timer = 5; 1384 1385 return; 1386 } 1387 1388 static void sf_stop(sc) 1389 struct sf_softc *sc; 1390 { 1391 int i; 1392 struct ifnet *ifp; 1393 1394 ifp = &sc->arpcom.ac_if; 1395 1396 callout_stop(&sc->sf_stat_timer); 1397 1398 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1399 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1400 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1401 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1402 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1403 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1404 csr_write_4(sc, SF_TXCQ_CTL, 0); 1405 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1406 csr_write_4(sc, SF_TXDQ_CTL, 0); 1407 sf_reset(sc); 1408 1409 sc->sf_link = 0; 1410 1411 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1412 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1413 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1414 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1415 } 1416 } 1417 1418 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1419 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1420 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1421 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1422 } 1423 } 1424 1425 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1426 1427 return; 1428 } 1429 1430 /* 1431 * Note: it is important that this function not be interrupted. We 1432 * use a two-stage register access scheme: if we are interrupted in 1433 * between setting the indirect address register and reading from the 1434 * indirect data register, the contents of the address register could 1435 * be changed out from under us. 1436 */ 1437 static void sf_stats_update(xsc) 1438 void *xsc; 1439 { 1440 struct sf_softc *sc; 1441 struct ifnet *ifp; 1442 struct mii_data *mii; 1443 struct sf_stats stats; 1444 u_int32_t *ptr; 1445 int i, s; 1446 1447 s = splimp(); 1448 1449 sc = xsc; 1450 ifp = &sc->arpcom.ac_if; 1451 mii = device_get_softc(sc->sf_miibus); 1452 1453 ptr = (u_int32_t *)&stats; 1454 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1455 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1456 (i + sizeof(u_int32_t))); 1457 1458 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1459 csr_write_4(sc, SF_STATS_BASE + 1460 (i + sizeof(u_int32_t)), 0); 1461 1462 ifp->if_collisions += stats.sf_tx_single_colls + 1463 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1464 1465 mii_tick(mii); 1466 if (!sc->sf_link) { 1467 mii_pollstat(mii); 1468 if (mii->mii_media_status & IFM_ACTIVE && 1469 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1470 sc->sf_link++; 1471 if (!ifq_is_empty(&ifp->if_snd)) 1472 sf_start(ifp); 1473 } 1474 1475 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1476 1477 splx(s); 1478 1479 return; 1480 } 1481 1482 static void sf_watchdog(ifp) 1483 struct ifnet *ifp; 1484 { 1485 struct sf_softc *sc; 1486 1487 sc = ifp->if_softc; 1488 1489 ifp->if_oerrors++; 1490 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1491 1492 sf_stop(sc); 1493 sf_reset(sc); 1494 sf_init(sc); 1495 1496 if (!ifq_is_empty(&ifp->if_snd)) 1497 sf_start(ifp); 1498 1499 return; 1500 } 1501 1502 static void sf_shutdown(dev) 1503 device_t dev; 1504 { 1505 struct sf_softc *sc; 1506 1507 sc = device_get_softc(dev); 1508 1509 sf_stop(sc); 1510 1511 return; 1512 } 1513