1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.15 2005/02/20 05:44:34 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 36 */ 37 38 /* 39 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 40 * Programming manual is available from: 41 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Department of Electical Engineering 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 50 * controller designed with flexibility and reducing CPU load in mind. 51 * The Starfire offers high and low priority buffer queues, a 52 * producer/consumer index mechanism and several different buffer 53 * queue and completion queue descriptor types. Any one of a number 54 * of different driver designs can be used, depending on system and 55 * OS requirements. This driver makes use of type0 transmit frame 56 * descriptors (since BSD fragments packets across an mbuf chain) 57 * and two RX buffer queues prioritized on size (one queue for small 58 * frames that will fit into a single mbuf, another with full size 59 * mbuf clusters for everything else). The producer/consumer indexes 60 * and completion queues are also used. 61 * 62 * One downside to the Starfire has to do with alignment: buffer 63 * queues must be aligned on 256-byte boundaries, and receive buffers 64 * must be aligned on longword boundaries. The receive buffer alignment 65 * causes problems on the Alpha platform, where the packet payload 66 * should be longword aligned. There is no simple way around this. 67 * 68 * For receive filtering, the Starfire offers 16 perfect filter slots 69 * and a 512-bit hash table. 70 * 71 * The Starfire has no internal transceiver, relying instead on an 72 * external MII-based transceiver. Accessing registers on external 73 * PHYs is done through a special register map rather than with the 74 * usual bitbang MDIO method. 75 * 76 * Acesssing the registers on the Starfire is a little tricky. The 77 * Starfire has a 512K internal register space. When programmed for 78 * PCI memory mapped mode, the entire register space can be accessed 79 * directly. However in I/O space mode, only 256 bytes are directly 80 * mapped into PCI I/O space. The other registers can be accessed 81 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 82 * registers inside the 256-byte I/O window. 83 */ 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/socket.h> 92 93 #include <net/if.h> 94 #include <net/ifq_var.h> 95 #include <net/if_arp.h> 96 #include <net/ethernet.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 100 #include <net/bpf.h> 101 102 #include <vm/vm.h> /* for vtophys */ 103 #include <vm/pmap.h> /* for vtophys */ 104 #include <machine/clock.h> /* for DELAY */ 105 #include <machine/bus_pio.h> 106 #include <machine/bus_memio.h> 107 #include <machine/bus.h> 108 #include <machine/resource.h> 109 #include <sys/bus.h> 110 #include <sys/rman.h> 111 112 #include "../mii_layer/mii.h" 113 #include "../mii_layer/miivar.h" 114 115 /* "controller miibus0" required. See GENERIC if you get errors here. */ 116 #include "miibus_if.h" 117 118 #include <bus/pci/pcireg.h> 119 #include <bus/pci/pcivar.h> 120 121 #define SF_USEIOSPACE 122 123 #include "if_sfreg.h" 124 125 static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129 }; 130 131 static int sf_probe (device_t); 132 static int sf_attach (device_t); 133 static int sf_detach (device_t); 134 static void sf_intr (void *); 135 static void sf_stats_update (void *); 136 static void sf_rxeof (struct sf_softc *); 137 static void sf_txeof (struct sf_softc *); 138 static int sf_encap (struct sf_softc *, 139 struct sf_tx_bufdesc_type0 *, 140 struct mbuf *); 141 static void sf_start (struct ifnet *); 142 static int sf_ioctl (struct ifnet *, u_long, caddr_t, 143 struct ucred *); 144 static void sf_init (void *); 145 static void sf_stop (struct sf_softc *); 146 static void sf_watchdog (struct ifnet *); 147 static void sf_shutdown (device_t); 148 static int sf_ifmedia_upd (struct ifnet *); 149 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 150 static void sf_reset (struct sf_softc *); 151 static int sf_init_rx_ring (struct sf_softc *); 152 static void sf_init_tx_ring (struct sf_softc *); 153 static int sf_newbuf (struct sf_softc *, 154 struct sf_rx_bufdesc_type0 *, 155 struct mbuf *); 156 static void sf_setmulti (struct sf_softc *); 157 static int sf_setperf (struct sf_softc *, int, caddr_t); 158 static int sf_sethash (struct sf_softc *, caddr_t, int); 159 #ifdef notdef 160 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 161 #endif 162 163 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 164 static u_int32_t sf_calchash (caddr_t); 165 166 static int sf_miibus_readreg (device_t, int, int); 167 static int sf_miibus_writereg (device_t, int, int, int); 168 static void sf_miibus_statchg (device_t); 169 170 static u_int32_t csr_read_4 (struct sf_softc *, int); 171 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 172 static void sf_txthresh_adjust (struct sf_softc *); 173 174 #ifdef SF_USEIOSPACE 175 #define SF_RES SYS_RES_IOPORT 176 #define SF_RID SF_PCI_LOIO 177 #else 178 #define SF_RES SYS_RES_MEMORY 179 #define SF_RID SF_PCI_LOMEM 180 #endif 181 182 static device_method_t sf_methods[] = { 183 /* Device interface */ 184 DEVMETHOD(device_probe, sf_probe), 185 DEVMETHOD(device_attach, sf_attach), 186 DEVMETHOD(device_detach, sf_detach), 187 DEVMETHOD(device_shutdown, sf_shutdown), 188 189 /* bus interface */ 190 DEVMETHOD(bus_print_child, bus_generic_print_child), 191 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 192 193 /* MII interface */ 194 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 195 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 196 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 197 198 { 0, 0 } 199 }; 200 201 static driver_t sf_driver = { 202 "sf", 203 sf_methods, 204 sizeof(struct sf_softc), 205 }; 206 207 static devclass_t sf_devclass; 208 209 DECLARE_DUMMY_MODULE(if_sf); 210 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 211 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 212 213 #define SF_SETBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 215 216 #define SF_CLRBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 218 219 static u_int32_t csr_read_4(sc, reg) 220 struct sf_softc *sc; 221 int reg; 222 { 223 u_int32_t val; 224 225 #ifdef SF_USEIOSPACE 226 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 227 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 228 #else 229 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 230 #endif 231 232 return(val); 233 } 234 235 static u_int8_t sf_read_eeprom(sc, reg) 236 struct sf_softc *sc; 237 int reg; 238 { 239 u_int8_t val; 240 241 val = (csr_read_4(sc, SF_EEADDR_BASE + 242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 243 244 return(val); 245 } 246 247 static void csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251 { 252 #ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255 #else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257 #endif 258 return; 259 } 260 261 static u_int32_t sf_calchash(addr) 262 caddr_t addr; 263 { 264 u_int32_t crc, carry; 265 int i, j; 266 u_int8_t c; 267 268 /* Compute CRC for the address value. */ 269 crc = 0xFFFFFFFF; /* initial value */ 270 271 for (i = 0; i < 6; i++) { 272 c = *(addr + i); 273 for (j = 0; j < 8; j++) { 274 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 275 crc <<= 1; 276 c >>= 1; 277 if (carry) 278 crc = (crc ^ 0x04c11db6) | carry; 279 } 280 } 281 282 /* return the filter bit position */ 283 return(crc >> 23 & 0x1FF); 284 } 285 286 /* 287 * Copy the address 'mac' into the perfect RX filter entry at 288 * offset 'idx.' The perfect filter only has 16 entries so do 289 * some sanity tests. 290 */ 291 static int sf_setperf(sc, idx, mac) 292 struct sf_softc *sc; 293 int idx; 294 caddr_t mac; 295 { 296 u_int16_t *p; 297 298 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 299 return(EINVAL); 300 301 if (mac == NULL) 302 return(EINVAL); 303 304 p = (u_int16_t *)mac; 305 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 310 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 311 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 312 313 return(0); 314 } 315 316 /* 317 * Set the bit in the 512-bit hash table that corresponds to the 318 * specified mac address 'mac.' If 'prio' is nonzero, update the 319 * priority hash table instead of the filter hash table. 320 */ 321 static int sf_sethash(sc, mac, prio) 322 struct sf_softc *sc; 323 caddr_t mac; 324 int prio; 325 { 326 u_int32_t h = 0; 327 328 if (mac == NULL) 329 return(EINVAL); 330 331 h = sf_calchash(mac); 332 333 if (prio) { 334 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 335 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 336 } else { 337 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 338 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 339 } 340 341 return(0); 342 } 343 344 #ifdef notdef 345 /* 346 * Set a VLAN tag in the receive filter. 347 */ 348 static int sf_setvlan(sc, idx, vlan) 349 struct sf_softc *sc; 350 int idx; 351 u_int32_t vlan; 352 { 353 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 354 return(EINVAL); 355 356 csr_write_4(sc, SF_RXFILT_HASH_BASE + 357 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 358 359 return(0); 360 } 361 #endif 362 363 static int sf_miibus_readreg(dev, phy, reg) 364 device_t dev; 365 int phy, reg; 366 { 367 struct sf_softc *sc; 368 int i; 369 u_int32_t val = 0; 370 371 sc = device_get_softc(dev); 372 373 for (i = 0; i < SF_TIMEOUT; i++) { 374 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 375 if (val & SF_MII_DATAVALID) 376 break; 377 } 378 379 if (i == SF_TIMEOUT) 380 return(0); 381 382 if ((val & 0x0000FFFF) == 0xFFFF) 383 return(0); 384 385 return(val & 0x0000FFFF); 386 } 387 388 static int sf_miibus_writereg(dev, phy, reg, val) 389 device_t dev; 390 int phy, reg, val; 391 { 392 struct sf_softc *sc; 393 int i; 394 int busy; 395 396 sc = device_get_softc(dev); 397 398 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 399 400 for (i = 0; i < SF_TIMEOUT; i++) { 401 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 402 if (!(busy & SF_MII_BUSY)) 403 break; 404 } 405 406 return(0); 407 } 408 409 static void sf_miibus_statchg(dev) 410 device_t dev; 411 { 412 struct sf_softc *sc; 413 struct mii_data *mii; 414 415 sc = device_get_softc(dev); 416 mii = device_get_softc(sc->sf_miibus); 417 418 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 419 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 420 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 421 } else { 422 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 423 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 424 } 425 426 return; 427 } 428 429 static void sf_setmulti(sc) 430 struct sf_softc *sc; 431 { 432 struct ifnet *ifp; 433 int i; 434 struct ifmultiaddr *ifma; 435 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 436 437 ifp = &sc->arpcom.ac_if; 438 439 /* First zot all the existing filters. */ 440 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 441 sf_setperf(sc, i, (char *)&dummy); 442 for (i = SF_RXFILT_HASH_BASE; 443 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 444 csr_write_4(sc, i, 0); 445 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 446 447 /* Now program new ones. */ 448 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 449 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 450 } else { 451 i = 1; 452 /* First find the tail of the list. */ 453 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 454 ifma = ifma->ifma_link.le_next) { 455 if (ifma->ifma_link.le_next == NULL) 456 break; 457 } 458 /* Now traverse the list backwards. */ 459 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 460 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 461 if (ifma->ifma_addr->sa_family != AF_LINK) 462 continue; 463 /* 464 * Program the first 15 multicast groups 465 * into the perfect filter. For all others, 466 * use the hash table. 467 */ 468 if (i < SF_RXFILT_PERFECT_CNT) { 469 sf_setperf(sc, i, 470 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 471 i++; 472 continue; 473 } 474 475 sf_sethash(sc, 476 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 477 } 478 } 479 480 return; 481 } 482 483 /* 484 * Set media options. 485 */ 486 static int sf_ifmedia_upd(ifp) 487 struct ifnet *ifp; 488 { 489 struct sf_softc *sc; 490 struct mii_data *mii; 491 492 sc = ifp->if_softc; 493 mii = device_get_softc(sc->sf_miibus); 494 sc->sf_link = 0; 495 if (mii->mii_instance) { 496 struct mii_softc *miisc; 497 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 498 miisc = LIST_NEXT(miisc, mii_list)) 499 mii_phy_reset(miisc); 500 } 501 mii_mediachg(mii); 502 503 return(0); 504 } 505 506 /* 507 * Report current media status. 508 */ 509 static void sf_ifmedia_sts(ifp, ifmr) 510 struct ifnet *ifp; 511 struct ifmediareq *ifmr; 512 { 513 struct sf_softc *sc; 514 struct mii_data *mii; 515 516 sc = ifp->if_softc; 517 mii = device_get_softc(sc->sf_miibus); 518 519 mii_pollstat(mii); 520 ifmr->ifm_active = mii->mii_media_active; 521 ifmr->ifm_status = mii->mii_media_status; 522 523 return; 524 } 525 526 static int sf_ioctl(ifp, command, data, cr) 527 struct ifnet *ifp; 528 u_long command; 529 caddr_t data; 530 struct ucred *cr; 531 { 532 struct sf_softc *sc = ifp->if_softc; 533 struct ifreq *ifr = (struct ifreq *) data; 534 struct mii_data *mii; 535 int s, error = 0; 536 537 s = splimp(); 538 539 switch(command) { 540 case SIOCSIFADDR: 541 case SIOCGIFADDR: 542 case SIOCSIFMTU: 543 error = ether_ioctl(ifp, command, data); 544 break; 545 case SIOCSIFFLAGS: 546 if (ifp->if_flags & IFF_UP) { 547 if (ifp->if_flags & IFF_RUNNING && 548 ifp->if_flags & IFF_PROMISC && 549 !(sc->sf_if_flags & IFF_PROMISC)) { 550 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 551 } else if (ifp->if_flags & IFF_RUNNING && 552 !(ifp->if_flags & IFF_PROMISC) && 553 sc->sf_if_flags & IFF_PROMISC) { 554 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 555 } else if (!(ifp->if_flags & IFF_RUNNING)) 556 sf_init(sc); 557 } else { 558 if (ifp->if_flags & IFF_RUNNING) 559 sf_stop(sc); 560 } 561 sc->sf_if_flags = ifp->if_flags; 562 error = 0; 563 break; 564 case SIOCADDMULTI: 565 case SIOCDELMULTI: 566 sf_setmulti(sc); 567 error = 0; 568 break; 569 case SIOCGIFMEDIA: 570 case SIOCSIFMEDIA: 571 mii = device_get_softc(sc->sf_miibus); 572 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 573 break; 574 default: 575 error = EINVAL; 576 break; 577 } 578 579 (void)splx(s); 580 581 return(error); 582 } 583 584 static void sf_reset(sc) 585 struct sf_softc *sc; 586 { 587 int i; 588 589 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 590 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 591 DELAY(1000); 592 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 593 594 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 595 596 for (i = 0; i < SF_TIMEOUT; i++) { 597 DELAY(10); 598 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 599 break; 600 } 601 602 if (i == SF_TIMEOUT) 603 printf("sf%d: reset never completed!\n", sc->sf_unit); 604 605 /* Wait a little while for the chip to get its brains in order. */ 606 DELAY(1000); 607 return; 608 } 609 610 /* 611 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 612 * IDs against our list and return a device name if we find a match. 613 * We also check the subsystem ID so that we can identify exactly which 614 * NIC has been found, if possible. 615 */ 616 static int sf_probe(dev) 617 device_t dev; 618 { 619 struct sf_type *t; 620 621 t = sf_devs; 622 623 while(t->sf_name != NULL) { 624 if ((pci_get_vendor(dev) == t->sf_vid) && 625 (pci_get_device(dev) == t->sf_did)) { 626 switch((pci_read_config(dev, 627 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 628 case AD_SUBSYSID_62011_REV0: 629 case AD_SUBSYSID_62011_REV1: 630 device_set_desc(dev, 631 "Adaptec ANA-62011 10/100BaseTX"); 632 return(0); 633 break; 634 case AD_SUBSYSID_62022: 635 device_set_desc(dev, 636 "Adaptec ANA-62022 10/100BaseTX"); 637 return(0); 638 break; 639 case AD_SUBSYSID_62044_REV0: 640 case AD_SUBSYSID_62044_REV1: 641 device_set_desc(dev, 642 "Adaptec ANA-62044 10/100BaseTX"); 643 return(0); 644 break; 645 case AD_SUBSYSID_62020: 646 device_set_desc(dev, 647 "Adaptec ANA-62020 10/100BaseFX"); 648 return(0); 649 break; 650 case AD_SUBSYSID_69011: 651 device_set_desc(dev, 652 "Adaptec ANA-69011 10/100BaseTX"); 653 return(0); 654 break; 655 default: 656 device_set_desc(dev, t->sf_name); 657 return(0); 658 break; 659 } 660 } 661 t++; 662 } 663 664 return(ENXIO); 665 } 666 667 /* 668 * Attach the interface. Allocate softc structures, do ifmedia 669 * setup and ethernet/BPF attach. 670 */ 671 static int sf_attach(dev) 672 device_t dev; 673 { 674 int s, i; 675 u_int32_t command; 676 struct sf_softc *sc; 677 struct ifnet *ifp; 678 int unit, rid, error = 0; 679 680 s = splimp(); 681 682 sc = device_get_softc(dev); 683 unit = device_get_unit(dev); 684 bzero(sc, sizeof(struct sf_softc)); 685 686 /* 687 * Handle power management nonsense. 688 */ 689 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 690 if (command == 0x01) { 691 692 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 693 if (command & SF_PSTATE_MASK) { 694 u_int32_t iobase, membase, irq; 695 696 /* Save important PCI config data. */ 697 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 698 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 699 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 700 701 /* Reset the power state. */ 702 printf("sf%d: chip is in D%d power mode " 703 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 704 command &= 0xFFFFFFFC; 705 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 706 707 /* Restore PCI config data. */ 708 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 709 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 710 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 711 } 712 } 713 714 /* 715 * Map control/status registers. 716 */ 717 command = pci_read_config(dev, PCIR_COMMAND, 4); 718 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 719 pci_write_config(dev, PCIR_COMMAND, command, 4); 720 command = pci_read_config(dev, PCIR_COMMAND, 4); 721 722 #ifdef SF_USEIOSPACE 723 if (!(command & PCIM_CMD_PORTEN)) { 724 printf("sf%d: failed to enable I/O ports!\n", unit); 725 error = ENXIO; 726 goto fail; 727 } 728 #else 729 if (!(command & PCIM_CMD_MEMEN)) { 730 printf("sf%d: failed to enable memory mapping!\n", unit); 731 error = ENXIO; 732 goto fail; 733 } 734 #endif 735 736 rid = SF_RID; 737 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 738 0, ~0, 1, RF_ACTIVE); 739 740 if (sc->sf_res == NULL) { 741 printf ("sf%d: couldn't map ports\n", unit); 742 error = ENXIO; 743 goto fail; 744 } 745 746 sc->sf_btag = rman_get_bustag(sc->sf_res); 747 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 748 749 /* Allocate interrupt */ 750 rid = 0; 751 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 752 RF_SHAREABLE | RF_ACTIVE); 753 754 if (sc->sf_irq == NULL) { 755 printf("sf%d: couldn't map interrupt\n", unit); 756 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 757 error = ENXIO; 758 goto fail; 759 } 760 761 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 762 sf_intr, sc, &sc->sf_intrhand); 763 764 if (error) { 765 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 766 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 767 printf("sf%d: couldn't set up irq\n", unit); 768 goto fail; 769 } 770 771 callout_init(&sc->sf_stat_timer); 772 773 /* Reset the adapter. */ 774 sf_reset(sc); 775 776 /* 777 * Get station address from the EEPROM. 778 */ 779 for (i = 0; i < ETHER_ADDR_LEN; i++) 780 sc->arpcom.ac_enaddr[i] = 781 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 782 783 sc->sf_unit = unit; 784 785 /* Allocate the descriptor queues. */ 786 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 787 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 788 789 if (sc->sf_ldata == NULL) { 790 printf("sf%d: no memory for list buffers!\n", unit); 791 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 792 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 793 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 794 error = ENXIO; 795 goto fail; 796 } 797 798 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 799 800 /* Do MII setup. */ 801 if (mii_phy_probe(dev, &sc->sf_miibus, 802 sf_ifmedia_upd, sf_ifmedia_sts)) { 803 printf("sf%d: MII without any phy!\n", sc->sf_unit); 804 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 805 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 806 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 807 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 808 error = ENXIO; 809 goto fail; 810 } 811 812 ifp = &sc->arpcom.ac_if; 813 ifp->if_softc = sc; 814 if_initname(ifp, "sf", unit); 815 ifp->if_mtu = ETHERMTU; 816 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 817 ifp->if_ioctl = sf_ioctl; 818 ifp->if_start = sf_start; 819 ifp->if_watchdog = sf_watchdog; 820 ifp->if_init = sf_init; 821 ifp->if_baudrate = 10000000; 822 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 823 ifq_set_ready(&ifp->if_snd); 824 825 /* 826 * Call MI attach routine. 827 */ 828 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 829 830 fail: 831 splx(s); 832 return(error); 833 } 834 835 static int sf_detach(dev) 836 device_t dev; 837 { 838 struct sf_softc *sc; 839 struct ifnet *ifp; 840 int s; 841 842 s = splimp(); 843 844 sc = device_get_softc(dev); 845 ifp = &sc->arpcom.ac_if; 846 847 ether_ifdetach(ifp); 848 sf_stop(sc); 849 850 bus_generic_detach(dev); 851 device_delete_child(dev, sc->sf_miibus); 852 853 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 854 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 855 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 856 857 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 858 859 splx(s); 860 861 return(0); 862 } 863 864 static int sf_init_rx_ring(sc) 865 struct sf_softc *sc; 866 { 867 struct sf_list_data *ld; 868 int i; 869 870 ld = sc->sf_ldata; 871 872 bzero((char *)ld->sf_rx_dlist_big, 873 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 874 bzero((char *)ld->sf_rx_clist, 875 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 876 877 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 878 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 879 return(ENOBUFS); 880 } 881 882 return(0); 883 } 884 885 static void sf_init_tx_ring(sc) 886 struct sf_softc *sc; 887 { 888 struct sf_list_data *ld; 889 int i; 890 891 ld = sc->sf_ldata; 892 893 bzero((char *)ld->sf_tx_dlist, 894 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 895 bzero((char *)ld->sf_tx_clist, 896 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 897 898 for (i = 0; i < SF_TX_DLIST_CNT; i++) 899 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 900 for (i = 0; i < SF_TX_CLIST_CNT; i++) 901 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 902 903 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 904 sc->sf_tx_cnt = 0; 905 906 return; 907 } 908 909 static int sf_newbuf(sc, c, m) 910 struct sf_softc *sc; 911 struct sf_rx_bufdesc_type0 *c; 912 struct mbuf *m; 913 { 914 struct mbuf *m_new = NULL; 915 916 if (m == NULL) { 917 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 918 if (m_new == NULL) 919 return(ENOBUFS); 920 921 MCLGET(m_new, MB_DONTWAIT); 922 if (!(m_new->m_flags & M_EXT)) { 923 m_freem(m_new); 924 return(ENOBUFS); 925 } 926 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 927 } else { 928 m_new = m; 929 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 930 m_new->m_data = m_new->m_ext.ext_buf; 931 } 932 933 m_adj(m_new, sizeof(u_int64_t)); 934 935 c->sf_mbuf = m_new; 936 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 937 c->sf_valid = 1; 938 939 return(0); 940 } 941 942 /* 943 * The starfire is programmed to use 'normal' mode for packet reception, 944 * which means we use the consumer/producer model for both the buffer 945 * descriptor queue and the completion descriptor queue. The only problem 946 * with this is that it involves a lot of register accesses: we have to 947 * read the RX completion consumer and producer indexes and the RX buffer 948 * producer index, plus the RX completion consumer and RX buffer producer 949 * indexes have to be updated. It would have been easier if Adaptec had 950 * put each index in a separate register, especially given that the damn 951 * NIC has a 512K register space. 952 * 953 * In spite of all the lovely features that Adaptec crammed into the 6915, 954 * it is marred by one truly stupid design flaw, which is that receive 955 * buffer addresses must be aligned on a longword boundary. This forces 956 * the packet payload to be unaligned, which is suboptimal on the x86 and 957 * completely unuseable on the Alpha. Our only recourse is to copy received 958 * packets into properly aligned buffers before handing them off. 959 */ 960 961 static void sf_rxeof(sc) 962 struct sf_softc *sc; 963 { 964 struct mbuf *m; 965 struct ifnet *ifp; 966 struct sf_rx_bufdesc_type0 *desc; 967 struct sf_rx_cmpdesc_type3 *cur_rx; 968 u_int32_t rxcons, rxprod; 969 int cmpprodidx, cmpconsidx, bufprodidx; 970 971 ifp = &sc->arpcom.ac_if; 972 973 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 974 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 975 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 976 cmpconsidx = SF_IDX_LO(rxcons); 977 bufprodidx = SF_IDX_LO(rxprod); 978 979 while (cmpconsidx != cmpprodidx) { 980 struct mbuf *m0; 981 982 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 983 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 984 m = desc->sf_mbuf; 985 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 986 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 987 988 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 989 ifp->if_ierrors++; 990 sf_newbuf(sc, desc, m); 991 continue; 992 } 993 994 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 995 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 996 sf_newbuf(sc, desc, m); 997 if (m0 == NULL) { 998 ifp->if_ierrors++; 999 continue; 1000 } 1001 m_adj(m0, ETHER_ALIGN); 1002 m = m0; 1003 1004 ifp->if_ipackets++; 1005 1006 (*ifp->if_input)(ifp, m); 1007 } 1008 1009 csr_write_4(sc, SF_CQ_CONSIDX, 1010 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1011 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1012 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1013 1014 return; 1015 } 1016 1017 /* 1018 * Read the transmit status from the completion queue and release 1019 * mbufs. Note that the buffer descriptor index in the completion 1020 * descriptor is an offset from the start of the transmit buffer 1021 * descriptor list in bytes. This is important because the manual 1022 * gives the impression that it should match the producer/consumer 1023 * index, which is the offset in 8 byte blocks. 1024 */ 1025 static void sf_txeof(sc) 1026 struct sf_softc *sc; 1027 { 1028 int txcons, cmpprodidx, cmpconsidx; 1029 struct sf_tx_cmpdesc_type1 *cur_cmp; 1030 struct sf_tx_bufdesc_type0 *cur_tx; 1031 struct ifnet *ifp; 1032 1033 ifp = &sc->arpcom.ac_if; 1034 1035 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1036 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1037 cmpconsidx = SF_IDX_HI(txcons); 1038 1039 while (cmpconsidx != cmpprodidx) { 1040 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1041 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1042 1043 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1044 ifp->if_opackets++; 1045 else { 1046 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1047 sf_txthresh_adjust(sc); 1048 ifp->if_oerrors++; 1049 } 1050 1051 sc->sf_tx_cnt--; 1052 if (cur_tx->sf_mbuf != NULL) { 1053 m_freem(cur_tx->sf_mbuf); 1054 cur_tx->sf_mbuf = NULL; 1055 } else 1056 break; 1057 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1058 } 1059 1060 ifp->if_timer = 0; 1061 ifp->if_flags &= ~IFF_OACTIVE; 1062 1063 csr_write_4(sc, SF_CQ_CONSIDX, 1064 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1065 ((cmpconsidx << 16) & 0xFFFF0000)); 1066 1067 return; 1068 } 1069 1070 static void sf_txthresh_adjust(sc) 1071 struct sf_softc *sc; 1072 { 1073 u_int32_t txfctl; 1074 u_int8_t txthresh; 1075 1076 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1077 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1078 if (txthresh < 0xFF) { 1079 txthresh++; 1080 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1081 txfctl |= txthresh; 1082 #ifdef DIAGNOSTIC 1083 printf("sf%d: tx underrun, increasing " 1084 "tx threshold to %d bytes\n", 1085 sc->sf_unit, txthresh * 4); 1086 #endif 1087 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1088 } 1089 1090 return; 1091 } 1092 1093 static void sf_intr(arg) 1094 void *arg; 1095 { 1096 struct sf_softc *sc; 1097 struct ifnet *ifp; 1098 u_int32_t status; 1099 1100 sc = arg; 1101 ifp = &sc->arpcom.ac_if; 1102 1103 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1104 return; 1105 1106 /* Disable interrupts. */ 1107 csr_write_4(sc, SF_IMR, 0x00000000); 1108 1109 for (;;) { 1110 status = csr_read_4(sc, SF_ISR); 1111 if (status) 1112 csr_write_4(sc, SF_ISR, status); 1113 1114 if (!(status & SF_INTRS)) 1115 break; 1116 1117 if (status & SF_ISR_RXDQ1_DMADONE) 1118 sf_rxeof(sc); 1119 1120 if (status & SF_ISR_TX_TXDONE || 1121 status & SF_ISR_TX_DMADONE || 1122 status & SF_ISR_TX_QUEUEDONE) 1123 sf_txeof(sc); 1124 1125 if (status & SF_ISR_TX_LOFIFO) 1126 sf_txthresh_adjust(sc); 1127 1128 if (status & SF_ISR_ABNORMALINTR) { 1129 if (status & SF_ISR_STATSOFLOW) { 1130 callout_stop(&sc->sf_stat_timer); 1131 sf_stats_update(sc); 1132 } else 1133 sf_init(sc); 1134 } 1135 } 1136 1137 /* Re-enable interrupts. */ 1138 csr_write_4(sc, SF_IMR, SF_INTRS); 1139 1140 if (!ifq_is_empty(&ifp->if_snd)) 1141 sf_start(ifp); 1142 1143 return; 1144 } 1145 1146 static void sf_init(xsc) 1147 void *xsc; 1148 { 1149 struct sf_softc *sc; 1150 struct ifnet *ifp; 1151 struct mii_data *mii; 1152 int i, s; 1153 1154 s = splimp(); 1155 1156 sc = xsc; 1157 ifp = &sc->arpcom.ac_if; 1158 mii = device_get_softc(sc->sf_miibus); 1159 1160 sf_stop(sc); 1161 sf_reset(sc); 1162 1163 /* Init all the receive filter registers */ 1164 for (i = SF_RXFILT_PERFECT_BASE; 1165 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1166 csr_write_4(sc, i, 0); 1167 1168 /* Empty stats counter registers. */ 1169 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1170 csr_write_4(sc, SF_STATS_BASE + 1171 (i + sizeof(u_int32_t)), 0); 1172 1173 /* Init our MAC address */ 1174 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1175 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1176 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1177 1178 if (sf_init_rx_ring(sc) == ENOBUFS) { 1179 printf("sf%d: initialization failed: no " 1180 "memory for rx buffers\n", sc->sf_unit); 1181 (void)splx(s); 1182 return; 1183 } 1184 1185 sf_init_tx_ring(sc); 1186 1187 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1188 1189 /* If we want promiscuous mode, set the allframes bit. */ 1190 if (ifp->if_flags & IFF_PROMISC) { 1191 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1192 } else { 1193 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1194 } 1195 1196 if (ifp->if_flags & IFF_BROADCAST) { 1197 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1198 } else { 1199 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1200 } 1201 1202 /* 1203 * Load the multicast filter. 1204 */ 1205 sf_setmulti(sc); 1206 1207 /* Init the completion queue indexes */ 1208 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1209 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1210 1211 /* Init the RX completion queue */ 1212 csr_write_4(sc, SF_RXCQ_CTL_1, 1213 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1214 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1215 1216 /* Init RX DMA control. */ 1217 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1218 1219 /* Init the RX buffer descriptor queue. */ 1220 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1221 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1222 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1223 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1224 1225 /* Init the TX completion queue */ 1226 csr_write_4(sc, SF_TXCQ_CTL, 1227 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1228 1229 /* Init the TX buffer descriptor queue. */ 1230 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1231 vtophys(sc->sf_ldata->sf_tx_dlist)); 1232 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1233 csr_write_4(sc, SF_TXDQ_CTL, 1234 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1235 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1236 1237 /* Enable autopadding of short TX frames. */ 1238 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1239 1240 /* Enable interrupts. */ 1241 csr_write_4(sc, SF_IMR, SF_INTRS); 1242 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1243 1244 /* Enable the RX and TX engines. */ 1245 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1246 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1247 1248 /*mii_mediachg(mii);*/ 1249 sf_ifmedia_upd(ifp); 1250 1251 ifp->if_flags |= IFF_RUNNING; 1252 ifp->if_flags &= ~IFF_OACTIVE; 1253 1254 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1255 1256 splx(s); 1257 1258 return; 1259 } 1260 1261 static int sf_encap(sc, c, m_head) 1262 struct sf_softc *sc; 1263 struct sf_tx_bufdesc_type0 *c; 1264 struct mbuf *m_head; 1265 { 1266 int frag = 0; 1267 struct sf_frag *f = NULL; 1268 struct mbuf *m; 1269 1270 m = m_head; 1271 1272 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1273 if (m->m_len != 0) { 1274 if (frag == SF_MAXFRAGS) 1275 break; 1276 f = &c->sf_frags[frag]; 1277 if (frag == 0) 1278 f->sf_pktlen = m_head->m_pkthdr.len; 1279 f->sf_fraglen = m->m_len; 1280 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1281 frag++; 1282 } 1283 } 1284 1285 if (m != NULL) { 1286 struct mbuf *m_new = NULL; 1287 1288 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1289 if (m_new == NULL) { 1290 printf("sf%d: no memory for tx list", sc->sf_unit); 1291 return(1); 1292 } 1293 1294 if (m_head->m_pkthdr.len > MHLEN) { 1295 MCLGET(m_new, MB_DONTWAIT); 1296 if (!(m_new->m_flags & M_EXT)) { 1297 m_freem(m_new); 1298 printf("sf%d: no memory for tx list", 1299 sc->sf_unit); 1300 return(1); 1301 } 1302 } 1303 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1304 mtod(m_new, caddr_t)); 1305 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1306 m_freem(m_head); 1307 m_head = m_new; 1308 f = &c->sf_frags[0]; 1309 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1310 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1311 frag = 1; 1312 } 1313 1314 c->sf_mbuf = m_head; 1315 c->sf_id = SF_TX_BUFDESC_ID; 1316 c->sf_fragcnt = frag; 1317 c->sf_intr = 1; 1318 c->sf_caltcp = 0; 1319 c->sf_crcen = 1; 1320 1321 return(0); 1322 } 1323 1324 static void sf_start(ifp) 1325 struct ifnet *ifp; 1326 { 1327 struct sf_softc *sc; 1328 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1329 struct mbuf *m_head = NULL; 1330 int i, txprod; 1331 1332 sc = ifp->if_softc; 1333 1334 if (!sc->sf_link) 1335 return; 1336 1337 if (ifp->if_flags & IFF_OACTIVE) 1338 return; 1339 1340 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1341 i = SF_IDX_HI(txprod) >> 4; 1342 1343 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1344 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1345 sf_init(sc); 1346 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1347 i = SF_IDX_HI(txprod) >> 4; 1348 } 1349 1350 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1351 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1352 ifp->if_flags |= IFF_OACTIVE; 1353 cur_tx = NULL; 1354 break; 1355 } 1356 m_head = ifq_poll(&ifp->if_snd); 1357 if (m_head == NULL) 1358 break; 1359 1360 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1361 if (sf_encap(sc, cur_tx, m_head)) { 1362 ifp->if_flags |= IFF_OACTIVE; 1363 cur_tx = NULL; 1364 break; 1365 } 1366 ifq_dequeue(&ifp->if_snd); 1367 BPF_MTAP(ifp, cur_tx->sf_mbuf); 1368 1369 SF_INC(i, SF_TX_DLIST_CNT); 1370 sc->sf_tx_cnt++; 1371 /* 1372 * Don't get the TX DMA queue get too full. 1373 */ 1374 if (sc->sf_tx_cnt > 64) 1375 break; 1376 } 1377 1378 if (cur_tx == NULL) 1379 return; 1380 1381 /* Transmit */ 1382 csr_write_4(sc, SF_TXDQ_PRODIDX, 1383 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1384 ((i << 20) & 0xFFFF0000)); 1385 1386 ifp->if_timer = 5; 1387 1388 return; 1389 } 1390 1391 static void sf_stop(sc) 1392 struct sf_softc *sc; 1393 { 1394 int i; 1395 struct ifnet *ifp; 1396 1397 ifp = &sc->arpcom.ac_if; 1398 1399 callout_stop(&sc->sf_stat_timer); 1400 1401 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1402 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1403 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1404 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1405 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1406 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1407 csr_write_4(sc, SF_TXCQ_CTL, 0); 1408 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1409 csr_write_4(sc, SF_TXDQ_CTL, 0); 1410 sf_reset(sc); 1411 1412 sc->sf_link = 0; 1413 1414 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1415 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1416 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1417 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1418 } 1419 } 1420 1421 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1422 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1423 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1424 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1425 } 1426 } 1427 1428 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1429 1430 return; 1431 } 1432 1433 /* 1434 * Note: it is important that this function not be interrupted. We 1435 * use a two-stage register access scheme: if we are interrupted in 1436 * between setting the indirect address register and reading from the 1437 * indirect data register, the contents of the address register could 1438 * be changed out from under us. 1439 */ 1440 static void sf_stats_update(xsc) 1441 void *xsc; 1442 { 1443 struct sf_softc *sc; 1444 struct ifnet *ifp; 1445 struct mii_data *mii; 1446 struct sf_stats stats; 1447 u_int32_t *ptr; 1448 int i, s; 1449 1450 s = splimp(); 1451 1452 sc = xsc; 1453 ifp = &sc->arpcom.ac_if; 1454 mii = device_get_softc(sc->sf_miibus); 1455 1456 ptr = (u_int32_t *)&stats; 1457 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1458 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1459 (i + sizeof(u_int32_t))); 1460 1461 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1462 csr_write_4(sc, SF_STATS_BASE + 1463 (i + sizeof(u_int32_t)), 0); 1464 1465 ifp->if_collisions += stats.sf_tx_single_colls + 1466 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1467 1468 mii_tick(mii); 1469 if (!sc->sf_link) { 1470 mii_pollstat(mii); 1471 if (mii->mii_media_status & IFM_ACTIVE && 1472 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1473 sc->sf_link++; 1474 if (!ifq_is_empty(&ifp->if_snd)) 1475 sf_start(ifp); 1476 } 1477 1478 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1479 1480 splx(s); 1481 1482 return; 1483 } 1484 1485 static void sf_watchdog(ifp) 1486 struct ifnet *ifp; 1487 { 1488 struct sf_softc *sc; 1489 1490 sc = ifp->if_softc; 1491 1492 ifp->if_oerrors++; 1493 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1494 1495 sf_stop(sc); 1496 sf_reset(sc); 1497 sf_init(sc); 1498 1499 if (!ifq_is_empty(&ifp->if_snd)) 1500 sf_start(ifp); 1501 1502 return; 1503 } 1504 1505 static void sf_shutdown(dev) 1506 device_t dev; 1507 { 1508 struct sf_softc *sc; 1509 1510 sc = device_get_softc(dev); 1511 1512 sf_stop(sc); 1513 1514 return; 1515 } 1516