1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.25 2005/11/28 17:13:44 dillon Exp $ 34 */ 35 36 /* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45 46 /* 47 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 48 * controller designed with flexibility and reducing CPU load in mind. 49 * The Starfire offers high and low priority buffer queues, a 50 * producer/consumer index mechanism and several different buffer 51 * queue and completion queue descriptor types. Any one of a number 52 * of different driver designs can be used, depending on system and 53 * OS requirements. This driver makes use of type0 transmit frame 54 * descriptors (since BSD fragments packets across an mbuf chain) 55 * and two RX buffer queues prioritized on size (one queue for small 56 * frames that will fit into a single mbuf, another with full size 57 * mbuf clusters for everything else). The producer/consumer indexes 58 * and completion queues are also used. 59 * 60 * One downside to the Starfire has to do with alignment: buffer 61 * queues must be aligned on 256-byte boundaries, and receive buffers 62 * must be aligned on longword boundaries. The receive buffer alignment 63 * causes problems on the Alpha platform, where the packet payload 64 * should be longword aligned. There is no simple way around this. 65 * 66 * For receive filtering, the Starfire offers 16 perfect filter slots 67 * and a 512-bit hash table. 68 * 69 * The Starfire has no internal transceiver, relying instead on an 70 * external MII-based transceiver. Accessing registers on external 71 * PHYs is done through a special register map rather than with the 72 * usual bitbang MDIO method. 73 * 74 * Acesssing the registers on the Starfire is a little tricky. The 75 * Starfire has a 512K internal register space. When programmed for 76 * PCI memory mapped mode, the entire register space can be accessed 77 * directly. However in I/O space mode, only 256 bytes are directly 78 * mapped into PCI I/O space. The other registers can be accessed 79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 80 * registers inside the 256-byte I/O window. 81 */ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/socket.h> 90 #include <sys/serialize.h> 91 92 #include <sys/thread2.h> 93 94 #include <net/if.h> 95 #include <net/ifq_var.h> 96 #include <net/if_arp.h> 97 #include <net/ethernet.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 101 #include <net/bpf.h> 102 103 #include <vm/vm.h> /* for vtophys */ 104 #include <vm/pmap.h> /* for vtophys */ 105 #include <machine/clock.h> /* for DELAY */ 106 #include <machine/bus_pio.h> 107 #include <machine/bus_memio.h> 108 #include <machine/bus.h> 109 #include <machine/resource.h> 110 #include <sys/bus.h> 111 #include <sys/rman.h> 112 113 #include "../mii_layer/mii.h" 114 #include "../mii_layer/miivar.h" 115 116 /* "controller miibus0" required. See GENERIC if you get errors here. */ 117 #include "miibus_if.h" 118 119 #include <bus/pci/pcireg.h> 120 #include <bus/pci/pcivar.h> 121 122 #define SF_USEIOSPACE 123 124 #include "if_sfreg.h" 125 126 static struct sf_type sf_devs[] = { 127 { AD_VENDORID, AD_DEVICEID_STARFIRE, 128 "Adaptec AIC-6915 10/100BaseTX" }, 129 { 0, 0, NULL } 130 }; 131 132 static int sf_probe (device_t); 133 static int sf_attach (device_t); 134 static int sf_detach (device_t); 135 static void sf_intr (void *); 136 static void sf_stats_update (void *); 137 static void sf_rxeof (struct sf_softc *); 138 static void sf_txeof (struct sf_softc *); 139 static int sf_encap (struct sf_softc *, 140 struct sf_tx_bufdesc_type0 *, 141 struct mbuf *); 142 static void sf_start (struct ifnet *); 143 static int sf_ioctl (struct ifnet *, u_long, caddr_t, 144 struct ucred *); 145 static void sf_init (void *); 146 static void sf_stop (struct sf_softc *); 147 static void sf_watchdog (struct ifnet *); 148 static void sf_shutdown (device_t); 149 static int sf_ifmedia_upd (struct ifnet *); 150 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151 static void sf_reset (struct sf_softc *); 152 static int sf_init_rx_ring (struct sf_softc *); 153 static void sf_init_tx_ring (struct sf_softc *); 154 static int sf_newbuf (struct sf_softc *, 155 struct sf_rx_bufdesc_type0 *, 156 struct mbuf *); 157 static void sf_setmulti (struct sf_softc *); 158 static int sf_setperf (struct sf_softc *, int, caddr_t); 159 static int sf_sethash (struct sf_softc *, caddr_t, int); 160 #ifdef notdef 161 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 162 #endif 163 164 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 165 static u_int32_t sf_calchash (caddr_t); 166 167 static int sf_miibus_readreg (device_t, int, int); 168 static int sf_miibus_writereg (device_t, int, int, int); 169 static void sf_miibus_statchg (device_t); 170 171 static u_int32_t csr_read_4 (struct sf_softc *, int); 172 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 173 static void sf_txthresh_adjust (struct sf_softc *); 174 175 #ifdef SF_USEIOSPACE 176 #define SF_RES SYS_RES_IOPORT 177 #define SF_RID SF_PCI_LOIO 178 #else 179 #define SF_RES SYS_RES_MEMORY 180 #define SF_RID SF_PCI_LOMEM 181 #endif 182 183 static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200 }; 201 202 static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206 }; 207 208 static devclass_t sf_devclass; 209 210 DECLARE_DUMMY_MODULE(if_sf); 211 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 212 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 213 214 #define SF_SETBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 216 217 #define SF_CLRBIT(sc, reg, x) \ 218 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 219 220 static u_int32_t csr_read_4(sc, reg) 221 struct sf_softc *sc; 222 int reg; 223 { 224 u_int32_t val; 225 226 #ifdef SF_USEIOSPACE 227 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 228 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 229 #else 230 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 231 #endif 232 233 return(val); 234 } 235 236 static u_int8_t sf_read_eeprom(sc, reg) 237 struct sf_softc *sc; 238 int reg; 239 { 240 u_int8_t val; 241 242 val = (csr_read_4(sc, SF_EEADDR_BASE + 243 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 244 245 return(val); 246 } 247 248 static void csr_write_4(sc, reg, val) 249 struct sf_softc *sc; 250 int reg; 251 u_int32_t val; 252 { 253 #ifdef SF_USEIOSPACE 254 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 255 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 256 #else 257 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 258 #endif 259 return; 260 } 261 262 static u_int32_t sf_calchash(addr) 263 caddr_t addr; 264 { 265 u_int32_t crc, carry; 266 int i, j; 267 u_int8_t c; 268 269 /* Compute CRC for the address value. */ 270 crc = 0xFFFFFFFF; /* initial value */ 271 272 for (i = 0; i < 6; i++) { 273 c = *(addr + i); 274 for (j = 0; j < 8; j++) { 275 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 276 crc <<= 1; 277 c >>= 1; 278 if (carry) 279 crc = (crc ^ 0x04c11db6) | carry; 280 } 281 } 282 283 /* return the filter bit position */ 284 return(crc >> 23 & 0x1FF); 285 } 286 287 /* 288 * Copy the address 'mac' into the perfect RX filter entry at 289 * offset 'idx.' The perfect filter only has 16 entries so do 290 * some sanity tests. 291 */ 292 static int sf_setperf(sc, idx, mac) 293 struct sf_softc *sc; 294 int idx; 295 caddr_t mac; 296 { 297 u_int16_t *p; 298 299 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 300 return(EINVAL); 301 302 if (mac == NULL) 303 return(EINVAL); 304 305 p = (u_int16_t *)mac; 306 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 312 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 313 314 return(0); 315 } 316 317 /* 318 * Set the bit in the 512-bit hash table that corresponds to the 319 * specified mac address 'mac.' If 'prio' is nonzero, update the 320 * priority hash table instead of the filter hash table. 321 */ 322 static int sf_sethash(sc, mac, prio) 323 struct sf_softc *sc; 324 caddr_t mac; 325 int prio; 326 { 327 u_int32_t h = 0; 328 329 if (mac == NULL) 330 return(EINVAL); 331 332 h = sf_calchash(mac); 333 334 if (prio) { 335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 337 } else { 338 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 339 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 340 } 341 342 return(0); 343 } 344 345 #ifdef notdef 346 /* 347 * Set a VLAN tag in the receive filter. 348 */ 349 static int sf_setvlan(sc, idx, vlan) 350 struct sf_softc *sc; 351 int idx; 352 u_int32_t vlan; 353 { 354 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 355 return(EINVAL); 356 357 csr_write_4(sc, SF_RXFILT_HASH_BASE + 358 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 359 360 return(0); 361 } 362 #endif 363 364 static int sf_miibus_readreg(dev, phy, reg) 365 device_t dev; 366 int phy, reg; 367 { 368 struct sf_softc *sc; 369 int i; 370 u_int32_t val = 0; 371 372 sc = device_get_softc(dev); 373 374 for (i = 0; i < SF_TIMEOUT; i++) { 375 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 376 if (val & SF_MII_DATAVALID) 377 break; 378 } 379 380 if (i == SF_TIMEOUT) 381 return(0); 382 383 if ((val & 0x0000FFFF) == 0xFFFF) 384 return(0); 385 386 return(val & 0x0000FFFF); 387 } 388 389 static int sf_miibus_writereg(dev, phy, reg, val) 390 device_t dev; 391 int phy, reg, val; 392 { 393 struct sf_softc *sc; 394 int i; 395 int busy; 396 397 sc = device_get_softc(dev); 398 399 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 400 401 for (i = 0; i < SF_TIMEOUT; i++) { 402 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 403 if (!(busy & SF_MII_BUSY)) 404 break; 405 } 406 407 return(0); 408 } 409 410 static void sf_miibus_statchg(dev) 411 device_t dev; 412 { 413 struct sf_softc *sc; 414 struct mii_data *mii; 415 416 sc = device_get_softc(dev); 417 mii = device_get_softc(sc->sf_miibus); 418 419 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 420 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 421 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 422 } else { 423 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 424 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 425 } 426 427 return; 428 } 429 430 static void sf_setmulti(sc) 431 struct sf_softc *sc; 432 { 433 struct ifnet *ifp; 434 int i; 435 struct ifmultiaddr *ifma; 436 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 437 438 ifp = &sc->arpcom.ac_if; 439 440 /* First zot all the existing filters. */ 441 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 442 sf_setperf(sc, i, (char *)&dummy); 443 for (i = SF_RXFILT_HASH_BASE; 444 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 445 csr_write_4(sc, i, 0); 446 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 447 448 /* Now program new ones. */ 449 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 450 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 451 } else { 452 i = 1; 453 /* First find the tail of the list. */ 454 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 455 ifma = ifma->ifma_link.le_next) { 456 if (ifma->ifma_link.le_next == NULL) 457 break; 458 } 459 /* Now traverse the list backwards. */ 460 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 461 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 462 if (ifma->ifma_addr->sa_family != AF_LINK) 463 continue; 464 /* 465 * Program the first 15 multicast groups 466 * into the perfect filter. For all others, 467 * use the hash table. 468 */ 469 if (i < SF_RXFILT_PERFECT_CNT) { 470 sf_setperf(sc, i, 471 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 472 i++; 473 continue; 474 } 475 476 sf_sethash(sc, 477 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 478 } 479 } 480 481 return; 482 } 483 484 /* 485 * Set media options. 486 */ 487 static int sf_ifmedia_upd(ifp) 488 struct ifnet *ifp; 489 { 490 struct sf_softc *sc; 491 struct mii_data *mii; 492 493 sc = ifp->if_softc; 494 mii = device_get_softc(sc->sf_miibus); 495 sc->sf_link = 0; 496 if (mii->mii_instance) { 497 struct mii_softc *miisc; 498 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 499 miisc = LIST_NEXT(miisc, mii_list)) 500 mii_phy_reset(miisc); 501 } 502 mii_mediachg(mii); 503 504 return(0); 505 } 506 507 /* 508 * Report current media status. 509 */ 510 static void sf_ifmedia_sts(ifp, ifmr) 511 struct ifnet *ifp; 512 struct ifmediareq *ifmr; 513 { 514 struct sf_softc *sc; 515 struct mii_data *mii; 516 517 sc = ifp->if_softc; 518 mii = device_get_softc(sc->sf_miibus); 519 520 mii_pollstat(mii); 521 ifmr->ifm_active = mii->mii_media_active; 522 ifmr->ifm_status = mii->mii_media_status; 523 524 return; 525 } 526 527 static int sf_ioctl(ifp, command, data, cr) 528 struct ifnet *ifp; 529 u_long command; 530 caddr_t data; 531 struct ucred *cr; 532 { 533 struct sf_softc *sc = ifp->if_softc; 534 struct ifreq *ifr = (struct ifreq *) data; 535 struct mii_data *mii; 536 int error = 0; 537 538 switch(command) { 539 case SIOCSIFFLAGS: 540 if (ifp->if_flags & IFF_UP) { 541 if (ifp->if_flags & IFF_RUNNING && 542 ifp->if_flags & IFF_PROMISC && 543 !(sc->sf_if_flags & IFF_PROMISC)) { 544 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 545 } else if (ifp->if_flags & IFF_RUNNING && 546 !(ifp->if_flags & IFF_PROMISC) && 547 sc->sf_if_flags & IFF_PROMISC) { 548 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 549 } else if (!(ifp->if_flags & IFF_RUNNING)) 550 sf_init(sc); 551 } else { 552 if (ifp->if_flags & IFF_RUNNING) 553 sf_stop(sc); 554 } 555 sc->sf_if_flags = ifp->if_flags; 556 error = 0; 557 break; 558 case SIOCADDMULTI: 559 case SIOCDELMULTI: 560 sf_setmulti(sc); 561 error = 0; 562 break; 563 case SIOCGIFMEDIA: 564 case SIOCSIFMEDIA: 565 mii = device_get_softc(sc->sf_miibus); 566 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 567 break; 568 default: 569 error = ether_ioctl(ifp, command, data); 570 break; 571 } 572 573 return(error); 574 } 575 576 static void sf_reset(sc) 577 struct sf_softc *sc; 578 { 579 int i; 580 581 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 582 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 583 DELAY(1000); 584 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 585 586 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 587 588 for (i = 0; i < SF_TIMEOUT; i++) { 589 DELAY(10); 590 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 591 break; 592 } 593 594 if (i == SF_TIMEOUT) 595 printf("sf%d: reset never completed!\n", sc->sf_unit); 596 597 /* Wait a little while for the chip to get its brains in order. */ 598 DELAY(1000); 599 return; 600 } 601 602 /* 603 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 604 * IDs against our list and return a device name if we find a match. 605 * We also check the subsystem ID so that we can identify exactly which 606 * NIC has been found, if possible. 607 */ 608 static int sf_probe(dev) 609 device_t dev; 610 { 611 struct sf_type *t; 612 613 t = sf_devs; 614 615 while(t->sf_name != NULL) { 616 if ((pci_get_vendor(dev) == t->sf_vid) && 617 (pci_get_device(dev) == t->sf_did)) { 618 switch((pci_read_config(dev, 619 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 620 case AD_SUBSYSID_62011_REV0: 621 case AD_SUBSYSID_62011_REV1: 622 device_set_desc(dev, 623 "Adaptec ANA-62011 10/100BaseTX"); 624 return(0); 625 break; 626 case AD_SUBSYSID_62022: 627 device_set_desc(dev, 628 "Adaptec ANA-62022 10/100BaseTX"); 629 return(0); 630 break; 631 case AD_SUBSYSID_62044_REV0: 632 case AD_SUBSYSID_62044_REV1: 633 device_set_desc(dev, 634 "Adaptec ANA-62044 10/100BaseTX"); 635 return(0); 636 break; 637 case AD_SUBSYSID_62020: 638 device_set_desc(dev, 639 "Adaptec ANA-62020 10/100BaseFX"); 640 return(0); 641 break; 642 case AD_SUBSYSID_69011: 643 device_set_desc(dev, 644 "Adaptec ANA-69011 10/100BaseTX"); 645 return(0); 646 break; 647 default: 648 device_set_desc(dev, t->sf_name); 649 return(0); 650 break; 651 } 652 } 653 t++; 654 } 655 656 return(ENXIO); 657 } 658 659 /* 660 * Attach the interface. Allocate softc structures, do ifmedia 661 * setup and ethernet/BPF attach. 662 */ 663 static int sf_attach(dev) 664 device_t dev; 665 { 666 int i; 667 u_int32_t command; 668 struct sf_softc *sc; 669 struct ifnet *ifp; 670 int unit, rid, error = 0; 671 672 sc = device_get_softc(dev); 673 unit = device_get_unit(dev); 674 675 /* 676 * Handle power management nonsense. 677 */ 678 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 679 if (command == 0x01) { 680 681 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 682 if (command & SF_PSTATE_MASK) { 683 u_int32_t iobase, membase, irq; 684 685 /* Save important PCI config data. */ 686 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 687 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 688 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 689 690 /* Reset the power state. */ 691 printf("sf%d: chip is in D%d power mode " 692 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 693 command &= 0xFFFFFFFC; 694 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 695 696 /* Restore PCI config data. */ 697 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 698 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 699 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 700 } 701 } 702 703 /* 704 * Map control/status registers. 705 */ 706 command = pci_read_config(dev, PCIR_COMMAND, 4); 707 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 708 pci_write_config(dev, PCIR_COMMAND, command, 4); 709 command = pci_read_config(dev, PCIR_COMMAND, 4); 710 711 #ifdef SF_USEIOSPACE 712 if (!(command & PCIM_CMD_PORTEN)) { 713 printf("sf%d: failed to enable I/O ports!\n", unit); 714 error = ENXIO; 715 return(error); 716 } 717 #else 718 if (!(command & PCIM_CMD_MEMEN)) { 719 printf("sf%d: failed to enable memory mapping!\n", unit); 720 error = ENXIO; 721 return(error); 722 } 723 #endif 724 725 rid = SF_RID; 726 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 727 728 if (sc->sf_res == NULL) { 729 printf ("sf%d: couldn't map ports\n", unit); 730 error = ENXIO; 731 return(error); 732 } 733 734 sc->sf_btag = rman_get_bustag(sc->sf_res); 735 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 736 737 /* Allocate interrupt */ 738 rid = 0; 739 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 740 RF_SHAREABLE | RF_ACTIVE); 741 742 if (sc->sf_irq == NULL) { 743 printf("sf%d: couldn't map interrupt\n", unit); 744 error = ENXIO; 745 goto fail; 746 } 747 748 callout_init(&sc->sf_stat_timer); 749 750 /* Reset the adapter. */ 751 sf_reset(sc); 752 753 /* 754 * Get station address from the EEPROM. 755 */ 756 for (i = 0; i < ETHER_ADDR_LEN; i++) 757 sc->arpcom.ac_enaddr[i] = 758 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 759 760 sc->sf_unit = unit; 761 762 /* Allocate the descriptor queues. */ 763 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 764 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 765 766 if (sc->sf_ldata == NULL) { 767 printf("sf%d: no memory for list buffers!\n", unit); 768 error = ENXIO; 769 goto fail; 770 } 771 772 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 773 774 /* Do MII setup. */ 775 if (mii_phy_probe(dev, &sc->sf_miibus, 776 sf_ifmedia_upd, sf_ifmedia_sts)) { 777 printf("sf%d: MII without any phy!\n", sc->sf_unit); 778 error = ENXIO; 779 goto fail; 780 } 781 782 ifp = &sc->arpcom.ac_if; 783 ifp->if_softc = sc; 784 if_initname(ifp, "sf", unit); 785 ifp->if_mtu = ETHERMTU; 786 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 787 ifp->if_ioctl = sf_ioctl; 788 ifp->if_start = sf_start; 789 ifp->if_watchdog = sf_watchdog; 790 ifp->if_init = sf_init; 791 ifp->if_baudrate = 10000000; 792 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 793 ifq_set_ready(&ifp->if_snd); 794 795 /* 796 * Call MI attach routine. 797 */ 798 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 799 800 error = bus_setup_intr(dev, sc->sf_irq, INTR_NETSAFE, 801 sf_intr, sc, &sc->sf_intrhand, 802 ifp->if_serializer); 803 804 if (error) { 805 ether_ifdetach(ifp); 806 device_printf(dev, "couldn't set up irq\n"); 807 goto fail; 808 } 809 810 return(0); 811 812 fail: 813 sf_detach(dev); 814 return(error); 815 } 816 817 static int sf_detach(dev) 818 device_t dev; 819 { 820 struct sf_softc *sc = device_get_softc(dev); 821 struct ifnet *ifp = &sc->arpcom.ac_if; 822 823 lwkt_serialize_enter(ifp->if_serializer); 824 825 if (device_is_attached(dev)) { 826 ether_ifdetach(ifp); 827 sf_stop(sc); 828 } 829 830 if (sc->sf_miibus) 831 device_delete_child(dev, sc->sf_miibus); 832 bus_generic_detach(dev); 833 834 if (sc->sf_intrhand) 835 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 836 837 if (sc->sf_irq) 838 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 839 if(sc->sf_res) 840 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 841 842 if (sc->sf_ldata) { 843 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), 844 M_DEVBUF); 845 } 846 847 lwkt_serialize_exit(ifp->if_serializer); 848 return(0); 849 } 850 851 static int sf_init_rx_ring(sc) 852 struct sf_softc *sc; 853 { 854 struct sf_list_data *ld; 855 int i; 856 857 ld = sc->sf_ldata; 858 859 bzero((char *)ld->sf_rx_dlist_big, 860 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 861 bzero((char *)ld->sf_rx_clist, 862 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 863 864 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 865 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 866 return(ENOBUFS); 867 } 868 869 return(0); 870 } 871 872 static void sf_init_tx_ring(sc) 873 struct sf_softc *sc; 874 { 875 struct sf_list_data *ld; 876 int i; 877 878 ld = sc->sf_ldata; 879 880 bzero((char *)ld->sf_tx_dlist, 881 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 882 bzero((char *)ld->sf_tx_clist, 883 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 884 885 for (i = 0; i < SF_TX_DLIST_CNT; i++) 886 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 887 for (i = 0; i < SF_TX_CLIST_CNT; i++) 888 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 889 890 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 891 sc->sf_tx_cnt = 0; 892 893 return; 894 } 895 896 static int sf_newbuf(sc, c, m) 897 struct sf_softc *sc; 898 struct sf_rx_bufdesc_type0 *c; 899 struct mbuf *m; 900 { 901 struct mbuf *m_new = NULL; 902 903 if (m == NULL) { 904 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 905 if (m_new == NULL) 906 return(ENOBUFS); 907 908 MCLGET(m_new, MB_DONTWAIT); 909 if (!(m_new->m_flags & M_EXT)) { 910 m_freem(m_new); 911 return(ENOBUFS); 912 } 913 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 914 } else { 915 m_new = m; 916 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 917 m_new->m_data = m_new->m_ext.ext_buf; 918 } 919 920 m_adj(m_new, sizeof(u_int64_t)); 921 922 c->sf_mbuf = m_new; 923 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 924 c->sf_valid = 1; 925 926 return(0); 927 } 928 929 /* 930 * The starfire is programmed to use 'normal' mode for packet reception, 931 * which means we use the consumer/producer model for both the buffer 932 * descriptor queue and the completion descriptor queue. The only problem 933 * with this is that it involves a lot of register accesses: we have to 934 * read the RX completion consumer and producer indexes and the RX buffer 935 * producer index, plus the RX completion consumer and RX buffer producer 936 * indexes have to be updated. It would have been easier if Adaptec had 937 * put each index in a separate register, especially given that the damn 938 * NIC has a 512K register space. 939 * 940 * In spite of all the lovely features that Adaptec crammed into the 6915, 941 * it is marred by one truly stupid design flaw, which is that receive 942 * buffer addresses must be aligned on a longword boundary. This forces 943 * the packet payload to be unaligned, which is suboptimal on the x86 and 944 * completely unuseable on the Alpha. Our only recourse is to copy received 945 * packets into properly aligned buffers before handing them off. 946 */ 947 948 static void sf_rxeof(sc) 949 struct sf_softc *sc; 950 { 951 struct mbuf *m; 952 struct ifnet *ifp; 953 struct sf_rx_bufdesc_type0 *desc; 954 struct sf_rx_cmpdesc_type3 *cur_rx; 955 u_int32_t rxcons, rxprod; 956 int cmpprodidx, cmpconsidx, bufprodidx; 957 958 ifp = &sc->arpcom.ac_if; 959 960 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 961 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 962 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 963 cmpconsidx = SF_IDX_LO(rxcons); 964 bufprodidx = SF_IDX_LO(rxprod); 965 966 while (cmpconsidx != cmpprodidx) { 967 struct mbuf *m0; 968 969 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 970 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 971 m = desc->sf_mbuf; 972 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 973 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 974 975 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 976 ifp->if_ierrors++; 977 sf_newbuf(sc, desc, m); 978 continue; 979 } 980 981 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 982 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 983 sf_newbuf(sc, desc, m); 984 if (m0 == NULL) { 985 ifp->if_ierrors++; 986 continue; 987 } 988 m_adj(m0, ETHER_ALIGN); 989 m = m0; 990 991 ifp->if_ipackets++; 992 993 ifp->if_input(ifp, m); 994 } 995 996 csr_write_4(sc, SF_CQ_CONSIDX, 997 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 998 csr_write_4(sc, SF_RXDQ_PTR_Q1, 999 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1000 1001 return; 1002 } 1003 1004 /* 1005 * Read the transmit status from the completion queue and release 1006 * mbufs. Note that the buffer descriptor index in the completion 1007 * descriptor is an offset from the start of the transmit buffer 1008 * descriptor list in bytes. This is important because the manual 1009 * gives the impression that it should match the producer/consumer 1010 * index, which is the offset in 8 byte blocks. 1011 */ 1012 static void sf_txeof(sc) 1013 struct sf_softc *sc; 1014 { 1015 int txcons, cmpprodidx, cmpconsidx; 1016 struct sf_tx_cmpdesc_type1 *cur_cmp; 1017 struct sf_tx_bufdesc_type0 *cur_tx; 1018 struct ifnet *ifp; 1019 1020 ifp = &sc->arpcom.ac_if; 1021 1022 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1023 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1024 cmpconsidx = SF_IDX_HI(txcons); 1025 1026 while (cmpconsidx != cmpprodidx) { 1027 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1028 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1029 1030 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1031 ifp->if_opackets++; 1032 else { 1033 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1034 sf_txthresh_adjust(sc); 1035 ifp->if_oerrors++; 1036 } 1037 1038 sc->sf_tx_cnt--; 1039 if (cur_tx->sf_mbuf != NULL) { 1040 m_freem(cur_tx->sf_mbuf); 1041 cur_tx->sf_mbuf = NULL; 1042 } else 1043 break; 1044 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1045 } 1046 1047 ifp->if_timer = 0; 1048 ifp->if_flags &= ~IFF_OACTIVE; 1049 1050 csr_write_4(sc, SF_CQ_CONSIDX, 1051 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1052 ((cmpconsidx << 16) & 0xFFFF0000)); 1053 1054 return; 1055 } 1056 1057 static void sf_txthresh_adjust(sc) 1058 struct sf_softc *sc; 1059 { 1060 u_int32_t txfctl; 1061 u_int8_t txthresh; 1062 1063 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1064 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1065 if (txthresh < 0xFF) { 1066 txthresh++; 1067 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1068 txfctl |= txthresh; 1069 #ifdef DIAGNOSTIC 1070 printf("sf%d: tx underrun, increasing " 1071 "tx threshold to %d bytes\n", 1072 sc->sf_unit, txthresh * 4); 1073 #endif 1074 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1075 } 1076 1077 return; 1078 } 1079 1080 static void sf_intr(arg) 1081 void *arg; 1082 { 1083 struct sf_softc *sc; 1084 struct ifnet *ifp; 1085 u_int32_t status; 1086 1087 sc = arg; 1088 ifp = &sc->arpcom.ac_if; 1089 1090 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1091 return; 1092 1093 /* Disable interrupts. */ 1094 csr_write_4(sc, SF_IMR, 0x00000000); 1095 1096 for (;;) { 1097 status = csr_read_4(sc, SF_ISR); 1098 if (status) 1099 csr_write_4(sc, SF_ISR, status); 1100 1101 if (!(status & SF_INTRS)) 1102 break; 1103 1104 if (status & SF_ISR_RXDQ1_DMADONE) 1105 sf_rxeof(sc); 1106 1107 if (status & SF_ISR_TX_TXDONE || 1108 status & SF_ISR_TX_DMADONE || 1109 status & SF_ISR_TX_QUEUEDONE) 1110 sf_txeof(sc); 1111 1112 if (status & SF_ISR_TX_LOFIFO) 1113 sf_txthresh_adjust(sc); 1114 1115 if (status & SF_ISR_ABNORMALINTR) { 1116 if (status & SF_ISR_STATSOFLOW) { 1117 callout_stop(&sc->sf_stat_timer); 1118 sf_stats_update(sc); 1119 } else 1120 sf_init(sc); 1121 } 1122 } 1123 1124 /* Re-enable interrupts. */ 1125 csr_write_4(sc, SF_IMR, SF_INTRS); 1126 1127 if (!ifq_is_empty(&ifp->if_snd)) 1128 sf_start(ifp); 1129 1130 return; 1131 } 1132 1133 static void sf_init(xsc) 1134 void *xsc; 1135 { 1136 struct sf_softc *sc = xsc; 1137 struct ifnet *ifp = &sc->arpcom.ac_if; 1138 int i; 1139 1140 sf_stop(sc); 1141 sf_reset(sc); 1142 1143 /* Init all the receive filter registers */ 1144 for (i = SF_RXFILT_PERFECT_BASE; 1145 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1146 csr_write_4(sc, i, 0); 1147 1148 /* Empty stats counter registers. */ 1149 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1150 csr_write_4(sc, SF_STATS_BASE + 1151 (i + sizeof(u_int32_t)), 0); 1152 1153 /* Init our MAC address */ 1154 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1155 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1156 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1157 1158 if (sf_init_rx_ring(sc) == ENOBUFS) { 1159 printf("sf%d: initialization failed: no " 1160 "memory for rx buffers\n", sc->sf_unit); 1161 return; 1162 } 1163 1164 sf_init_tx_ring(sc); 1165 1166 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1167 1168 /* If we want promiscuous mode, set the allframes bit. */ 1169 if (ifp->if_flags & IFF_PROMISC) { 1170 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1171 } else { 1172 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1173 } 1174 1175 if (ifp->if_flags & IFF_BROADCAST) { 1176 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1177 } else { 1178 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1179 } 1180 1181 /* 1182 * Load the multicast filter. 1183 */ 1184 sf_setmulti(sc); 1185 1186 /* Init the completion queue indexes */ 1187 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1188 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1189 1190 /* Init the RX completion queue */ 1191 csr_write_4(sc, SF_RXCQ_CTL_1, 1192 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1193 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1194 1195 /* Init RX DMA control. */ 1196 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1197 1198 /* Init the RX buffer descriptor queue. */ 1199 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1200 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1201 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1202 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1203 1204 /* Init the TX completion queue */ 1205 csr_write_4(sc, SF_TXCQ_CTL, 1206 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1207 1208 /* Init the TX buffer descriptor queue. */ 1209 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1210 vtophys(sc->sf_ldata->sf_tx_dlist)); 1211 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1212 csr_write_4(sc, SF_TXDQ_CTL, 1213 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1214 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1215 1216 /* Enable autopadding of short TX frames. */ 1217 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1218 1219 /* Enable interrupts. */ 1220 csr_write_4(sc, SF_IMR, SF_INTRS); 1221 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1222 1223 /* Enable the RX and TX engines. */ 1224 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1225 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1226 1227 /*mii_mediachg(mii);*/ 1228 sf_ifmedia_upd(ifp); 1229 1230 ifp->if_flags |= IFF_RUNNING; 1231 ifp->if_flags &= ~IFF_OACTIVE; 1232 1233 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1234 } 1235 1236 static int sf_encap(sc, c, m_head) 1237 struct sf_softc *sc; 1238 struct sf_tx_bufdesc_type0 *c; 1239 struct mbuf *m_head; 1240 { 1241 int frag = 0; 1242 struct sf_frag *f = NULL; 1243 struct mbuf *m; 1244 1245 m = m_head; 1246 1247 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1248 if (m->m_len != 0) { 1249 if (frag == SF_MAXFRAGS) 1250 break; 1251 f = &c->sf_frags[frag]; 1252 if (frag == 0) 1253 f->sf_pktlen = m_head->m_pkthdr.len; 1254 f->sf_fraglen = m->m_len; 1255 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1256 frag++; 1257 } 1258 } 1259 1260 if (m != NULL) { 1261 struct mbuf *m_new = NULL; 1262 1263 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1264 if (m_new == NULL) { 1265 printf("sf%d: no memory for tx list", sc->sf_unit); 1266 return(1); 1267 } 1268 1269 if (m_head->m_pkthdr.len > MHLEN) { 1270 MCLGET(m_new, MB_DONTWAIT); 1271 if (!(m_new->m_flags & M_EXT)) { 1272 m_freem(m_new); 1273 printf("sf%d: no memory for tx list", 1274 sc->sf_unit); 1275 return(1); 1276 } 1277 } 1278 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1279 mtod(m_new, caddr_t)); 1280 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1281 m_freem(m_head); 1282 m_head = m_new; 1283 f = &c->sf_frags[0]; 1284 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1285 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1286 frag = 1; 1287 } 1288 1289 c->sf_mbuf = m_head; 1290 c->sf_id = SF_TX_BUFDESC_ID; 1291 c->sf_fragcnt = frag; 1292 c->sf_intr = 1; 1293 c->sf_caltcp = 0; 1294 c->sf_crcen = 1; 1295 1296 return(0); 1297 } 1298 1299 static void sf_start(ifp) 1300 struct ifnet *ifp; 1301 { 1302 struct sf_softc *sc; 1303 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1304 struct mbuf *m_head = NULL; 1305 int i, txprod; 1306 1307 sc = ifp->if_softc; 1308 1309 if (!sc->sf_link) 1310 return; 1311 1312 if (ifp->if_flags & IFF_OACTIVE) 1313 return; 1314 1315 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1316 i = SF_IDX_HI(txprod) >> 4; 1317 1318 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1319 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1320 sf_init(sc); 1321 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1322 i = SF_IDX_HI(txprod) >> 4; 1323 } 1324 1325 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1326 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1327 ifp->if_flags |= IFF_OACTIVE; 1328 cur_tx = NULL; 1329 break; 1330 } 1331 m_head = ifq_poll(&ifp->if_snd); 1332 if (m_head == NULL) 1333 break; 1334 1335 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1336 if (sf_encap(sc, cur_tx, m_head)) { 1337 ifp->if_flags |= IFF_OACTIVE; 1338 cur_tx = NULL; 1339 break; 1340 } 1341 ifq_dequeue(&ifp->if_snd, m_head); 1342 BPF_MTAP(ifp, cur_tx->sf_mbuf); 1343 1344 SF_INC(i, SF_TX_DLIST_CNT); 1345 sc->sf_tx_cnt++; 1346 /* 1347 * Don't get the TX DMA queue get too full. 1348 */ 1349 if (sc->sf_tx_cnt > 64) 1350 break; 1351 } 1352 1353 if (cur_tx == NULL) 1354 return; 1355 1356 /* Transmit */ 1357 csr_write_4(sc, SF_TXDQ_PRODIDX, 1358 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1359 ((i << 20) & 0xFFFF0000)); 1360 1361 ifp->if_timer = 5; 1362 1363 return; 1364 } 1365 1366 static void sf_stop(sc) 1367 struct sf_softc *sc; 1368 { 1369 int i; 1370 struct ifnet *ifp; 1371 1372 ifp = &sc->arpcom.ac_if; 1373 1374 callout_stop(&sc->sf_stat_timer); 1375 1376 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1377 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1378 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1379 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1380 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1381 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1382 csr_write_4(sc, SF_TXCQ_CTL, 0); 1383 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1384 csr_write_4(sc, SF_TXDQ_CTL, 0); 1385 sf_reset(sc); 1386 1387 sc->sf_link = 0; 1388 1389 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1390 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1391 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1392 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1393 } 1394 } 1395 1396 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1397 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1398 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1399 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1400 } 1401 } 1402 1403 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1404 1405 return; 1406 } 1407 1408 /* 1409 * Note: it is important that this function not be interrupted. We 1410 * use a two-stage register access scheme: if we are interrupted in 1411 * between setting the indirect address register and reading from the 1412 * indirect data register, the contents of the address register could 1413 * be changed out from under us. 1414 */ 1415 static void sf_stats_update(xsc) 1416 void *xsc; 1417 { 1418 struct sf_softc *sc = xsc; 1419 struct ifnet *ifp = &sc->arpcom.ac_if; 1420 struct mii_data *mii = device_get_softc(sc->sf_miibus); 1421 struct sf_stats stats; 1422 u_int32_t *ptr; 1423 int i; 1424 1425 lwkt_serialize_enter(ifp->if_serializer); 1426 1427 ptr = (u_int32_t *)&stats; 1428 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1429 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1430 (i + sizeof(u_int32_t))); 1431 1432 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1433 csr_write_4(sc, SF_STATS_BASE + 1434 (i + sizeof(u_int32_t)), 0); 1435 1436 ifp->if_collisions += stats.sf_tx_single_colls + 1437 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1438 1439 mii_tick(mii); 1440 if (!sc->sf_link) { 1441 mii_pollstat(mii); 1442 if (mii->mii_media_status & IFM_ACTIVE && 1443 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1444 sc->sf_link++; 1445 if (!ifq_is_empty(&ifp->if_snd)) 1446 sf_start(ifp); 1447 } 1448 1449 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1450 1451 lwkt_serialize_exit(ifp->if_serializer); 1452 } 1453 1454 static void sf_watchdog(ifp) 1455 struct ifnet *ifp; 1456 { 1457 struct sf_softc *sc; 1458 1459 sc = ifp->if_softc; 1460 1461 ifp->if_oerrors++; 1462 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1463 1464 sf_stop(sc); 1465 sf_reset(sc); 1466 sf_init(sc); 1467 1468 if (!ifq_is_empty(&ifp->if_snd)) 1469 sf_start(ifp); 1470 1471 return; 1472 } 1473 1474 static void sf_shutdown(dev) 1475 device_t dev; 1476 { 1477 struct sf_softc *sc; 1478 struct ifnet *ifp; 1479 1480 sc = device_get_softc(dev); 1481 ifp = &sc->arpcom.ac_if; 1482 lwkt_serialize_enter(ifp->if_serializer); 1483 sf_stop(sc); 1484 lwkt_serialize_exit(ifp->if_serializer); 1485 1486 return; 1487 } 1488