1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.19 2005/05/27 15:36:10 joerg Exp $ 34 */ 35 36 /* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45 46 /* 47 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 48 * controller designed with flexibility and reducing CPU load in mind. 49 * The Starfire offers high and low priority buffer queues, a 50 * producer/consumer index mechanism and several different buffer 51 * queue and completion queue descriptor types. Any one of a number 52 * of different driver designs can be used, depending on system and 53 * OS requirements. This driver makes use of type0 transmit frame 54 * descriptors (since BSD fragments packets across an mbuf chain) 55 * and two RX buffer queues prioritized on size (one queue for small 56 * frames that will fit into a single mbuf, another with full size 57 * mbuf clusters for everything else). The producer/consumer indexes 58 * and completion queues are also used. 59 * 60 * One downside to the Starfire has to do with alignment: buffer 61 * queues must be aligned on 256-byte boundaries, and receive buffers 62 * must be aligned on longword boundaries. The receive buffer alignment 63 * causes problems on the Alpha platform, where the packet payload 64 * should be longword aligned. There is no simple way around this. 65 * 66 * For receive filtering, the Starfire offers 16 perfect filter slots 67 * and a 512-bit hash table. 68 * 69 * The Starfire has no internal transceiver, relying instead on an 70 * external MII-based transceiver. Accessing registers on external 71 * PHYs is done through a special register map rather than with the 72 * usual bitbang MDIO method. 73 * 74 * Acesssing the registers on the Starfire is a little tricky. The 75 * Starfire has a 512K internal register space. When programmed for 76 * PCI memory mapped mode, the entire register space can be accessed 77 * directly. However in I/O space mode, only 256 bytes are directly 78 * mapped into PCI I/O space. The other registers can be accessed 79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 80 * registers inside the 256-byte I/O window. 81 */ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/socket.h> 90 91 #include <net/if.h> 92 #include <net/ifq_var.h> 93 #include <net/if_arp.h> 94 #include <net/ethernet.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 98 #include <net/bpf.h> 99 100 #include <vm/vm.h> /* for vtophys */ 101 #include <vm/pmap.h> /* for vtophys */ 102 #include <machine/clock.h> /* for DELAY */ 103 #include <machine/bus_pio.h> 104 #include <machine/bus_memio.h> 105 #include <machine/bus.h> 106 #include <machine/resource.h> 107 #include <sys/bus.h> 108 #include <sys/rman.h> 109 110 #include "../mii_layer/mii.h" 111 #include "../mii_layer/miivar.h" 112 113 /* "controller miibus0" required. See GENERIC if you get errors here. */ 114 #include "miibus_if.h" 115 116 #include <bus/pci/pcireg.h> 117 #include <bus/pci/pcivar.h> 118 119 #define SF_USEIOSPACE 120 121 #include "if_sfreg.h" 122 123 static struct sf_type sf_devs[] = { 124 { AD_VENDORID, AD_DEVICEID_STARFIRE, 125 "Adaptec AIC-6915 10/100BaseTX" }, 126 { 0, 0, NULL } 127 }; 128 129 static int sf_probe (device_t); 130 static int sf_attach (device_t); 131 static int sf_detach (device_t); 132 static void sf_intr (void *); 133 static void sf_stats_update (void *); 134 static void sf_rxeof (struct sf_softc *); 135 static void sf_txeof (struct sf_softc *); 136 static int sf_encap (struct sf_softc *, 137 struct sf_tx_bufdesc_type0 *, 138 struct mbuf *); 139 static void sf_start (struct ifnet *); 140 static int sf_ioctl (struct ifnet *, u_long, caddr_t, 141 struct ucred *); 142 static void sf_init (void *); 143 static void sf_stop (struct sf_softc *); 144 static void sf_watchdog (struct ifnet *); 145 static void sf_shutdown (device_t); 146 static int sf_ifmedia_upd (struct ifnet *); 147 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148 static void sf_reset (struct sf_softc *); 149 static int sf_init_rx_ring (struct sf_softc *); 150 static void sf_init_tx_ring (struct sf_softc *); 151 static int sf_newbuf (struct sf_softc *, 152 struct sf_rx_bufdesc_type0 *, 153 struct mbuf *); 154 static void sf_setmulti (struct sf_softc *); 155 static int sf_setperf (struct sf_softc *, int, caddr_t); 156 static int sf_sethash (struct sf_softc *, caddr_t, int); 157 #ifdef notdef 158 static int sf_setvlan (struct sf_softc *, int, u_int32_t); 159 #endif 160 161 static u_int8_t sf_read_eeprom (struct sf_softc *, int); 162 static u_int32_t sf_calchash (caddr_t); 163 164 static int sf_miibus_readreg (device_t, int, int); 165 static int sf_miibus_writereg (device_t, int, int, int); 166 static void sf_miibus_statchg (device_t); 167 168 static u_int32_t csr_read_4 (struct sf_softc *, int); 169 static void csr_write_4 (struct sf_softc *, int, u_int32_t); 170 static void sf_txthresh_adjust (struct sf_softc *); 171 172 #ifdef SF_USEIOSPACE 173 #define SF_RES SYS_RES_IOPORT 174 #define SF_RID SF_PCI_LOIO 175 #else 176 #define SF_RES SYS_RES_MEMORY 177 #define SF_RID SF_PCI_LOMEM 178 #endif 179 180 static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197 }; 198 199 static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203 }; 204 205 static devclass_t sf_devclass; 206 207 DECLARE_DUMMY_MODULE(if_sf); 208 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 209 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 210 211 #define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 213 214 #define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 216 217 static u_int32_t csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220 { 221 u_int32_t val; 222 223 #ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226 #else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228 #endif 229 230 return(val); 231 } 232 233 static u_int8_t sf_read_eeprom(sc, reg) 234 struct sf_softc *sc; 235 int reg; 236 { 237 u_int8_t val; 238 239 val = (csr_read_4(sc, SF_EEADDR_BASE + 240 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 241 242 return(val); 243 } 244 245 static void csr_write_4(sc, reg, val) 246 struct sf_softc *sc; 247 int reg; 248 u_int32_t val; 249 { 250 #ifdef SF_USEIOSPACE 251 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 252 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 253 #else 254 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 255 #endif 256 return; 257 } 258 259 static u_int32_t sf_calchash(addr) 260 caddr_t addr; 261 { 262 u_int32_t crc, carry; 263 int i, j; 264 u_int8_t c; 265 266 /* Compute CRC for the address value. */ 267 crc = 0xFFFFFFFF; /* initial value */ 268 269 for (i = 0; i < 6; i++) { 270 c = *(addr + i); 271 for (j = 0; j < 8; j++) { 272 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 273 crc <<= 1; 274 c >>= 1; 275 if (carry) 276 crc = (crc ^ 0x04c11db6) | carry; 277 } 278 } 279 280 /* return the filter bit position */ 281 return(crc >> 23 & 0x1FF); 282 } 283 284 /* 285 * Copy the address 'mac' into the perfect RX filter entry at 286 * offset 'idx.' The perfect filter only has 16 entries so do 287 * some sanity tests. 288 */ 289 static int sf_setperf(sc, idx, mac) 290 struct sf_softc *sc; 291 int idx; 292 caddr_t mac; 293 { 294 u_int16_t *p; 295 296 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 297 return(EINVAL); 298 299 if (mac == NULL) 300 return(EINVAL); 301 302 p = (u_int16_t *)mac; 303 304 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 305 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 310 311 return(0); 312 } 313 314 /* 315 * Set the bit in the 512-bit hash table that corresponds to the 316 * specified mac address 'mac.' If 'prio' is nonzero, update the 317 * priority hash table instead of the filter hash table. 318 */ 319 static int sf_sethash(sc, mac, prio) 320 struct sf_softc *sc; 321 caddr_t mac; 322 int prio; 323 { 324 u_int32_t h = 0; 325 326 if (mac == NULL) 327 return(EINVAL); 328 329 h = sf_calchash(mac); 330 331 if (prio) { 332 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 333 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 334 } else { 335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 337 } 338 339 return(0); 340 } 341 342 #ifdef notdef 343 /* 344 * Set a VLAN tag in the receive filter. 345 */ 346 static int sf_setvlan(sc, idx, vlan) 347 struct sf_softc *sc; 348 int idx; 349 u_int32_t vlan; 350 { 351 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 352 return(EINVAL); 353 354 csr_write_4(sc, SF_RXFILT_HASH_BASE + 355 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 356 357 return(0); 358 } 359 #endif 360 361 static int sf_miibus_readreg(dev, phy, reg) 362 device_t dev; 363 int phy, reg; 364 { 365 struct sf_softc *sc; 366 int i; 367 u_int32_t val = 0; 368 369 sc = device_get_softc(dev); 370 371 for (i = 0; i < SF_TIMEOUT; i++) { 372 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 373 if (val & SF_MII_DATAVALID) 374 break; 375 } 376 377 if (i == SF_TIMEOUT) 378 return(0); 379 380 if ((val & 0x0000FFFF) == 0xFFFF) 381 return(0); 382 383 return(val & 0x0000FFFF); 384 } 385 386 static int sf_miibus_writereg(dev, phy, reg, val) 387 device_t dev; 388 int phy, reg, val; 389 { 390 struct sf_softc *sc; 391 int i; 392 int busy; 393 394 sc = device_get_softc(dev); 395 396 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 397 398 for (i = 0; i < SF_TIMEOUT; i++) { 399 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 400 if (!(busy & SF_MII_BUSY)) 401 break; 402 } 403 404 return(0); 405 } 406 407 static void sf_miibus_statchg(dev) 408 device_t dev; 409 { 410 struct sf_softc *sc; 411 struct mii_data *mii; 412 413 sc = device_get_softc(dev); 414 mii = device_get_softc(sc->sf_miibus); 415 416 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 417 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 418 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 419 } else { 420 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 421 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 422 } 423 424 return; 425 } 426 427 static void sf_setmulti(sc) 428 struct sf_softc *sc; 429 { 430 struct ifnet *ifp; 431 int i; 432 struct ifmultiaddr *ifma; 433 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 434 435 ifp = &sc->arpcom.ac_if; 436 437 /* First zot all the existing filters. */ 438 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 439 sf_setperf(sc, i, (char *)&dummy); 440 for (i = SF_RXFILT_HASH_BASE; 441 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 442 csr_write_4(sc, i, 0); 443 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 444 445 /* Now program new ones. */ 446 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 447 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 448 } else { 449 i = 1; 450 /* First find the tail of the list. */ 451 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 452 ifma = ifma->ifma_link.le_next) { 453 if (ifma->ifma_link.le_next == NULL) 454 break; 455 } 456 /* Now traverse the list backwards. */ 457 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 458 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 459 if (ifma->ifma_addr->sa_family != AF_LINK) 460 continue; 461 /* 462 * Program the first 15 multicast groups 463 * into the perfect filter. For all others, 464 * use the hash table. 465 */ 466 if (i < SF_RXFILT_PERFECT_CNT) { 467 sf_setperf(sc, i, 468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 469 i++; 470 continue; 471 } 472 473 sf_sethash(sc, 474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 475 } 476 } 477 478 return; 479 } 480 481 /* 482 * Set media options. 483 */ 484 static int sf_ifmedia_upd(ifp) 485 struct ifnet *ifp; 486 { 487 struct sf_softc *sc; 488 struct mii_data *mii; 489 490 sc = ifp->if_softc; 491 mii = device_get_softc(sc->sf_miibus); 492 sc->sf_link = 0; 493 if (mii->mii_instance) { 494 struct mii_softc *miisc; 495 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 496 miisc = LIST_NEXT(miisc, mii_list)) 497 mii_phy_reset(miisc); 498 } 499 mii_mediachg(mii); 500 501 return(0); 502 } 503 504 /* 505 * Report current media status. 506 */ 507 static void sf_ifmedia_sts(ifp, ifmr) 508 struct ifnet *ifp; 509 struct ifmediareq *ifmr; 510 { 511 struct sf_softc *sc; 512 struct mii_data *mii; 513 514 sc = ifp->if_softc; 515 mii = device_get_softc(sc->sf_miibus); 516 517 mii_pollstat(mii); 518 ifmr->ifm_active = mii->mii_media_active; 519 ifmr->ifm_status = mii->mii_media_status; 520 521 return; 522 } 523 524 static int sf_ioctl(ifp, command, data, cr) 525 struct ifnet *ifp; 526 u_long command; 527 caddr_t data; 528 struct ucred *cr; 529 { 530 struct sf_softc *sc = ifp->if_softc; 531 struct ifreq *ifr = (struct ifreq *) data; 532 struct mii_data *mii; 533 int s, error = 0; 534 535 s = splimp(); 536 537 switch(command) { 538 case SIOCSIFFLAGS: 539 if (ifp->if_flags & IFF_UP) { 540 if (ifp->if_flags & IFF_RUNNING && 541 ifp->if_flags & IFF_PROMISC && 542 !(sc->sf_if_flags & IFF_PROMISC)) { 543 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 544 } else if (ifp->if_flags & IFF_RUNNING && 545 !(ifp->if_flags & IFF_PROMISC) && 546 sc->sf_if_flags & IFF_PROMISC) { 547 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 548 } else if (!(ifp->if_flags & IFF_RUNNING)) 549 sf_init(sc); 550 } else { 551 if (ifp->if_flags & IFF_RUNNING) 552 sf_stop(sc); 553 } 554 sc->sf_if_flags = ifp->if_flags; 555 error = 0; 556 break; 557 case SIOCADDMULTI: 558 case SIOCDELMULTI: 559 sf_setmulti(sc); 560 error = 0; 561 break; 562 case SIOCGIFMEDIA: 563 case SIOCSIFMEDIA: 564 mii = device_get_softc(sc->sf_miibus); 565 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 566 break; 567 default: 568 error = ether_ioctl(ifp, command, data); 569 break; 570 } 571 572 (void)splx(s); 573 574 return(error); 575 } 576 577 static void sf_reset(sc) 578 struct sf_softc *sc; 579 { 580 int i; 581 582 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 583 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 584 DELAY(1000); 585 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 586 587 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 588 589 for (i = 0; i < SF_TIMEOUT; i++) { 590 DELAY(10); 591 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 592 break; 593 } 594 595 if (i == SF_TIMEOUT) 596 printf("sf%d: reset never completed!\n", sc->sf_unit); 597 598 /* Wait a little while for the chip to get its brains in order. */ 599 DELAY(1000); 600 return; 601 } 602 603 /* 604 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 605 * IDs against our list and return a device name if we find a match. 606 * We also check the subsystem ID so that we can identify exactly which 607 * NIC has been found, if possible. 608 */ 609 static int sf_probe(dev) 610 device_t dev; 611 { 612 struct sf_type *t; 613 614 t = sf_devs; 615 616 while(t->sf_name != NULL) { 617 if ((pci_get_vendor(dev) == t->sf_vid) && 618 (pci_get_device(dev) == t->sf_did)) { 619 switch((pci_read_config(dev, 620 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 621 case AD_SUBSYSID_62011_REV0: 622 case AD_SUBSYSID_62011_REV1: 623 device_set_desc(dev, 624 "Adaptec ANA-62011 10/100BaseTX"); 625 return(0); 626 break; 627 case AD_SUBSYSID_62022: 628 device_set_desc(dev, 629 "Adaptec ANA-62022 10/100BaseTX"); 630 return(0); 631 break; 632 case AD_SUBSYSID_62044_REV0: 633 case AD_SUBSYSID_62044_REV1: 634 device_set_desc(dev, 635 "Adaptec ANA-62044 10/100BaseTX"); 636 return(0); 637 break; 638 case AD_SUBSYSID_62020: 639 device_set_desc(dev, 640 "Adaptec ANA-62020 10/100BaseFX"); 641 return(0); 642 break; 643 case AD_SUBSYSID_69011: 644 device_set_desc(dev, 645 "Adaptec ANA-69011 10/100BaseTX"); 646 return(0); 647 break; 648 default: 649 device_set_desc(dev, t->sf_name); 650 return(0); 651 break; 652 } 653 } 654 t++; 655 } 656 657 return(ENXIO); 658 } 659 660 /* 661 * Attach the interface. Allocate softc structures, do ifmedia 662 * setup and ethernet/BPF attach. 663 */ 664 static int sf_attach(dev) 665 device_t dev; 666 { 667 int s, i; 668 u_int32_t command; 669 struct sf_softc *sc; 670 struct ifnet *ifp; 671 int unit, rid, error = 0; 672 673 s = splimp(); 674 675 sc = device_get_softc(dev); 676 unit = device_get_unit(dev); 677 bzero(sc, sizeof(struct sf_softc)); 678 679 /* 680 * Handle power management nonsense. 681 */ 682 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 683 if (command == 0x01) { 684 685 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 686 if (command & SF_PSTATE_MASK) { 687 u_int32_t iobase, membase, irq; 688 689 /* Save important PCI config data. */ 690 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 691 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 692 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 693 694 /* Reset the power state. */ 695 printf("sf%d: chip is in D%d power mode " 696 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 697 command &= 0xFFFFFFFC; 698 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 699 700 /* Restore PCI config data. */ 701 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 702 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 703 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 704 } 705 } 706 707 /* 708 * Map control/status registers. 709 */ 710 command = pci_read_config(dev, PCIR_COMMAND, 4); 711 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 712 pci_write_config(dev, PCIR_COMMAND, command, 4); 713 command = pci_read_config(dev, PCIR_COMMAND, 4); 714 715 #ifdef SF_USEIOSPACE 716 if (!(command & PCIM_CMD_PORTEN)) { 717 printf("sf%d: failed to enable I/O ports!\n", unit); 718 error = ENXIO; 719 goto fail; 720 } 721 #else 722 if (!(command & PCIM_CMD_MEMEN)) { 723 printf("sf%d: failed to enable memory mapping!\n", unit); 724 error = ENXIO; 725 goto fail; 726 } 727 #endif 728 729 rid = SF_RID; 730 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 731 732 if (sc->sf_res == NULL) { 733 printf ("sf%d: couldn't map ports\n", unit); 734 error = ENXIO; 735 goto fail; 736 } 737 738 sc->sf_btag = rman_get_bustag(sc->sf_res); 739 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 740 741 /* Allocate interrupt */ 742 rid = 0; 743 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 744 RF_SHAREABLE | RF_ACTIVE); 745 746 if (sc->sf_irq == NULL) { 747 printf("sf%d: couldn't map interrupt\n", unit); 748 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 749 error = ENXIO; 750 goto fail; 751 } 752 753 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 754 sf_intr, sc, &sc->sf_intrhand, NULL); 755 756 if (error) { 757 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 758 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 759 printf("sf%d: couldn't set up irq\n", unit); 760 goto fail; 761 } 762 763 callout_init(&sc->sf_stat_timer); 764 765 /* Reset the adapter. */ 766 sf_reset(sc); 767 768 /* 769 * Get station address from the EEPROM. 770 */ 771 for (i = 0; i < ETHER_ADDR_LEN; i++) 772 sc->arpcom.ac_enaddr[i] = 773 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 774 775 sc->sf_unit = unit; 776 777 /* Allocate the descriptor queues. */ 778 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 779 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 780 781 if (sc->sf_ldata == NULL) { 782 printf("sf%d: no memory for list buffers!\n", unit); 783 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 784 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 785 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 786 error = ENXIO; 787 goto fail; 788 } 789 790 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 791 792 /* Do MII setup. */ 793 if (mii_phy_probe(dev, &sc->sf_miibus, 794 sf_ifmedia_upd, sf_ifmedia_sts)) { 795 printf("sf%d: MII without any phy!\n", sc->sf_unit); 796 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 797 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 798 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 799 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 800 error = ENXIO; 801 goto fail; 802 } 803 804 ifp = &sc->arpcom.ac_if; 805 ifp->if_softc = sc; 806 if_initname(ifp, "sf", unit); 807 ifp->if_mtu = ETHERMTU; 808 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 809 ifp->if_ioctl = sf_ioctl; 810 ifp->if_start = sf_start; 811 ifp->if_watchdog = sf_watchdog; 812 ifp->if_init = sf_init; 813 ifp->if_baudrate = 10000000; 814 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 815 ifq_set_ready(&ifp->if_snd); 816 817 /* 818 * Call MI attach routine. 819 */ 820 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 821 822 fail: 823 splx(s); 824 return(error); 825 } 826 827 static int sf_detach(dev) 828 device_t dev; 829 { 830 struct sf_softc *sc; 831 struct ifnet *ifp; 832 int s; 833 834 s = splimp(); 835 836 sc = device_get_softc(dev); 837 ifp = &sc->arpcom.ac_if; 838 839 ether_ifdetach(ifp); 840 sf_stop(sc); 841 842 bus_generic_detach(dev); 843 device_delete_child(dev, sc->sf_miibus); 844 845 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 846 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 847 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 848 849 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 850 851 splx(s); 852 853 return(0); 854 } 855 856 static int sf_init_rx_ring(sc) 857 struct sf_softc *sc; 858 { 859 struct sf_list_data *ld; 860 int i; 861 862 ld = sc->sf_ldata; 863 864 bzero((char *)ld->sf_rx_dlist_big, 865 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 866 bzero((char *)ld->sf_rx_clist, 867 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 868 869 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 870 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 871 return(ENOBUFS); 872 } 873 874 return(0); 875 } 876 877 static void sf_init_tx_ring(sc) 878 struct sf_softc *sc; 879 { 880 struct sf_list_data *ld; 881 int i; 882 883 ld = sc->sf_ldata; 884 885 bzero((char *)ld->sf_tx_dlist, 886 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 887 bzero((char *)ld->sf_tx_clist, 888 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 889 890 for (i = 0; i < SF_TX_DLIST_CNT; i++) 891 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 892 for (i = 0; i < SF_TX_CLIST_CNT; i++) 893 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 894 895 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 896 sc->sf_tx_cnt = 0; 897 898 return; 899 } 900 901 static int sf_newbuf(sc, c, m) 902 struct sf_softc *sc; 903 struct sf_rx_bufdesc_type0 *c; 904 struct mbuf *m; 905 { 906 struct mbuf *m_new = NULL; 907 908 if (m == NULL) { 909 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 910 if (m_new == NULL) 911 return(ENOBUFS); 912 913 MCLGET(m_new, MB_DONTWAIT); 914 if (!(m_new->m_flags & M_EXT)) { 915 m_freem(m_new); 916 return(ENOBUFS); 917 } 918 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 919 } else { 920 m_new = m; 921 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 922 m_new->m_data = m_new->m_ext.ext_buf; 923 } 924 925 m_adj(m_new, sizeof(u_int64_t)); 926 927 c->sf_mbuf = m_new; 928 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 929 c->sf_valid = 1; 930 931 return(0); 932 } 933 934 /* 935 * The starfire is programmed to use 'normal' mode for packet reception, 936 * which means we use the consumer/producer model for both the buffer 937 * descriptor queue and the completion descriptor queue. The only problem 938 * with this is that it involves a lot of register accesses: we have to 939 * read the RX completion consumer and producer indexes and the RX buffer 940 * producer index, plus the RX completion consumer and RX buffer producer 941 * indexes have to be updated. It would have been easier if Adaptec had 942 * put each index in a separate register, especially given that the damn 943 * NIC has a 512K register space. 944 * 945 * In spite of all the lovely features that Adaptec crammed into the 6915, 946 * it is marred by one truly stupid design flaw, which is that receive 947 * buffer addresses must be aligned on a longword boundary. This forces 948 * the packet payload to be unaligned, which is suboptimal on the x86 and 949 * completely unuseable on the Alpha. Our only recourse is to copy received 950 * packets into properly aligned buffers before handing them off. 951 */ 952 953 static void sf_rxeof(sc) 954 struct sf_softc *sc; 955 { 956 struct mbuf *m; 957 struct ifnet *ifp; 958 struct sf_rx_bufdesc_type0 *desc; 959 struct sf_rx_cmpdesc_type3 *cur_rx; 960 u_int32_t rxcons, rxprod; 961 int cmpprodidx, cmpconsidx, bufprodidx; 962 963 ifp = &sc->arpcom.ac_if; 964 965 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 966 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 967 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 968 cmpconsidx = SF_IDX_LO(rxcons); 969 bufprodidx = SF_IDX_LO(rxprod); 970 971 while (cmpconsidx != cmpprodidx) { 972 struct mbuf *m0; 973 974 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 975 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 976 m = desc->sf_mbuf; 977 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 978 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 979 980 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 981 ifp->if_ierrors++; 982 sf_newbuf(sc, desc, m); 983 continue; 984 } 985 986 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 987 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 988 sf_newbuf(sc, desc, m); 989 if (m0 == NULL) { 990 ifp->if_ierrors++; 991 continue; 992 } 993 m_adj(m0, ETHER_ALIGN); 994 m = m0; 995 996 ifp->if_ipackets++; 997 998 (*ifp->if_input)(ifp, m); 999 } 1000 1001 csr_write_4(sc, SF_CQ_CONSIDX, 1002 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1003 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1004 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1005 1006 return; 1007 } 1008 1009 /* 1010 * Read the transmit status from the completion queue and release 1011 * mbufs. Note that the buffer descriptor index in the completion 1012 * descriptor is an offset from the start of the transmit buffer 1013 * descriptor list in bytes. This is important because the manual 1014 * gives the impression that it should match the producer/consumer 1015 * index, which is the offset in 8 byte blocks. 1016 */ 1017 static void sf_txeof(sc) 1018 struct sf_softc *sc; 1019 { 1020 int txcons, cmpprodidx, cmpconsidx; 1021 struct sf_tx_cmpdesc_type1 *cur_cmp; 1022 struct sf_tx_bufdesc_type0 *cur_tx; 1023 struct ifnet *ifp; 1024 1025 ifp = &sc->arpcom.ac_if; 1026 1027 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1028 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1029 cmpconsidx = SF_IDX_HI(txcons); 1030 1031 while (cmpconsidx != cmpprodidx) { 1032 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1033 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1034 1035 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1036 ifp->if_opackets++; 1037 else { 1038 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1039 sf_txthresh_adjust(sc); 1040 ifp->if_oerrors++; 1041 } 1042 1043 sc->sf_tx_cnt--; 1044 if (cur_tx->sf_mbuf != NULL) { 1045 m_freem(cur_tx->sf_mbuf); 1046 cur_tx->sf_mbuf = NULL; 1047 } else 1048 break; 1049 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1050 } 1051 1052 ifp->if_timer = 0; 1053 ifp->if_flags &= ~IFF_OACTIVE; 1054 1055 csr_write_4(sc, SF_CQ_CONSIDX, 1056 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1057 ((cmpconsidx << 16) & 0xFFFF0000)); 1058 1059 return; 1060 } 1061 1062 static void sf_txthresh_adjust(sc) 1063 struct sf_softc *sc; 1064 { 1065 u_int32_t txfctl; 1066 u_int8_t txthresh; 1067 1068 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1069 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1070 if (txthresh < 0xFF) { 1071 txthresh++; 1072 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1073 txfctl |= txthresh; 1074 #ifdef DIAGNOSTIC 1075 printf("sf%d: tx underrun, increasing " 1076 "tx threshold to %d bytes\n", 1077 sc->sf_unit, txthresh * 4); 1078 #endif 1079 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1080 } 1081 1082 return; 1083 } 1084 1085 static void sf_intr(arg) 1086 void *arg; 1087 { 1088 struct sf_softc *sc; 1089 struct ifnet *ifp; 1090 u_int32_t status; 1091 1092 sc = arg; 1093 ifp = &sc->arpcom.ac_if; 1094 1095 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1096 return; 1097 1098 /* Disable interrupts. */ 1099 csr_write_4(sc, SF_IMR, 0x00000000); 1100 1101 for (;;) { 1102 status = csr_read_4(sc, SF_ISR); 1103 if (status) 1104 csr_write_4(sc, SF_ISR, status); 1105 1106 if (!(status & SF_INTRS)) 1107 break; 1108 1109 if (status & SF_ISR_RXDQ1_DMADONE) 1110 sf_rxeof(sc); 1111 1112 if (status & SF_ISR_TX_TXDONE || 1113 status & SF_ISR_TX_DMADONE || 1114 status & SF_ISR_TX_QUEUEDONE) 1115 sf_txeof(sc); 1116 1117 if (status & SF_ISR_TX_LOFIFO) 1118 sf_txthresh_adjust(sc); 1119 1120 if (status & SF_ISR_ABNORMALINTR) { 1121 if (status & SF_ISR_STATSOFLOW) { 1122 callout_stop(&sc->sf_stat_timer); 1123 sf_stats_update(sc); 1124 } else 1125 sf_init(sc); 1126 } 1127 } 1128 1129 /* Re-enable interrupts. */ 1130 csr_write_4(sc, SF_IMR, SF_INTRS); 1131 1132 if (!ifq_is_empty(&ifp->if_snd)) 1133 sf_start(ifp); 1134 1135 return; 1136 } 1137 1138 static void sf_init(xsc) 1139 void *xsc; 1140 { 1141 struct sf_softc *sc; 1142 struct ifnet *ifp; 1143 struct mii_data *mii; 1144 int i, s; 1145 1146 s = splimp(); 1147 1148 sc = xsc; 1149 ifp = &sc->arpcom.ac_if; 1150 mii = device_get_softc(sc->sf_miibus); 1151 1152 sf_stop(sc); 1153 sf_reset(sc); 1154 1155 /* Init all the receive filter registers */ 1156 for (i = SF_RXFILT_PERFECT_BASE; 1157 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1158 csr_write_4(sc, i, 0); 1159 1160 /* Empty stats counter registers. */ 1161 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1162 csr_write_4(sc, SF_STATS_BASE + 1163 (i + sizeof(u_int32_t)), 0); 1164 1165 /* Init our MAC address */ 1166 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1167 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1168 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1169 1170 if (sf_init_rx_ring(sc) == ENOBUFS) { 1171 printf("sf%d: initialization failed: no " 1172 "memory for rx buffers\n", sc->sf_unit); 1173 (void)splx(s); 1174 return; 1175 } 1176 1177 sf_init_tx_ring(sc); 1178 1179 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1180 1181 /* If we want promiscuous mode, set the allframes bit. */ 1182 if (ifp->if_flags & IFF_PROMISC) { 1183 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1184 } else { 1185 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1186 } 1187 1188 if (ifp->if_flags & IFF_BROADCAST) { 1189 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1190 } else { 1191 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1192 } 1193 1194 /* 1195 * Load the multicast filter. 1196 */ 1197 sf_setmulti(sc); 1198 1199 /* Init the completion queue indexes */ 1200 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1201 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1202 1203 /* Init the RX completion queue */ 1204 csr_write_4(sc, SF_RXCQ_CTL_1, 1205 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1206 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1207 1208 /* Init RX DMA control. */ 1209 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1210 1211 /* Init the RX buffer descriptor queue. */ 1212 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1213 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1214 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1215 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1216 1217 /* Init the TX completion queue */ 1218 csr_write_4(sc, SF_TXCQ_CTL, 1219 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1220 1221 /* Init the TX buffer descriptor queue. */ 1222 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1223 vtophys(sc->sf_ldata->sf_tx_dlist)); 1224 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1225 csr_write_4(sc, SF_TXDQ_CTL, 1226 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1227 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1228 1229 /* Enable autopadding of short TX frames. */ 1230 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1231 1232 /* Enable interrupts. */ 1233 csr_write_4(sc, SF_IMR, SF_INTRS); 1234 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1235 1236 /* Enable the RX and TX engines. */ 1237 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1238 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1239 1240 /*mii_mediachg(mii);*/ 1241 sf_ifmedia_upd(ifp); 1242 1243 ifp->if_flags |= IFF_RUNNING; 1244 ifp->if_flags &= ~IFF_OACTIVE; 1245 1246 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1247 1248 splx(s); 1249 1250 return; 1251 } 1252 1253 static int sf_encap(sc, c, m_head) 1254 struct sf_softc *sc; 1255 struct sf_tx_bufdesc_type0 *c; 1256 struct mbuf *m_head; 1257 { 1258 int frag = 0; 1259 struct sf_frag *f = NULL; 1260 struct mbuf *m; 1261 1262 m = m_head; 1263 1264 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1265 if (m->m_len != 0) { 1266 if (frag == SF_MAXFRAGS) 1267 break; 1268 f = &c->sf_frags[frag]; 1269 if (frag == 0) 1270 f->sf_pktlen = m_head->m_pkthdr.len; 1271 f->sf_fraglen = m->m_len; 1272 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1273 frag++; 1274 } 1275 } 1276 1277 if (m != NULL) { 1278 struct mbuf *m_new = NULL; 1279 1280 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1281 if (m_new == NULL) { 1282 printf("sf%d: no memory for tx list", sc->sf_unit); 1283 return(1); 1284 } 1285 1286 if (m_head->m_pkthdr.len > MHLEN) { 1287 MCLGET(m_new, MB_DONTWAIT); 1288 if (!(m_new->m_flags & M_EXT)) { 1289 m_freem(m_new); 1290 printf("sf%d: no memory for tx list", 1291 sc->sf_unit); 1292 return(1); 1293 } 1294 } 1295 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1296 mtod(m_new, caddr_t)); 1297 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1298 m_freem(m_head); 1299 m_head = m_new; 1300 f = &c->sf_frags[0]; 1301 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1302 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1303 frag = 1; 1304 } 1305 1306 c->sf_mbuf = m_head; 1307 c->sf_id = SF_TX_BUFDESC_ID; 1308 c->sf_fragcnt = frag; 1309 c->sf_intr = 1; 1310 c->sf_caltcp = 0; 1311 c->sf_crcen = 1; 1312 1313 return(0); 1314 } 1315 1316 static void sf_start(ifp) 1317 struct ifnet *ifp; 1318 { 1319 struct sf_softc *sc; 1320 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1321 struct mbuf *m_head = NULL; 1322 int i, txprod; 1323 1324 sc = ifp->if_softc; 1325 1326 if (!sc->sf_link) 1327 return; 1328 1329 if (ifp->if_flags & IFF_OACTIVE) 1330 return; 1331 1332 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1333 i = SF_IDX_HI(txprod) >> 4; 1334 1335 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1336 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1337 sf_init(sc); 1338 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1339 i = SF_IDX_HI(txprod) >> 4; 1340 } 1341 1342 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1343 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1344 ifp->if_flags |= IFF_OACTIVE; 1345 cur_tx = NULL; 1346 break; 1347 } 1348 m_head = ifq_poll(&ifp->if_snd); 1349 if (m_head == NULL) 1350 break; 1351 1352 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1353 if (sf_encap(sc, cur_tx, m_head)) { 1354 ifp->if_flags |= IFF_OACTIVE; 1355 cur_tx = NULL; 1356 break; 1357 } 1358 ifq_dequeue(&ifp->if_snd); 1359 BPF_MTAP(ifp, cur_tx->sf_mbuf); 1360 1361 SF_INC(i, SF_TX_DLIST_CNT); 1362 sc->sf_tx_cnt++; 1363 /* 1364 * Don't get the TX DMA queue get too full. 1365 */ 1366 if (sc->sf_tx_cnt > 64) 1367 break; 1368 } 1369 1370 if (cur_tx == NULL) 1371 return; 1372 1373 /* Transmit */ 1374 csr_write_4(sc, SF_TXDQ_PRODIDX, 1375 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1376 ((i << 20) & 0xFFFF0000)); 1377 1378 ifp->if_timer = 5; 1379 1380 return; 1381 } 1382 1383 static void sf_stop(sc) 1384 struct sf_softc *sc; 1385 { 1386 int i; 1387 struct ifnet *ifp; 1388 1389 ifp = &sc->arpcom.ac_if; 1390 1391 callout_stop(&sc->sf_stat_timer); 1392 1393 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1394 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1395 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1396 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1397 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1398 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1399 csr_write_4(sc, SF_TXCQ_CTL, 0); 1400 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1401 csr_write_4(sc, SF_TXDQ_CTL, 0); 1402 sf_reset(sc); 1403 1404 sc->sf_link = 0; 1405 1406 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1407 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1408 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1409 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1410 } 1411 } 1412 1413 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1414 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1415 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1416 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1417 } 1418 } 1419 1420 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1421 1422 return; 1423 } 1424 1425 /* 1426 * Note: it is important that this function not be interrupted. We 1427 * use a two-stage register access scheme: if we are interrupted in 1428 * between setting the indirect address register and reading from the 1429 * indirect data register, the contents of the address register could 1430 * be changed out from under us. 1431 */ 1432 static void sf_stats_update(xsc) 1433 void *xsc; 1434 { 1435 struct sf_softc *sc; 1436 struct ifnet *ifp; 1437 struct mii_data *mii; 1438 struct sf_stats stats; 1439 u_int32_t *ptr; 1440 int i, s; 1441 1442 s = splimp(); 1443 1444 sc = xsc; 1445 ifp = &sc->arpcom.ac_if; 1446 mii = device_get_softc(sc->sf_miibus); 1447 1448 ptr = (u_int32_t *)&stats; 1449 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1450 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1451 (i + sizeof(u_int32_t))); 1452 1453 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1454 csr_write_4(sc, SF_STATS_BASE + 1455 (i + sizeof(u_int32_t)), 0); 1456 1457 ifp->if_collisions += stats.sf_tx_single_colls + 1458 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1459 1460 mii_tick(mii); 1461 if (!sc->sf_link) { 1462 mii_pollstat(mii); 1463 if (mii->mii_media_status & IFM_ACTIVE && 1464 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1465 sc->sf_link++; 1466 if (!ifq_is_empty(&ifp->if_snd)) 1467 sf_start(ifp); 1468 } 1469 1470 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc); 1471 1472 splx(s); 1473 1474 return; 1475 } 1476 1477 static void sf_watchdog(ifp) 1478 struct ifnet *ifp; 1479 { 1480 struct sf_softc *sc; 1481 1482 sc = ifp->if_softc; 1483 1484 ifp->if_oerrors++; 1485 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1486 1487 sf_stop(sc); 1488 sf_reset(sc); 1489 sf_init(sc); 1490 1491 if (!ifq_is_empty(&ifp->if_snd)) 1492 sf_start(ifp); 1493 1494 return; 1495 } 1496 1497 static void sf_shutdown(dev) 1498 device_t dev; 1499 { 1500 struct sf_softc *sc; 1501 1502 sc = device_get_softc(dev); 1503 1504 sf_stop(sc); 1505 1506 return; 1507 } 1508