1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $ 33 */ 34 35 /* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86 #include "opt_ifpoll.h" 87 88 #include <sys/param.h> 89 #include <sys/endian.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/module.h> 96 #include <sys/socket.h> 97 #include <sys/serialize.h> 98 #include <sys/bus.h> 99 #include <sys/rman.h> 100 #include <sys/thread2.h> 101 #include <sys/interrupt.h> 102 103 #include <net/if.h> 104 #include <net/ifq_var.h> 105 #include <net/if_arp.h> 106 #include <net/ethernet.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_poll.h> 110 111 #include <net/bpf.h> 112 113 #include <dev/netif/mii_layer/mii.h> 114 #include <dev/netif/mii_layer/miivar.h> 115 116 #include <bus/pci/pcidevs.h> 117 #include <bus/pci/pcireg.h> 118 #include <bus/pci/pcivar.h> 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 /* 124 * Default to using PIO access for this driver. On SMP systems, 125 * there appear to be problems with memory mapped mode: it looks like 126 * doing too many memory mapped access back to back in rapid succession 127 * can hang the bus. I'm inclined to blame this on crummy design/construction 128 * on the part of RealTek. Memory mapped mode does appear to work on 129 * uniprocessor systems though. 130 */ 131 #define RL_USEIOSPACE 132 133 #include <dev/netif/rl/if_rlreg.h> 134 135 /* 136 * Various supported device vendors/types and their names. 137 */ 138 static struct rl_type { 139 uint16_t rl_vid; 140 uint16_t rl_did; 141 const char *rl_name; 142 } rl_devs[] = { 143 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8129, 144 "RealTek 8129 10/100BaseTX" }, 145 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 146 "RealTek 8139 10/100BaseTX" }, 147 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139B, 148 "RealTek 8139 10/100BaseTX CardBus" }, 149 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_MPX5030, 150 "Accton MPX 5030/5038 10/100BaseTX" }, 151 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_8139, 152 "Delta Electronics 8139 10/100BaseTX" }, 153 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_8139, 154 "Addtron Technology 8139 10/100BaseTX" }, 155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE530TXPLUS, 156 "D-Link DFE-530TX+ 10/100BaseTX" }, 157 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD, 158 "D-Link DFE-690TX 10/100BaseTX" }, 159 { PCI_VENDOR_NORTEL, PCI_PRODUCT_NORTEL_BAYSTACK_21, 160 "Nortel Networks 10/100BaseTX" }, 161 { PCI_VENDOR_PEPPERCON, PCI_PRODUCT_PEPPERCON_ROLF, 162 "Peppercon AG ROL/F" }, 163 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD, 164 "Corega FEther CB-TXD" }, 165 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD, 166 "Corega FEtherII CB-TXD" }, 167 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX, 168 "Planex FNW-3800-TX" }, 169 { 0, 0, NULL } 170 }; 171 172 static int rl_probe(device_t); 173 static int rl_attach(device_t); 174 static int rl_detach(device_t); 175 176 static int rl_encap(struct rl_softc *, struct mbuf * ); 177 178 static void rl_rxeof(struct rl_softc *); 179 static void rl_txeof(struct rl_softc *); 180 static void rl_intr(void *); 181 static void rl_tick(void *); 182 static void rl_start(struct ifnet *); 183 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 184 static void rl_init(void *); 185 static void rl_stop (struct rl_softc *); 186 static void rl_watchdog(struct ifnet *); 187 static int rl_suspend(device_t); 188 static int rl_resume(device_t); 189 static void rl_shutdown(device_t); 190 static int rl_ifmedia_upd(struct ifnet *); 191 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 192 193 static void rl_eeprom_putbyte(struct rl_softc *, int); 194 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 195 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int); 196 static void rl_mii_sync(struct rl_softc *); 197 static void rl_mii_send(struct rl_softc *, uint32_t, int); 198 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 199 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 200 201 static int rl_miibus_readreg(device_t, int, int); 202 static int rl_miibus_writereg(device_t, int, int, int); 203 static void rl_miibus_statchg(device_t); 204 205 static void rl_setmulti(struct rl_softc *); 206 static void rl_reset(struct rl_softc *); 207 static void rl_list_tx_init(struct rl_softc *); 208 209 #ifdef IFPOLL_ENABLE 210 static void rl_npoll(struct ifnet *, struct ifpoll_info *); 211 static void rl_npoll_compat(struct ifnet *, void *, int); 212 #endif 213 214 static int rl_dma_alloc(struct rl_softc *); 215 static void rl_dma_free(struct rl_softc *); 216 217 #ifdef RL_USEIOSPACE 218 #define RL_RES SYS_RES_IOPORT 219 #define RL_RID RL_PCI_LOIO 220 #else 221 #define RL_RES SYS_RES_MEMORY 222 #define RL_RID RL_PCI_LOMEM 223 #endif 224 225 static device_method_t rl_methods[] = { 226 /* Device interface */ 227 DEVMETHOD(device_probe, rl_probe), 228 DEVMETHOD(device_attach, rl_attach), 229 DEVMETHOD(device_detach, rl_detach), 230 DEVMETHOD(device_suspend, rl_suspend), 231 DEVMETHOD(device_resume, rl_resume), 232 DEVMETHOD(device_shutdown, rl_shutdown), 233 234 /* bus interface */ 235 DEVMETHOD(bus_print_child, bus_generic_print_child), 236 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 237 238 /* MII interface */ 239 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 240 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 241 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 242 243 { 0, 0 } 244 }; 245 246 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc)); 247 static devclass_t rl_devclass; 248 249 DECLARE_DUMMY_MODULE(if_rl); 250 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, NULL, NULL); 251 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, NULL, NULL); 252 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, NULL, NULL); 253 MODULE_DEPEND(if_rl, miibus, 1, 1, 1); 254 255 #define EE_SET(x) \ 256 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x)) 257 258 #define EE_CLR(x) \ 259 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x)) 260 261 /* 262 * Send a read command and address to the EEPROM, check for ACK. 263 */ 264 static void 265 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 266 { 267 int d, i; 268 269 d = addr | sc->rl_eecmd_read; 270 271 /* 272 * Feed in each bit and strobe the clock. 273 */ 274 for (i = 0x400; i; i >>= 1) { 275 if (d & i) 276 EE_SET(RL_EE_DATAIN); 277 else 278 EE_CLR(RL_EE_DATAIN); 279 DELAY(100); 280 EE_SET(RL_EE_CLK); 281 DELAY(150); 282 EE_CLR(RL_EE_CLK); 283 DELAY(100); 284 } 285 } 286 287 /* 288 * Read a word of data stored in the EEPROM at address 'addr.' 289 */ 290 static void 291 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 292 { 293 int i; 294 uint16_t word = 0; 295 296 /* Enter EEPROM access mode. */ 297 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 298 299 /* 300 * Send address of word we want to read. 301 */ 302 rl_eeprom_putbyte(sc, addr); 303 304 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 305 306 /* 307 * Start reading bits from EEPROM. 308 */ 309 for (i = 0x8000; i; i >>= 1) { 310 EE_SET(RL_EE_CLK); 311 DELAY(100); 312 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 313 word |= i; 314 EE_CLR(RL_EE_CLK); 315 DELAY(100); 316 } 317 318 /* Turn off EEPROM access mode. */ 319 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 320 321 *dest = word; 322 } 323 324 /* 325 * Read a sequence of words from the EEPROM. 326 */ 327 static void 328 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap) 329 { 330 int i; 331 u_int16_t word = 0, *ptr; 332 333 for (i = 0; i < cnt; i++) { 334 rl_eeprom_getword(sc, off + i, &word); 335 ptr = (u_int16_t *)(dest + (i * 2)); 336 if (swap) 337 *ptr = ntohs(word); 338 else 339 *ptr = word; 340 } 341 } 342 343 344 /* 345 * MII access routines are provided for the 8129, which 346 * doesn't have a built-in PHY. For the 8139, we fake things 347 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 348 * direct access PHY registers. 349 */ 350 #define MII_SET(x) \ 351 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x) 352 353 #define MII_CLR(x) \ 354 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x) 355 356 /* 357 * Sync the PHYs by setting data bit and strobing the clock 32 times. 358 */ 359 static void 360 rl_mii_sync(struct rl_softc *sc) 361 { 362 int i; 363 364 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 365 366 for (i = 0; i < 32; i++) { 367 MII_SET(RL_MII_CLK); 368 DELAY(1); 369 MII_CLR(RL_MII_CLK); 370 DELAY(1); 371 } 372 } 373 374 /* 375 * Clock a series of bits through the MII. 376 */ 377 static void 378 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 379 { 380 int i; 381 382 MII_CLR(RL_MII_CLK); 383 384 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 385 if (bits & i) 386 MII_SET(RL_MII_DATAOUT); 387 else 388 MII_CLR(RL_MII_DATAOUT); 389 DELAY(1); 390 MII_CLR(RL_MII_CLK); 391 DELAY(1); 392 MII_SET(RL_MII_CLK); 393 } 394 } 395 396 /* 397 * Read an PHY register through the MII. 398 */ 399 static int 400 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 401 { 402 int ack, i; 403 404 /* 405 * Set up frame for RX. 406 */ 407 frame->mii_stdelim = RL_MII_STARTDELIM; 408 frame->mii_opcode = RL_MII_READOP; 409 frame->mii_turnaround = 0; 410 frame->mii_data = 0; 411 412 CSR_WRITE_2(sc, RL_MII, 0); 413 414 /* 415 * Turn on data xmit. 416 */ 417 MII_SET(RL_MII_DIR); 418 419 rl_mii_sync(sc); 420 421 /* 422 * Send command/address info. 423 */ 424 rl_mii_send(sc, frame->mii_stdelim, 2); 425 rl_mii_send(sc, frame->mii_opcode, 2); 426 rl_mii_send(sc, frame->mii_phyaddr, 5); 427 rl_mii_send(sc, frame->mii_regaddr, 5); 428 429 /* Idle bit */ 430 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 431 DELAY(1); 432 MII_SET(RL_MII_CLK); 433 DELAY(1); 434 435 /* Turn off xmit. */ 436 MII_CLR(RL_MII_DIR); 437 438 /* Check for ack */ 439 MII_CLR(RL_MII_CLK); 440 DELAY(1); 441 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 442 MII_SET(RL_MII_CLK); 443 DELAY(1); 444 445 /* 446 * Now try reading data bits. If the ack failed, we still 447 * need to clock through 16 cycles to keep the PHY(s) in sync. 448 */ 449 if (ack) { 450 for(i = 0; i < 16; i++) { 451 MII_CLR(RL_MII_CLK); 452 DELAY(1); 453 MII_SET(RL_MII_CLK); 454 DELAY(1); 455 } 456 } else { 457 for (i = 0x8000; i; i >>= 1) { 458 MII_CLR(RL_MII_CLK); 459 DELAY(1); 460 if (!ack) { 461 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 462 frame->mii_data |= i; 463 DELAY(1); 464 } 465 MII_SET(RL_MII_CLK); 466 DELAY(1); 467 } 468 } 469 470 MII_CLR(RL_MII_CLK); 471 DELAY(1); 472 MII_SET(RL_MII_CLK); 473 DELAY(1); 474 475 return(ack ? 1 : 0); 476 } 477 478 /* 479 * Write to a PHY register through the MII. 480 */ 481 static int 482 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 483 { 484 /* 485 * Set up frame for TX. 486 */ 487 frame->mii_stdelim = RL_MII_STARTDELIM; 488 frame->mii_opcode = RL_MII_WRITEOP; 489 frame->mii_turnaround = RL_MII_TURNAROUND; 490 491 /* 492 * Turn on data output. 493 */ 494 MII_SET(RL_MII_DIR); 495 496 rl_mii_sync(sc); 497 498 rl_mii_send(sc, frame->mii_stdelim, 2); 499 rl_mii_send(sc, frame->mii_opcode, 2); 500 rl_mii_send(sc, frame->mii_phyaddr, 5); 501 rl_mii_send(sc, frame->mii_regaddr, 5); 502 rl_mii_send(sc, frame->mii_turnaround, 2); 503 rl_mii_send(sc, frame->mii_data, 16); 504 505 /* Idle bit. */ 506 MII_SET(RL_MII_CLK); 507 DELAY(1); 508 MII_CLR(RL_MII_CLK); 509 DELAY(1); 510 511 /* 512 * Turn off xmit. 513 */ 514 MII_CLR(RL_MII_DIR); 515 516 return(0); 517 } 518 519 static int 520 rl_miibus_readreg(device_t dev, int phy, int reg) 521 { 522 struct rl_softc *sc; 523 struct rl_mii_frame frame; 524 uint16_t rval = 0; 525 uint16_t rl8139_reg = 0; 526 527 sc = device_get_softc(dev); 528 529 if (sc->rl_type == RL_8139) { 530 /* Pretend the internal PHY is only at address 0 */ 531 if (phy) 532 return(0); 533 switch (reg) { 534 case MII_BMCR: 535 rl8139_reg = RL_BMCR; 536 break; 537 case MII_BMSR: 538 rl8139_reg = RL_BMSR; 539 break; 540 case MII_ANAR: 541 rl8139_reg = RL_ANAR; 542 break; 543 case MII_ANER: 544 rl8139_reg = RL_ANER; 545 break; 546 case MII_ANLPAR: 547 rl8139_reg = RL_LPAR; 548 break; 549 case MII_PHYIDR1: 550 case MII_PHYIDR2: 551 return(0); 552 break; 553 /* 554 * Allow the rlphy driver to read the media status 555 * register. If we have a link partner which does not 556 * support NWAY, this is the register which will tell 557 * us the results of parallel detection. 558 */ 559 case RL_MEDIASTAT: 560 rval = CSR_READ_1(sc, RL_MEDIASTAT); 561 return(rval); 562 default: 563 device_printf(dev, "bad phy register\n"); 564 return(0); 565 } 566 rval = CSR_READ_2(sc, rl8139_reg); 567 return(rval); 568 } 569 570 bzero(&frame, sizeof(frame)); 571 572 frame.mii_phyaddr = phy; 573 frame.mii_regaddr = reg; 574 rl_mii_readreg(sc, &frame); 575 576 return(frame.mii_data); 577 } 578 579 static int 580 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 581 { 582 struct rl_softc *sc; 583 struct rl_mii_frame frame; 584 u_int16_t rl8139_reg = 0; 585 586 sc = device_get_softc(dev); 587 588 if (sc->rl_type == RL_8139) { 589 /* Pretend the internal PHY is only at address 0 */ 590 if (phy) 591 return(0); 592 switch (reg) { 593 case MII_BMCR: 594 rl8139_reg = RL_BMCR; 595 break; 596 case MII_BMSR: 597 rl8139_reg = RL_BMSR; 598 break; 599 case MII_ANAR: 600 rl8139_reg = RL_ANAR; 601 break; 602 case MII_ANER: 603 rl8139_reg = RL_ANER; 604 break; 605 case MII_ANLPAR: 606 rl8139_reg = RL_LPAR; 607 break; 608 case MII_PHYIDR1: 609 case MII_PHYIDR2: 610 return(0); 611 default: 612 device_printf(dev, "bad phy register\n"); 613 return(0); 614 } 615 CSR_WRITE_2(sc, rl8139_reg, data); 616 return(0); 617 } 618 619 bzero(&frame, sizeof(frame)); 620 621 frame.mii_phyaddr = phy; 622 frame.mii_regaddr = reg; 623 frame.mii_data = data; 624 625 rl_mii_writereg(sc, &frame); 626 627 return(0); 628 } 629 630 static void 631 rl_miibus_statchg(device_t dev) 632 { 633 } 634 635 /* 636 * Program the 64-bit multicast hash filter. 637 */ 638 static void 639 rl_setmulti(struct rl_softc *sc) 640 { 641 struct ifnet *ifp; 642 int h = 0; 643 uint32_t hashes[2] = { 0, 0 }; 644 struct ifmultiaddr *ifma; 645 uint32_t rxfilt; 646 int mcnt = 0; 647 648 ifp = &sc->arpcom.ac_if; 649 650 rxfilt = CSR_READ_4(sc, RL_RXCFG); 651 652 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 653 rxfilt |= RL_RXCFG_RX_MULTI; 654 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 655 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 656 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 657 return; 658 } 659 660 /* first, zot all the existing hash bits */ 661 CSR_WRITE_4(sc, RL_MAR0, 0); 662 CSR_WRITE_4(sc, RL_MAR4, 0); 663 664 /* now program new ones */ 665 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 666 if (ifma->ifma_addr->sa_family != AF_LINK) 667 continue; 668 h = ether_crc32_be( 669 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 670 ETHER_ADDR_LEN) >> 26; 671 if (h < 32) 672 hashes[0] |= (1 << h); 673 else 674 hashes[1] |= (1 << (h - 32)); 675 mcnt++; 676 } 677 678 if (mcnt) 679 rxfilt |= RL_RXCFG_RX_MULTI; 680 else 681 rxfilt &= ~RL_RXCFG_RX_MULTI; 682 683 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 684 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 685 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 686 } 687 688 static void 689 rl_reset(struct rl_softc *sc) 690 { 691 int i; 692 693 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 694 695 for (i = 0; i < RL_TIMEOUT; i++) { 696 DELAY(10); 697 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 698 break; 699 } 700 if (i == RL_TIMEOUT) 701 device_printf(sc->rl_dev, "reset never completed!\n"); 702 } 703 704 /* 705 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 706 * IDs against our list and return a device name if we find a match. 707 * 708 * Return with a value < 0 to give re(4) a change to attach. 709 */ 710 static int 711 rl_probe(device_t dev) 712 { 713 struct rl_type *t; 714 uint16_t product = pci_get_device(dev); 715 uint16_t vendor = pci_get_vendor(dev); 716 717 for (t = rl_devs; t->rl_name != NULL; t++) { 718 if (vendor == t->rl_vid && product == t->rl_did) { 719 device_set_desc(dev, t->rl_name); 720 return(-100); 721 } 722 } 723 724 return(ENXIO); 725 } 726 727 /* 728 * Attach the interface. Allocate softc structures, do ifmedia 729 * setup and ethernet/BPF attach. 730 */ 731 static int 732 rl_attach(device_t dev) 733 { 734 uint8_t eaddr[ETHER_ADDR_LEN]; 735 uint16_t as[3]; 736 struct rl_softc *sc; 737 struct ifnet *ifp; 738 uint16_t rl_did = 0; 739 int error = 0, rid, i; 740 741 sc = device_get_softc(dev); 742 sc->rl_dev = dev; 743 744 /* 745 * Handle power management nonsense. 746 */ 747 748 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 749 uint32_t iobase, membase, irq; 750 751 /* Save important PCI config data. */ 752 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 753 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 754 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 755 756 /* Reset the power state. */ 757 device_printf(dev, "chip is in D%d power mode " 758 "-- setting to D0\n", pci_get_powerstate(dev)); 759 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 760 761 /* Restore PCI config data. */ 762 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 763 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 764 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 765 } 766 767 pci_enable_busmaster(dev); 768 769 rid = RL_RID; 770 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 771 772 if (sc->rl_res == NULL) { 773 device_printf(dev, "couldn't map ports/memory\n"); 774 error = ENXIO; 775 goto fail; 776 } 777 778 sc->rl_btag = rman_get_bustag(sc->rl_res); 779 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 780 781 rid = 0; 782 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 783 RF_SHAREABLE | RF_ACTIVE); 784 785 if (sc->rl_irq == NULL) { 786 device_printf(dev, "couldn't map interrupt\n"); 787 error = ENXIO; 788 goto fail; 789 } 790 791 callout_init(&sc->rl_stat_timer); 792 793 /* Reset the adapter. */ 794 rl_reset(sc); 795 796 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 797 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 798 if (rl_did != 0x8129) 799 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 800 801 /* 802 * Get station address from the EEPROM. 803 */ 804 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 805 for (i = 0; i < 3; i++) { 806 eaddr[(i * 2) + 0] = as[i] & 0xff; 807 eaddr[(i * 2) + 1] = as[i] >> 8; 808 } 809 810 /* 811 * Now read the exact device type from the EEPROM to find 812 * out if it's an 8129 or 8139. 813 */ 814 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 815 816 if (rl_did == PCI_PRODUCT_REALTEK_RT8139 || 817 rl_did == PCI_PRODUCT_ACCTON_MPX5030 || 818 rl_did == PCI_PRODUCT_DELTA_8139 || 819 rl_did == PCI_PRODUCT_ADDTRON_8139 || 820 rl_did == PCI_PRODUCT_DLINK_DFE530TXPLUS || 821 rl_did == PCI_PRODUCT_REALTEK_RT8139B || 822 rl_did == PCI_PRODUCT_DLINK_DFE690TXD || 823 rl_did == PCI_PRODUCT_COREGA_CB_TXD || 824 rl_did == PCI_PRODUCT_COREGA_2CB_TXD || 825 rl_did == PCI_PRODUCT_PLANEX_FNW_3800_TX) { 826 sc->rl_type = RL_8139; 827 } else if (rl_did == PCI_PRODUCT_REALTEK_RT8129) { 828 sc->rl_type = RL_8129; 829 } else { 830 device_printf(dev, "unknown device ID: %x\n", rl_did); 831 sc->rl_type = RL_8139; 832 /* 833 * Read RL_IDR register to get ethernet address as accessing 834 * EEPROM may not extract correct address. 835 */ 836 for (i = 0; i < ETHER_ADDR_LEN; i++) 837 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 838 } 839 840 error = rl_dma_alloc(sc); 841 if (error) 842 goto fail; 843 844 /* Do MII setup */ 845 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd, 846 rl_ifmedia_sts)) { 847 device_printf(dev, "MII without any phy!\n"); 848 error = ENXIO; 849 goto fail; 850 } 851 852 ifp = &sc->arpcom.ac_if; 853 ifp->if_softc = sc; 854 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 855 ifp->if_mtu = ETHERMTU; 856 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 857 ifp->if_ioctl = rl_ioctl; 858 ifp->if_start = rl_start; 859 ifp->if_watchdog = rl_watchdog; 860 ifp->if_init = rl_init; 861 ifp->if_baudrate = 10000000; 862 ifp->if_capabilities = IFCAP_VLAN_MTU; 863 #ifdef IFPOLL_ENABLE 864 ifp->if_npoll = rl_npoll; 865 #endif 866 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 867 ifq_set_ready(&ifp->if_snd); 868 869 /* 870 * Call MI attach routine. 871 */ 872 ether_ifattach(ifp, eaddr, NULL); 873 874 #ifdef IFPOLL_ENABLE 875 ifpoll_compat_setup(&sc->rl_npoll, NULL, NULL, device_get_unit(dev), 876 ifp->if_serializer); 877 #endif 878 879 error = bus_setup_intr(dev, sc->rl_irq, INTR_MPSAFE, rl_intr, 880 sc, &sc->rl_intrhand, ifp->if_serializer); 881 882 if (error) { 883 device_printf(dev, "couldn't set up irq\n"); 884 ether_ifdetach(ifp); 885 goto fail; 886 } 887 888 ifp->if_cpuid = rman_get_cpuid(sc->rl_irq); 889 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 890 891 return(0); 892 893 fail: 894 rl_detach(dev); 895 return(error); 896 } 897 898 static int 899 rl_detach(device_t dev) 900 { 901 struct rl_softc *sc; 902 struct ifnet *ifp; 903 904 sc = device_get_softc(dev); 905 ifp = &sc->arpcom.ac_if; 906 907 if (device_is_attached(dev)) { 908 lwkt_serialize_enter(ifp->if_serializer); 909 rl_stop(sc); 910 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 911 lwkt_serialize_exit(ifp->if_serializer); 912 913 ether_ifdetach(ifp); 914 } 915 916 if (sc->rl_miibus) 917 device_delete_child(dev, sc->rl_miibus); 918 bus_generic_detach(dev); 919 920 if (sc->rl_irq) 921 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 922 if (sc->rl_res) 923 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 924 925 rl_dma_free(sc); 926 927 return(0); 928 } 929 930 /* 931 * Initialize the transmit descriptors. 932 */ 933 static void 934 rl_list_tx_init(struct rl_softc *sc) 935 { 936 struct rl_chain_data *cd; 937 int i; 938 939 cd = &sc->rl_cdata; 940 for (i = 0; i < RL_TX_LIST_CNT; i++) { 941 cd->rl_tx_chain[i] = NULL; 942 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 943 0x0000000); 944 } 945 946 sc->rl_cdata.cur_tx = 0; 947 sc->rl_cdata.last_tx = 0; 948 } 949 950 /* 951 * A frame has been uploaded: pass the resulting mbuf chain up to 952 * the higher level protocols. 953 * 954 * You know there's something wrong with a PCI bus-master chip design 955 * when you have to use m_devget(). 956 * 957 * The receive operation is badly documented in the datasheet, so I'll 958 * attempt to document it here. The driver provides a buffer area and 959 * places its base address in the RX buffer start address register. 960 * The chip then begins copying frames into the RX buffer. Each frame 961 * is preceded by a 32-bit RX status word which specifies the length 962 * of the frame and certain other status bits. Each frame (starting with 963 * the status word) is also 32-bit aligned. The frame length is in the 964 * first 16 bits of the status word; the lower 15 bits correspond with 965 * the 'rx status register' mentioned in the datasheet. 966 * 967 * Note: to make the Alpha happy, the frame payload needs to be aligned 968 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 969 * the ring buffer starting at an address two bytes before the actual 970 * data location. We can then shave off the first two bytes using m_adj(). 971 * The reason we do this is because m_devget() doesn't let us specify an 972 * offset into the mbuf storage space, so we have to artificially create 973 * one. The ring is allocated in such a way that there are a few unused 974 * bytes of space preceecing it so that it will be safe for us to do the 975 * 2-byte backstep even if reading from the ring at offset 0. 976 */ 977 static void 978 rl_rxeof(struct rl_softc *sc) 979 { 980 struct mbuf *m; 981 struct ifnet *ifp; 982 int total_len = 0; 983 uint32_t rxstat; 984 caddr_t rxbufpos; 985 int wrap = 0, done = 0; 986 uint16_t cur_rx = 0, max_bytes = 0, rx_bytes = 0; 987 988 ifp = &sc->arpcom.ac_if; 989 990 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 991 if (!done) { 992 uint16_t limit; 993 994 done = 1; 995 996 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % 997 RL_RXBUFLEN; 998 999 /* Do not try to read past this point. */ 1000 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1001 if (limit < cur_rx) 1002 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1003 else 1004 max_bytes = limit - cur_rx; 1005 } 1006 #ifdef IFPOLL_ENABLE 1007 if (ifp->if_flags & IFF_NPOLLING) { 1008 if (sc->rxcycles <= 0) 1009 break; 1010 sc->rxcycles--; 1011 } 1012 #endif /* IFPOLL_ENABLE */ 1013 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1014 rxstat = le32toh(*(uint32_t *)rxbufpos); 1015 1016 /* 1017 * Here's a totally undocumented fact for you. When the 1018 * RealTek chip is in the process of copying a packet into 1019 * RAM for you, the length will be 0xfff0. If you spot a 1020 * packet header with this value, you need to stop. The 1021 * datasheet makes absolutely no mention of this and 1022 * RealTek should be shot for this. 1023 */ 1024 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1025 break; 1026 1027 if ((rxstat & RL_RXSTAT_RXOK) == 0) { 1028 ifp->if_ierrors++; 1029 rl_init(sc); 1030 return; 1031 } 1032 1033 /* No errors; receive the packet. */ 1034 total_len = rxstat >> 16; 1035 rx_bytes += total_len + 4; 1036 1037 /* 1038 * XXX The RealTek chip includes the CRC with every 1039 * received frame, and there's no way to turn this 1040 * behavior off (at least, I can't find anything in 1041 * the manual that explains how to do it) so we have 1042 * to trim off the CRC manually. 1043 */ 1044 total_len -= ETHER_CRC_LEN; 1045 1046 /* 1047 * Avoid trying to read more bytes than we know 1048 * the chip has prepared for us. 1049 */ 1050 if (rx_bytes > max_bytes) 1051 break; 1052 1053 rxbufpos = sc->rl_cdata.rl_rx_buf + 1054 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1055 1056 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1057 rxbufpos = sc->rl_cdata.rl_rx_buf; 1058 1059 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1060 1061 if (total_len > wrap) { 1062 /* 1063 * Fool m_devget() into thinking we want to copy 1064 * the whole buffer so we don't end up fragmenting 1065 * the data. 1066 */ 1067 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1068 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 1069 if (m == NULL) { 1070 ifp->if_ierrors++; 1071 } else { 1072 m_adj(m, RL_ETHER_ALIGN); 1073 m_copyback(m, wrap, total_len - wrap, 1074 sc->rl_cdata.rl_rx_buf); 1075 } 1076 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1077 } else { 1078 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1079 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1080 if (m == NULL) { 1081 ifp->if_ierrors++; 1082 } else 1083 m_adj(m, RL_ETHER_ALIGN); 1084 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1085 } 1086 1087 /* 1088 * Round up to 32-bit boundary. 1089 */ 1090 cur_rx = (cur_rx + 3) & ~3; 1091 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1092 1093 if (m == NULL) 1094 continue; 1095 1096 ifp->if_ipackets++; 1097 1098 ifp->if_input(ifp, m); 1099 } 1100 } 1101 1102 /* 1103 * A frame was downloaded to the chip. It's safe for us to clean up 1104 * the list buffers. 1105 */ 1106 static void 1107 rl_txeof(struct rl_softc *sc) 1108 { 1109 struct ifnet *ifp; 1110 uint32_t txstat; 1111 1112 ifp = &sc->arpcom.ac_if; 1113 1114 /* 1115 * Go through our tx list and free mbufs for those 1116 * frames that have been uploaded. 1117 */ 1118 do { 1119 if (RL_LAST_TXMBUF(sc) == NULL) 1120 break; 1121 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1122 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN | 1123 RL_TXSTAT_TXABRT)) == 0) 1124 break; 1125 1126 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1127 1128 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc)); 1129 m_freem(RL_LAST_TXMBUF(sc)); 1130 RL_LAST_TXMBUF(sc) = NULL; 1131 RL_INC(sc->rl_cdata.last_tx); 1132 1133 if (txstat & RL_TXSTAT_TX_UNDERRUN) { 1134 sc->rl_txthresh += 32; 1135 if (sc->rl_txthresh > RL_TX_THRESH_MAX) 1136 sc->rl_txthresh = RL_TX_THRESH_MAX; 1137 } 1138 1139 if (txstat & RL_TXSTAT_TX_OK) { 1140 ifp->if_opackets++; 1141 } else { 1142 ifp->if_oerrors++; 1143 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN)) 1144 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1145 } 1146 ifp->if_flags &= ~IFF_OACTIVE; 1147 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1148 1149 if (RL_LAST_TXMBUF(sc) == NULL) 1150 ifp->if_timer = 0; 1151 else if (ifp->if_timer == 0) 1152 ifp->if_timer = 5; 1153 } 1154 1155 static void 1156 rl_tick(void *xsc) 1157 { 1158 struct rl_softc *sc = xsc; 1159 struct mii_data *mii; 1160 1161 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1162 1163 mii = device_get_softc(sc->rl_miibus); 1164 mii_tick(mii); 1165 1166 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1167 1168 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1169 } 1170 1171 #ifdef IFPOLL_ENABLE 1172 1173 static void 1174 rl_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1175 { 1176 struct rl_softc *sc = ifp->if_softc; 1177 1178 ASSERT_SERIALIZED(ifp->if_serializer); 1179 1180 sc->rxcycles = count; 1181 rl_rxeof(sc); 1182 rl_txeof(sc); 1183 if (!ifq_is_empty(&ifp->if_snd)) 1184 if_devstart(ifp); 1185 1186 if (sc->rl_npoll.ifpc_stcount-- == 0) { 1187 uint16_t status; 1188 1189 sc->rl_npoll.ifpc_stcount = sc->rl_npoll.ifpc_stfrac; 1190 1191 status = CSR_READ_2(sc, RL_ISR); 1192 if (status == 0xffff) 1193 return; 1194 if (status) 1195 CSR_WRITE_2(sc, RL_ISR, status); 1196 1197 /* 1198 * XXX check behaviour on receiver stalls. 1199 */ 1200 1201 if (status & RL_ISR_SYSTEM_ERR) { 1202 rl_reset(sc); 1203 rl_init(sc); 1204 } 1205 } 1206 } 1207 1208 static void 1209 rl_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1210 { 1211 struct rl_softc *sc = ifp->if_softc; 1212 1213 ASSERT_SERIALIZED(ifp->if_serializer); 1214 1215 if (info != NULL) { 1216 int cpuid = sc->rl_npoll.ifpc_cpuid; 1217 1218 info->ifpi_rx[cpuid].poll_func = rl_npoll_compat; 1219 info->ifpi_rx[cpuid].arg = NULL; 1220 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1221 1222 if (ifp->if_flags & IFF_RUNNING) { 1223 /* disable interrupts */ 1224 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1225 sc->rl_npoll.ifpc_stcount = 0; 1226 } 1227 ifp->if_npoll_cpuid = cpuid; 1228 } else { 1229 if (ifp->if_flags & IFF_RUNNING) { 1230 /* enable interrupts */ 1231 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1232 } 1233 ifp->if_npoll_cpuid = -1; 1234 } 1235 } 1236 1237 #endif /* IFPOLL_ENABLE */ 1238 1239 static void 1240 rl_intr(void *arg) 1241 { 1242 struct rl_softc *sc; 1243 struct ifnet *ifp; 1244 uint16_t status; 1245 1246 sc = arg; 1247 1248 if (sc->suspended) 1249 return; 1250 1251 ifp = &sc->arpcom.ac_if; 1252 1253 for (;;) { 1254 status = CSR_READ_2(sc, RL_ISR); 1255 /* If the card has gone away, the read returns 0xffff. */ 1256 if (status == 0xffff) 1257 break; 1258 1259 if (status != 0) 1260 CSR_WRITE_2(sc, RL_ISR, status); 1261 1262 if ((status & RL_INTRS) == 0) 1263 break; 1264 1265 if (status & RL_ISR_RX_OK) 1266 rl_rxeof(sc); 1267 1268 if (status & RL_ISR_RX_ERR) 1269 rl_rxeof(sc); 1270 1271 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1272 rl_txeof(sc); 1273 1274 if (status & RL_ISR_SYSTEM_ERR) { 1275 rl_reset(sc); 1276 rl_init(sc); 1277 } 1278 1279 } 1280 1281 if (!ifq_is_empty(&ifp->if_snd)) 1282 if_devstart(ifp); 1283 } 1284 1285 /* 1286 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1287 * pointers to the fragment pointers. 1288 */ 1289 static int 1290 rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1291 { 1292 struct mbuf *m_new = NULL; 1293 bus_dma_segment_t seg; 1294 int nseg, error; 1295 1296 /* 1297 * The RealTek is brain damaged and wants longword-aligned 1298 * TX buffers, plus we can only have one fragment buffer 1299 * per packet. We have to copy pretty much all the time. 1300 */ 1301 m_new = m_defrag(m_head, MB_DONTWAIT); 1302 if (m_new == NULL) { 1303 m_freem(m_head); 1304 return ENOBUFS; 1305 } 1306 m_head = m_new; 1307 1308 /* Pad frames to at least 60 bytes. */ 1309 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1310 error = m_devpad(m_head, RL_MIN_FRAMELEN); 1311 if (error) { 1312 m_freem(m_head); 1313 return error; 1314 } 1315 } 1316 1317 /* Extract physical address. */ 1318 error = bus_dmamap_load_mbuf_segment(sc->rl_cdata.rl_tx_tag, 1319 RL_CUR_DMAMAP(sc), m_head, 1320 &seg, 1, &nseg, BUS_DMA_NOWAIT); 1321 if (error) { 1322 m_freem(m_head); 1323 return error; 1324 } 1325 1326 /* Sync the loaded TX buffer. */ 1327 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc), 1328 BUS_DMASYNC_PREWRITE); 1329 1330 /* Transmit */ 1331 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), seg.ds_addr); 1332 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1333 RL_TXTHRESH(sc->rl_txthresh) | seg.ds_len); 1334 1335 RL_CUR_TXMBUF(sc) = m_head; 1336 return 0; 1337 } 1338 1339 /* 1340 * Main transmit routine. 1341 */ 1342 1343 static void 1344 rl_start(struct ifnet *ifp) 1345 { 1346 struct rl_softc *sc = ifp->if_softc; 1347 struct mbuf *m_head = NULL; 1348 1349 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1350 return; 1351 1352 while (RL_CUR_TXMBUF(sc) == NULL) { 1353 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1354 if (m_head == NULL) 1355 break; 1356 1357 if (rl_encap(sc, m_head)) 1358 continue; 1359 1360 /* 1361 * If there's a BPF listener, bounce a copy of this frame 1362 * to him. 1363 */ 1364 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1365 1366 RL_INC(sc->rl_cdata.cur_tx); 1367 1368 /* 1369 * Set a timeout in case the chip goes out to lunch. 1370 */ 1371 ifp->if_timer = 5; 1372 } 1373 1374 /* 1375 * We broke out of the loop because all our TX slots are 1376 * full. Mark the NIC as busy until it drains some of the 1377 * packets from the queue. 1378 */ 1379 if (RL_CUR_TXMBUF(sc) != NULL) 1380 ifp->if_flags |= IFF_OACTIVE; 1381 } 1382 1383 static void 1384 rl_init(void *xsc) 1385 { 1386 struct rl_softc *sc = xsc; 1387 struct ifnet *ifp = &sc->arpcom.ac_if; 1388 struct mii_data *mii; 1389 uint32_t rxcfg = 0; 1390 1391 mii = device_get_softc(sc->rl_miibus); 1392 1393 /* 1394 * Cancel pending I/O and free all RX/TX buffers. 1395 */ 1396 rl_stop(sc); 1397 1398 /* 1399 * Init our MAC address. Even though the chipset documentation 1400 * doesn't mention it, we need to enter "Config register write enable" 1401 * mode to modify the ID registers. 1402 */ 1403 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1404 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1405 *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1406 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1407 *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1408 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1409 1410 /* Init the RX buffer pointer register. */ 1411 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr); 1412 1413 /* Init TX descriptors. */ 1414 rl_list_tx_init(sc); 1415 1416 /* 1417 * Enable transmit and receive. 1418 */ 1419 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1420 1421 /* 1422 * Set the initial TX and RX configuration. 1423 */ 1424 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1425 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1426 1427 /* Set the individual bit to receive frames for this host only. */ 1428 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1429 rxcfg |= RL_RXCFG_RX_INDIV; 1430 1431 /* If we want promiscuous mode, set the allframes bit. */ 1432 if (ifp->if_flags & IFF_PROMISC) { 1433 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1434 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1435 } else { 1436 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1437 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1438 } 1439 1440 /* 1441 * Set capture broadcast bit to capture broadcast frames. 1442 */ 1443 if (ifp->if_flags & IFF_BROADCAST) { 1444 rxcfg |= RL_RXCFG_RX_BROAD; 1445 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1446 } else { 1447 rxcfg &= ~RL_RXCFG_RX_BROAD; 1448 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1449 } 1450 1451 /* 1452 * Program the multicast filter, if necessary. 1453 */ 1454 rl_setmulti(sc); 1455 1456 #ifdef IFPOLL_ENABLE 1457 /* 1458 * Only enable interrupts if we are polling, keep them off otherwise. 1459 */ 1460 if (ifp->if_flags & IFF_NPOLLING) { 1461 CSR_WRITE_2(sc, RL_IMR, 0); 1462 sc->rl_npoll.ifpc_stcount = 0; 1463 } else 1464 #endif /* IFPOLL_ENABLE */ 1465 /* 1466 * Enable interrupts. 1467 */ 1468 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1469 1470 /* Set initial TX threshold */ 1471 sc->rl_txthresh = RL_TX_THRESH_INIT; 1472 1473 /* Start RX/TX process. */ 1474 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1475 1476 /* Enable receiver and transmitter. */ 1477 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1478 1479 mii_mediachg(mii); 1480 1481 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1482 1483 ifp->if_flags |= IFF_RUNNING; 1484 ifp->if_flags &= ~IFF_OACTIVE; 1485 1486 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc); 1487 } 1488 1489 /* 1490 * Set media options. 1491 */ 1492 static int 1493 rl_ifmedia_upd(struct ifnet *ifp) 1494 { 1495 struct rl_softc *sc; 1496 struct mii_data *mii; 1497 1498 sc = ifp->if_softc; 1499 mii = device_get_softc(sc->rl_miibus); 1500 mii_mediachg(mii); 1501 1502 return(0); 1503 } 1504 1505 /* 1506 * Report current media status. 1507 */ 1508 static void 1509 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1510 { 1511 struct rl_softc *sc = ifp->if_softc; 1512 struct mii_data *mii = device_get_softc(sc->rl_miibus); 1513 1514 mii_pollstat(mii); 1515 ifmr->ifm_active = mii->mii_media_active; 1516 ifmr->ifm_status = mii->mii_media_status; 1517 } 1518 1519 static int 1520 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1521 { 1522 struct rl_softc *sc = ifp->if_softc; 1523 struct ifreq *ifr = (struct ifreq *) data; 1524 struct mii_data *mii; 1525 int error = 0; 1526 1527 switch (command) { 1528 case SIOCSIFFLAGS: 1529 if (ifp->if_flags & IFF_UP) { 1530 rl_init(sc); 1531 } else { 1532 if (ifp->if_flags & IFF_RUNNING) 1533 rl_stop(sc); 1534 } 1535 error = 0; 1536 break; 1537 case SIOCADDMULTI: 1538 case SIOCDELMULTI: 1539 rl_setmulti(sc); 1540 error = 0; 1541 break; 1542 case SIOCGIFMEDIA: 1543 case SIOCSIFMEDIA: 1544 mii = device_get_softc(sc->rl_miibus); 1545 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1546 break; 1547 case SIOCSIFCAP: 1548 break; 1549 default: 1550 error = ether_ioctl(ifp, command, data); 1551 break; 1552 } 1553 1554 return(error); 1555 } 1556 1557 static void 1558 rl_watchdog(struct ifnet *ifp) 1559 { 1560 struct rl_softc *sc = ifp->if_softc; 1561 1562 device_printf(sc->rl_dev, "watchdog timeout\n"); 1563 1564 ifp->if_oerrors++; 1565 1566 rl_txeof(sc); 1567 rl_rxeof(sc); 1568 rl_init(sc); 1569 } 1570 1571 /* 1572 * Stop the adapter and free any mbufs allocated to the 1573 * RX and TX lists. 1574 */ 1575 static void 1576 rl_stop(struct rl_softc *sc) 1577 { 1578 struct ifnet *ifp = &sc->arpcom.ac_if; 1579 int i; 1580 1581 ifp->if_timer = 0; 1582 1583 callout_stop(&sc->rl_stat_timer); 1584 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1585 1586 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1587 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1588 1589 /* 1590 * Free the TX list buffers. 1591 */ 1592 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1593 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1594 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, 1595 sc->rl_cdata.rl_tx_dmamap[i]); 1596 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1597 sc->rl_cdata.rl_tx_chain[i] = NULL; 1598 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1599 0x0000000); 1600 } 1601 } 1602 } 1603 1604 /* 1605 * Stop all chip I/O so that the kernel's probe routines don't 1606 * get confused by errant DMAs when rebooting. 1607 */ 1608 static void 1609 rl_shutdown(device_t dev) 1610 { 1611 struct rl_softc *sc; 1612 1613 sc = device_get_softc(dev); 1614 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1615 rl_stop(sc); 1616 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1617 } 1618 1619 /* 1620 * Device suspend routine. Stop the interface and save some PCI 1621 * settings in case the BIOS doesn't restore them properly on 1622 * resume. 1623 */ 1624 static int 1625 rl_suspend(device_t dev) 1626 { 1627 struct rl_softc *sc = device_get_softc(dev); 1628 int i; 1629 1630 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1631 rl_stop(sc); 1632 1633 for (i = 0; i < 5; i++) 1634 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1635 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1636 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1637 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1638 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1639 1640 sc->suspended = 1; 1641 1642 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1643 return (0); 1644 } 1645 1646 /* 1647 * Device resume routine. Restore some PCI settings in case the BIOS 1648 * doesn't, re-enable busmastering, and restart the interface if 1649 * appropriate. 1650 */ 1651 static int 1652 rl_resume(device_t dev) 1653 { 1654 struct rl_softc *sc = device_get_softc(dev); 1655 struct ifnet *ifp = &sc->arpcom.ac_if; 1656 int i; 1657 1658 lwkt_serialize_enter(ifp->if_serializer); 1659 1660 /* better way to do this? */ 1661 for (i = 0; i < 5; i++) 1662 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 1663 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1664 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1665 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1666 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1667 1668 /* reenable busmastering */ 1669 pci_enable_busmaster(dev); 1670 pci_enable_io(dev, RL_RES); 1671 1672 /* reinitialize interface if necessary */ 1673 if (ifp->if_flags & IFF_UP) 1674 rl_init(sc); 1675 1676 sc->suspended = 0; 1677 lwkt_serialize_exit(ifp->if_serializer); 1678 return (0); 1679 } 1680 1681 static int 1682 rl_dma_alloc(struct rl_softc *sc) 1683 { 1684 bus_dmamem_t dmem; 1685 int error, i; 1686 1687 error = bus_dma_tag_create(NULL, /* parent */ 1688 1, 0, /* alignment, boundary */ 1689 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1690 BUS_SPACE_MAXADDR, /* highaddr */ 1691 NULL, NULL, /* filter, filterarg */ 1692 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1693 0, /* nsegments */ 1694 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1695 0, /* flags */ 1696 &sc->rl_parent_tag); 1697 if (error) { 1698 device_printf(sc->rl_dev, "can't create parent tag\n"); 1699 return error; 1700 } 1701 1702 /* Allocate a chunk of coherent memory for RX */ 1703 error = bus_dmamem_coherent(sc->rl_parent_tag, 1, 0, 1704 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1705 RL_RXBUFLEN + 1518, BUS_DMA_WAITOK, &dmem); 1706 if (error) 1707 return error; 1708 1709 sc->rl_cdata.rl_rx_tag = dmem.dmem_tag; 1710 sc->rl_cdata.rl_rx_dmamap = dmem.dmem_map; 1711 sc->rl_cdata.rl_rx_buf_ptr = dmem.dmem_addr; 1712 1713 /* NOTE: Apply same adjustment to vaddr and paddr */ 1714 sc->rl_cdata.rl_rx_buf = sc->rl_cdata.rl_rx_buf_ptr + sizeof(uint64_t); 1715 sc->rl_cdata.rl_rx_buf_paddr = dmem.dmem_busaddr + sizeof(uint64_t); 1716 1717 /* 1718 * Allocate TX mbuf's DMA tag and maps 1719 */ 1720 error = bus_dma_tag_create(sc->rl_parent_tag,/* parent */ 1721 RL_TXBUF_ALIGN, 0, /* alignment, boundary */ 1722 BUS_SPACE_MAXADDR, /* lowaddr */ 1723 BUS_SPACE_MAXADDR, /* highaddr */ 1724 NULL, NULL, /* filter, filterarg */ 1725 MCLBYTES, /* maxsize */ 1726 1, /* nsegments */ 1727 MCLBYTES, /* maxsegsize */ 1728 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 1729 BUS_DMA_ALIGNED, /* flags */ 1730 &sc->rl_cdata.rl_tx_tag); 1731 if (error) { 1732 device_printf(sc->rl_dev, "can't create TX mbuf tag\n"); 1733 return error; 1734 } 1735 1736 for (i = 0; i < RL_TX_LIST_CNT; ++i) { 1737 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 1738 BUS_DMA_WAITOK, &sc->rl_cdata.rl_tx_dmamap[i]); 1739 if (error) { 1740 int j; 1741 1742 for (j = 0; j < i; ++j) { 1743 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag, 1744 sc->rl_cdata.rl_tx_dmamap[j]); 1745 } 1746 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1747 sc->rl_cdata.rl_tx_tag = NULL; 1748 1749 device_printf(sc->rl_dev, "can't create TX mbuf map\n"); 1750 return error; 1751 } 1752 } 1753 return 0; 1754 } 1755 1756 static void 1757 rl_dma_free(struct rl_softc *sc) 1758 { 1759 if (sc->rl_cdata.rl_tx_tag != NULL) { 1760 int i; 1761 1762 for (i = 0; i < RL_TX_LIST_CNT; ++i) { 1763 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag, 1764 sc->rl_cdata.rl_tx_dmamap[i]); 1765 } 1766 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1767 } 1768 1769 if (sc->rl_cdata.rl_rx_tag != NULL) { 1770 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag, 1771 sc->rl_cdata.rl_rx_dmamap); 1772 /* NOTE: Use rl_rx_buf_ptr here */ 1773 bus_dmamem_free(sc->rl_cdata.rl_rx_tag, 1774 sc->rl_cdata.rl_rx_buf_ptr, 1775 sc->rl_cdata.rl_rx_dmamap); 1776 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag); 1777 } 1778 1779 if (sc->rl_parent_tag) 1780 bus_dma_tag_destroy(sc->rl_parent_tag); 1781 } 1782